ZHCSS37J may 2009 – january 2021 XIO2001
PRODUCTION DATA
This register enables and disables the PCI clock outputs (CLKOUT). See Table 8-50 for a complete description of the register contents.
PCI register offset: | D8h | |
Register type: | Read-only, Read/Write | |
Default value: | 00h |
BIT NUMBER | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET STATE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION | |
---|---|---|---|---|
7(1) | RSVD | R | Reserved. Returns 0b when read. | |
6(1) | CLOCK6_DISABLE | RW | Clock output 6 disable. This bit disables secondary CLKOUT6.
0 = Clock enabled (default) 1 = Clock disabled | |
5(1) | CLOCK5_DISABLE | RW | Clock output 5 disable. This bit disables secondary CLKOUT5.
0 = Clock enabled (default) 1 = Clock disabled | |
4(1) | CLOCK4_DISABLE | RW | Clock output 4 disable. This bit disables secondary CLKOUT4.
0 = Clock enabled (default) 1 = Clock disabled | |
3(1) | CLOCK3_DISABLE | RW | Clock output 3 disable. This bit disables secondary CLKOUT3.
0 = Clock enabled (default) 1 = Clock disabled | |
2(1) | CLOCK2_DISABLE | RW | Clock output 2 disable. This bit disables secondary CLKOUT2.
0 = Clock enabled (default) 1 = Clock disabled | |
1(1) | CLOCK1_DISABLE | RW | Clock output 1 disable. This bit disables secondary CLKOUT1.
0 = Clock enabled (default) 1 = Clock disabled | |
0(1) | CLOCK0_DISABLE | RW | Clock output 0 disable. This bit disables secondary CLKOUT0.
0 = Clock enabled (default) 1 = Clock disabled |