ZHCSS37J may 2009 – january 2021 XIO2001
PRODUCTION DATA
PCI Express configuration register transactions received by the bridge are decoded based on the transaction’s destination ID. These configuration transactions can be broken into three subcategories: type 0 transactions, type 1 transactions that target the secondary bus, and type 1 transactions that target a downstream bus other than the secondary bus.
PCI Express type 0 configuration register transactions always target the configuration space and are never passed on to the secondary interface.
Type 1 configuration register transactions that target a device on the secondary bus are converted to type 0 configuration register transactions on the PCI bus. Figure 8-1 shows the address phase of a type 0 configuration transaction on the PCI bus as defined by the PCI specification.
In addition, the bridge converts the destination ID device number to one of the AD[31:16] lines as the IDSEL signal. The implemented IDSEL signal mapping is shown in Table 8-6.
DEVICE NUMBER | AD[31:16] |
---|---|
00000 | 0000 0000 0000 0001 |
00001 | 0000 0000 0000 0010 |
00010 | 0000 0000 0000 0100 |
00011 | 0000 0000 0000 1000 |
00100 | 0000 0000 0001 0000 |
00101 | 0000 0000 0010 0000 |
00110 | 0000 0000 0100 0000 |
00111 | 0000 0000 1000 0000 |
01000 | 0000 0001 0000 0000 |
01001 | 0000 0010 0000 0000 |
01010 | 0000 0100 0000 0000 |
01011 | 0000 1000 0000 0000 |
01100 | 0001 0000 0000 0000 |
01101 | 0010 0000 0000 0000 |
01110 | 0100 0000 0000 0000 |
01111 | 1000 0000 0000 0000 |
1xxxx | 0000 0000 0000 0000 |
Type 1 configuration registers transactions that target a downstream bus other then the secondary bus are output on the PCI bus as type 1 PCI configuration transactions. Figure 8-2 shows the address phase of a type 1 configuration transaction on the PCI bus as defined by the PCI specification.