ZHCSS37J may 2009 – january 2021 XIO2001
PRODUCTION DATA
This read-only register provides a pointer into the PCI configuration header where the PCI power management block resides. Since the PCI power management registers begin at 40h, this register is hardwired to 40h.
PCI register offset: | 34h | |
Register type: | Read-only | |
Default value: | 40h |
BIT NUMBER | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET STATE | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |