SWCU191 February 2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA
#CC26_I2C_CC26_I2C_MAP1_TABLE_1 lists the memory-mapped registers for the I2C registers. All register offset addresses not listed in #CC26_I2C_CC26_I2C_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Complex bit access types are encoded to fit into small table cells. #CC26_I2C_CC26_I2C_MAP1_LEGEND shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
SOAR is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SOAR_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SOAR_TABLE.
Return to the Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OAR | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | 0h | Reserved |
6-0 | OAR | R/W | 0h | HASH(0x220a2e8) |
SSTAT is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SSTAT_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SSTAT_TABLE.
Return to the Summary Table.
Slave Status
Note: This register shares address with SCTL, meaning that this register functions as a control register when written, and a status register when read.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FBR | TREQ | RREQ | ||||
R-0h | R-0h | R-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | FBR | R | 0h | First byte received 0: The first byte has not been received. 1: The first byte following the slave's own address has been received. This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the SDR register. Note: This bit is not used for slave transmit operations. |
1 | TREQ | R | 0h | HASH(0x22256c8) |
0 | RREQ | R | 0h | HASH(0x2063970) |
SCTL is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SCTL_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SCTL_TABLE.
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Slave Control
Note: This register shares address with SSTAT, meaning that this register functions as a control register when written, and a status register when read.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DA | ||||||||||||||
W-0h | W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | 0h | Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. |
0 | DA | W | 0h | HASH(0x20acd50) |
SDR is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SDR_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SDR_TABLE.
Return to the Summary Table.
Slave Data
This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | DATA | R/W | 0h | Data for transfer This field contains the data for transfer during a slave receive or transmit operation. When written the register data is used as transmit data. When read, this register returns the last data received. Data is stored until next update, either by a system write for transmit or by an external master for receive. |
SIMR is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SIMR_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SIMR_TABLE.
Return to the Summary Table.
Slave Interrupt Mask
This register controls whether a raw interrupt is promoted to a controller interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STOPIM | STARTIM | DATAIM | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | STOPIM | R/W | 0h | Stop condition interrupt mask 0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt controller. 1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt controller. 0h = Disable Interrupt 1h = Enable Interrupt |
1 | STARTIM | R/W | 0h | Start condition interrupt mask 0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt controller. 1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt controller. 0h = Disable Interrupt 1h = Enable Interrupt |
0 | DATAIM | R/W | 0h | Data interrupt mask 0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt controller. 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt controller. |
SRIS is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SRIS_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SRIS_TABLE.
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Slave Raw Interrupt Status
This register shows the unmasked interrupt status.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STOPRIS | STARTRIS | DATARIS | ||||
R-0h | R-0h | R-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | STOPRIS | R | 0h | Stop condition raw interrupt status 0: No interrupt 1: A Stop condition interrupt is pending. This bit is cleared by writing a 1 to SICR.STOPIC. |
1 | STARTRIS | R | 0h | Start condition raw interrupt status 0: No interrupt 1: A Start condition interrupt is pending. This bit is cleared by writing a 1 to SICR.STARTIC. |
0 | DATARIS | R | 0h | Data raw interrupt status 0: No interrupt 1: A data received or data requested interrupt is pending. This bit is cleared by writing a 1 to the SICR.DATAIC. |
SMIS is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SMIS_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SMIS_TABLE.
Return to the Summary Table.
Slave Masked Interrupt Status
This register show which interrupt is active (based on result from SRIS and SIMR).
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STOPMIS | STARTMIS | DATAMIS | ||||
R-0h | R-0h | R-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | STOPMIS | R | 0h | Stop condition masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked Stop condition interrupt is pending. This bit is cleared by writing a 1 to the SICR.STOPIC. |
1 | STARTMIS | R | 0h | Start condition masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked Start condition interrupt is pending. This bit is cleared by writing a 1 to the SICR.STARTIC. |
0 | DATAMIS | R | 0h | Data masked interrupt status 0: An interrupt has not occurred or is masked/disabled. 1: An unmasked data received or data requested interrupt is pending. This bit is cleared by writing a 1 to the SICR.DATAIC. |
SICR is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SICR_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_SICR_TABLE.
Return to the Summary Table.
Slave Interrupt Clear
This register clears the raw interrupt SRIS.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STOPIC | STARTIC | DATAIC | ||||
R-0h | W-0h | W-0h | W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | STOPIC | W | 0h | Stop condition interrupt clear Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS. |
1 | STARTIC | W | 0h | Start condition interrupt clear Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS. |
0 | DATAIC | W | 0h | Data interrupt clear Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS. |
MSA is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MSA_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MSA_TABLE.
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Master Salve Address
This register contains seven address bits of the slave to be accessed by the master (a6-a0), and an RS bit determining if the next operation is a receive or transmit.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SA | RS | |||||||||||||
R-0h | R/W-0h | R/W-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-1 | SA | R/W | 0h | HASH(0x21b15d0) |
0 | RS | R/W | 0h | Receive or Send This bit-field specifies if the next operation is a receive (high) or a transmit/send (low) from the addressed slave SA. 0h = Transmit/send data to slave 1h = Receive data from slave |
MSTAT is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MSTAT_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MSTAT_TABLE.
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Master Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BUSBSY | IDLE | ARBLST | DATACK_N | ADRACK_N | ERR | BUSY |
R-0h | R-0h | R-1h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | 0h | Reserved |
6 | BUSBSY | R | 0h | HASH(0x201d238) |
5 | IDLE | R | 1h | HASH(0x2108c10) |
4 | ARBLST | R | 0h | HASH(0x2203910) |
3 | DATACK_N | R | 0h | Data Was Not Acknowledge 0: The transmitted data was acknowledged. 1: The transmitted data was not acknowledged. |
2 | ADRACK_N | R | 0h | Address Was Not Acknowledge 0: The transmitted address was acknowledged. 1: The transmitted address was not acknowledged. |
1 | ERR | R | 0h | Error 0: No error was detected on the last operation. 1: An error occurred on the last operation. |
0 | BUSY | R | 0h | HASH(0x1f67308) |
MCTRL is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MCTRL_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MCTRL_TABLE.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ACK | STOP | START | RUN | |||
R-0h | W-0h | W-0h | W-0h | W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | ACK | W | 0h | HASH(0x202c3d0)
0h = Disable acknowledge 1h = Enable acknowledge |
2 | STOP | W | 0h | This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. 0: The controller does not generate the Stop condition. 1: The controller generates the Stop condition. 0h = Disable STOP 1h = Enable STOP |
1 | START | W | 0h | This bit-field generates the Start or Repeated Start condition. 0: The controller does not generate the Start condition. 1: The controller generates the Start condition. 0h = Disable START 1h = Enable START |
0 | RUN | W | 0h | HASH(0x2231df8)
0h = Disable Master 1h = Enable Master |
MDR is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MDR_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MDR_TABLE.
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Master Data
This register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | DATA | R/W | 0h | When Read: Last RX Data is returned When Written: Data is transferred during TX transaction |
MTPR is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MTPR_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MTPR_TABLE.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TPR_7 | TPR | ||||||
R/W-0h | R/W-1h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7 | TPR_7 | R/W | 0h | Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. |
6-0 | TPR | R/W | 1h | HASH(0x224aab0) |
MIMR is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MIMR_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MIMR_TABLE.
Return to the Summary Table.
Master Interrupt Mask
This register controls whether a raw interrupt is promoted to a controller interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IM | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | IM | R/W | 0h | Interrupt mask 0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt controller. 1: The master interrupt is sent to the interrupt controller when the MRIS.RIS is set. 0h = Disable Interrupt 1h = Enable Interrupt |
MRIS is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MRIS_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MRIS_TABLE.
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Master Raw Interrupt Status
This register show the unmasked interrupt status.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RIS | ||||||||||||||
R-0h | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RIS | R | 0h | Raw interrupt status 0: No interrupt 1: A master interrupt is pending. This bit is cleared by writing 1 to the MICR.IC bit . |
MMIS is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MMIS_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MMIS_TABLE.
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Master Masked Interrupt Status
This register show which interrupt is active (based on result from MRIS and MIMR).
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MIS | ||||||||||||||
R-0h | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | MIS | R | 0h | Masked interrupt status 0: An interrupt has not occurred or is masked. 1: A master interrupt is pending. This bit is cleared by writing 1 to the MICR.IC bit . |
MICR is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MICR_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MICR_TABLE.
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Master Interrupt Clear
This register clears the raw and masked interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IC | ||||||||||||||
R-0h | W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | IC | W | 0h | Interrupt clear Writing 1 to this bit clears MRIS.RIS and MMIS.MIS . Reading this register returns no meaningful data. |
MCR is shown in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MCR_FIGURE and described in #CC26_I2C_CC26_I2C_MAP1_CC26_I2C_ALL_MCR_TABLE.
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Master Configuration
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SFE | MFE | RESERVED | LPBK | |||
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | SFE | R/W | 0h | HASH(0x254bf38)
0h = Slave mode is disabled. 1h = Slave mode is enabled. |
4 | MFE | R/W | 0h | HASH(0x254a130)
0h = Master mode is disabled. 1h = Master mode is enabled. |
3-1 | RESERVED | R | 0h | Reserved |
0 | LPBK | R/W | 0h | HASH(0x2546730)
0h = Disable Test Mode 1h = Enable Test Mode |