SWCU191 February 2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA
To maintain DMA operation, software must provide new memory block start addresses each time a memory block is finished.
When a block is finished, the following occurs:
To handle this operation, software must either poll if the I2S:AIFINPTRNEXT and (or) I2S:AIFOUTPTRNEXT registers are zero, or use the I2S:IRQFLAGS.AIF_DMA_IN and (or) I2S:IRQFLAGS.AIF_DMA_OUT interrupt requests.
Software must write the new memory block start addresses to I2S:AIFINPTRNEXT and (or) I2S:AIFOUTPTRNEXT before the running block finishes. If the running block finishes while I2S:AIFINPTRNEXT and (or) I2S:AIFOUTPTRNEXT are zero, the affected DMA channels stop and I2S:IRQFLAGS.PTR_ERR is set.