11.7.2 PASS PLL Control Registers
The PASS PLL, which is used to drive the network coprocessor, does not use a PLL controller. PASS PLL can be controlled using the PAPLLCTL0 and PAPLLCTL1 registers in the Bootcfg module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For suggested configuration values, see Section 10.1.4. See Section 10.2.3.4 for the address location of the registers and locking and unlocking sequences for accessing these registers. These registers are reset on POR only.
The PASS PLL control registers are shown in Figure 11-30 and Figure 11-31 and described in Table 11-33 and Table 11-34.
Figure 11-30 PASS PLL Control Register 0 (PASSPLLCTL0)
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
BWADJ[7:0] |
BYPASS |
CLKOD |
PLLM |
PLLD |
RW-0000 1001 |
RW-1 |
RW-0001 |
RW-0000000010011 |
RW-000000 |
LEGEND: RW = Read/Write; -n = value after reset |
Table 11-33 PASS PLL Control Register 0 Field Descriptions (PASSPLLCTL0)
Bit |
Field |
Description |
31-24 |
BWADJ[7:0] |
BWADJ[11:8] and BWADJ[7:0] are in PASSPLLCTL0 and PASSPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1. |
23 |
BYPASS |
PLL bypass mode:
- 0 = PLL is not in BYPASS mode
- 1 = PLL is in BYPASS mode
|
22-19 |
CLKOD |
A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values from 2 to 16. CLKOD field is loaded with output divide value minus 1 |
18-6 |
PLLM |
A 13-bit field that selects the values for the multiplication factor (see note below). PLLM field is loaded with the multiply factor minus 1. |
5-0 |
PLLD |
A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value minus 1. |
Figure 11-31 PASS PLL Control Register 1 (PASSPLLCTL1)
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Reserved |
PLLRST |
PAPLL |
Reserved |
ENSAT |
Reserved |
BWADJ[11:8] |
RW-00000000000000000 |
RW-0 |
RW-0 |
RW-0000000 |
RW-0 |
R-00 |
RW-0000 |
Legend: RW = Read/Write; – n = value after reset |
Table 11-34 PASS PLL Control Register 1 Field Descriptions (PASSPLLCTL1)
Bit |
Field |
Description |
31-15 |
Reserved |
Reserved |
14 |
PLLRST |
PLL Reset bit
- 0 = PLL Reset is released
- 1 = PLL Reset is asserted
|
13 |
PAPLL |
- 0 = Not supported
- 1 = PAPLL
|
12-7 |
Reserved |
Reserved |
6 |
ENSAT |
Needs to be set to 1 for proper PLL operation |
5-4 |
Reserved |
Reserved |
3-0 |
BWADJ[11:8] |
BWADJ[11:8] and BWADJ[7:0] are in PASSPLLCTL0 and PASSPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1. |