11.6.1 DDR3A PLL and DDR3B PLL Control Registers
The DDR3A PLL and DDR3B PLL, which are used to drive the DDR3A PHY and DDR3B PHY for the EMIF, do not use a PLL controller. DDR3A PLL and DDR3B PLL can be controlled using the DDR3APLLCTL0/DDR3BPLLCTL0 and DDR3APLLCTL1/DDR3BPLLCTL1 registers in the Bootcfg module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For suggested configurable values, see Section 10.1.4. See Section 10.2.3.4 for the address location of the registers and locking and unlocking sequences for accessing the registers. These registers are reset on POR only.
The DDR3A PLL and DDR3B PLL control registers are shown in Figure 11-26 and Figure 11-27 and described in Table 11-30 and Table 11-31.
Figure 11-26 DDR3A PLL and DDR3B PLL Control Register 0 (DDR3APLLCTL0/DDR3BPLLCTL0)
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
BWADJ[7:0] |
BYPASS |
CLKOD |
PLLM |
PLLD |
RW-0000 1001 |
RW-1 |
RW-0001 |
RW-0000000010011 |
RW-000000 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 11-30 DDR3A PLL and DDR3B PLL Control Register 0 Field Descriptions
Bit |
Field |
Description |
31-24 |
BWADJ[7:0] |
BWADJ[11:8] and BWADJ[7:0] are in DDR3PLLCTL0 and DDR3PLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1. |
23 |
BYPASS |
PLL bypass mode:
- 0 = PLL is not in BYPASS mode
- 1 = PLL is in BYPASS mode
|
22-19 |
CLKOD |
A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values from 2 to 16. CLKOD field is loaded with output divide value minus 1 |
18-6 |
PLLM |
A 13-bit field that selects the values for the PLL multiplication factor. PLLM field is loaded with the multiply factor minus 1 |
5-0 |
PLLD |
A 6-bit field that selects the values for the reference (input) divider. PLLD field is loaded with reference divide value minus 1 |
Figure 11-27 DDR3A PLL and DDR3B PLL Control Register 1 (DDR3APLLCTL0/DDR3BPLLCTL1)
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Reserved |
PLLRST |
Reserved |
ENSAT |
Reserved |
BWADJ[11:8] |
RW-00000000000000000 |
RW-0 |
RW-0000000 |
RW-0 |
R-00 |
RW-0000 |
Legend: RW = Read/Write; – n = value after reset |
Table 11-31 DDR3A PLL and DDR3B PLL Control Register 1 Field Descriptions
Bit |
Field |
Description |
31-15 |
Reserved |
Reserved |
14 |
PLLRST |
PLL Reset bit
- 0 = PLL Reset is released
- 1 = PLL Reset is asserted
|
13-7 |
Reserved |
Reserved |
6 |
ENSAT |
Needs to be set to 1 for proper PLL operation |
5-4 |
Reserved |
Reserved |
3-0 |
BWADJ[11:8] |
BWADJ[11:8] and BWADJ[7:0] are in DDR3PLLCTL0 and DDR3PLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1. |