ZHCSBT2G November 2012 – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14
PRODUCTION DATA.
The ARM PLL uses two chip-level registers (ARMPLLCTL0 and ARMPLLCTL1) without using the Main PLL controller like other PLLs for its configuration. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. These registers reset only on a POR reset.
For valid configurable values of the ARMPLLCTL registers, see Section 10.1.4. See Section 10.2.3.4 for the address location of the KICK registers and their locking and unlocking sequences.
See Figure 11-19 and Table 11-27 for ARMPLLCTL0 details and Figure 11-20 and Table 11-28 for ARMPLLCTL1 details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BWADJ[7:0] | BYPASS | CLKOD | PLLM | PLLD | |||||||||||||||||||||||||||
RW-0000 1001 | RW-1 | RW-0001 | RW-0000000010011 | RW-000000 |
Legend: RW = Read/Write; – n = value after reset |
Bit | Field | Description |
---|---|---|
31-24 | BWADJ[7:0] | BWADJ[11:8] and BWADJ[7:0] are in ARMPLLCTL0 and ARMPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1. |
23 | BYPASS | PLL bypass mode:
|
22-19 | CLKOD | A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values from 2 to 16. CLKOD field is loaded with output divide value minus 1 |
18-6 | PLLM | A 13-bit field that selects the values for the multiplication factor |
5-0 | PLLD | A 6-bit field that selects the values for the reference divider |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | PLLRST | Reserved | ENSAT | Reserved | BWADJ[11:8] | ||||||||||||||||||||||||||
RW-00000000000000000 | RW-0 | RW-0000000 | RW-0 | R-00 | RW-0000 |
Legend: RW = Read/Write; – n = value after reset |
Bit | Field | Description |
---|---|---|
31-15 | Reserved | Reserved |
14 | PLLRST | PLL Reset bit
|
13-7 | Reserved | Reserved |
6 | ENSAT | Needs to be set to 1 for proper PLL operation |
5-4 | Reserved | Reserved |
3-0 | BWADJ[11:8] | BWADJ[11:8] and BWADJ[7:0] are in ARMPLLCTL0 and ARMPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1. |
See the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide for the recommended programming sequence. Output Divide ratio and Bypass enable/disable of the ARM PLL is also controlled by the SECCTL register in the PLL Controller. See Section 11.5.2.1 for more details.