ZHCSBT2G November 2012 – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14
PRODUCTION DATA.
Software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 through RSTMUX11 (66AK2H12) or RSTMUX0 through RSTMUX3 (66AK2H06) for each of the C66x CorePacs and RSTMUX8 and RSTMUX9 (66AK2H06) for the ARM CorePac on the device. These registers are in Bootcfg memory space. The Reset Mux register is shown in Figure 10-29 and described in Table 10-48.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved | |||||||||||||||
R-0000 0000 0000 0000 0000 00 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | EVTSTATCLR | Rsvd | DELAY | EVTSTAT | OMODE | LOCK | |||||||||
R-0000 0000 0000 0000 0000 00 | RC-0 | R-0 | RW-100 | R-0 | RW-000 | RW-0 |
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear |
Bit | Field | Description |
---|---|---|
31-10 | Reserved | Reserved |
9 | EVTSTATCLR | Clear event status
|
8 | Reserved | Reserved |
7-5 | DELAY | Delay cycles between NMI and local reset
|
4 | EVTSTAT | Event status
|
3-1 | OMODE | Timer event operation mode
|
0 | LOCK | Lock register fields
|