SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
In cases when the input data arrives at the MISO pin with additional delay due to runtime conditions or path delays, on the following input data sampling stage, the previous data would be sampled at the sampling clock edge. To compensate for this, sampling of input data in master mode can be delayed using CLKCTL.DSAMPLE bits. The delayed sampling is only available in master mode. The delay can be adjusted in steps of undivided SPI input clocks programmed within SPI:CLKCTL.DSAMPLE. The programmed value of DSAMPLE must be within 0 to SCR+1. Typically, values of 1 and 2 are sufficient even for the highest supported SPI frequencies.