SWCU194 March   2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1 Target Applications
    2. 1.2 Overview
    3. 1.3 Functional Overview
      1. 1.3.1  ArmCortex-M33 with FPU
        1. 1.3.1.1 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block (SCB)
      2. 1.3.2  On-Chip Memory
        1. 1.3.2.1 SRAM
        2. 1.3.2.2 Flash Memory
        3. 1.3.2.3 ROM
      3. 1.3.3  Radio
      4. 1.3.4  Security Core
      5. 1.3.5  Runtime Security
      6. 1.3.6  General-Purpose Timers
        1. 1.3.6.1 Watchdog Timer
        2. 1.3.6.2 Always-On Domain
      7. 1.3.7  Direct Memory Access
      8. 1.3.8  System Control and Clock
      9. 1.3.9  Serial Communication Peripherals
        1. 1.3.9.1 UART
        2. 1.3.9.2 I2C
        3. 1.3.9.3 I2S
        4. 1.3.9.4 SPI
      10. 1.3.10 Programmable I/Os
      11. 1.3.11 Sensor Controller
      12. 1.3.12 Random Number Generator
      13. 1.3.13 cJTAG and JTAG
      14. 1.3.14 Power Supply System
        1. 1.3.14.1 Supply System
          1. 1.3.14.1.1 VDDS
          2. 1.3.14.1.2 VDDR
          3. 1.3.14.1.3 Digital Core Supply
          4. 1.3.14.1.4 Other Internal Supplies
        2. 1.3.14.2 DC/DC Converter
  3. 2  Arm Cortex-M33 Processor with FPU
    1. 2.1 Arm Cortex-M33 Processor Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Integrated Configurable Debug
      2. 2.3.2 Trace Port Interface Unit
      3. 2.3.3 Arm Cortex-M33 System Peripheral Details
        1. 2.3.3.1 Floating Point Unit (FPU)
        2. 2.3.3.2 Memory Protection Unit (MPU)
        3. 2.3.3.3 System Timer (SysTick)
        4. 2.3.3.4 Nested Vectored Interrupt Controller (NVIC)
        5. 2.3.3.5 System Control Block (SCB)
        6. 2.3.3.6 System Control Space (SCS)
        7. 2.3.3.7 Security Attribution Unit (SAU)
    4. 2.4 Programming Model
      1. 2.4.1 Modes of Operation and Execution
        1. 2.4.1.1 Security States
        2. 2.4.1.2 Operating Modes
        3. 2.4.1.3 Operating States
        4. 2.4.1.4 Privileged Access and Unprivileged User Access
      2. 2.4.2 Instruction Set Summary
      3. 2.4.3 Memory Model
        1. 2.4.3.1 Private Peripheral Bus
        2. 2.4.3.2 Unaligned Accesses
      4. 2.4.4 Exclusive Monitor
      5. 2.4.5 Processor Core Registers Summary
      6. 2.4.6 Exceptions
        1. 2.4.6.1 Exception Handling and Prioritization
      7. 2.4.7 Runtime Security
        1. 2.4.7.1 IDAU Watermark Registers
        2. 2.4.7.2 Secure Memory Range for Registers
        3. 2.4.7.3 Bus Topology
        4. 2.4.7.4 Intended Use
    5. 2.5 Arm® Cortex®-M33 Registers
      1. 2.5.1  CPU_ITM Registers
      2. 2.5.2  CPU_DWT Registers
      3. 2.5.3  CPU_SYSTICK Registers
      4. 2.5.4  CPU_NVIC Registers
      5. 2.5.5  CPU_SCS Registers
      6. 2.5.6  CPU_MPU Registers
      7. 2.5.7  CPU_SAU Registers
      8. 2.5.8  CPU_DCB Registers
      9. 2.5.9  CPU_SIG Registers
      10. 2.5.10 CPU_FPU Registers
      11. 2.5.11 CPU_TPIU Registers
  4. 3 Memory Map
    1. 3.1 Introduction
    2. 3.2 Memory Map (Secure and Non-secure)
      1. 3.2.1 Bus Security
    3. 3.3 Memory Map
  5. 4  Arm Cortex-M33 Peripherals
    1. 4.1 Arm Cortex-M33 Peripherals Introduction
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation and Hard Faults
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Fabric
      1. 5.4.1 Introduction
      2. 5.4.2 Event Fabric Overview
        1. 5.4.2.1 Registers
    5. 5.5 AON Event Fabric
      1. 5.5.1 Common Input Event List
      2. 5.5.2 Event Subscribers
        1. 5.5.2.1 AON Power Management Controller (AON_PMCTL)
        2. 5.5.2.2 Real-Time Clock
        3. 5.5.2.3 MCU Event Fabric
    6. 5.6 MCU Event Fabric
      1. 5.6.1 Common Input Event List
      2. 5.6.2 Event Subscribers
        1. 5.6.2.1 System CPU
        2. 5.6.2.2 NMI
        3. 5.6.2.3 Freeze
    7. 5.7 AON Events
    8. 5.8 Interrupts and Events Registers
      1. 5.8.1 AON_EVENT Registers
      2. 5.8.2 EVENT Registers
  7. 6 JTAG Interface
    1. 6.1 Overview
    2. 6.2 cJTAG
    3. 6.3 ICEPick
      1. 6.3.1 Secondary TAPs
        1. 6.3.1.1 Slave DAP (CPU DAP)
      2. 6.3.2 ICEPick Registers
        1. 6.3.2.1 IR Instructions
        2. 6.3.2.2 Data Shift Register
        3. 6.3.2.3 Instruction Register
        4. 6.3.2.4 Bypass Register
        5. 6.3.2.5 Device Identification Register
        6. 6.3.2.6 User Code Register
        7. 6.3.2.7 ICEPick Identification Register
        8. 6.3.2.8 Connect Register
      3. 6.3.3 Router Scan Chain
      4. 6.3.4 TAP Routing Registers
        1. 6.3.4.1 ICEPick Control Block
          1. 6.3.4.1.1 All0s Register
          2. 6.3.4.1.2 ICEPick Control Register
          3. 6.3.4.1.3 Linking Mode Register
        2. 6.3.4.2 Test TAP Linking Block
          1. 6.3.4.2.1 Secondary Test TAP Register
        3. 6.3.4.3 Debug TAP Linking Block
          1. 6.3.4.3.1 Secondary Debug TAP Register
    4. 6.4 ICEMelter
    5. 6.5 Serial Wire Viewer (SWV)
    6. 6.6 Halt In Boot (HIB)
    7. 6.7 Debug and Shutdown
    8. 6.8 Boundary Scan
  8. 7 Power, Reset, and Clock Management (PRCM)
    1. 7.1 Introduction
    2. 7.2 System CPU Mode
    3. 7.3 Supply System
      1. 7.3.1 Internal DC/DC Converter and Global LDO
      2. 7.3.2 External Regulator Mode
    4. 7.4 Digital Power Partitioning
      1. 7.4.1 MCU_VD
        1. 7.4.1.1 MCU_VD Power Domains
      2. 7.4.2 AON_VD
        1. 7.4.2.1 AON_VD Power Domains
    5. 7.5 Clock Management
      1. 7.5.1 System Clocks
        1. 7.5.1.1 Controlling the Oscillators
      2. 7.5.2 Clocks in MCU_VD
        1. 7.5.2.1 Clock Gating
        2. 7.5.2.2 Scaler to GPTs
        3. 7.5.2.3 Scaler to WDT
      3. 7.5.3 Clocks in AON_VD
    6. 7.6 Power Modes
      1. 7.6.1 Start-Up State
      2. 7.6.2 Active Mode
      3. 7.6.3 Idle Mode
      4. 7.6.4 Standby Mode
      5. 7.6.5 Shutdown Mode
    7. 7.7 Reset
      1. 7.7.1 System Resets
        1. 7.7.1.1 Clock Loss Detection
        2. 7.7.1.2 Software-Initiated System Reset
        3. 7.7.1.3 Warm Reset Converted to System Reset
      2. 7.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 7.7.3 Reset of AON_VD
      4. 7.7.4 Always On Watchdog Timer (AON_WDT)
    8. 7.8 PRCM Registers
      1. 7.8.1 PRCM Registers
      2. 7.8.2 AON_PMCTL Registers
      3. 7.8.3 DDI_0_OSC Registers
  9. 8 Versatile Instruction Memory System (VIMS)
    1. 8.1 Introduction
    2. 8.2 VIMS Configurations
      1. 8.2.1 VIMS Modes
        1. 8.2.1.1 GPRAM Mode
        2. 8.2.1.2 Off Mode
        3. 8.2.1.3 Cache Mode
      2. 8.2.2 VIMS FLASH Line Buffers
      3. 8.2.3 VIMS Arbitration
      4. 8.2.4 VIMS Cache TAG Prefetch
    3. 8.3 VIMS Software Remarks
      1. 8.3.1 FLASH Program or Update
      2. 8.3.2 VIMS Retention
        1. 8.3.2.1 Mode 1
        2. 8.3.2.2 Mode 2
        3. 8.3.2.3 Mode 3
    4. 8.4 FLASH
      1. 8.4.1 Flash Memory Protection
      2. 8.4.2 Flash Memory Programming
    5. 8.5 ROM Functions
    6. 8.6 VIMS Registers
      1. 8.6.1 FLASH Registers
      2. 8.6.2 VIMS Registers
      3. 8.6.3 NVMNW Registers
  10. 9 SRAM
    1. 9.1 Introduction
    2. 9.2 Main Features
    3. 9.3 Data Retention
    4. 9.4 Parity and SRAM Error Support
      1. 9.4.1 SRAM Extension Mode
    5. 9.5 SRAM Auto-Initialization
    6. 9.6 Parity Debug Behavior
    7. 9.7 SRAM Registers
      1. 9.7.1 SRAM_MMR Registers
      2. 9.7.2 SRAM Registers
  11. 10Bootloader
    1. 10.1 Bootloader Functionality
      1. 10.1.1 Bootloader Disabling
      2. 10.1.2 Bootloader Backdoor
    2. 10.2 Bootloader Interfaces
      1. 10.2.1 Packet Handling
        1. 10.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 10.2.2 Transport Layer
        1. 10.2.2.1 UART Transport
          1. 10.2.2.1.1 UART Baud Rate Automatic Detection
        2. 10.2.2.2 SPI Transport
      3. 10.2.3 Serial Bus Commands
        1. 10.2.3.1  COMMAND_PING
        2. 10.2.3.2  COMMAND_DOWNLOAD
        3. 10.2.3.3  COMMAND_GET_STATUS
        4. 10.2.3.4  COMMAND_SEND_DATA
        5. 10.2.3.5  COMMAND_RESET
        6. 10.2.3.6  COMMAND_SECTOR_ERASE
        7. 10.2.3.7  COMMAND_CRC32
        8. 10.2.3.8  COMMAND_GET_CHIP_ID
        9. 10.2.3.9  COMMAND_MEMORY_READ
        10. 10.2.3.10 COMMAND_MEMORY_WRITE
        11. 10.2.3.11 COMMAND_BANK_ERASE
        12. 10.2.3.12 COMMAND_SET_CCFG
        13. 10.2.3.13 COMMAND_DOWNLOAD_CRC
  12. 11Device Configuration
    1. 11.1 Customer Configuration (CCFG)
      1. 11.1.1 CCFG Recommendations for Final Production
    2. 11.2 CCFG Registers
    3. 11.3 Factory Configuration (FCFG)
    4. 11.4 FCFG1 Registers
  13. 12AES and Hash Cryptoprocessor
    1. 12.1 Introduction
    2. 12.2 Functional Description
      1. 12.2.1 Debug Capabilities
      2. 12.2.2 Exception Handling
      3. 12.2.3 Power Management and Sleep Modes
      4. 12.2.4 Interrupts
      5. 12.2.5 Module Memory Map
      6. 12.2.6 Master Control and Select Module
        1. 12.2.6.1 Algorithm Select Register
          1. 12.2.6.1.1 Algorithm Select
        2. 12.2.6.2 Master PROT Enable
          1. 12.2.6.2.1 Master PROT-Privileged Access-Enable
        3. 12.2.6.3 Software Reset
      7. 12.2.7 AES Engine
        1. 12.2.7.1 Second and Third Key Registers (Internal, but Clearable)
        2. 12.2.7.2 AES Initialization Vector (IV) Registers
        3. 12.2.7.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 12.2.7.4 AES Data Input and Output Registers
        5. 12.2.7.5 TAG Registers
      8. 12.2.8 Key Area Registers
        1. 12.2.8.1 Key Store Write Area Register
        2. 12.2.8.2 Key Store Written Area Register
        3. 12.2.8.3 Key Store Size Register
        4. 12.2.8.4 Key Store Read Area Register
      9. 12.2.9 Hash Engine
        1. 12.2.9.1 Hash I/O Buffer Control and Status Register, Mode, and Length Registers
        2. 12.2.9.2 Hash Data Input and Digest Registers
    3. 12.3 DMA Controller
      1. 12.3.1 Internal Operation
      2. 12.3.2 Supported DMA Operations
    4. 12.4 AES and Hash Cryptoprocessor Performance
      1. 12.4.1 Introduction
      2. 12.4.2 Performance for DMA-Based Operations
    5. 12.5 Programming Guidelines
      1. 12.5.1 One-Time Initialization After a Reset
      2. 12.5.2 DMAC and Master Control
        1. 12.5.2.1 Regular Use
        2. 12.5.2.2 Interrupting DMA Transfers
        3. 12.5.2.3 Interrupts, Hardware, and Software Synchronization
      3. 12.5.3 Hashing
        1. 12.5.3.1 Data Format and Byte Order
        2. 12.5.3.2 Basic Hash with Data From DMA
          1. 12.5.3.2.1 New Hash Session with Digest Read Through Slave
          2. 12.5.3.2.2 New Hash Session with Digest to External Memory
          3. 12.5.3.2.3 Resumed Hash Session
        3. 12.5.3.3 HMAC
          1. 12.5.3.3.1 Secure HMAC
        4. 12.5.3.4 Alternative Basic Hash Where Data Originates from Slave Interface
          1. 12.5.3.4.1 New Hash Session
          2. 12.5.3.4.2 Resumed Hash Session
      4. 12.5.4 Encryption and Decryption
        1. 12.5.4.1 Data Format and Byte Order
        2. 12.5.4.2 Key Store
          1. 12.5.4.2.1 Load Keys from External Memory
        3. 12.5.4.3 Basic AES Modes
          1. 12.5.4.3.1 AES-ECB
          2. 12.5.4.3.2 AES-CBC
          3. 12.5.4.3.3 AES-CTR
          4. 12.5.4.3.4 Programming Sequence with DMA Data
        4. 12.5.4.4 CBC-MAC
          1. 12.5.4.4.1 Programming Sequence for Regular CBC-MAC
          2. 12.5.4.4.2 Programming Sequence for Regular CBC-MAC with Continuation
          3. 12.5.4.4.3 Programming Sequence for CMAC CBC-MAC
          4. 12.5.4.4.4 Programming Sequence for CMAC CBC-MAC with Continuation
        5. 12.5.4.5 AES-CCM
          1. 12.5.4.5.1 Continued CCM Processing
          2. 12.5.4.5.2 Programming Sequence for AES-CCM
          3. 12.5.4.5.3 Programming Sequence for Continued AES-CCM in the AAD Phase
          4. 12.5.4.5.4 Programming Sequence for Continued AES-CCM in the Payload Phase
        6. 12.5.4.6 AES-GCM
          1. 12.5.4.6.1 Continued AES-GCM Processing
          2. 12.5.4.6.2 Programming Sequence for AES-GCM
          3. 12.5.4.6.3 Programming Sequence for Continued AES-GCM in the AAD Phase
          4. 12.5.4.6.4 Programming Sequence for Continued AES-GCM in the Payload Phase
      5. 12.5.5 Exceptions Handling
        1. 12.5.5.1 Soft Reset
        2. 12.5.5.2 External Port Errors
        3. 12.5.5.3 Key Store Errors
    6. 12.6 Conventions and Compliances
      1. 12.6.1 Conventions Used in This Manual
        1. 12.6.1.1 Terminology
        2. 12.6.1.2 Formulas and Nomenclature
      2. 12.6.2 Compliance
    7. 12.7 CRYPTO Registers
  14. 13PKA Engine
    1. 13.1 Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Module Architecture
      2. 13.2.2 PKA RAM
      3. 13.2.3 PKCP Operations
      4. 13.2.4 Sequencer Operations
        1. 13.2.4.1 Modular Exponentiation Operations
        2. 13.2.4.2 Modular Inversion Operation
        3. 13.2.4.3 ECC Operations
      5. 13.2.5 Operation Sequence
    3. 13.3 PKA Engine Performance
      1. 13.3.1 Basic Operations Performance
      2. 13.3.2 ExpMod Performance
      3. 13.3.3 Modular Inversion Performance
      4. 13.3.4 ECC Operation Performance
    4. 13.4 PKA Registers
  15. 14True Random Number Generator (TRNG)
    1. 14.1 Introduction
    2. 14.2 Block Diagram
    3. 14.3 TRNG Software Reset
    4. 14.4 Interrupt Requests
    5. 14.5 TRNG Operation Description
      1. 14.5.1 TRNG Shutdown
      2. 14.5.2 TRNG Alarms
      3. 14.5.3 TRNG Entropy
    6. 14.6 TRNG Low-Level Programming Guide
      1. 14.6.1 Initialization
        1. 14.6.1.1 Interfacing Modules
        2. 14.6.1.2 TRNG Main Sequence
        3. 14.6.1.3 TRNG Operating Modes
          1. 14.6.1.3.1 Polling Mode
          2. 14.6.1.3.2 Interrupt Mode
    7. 14.7 TRNG Registers
  16. 15I/O Controller (IOC)
    1. 15.1  Introduction
    2. 15.2  IOC Overview
    3. 15.3  I/O Mapping and Configuration
      1. 15.3.1 Basic I/O Mapping
      2. 15.3.2 Mapping AUXIOs to DIO Pins
      3. 15.3.3 Control External LNA/PA (Range Extender) with I/Os
      4. 15.3.4 Map the 32 kHz System Clock (SCLK_LF Clock) to DIO
    4. 15.4  Edge Detection on DIO Pins
      1. 15.4.1 Configure DIO as GPIO Input to Generate Interrupt on Edge Detect
    5. 15.5  Unused I/O Pins
    6. 15.6  GPIO
    7. 15.7  I/O Pin Capability
    8. 15.8  Peripheral PORT_IDs
    9. 15.9  I/O Pins
      1. 15.9.1 Input/Output Modes
        1. 15.9.1.1 Physical Pin
        2. 15.9.1.2 Pin Configuration
    10. 15.10 IOC Registers
      1. 15.10.1 AON_IOC Registers
      2. 15.10.2 GPIO Registers
      3. 15.10.3 IOC Registers
  17. 16Micro Direct Memory Access (µDMA)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1  Channel Assignments
      2. 16.3.2  Priority
      3. 16.3.3  Arbitration Size
      4. 16.3.4  Request Types
        1. 16.3.4.1 Single Request
        2. 16.3.4.2 Burst Request
      5. 16.3.5  Channel Configuration
      6. 16.3.6  Transfer Modes
        1. 16.3.6.1 Stop Mode
        2. 16.3.6.2 Basic Mode
        3. 16.3.6.3 Auto Mode
        4. 16.3.6.4 Ping-Pong Mode
        5. 16.3.6.5 Memory Scatter-Gather Mode
        6. 16.3.6.6 Peripheral Scatter-Gather Mode
      7. 16.3.7  Transfer Size and Increments
      8. 16.3.8  Peripheral Interface
      9. 16.3.9  Software Request
      10. 16.3.10 Interrupts and Errors
    4. 16.4 Initialization and Configuration
      1. 16.4.1 Module Initialization
      2. 16.4.2 Configuring a Memory-to-Memory Transfer
        1. 16.4.2.1 Configure the Channel Attributes
        2. 16.4.2.2 Configure the Channel Control Structure
        3. 16.4.2.3 Start the Transfer
    5. 16.5 UDMA Registers
  18. 17Timers
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 GPTM Reset Conditions
      2. 17.3.2 Timer Modes
        1. 17.3.2.1 One-Shot or Periodic Timer Mode
        2. 17.3.2.2 Input Edge-Count Mode
        3. 17.3.2.3 Input Edge-Time Mode
        4. 17.3.2.4 PWM Mode
        5. 17.3.2.5 Wait-for-Trigger Mode
      3. 17.3.3 Synchronizing GPT Blocks
      4. 17.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 17.4 Initialization and Configuration
      1. 17.4.1 One-Shot and Periodic Timer Modes
      2. 17.4.2 Input Edge-Count Mode
      3. 17.4.3 Input Edge-Timing Mode
      4. 17.4.4 PWM Mode
      5. 17.4.5 Producing DMA Trigger Events
    5. 17.5 GPT Registers
  19. 18Real-Time Clock (RTC)
    1. 18.1 Introduction
    2. 18.2 Functional Specifications
      1. 18.2.1 Functional Overview
      2. 18.2.2 Free-Running Counter
      3. 18.2.3 Channels
        1. 18.2.3.1 Capture and Compare
      4. 18.2.4 Events
    3. 18.3 RTC Register Information
      1. 18.3.1 Register Access
      2. 18.3.2 Entering Sleep and Wakeup From Sleep
      3. 18.3.3 AON_RTC:SYNC Register
    4. 18.4 RTC Registers
      1. 18.4.1 AON_RTC Registers
  20. 19Watchdog Timer (WDT)
    1. 19.1 Introduction
    2. 19.2 Functional Description
    3. 19.3 Initialization and Configuration
    4. 19.4 WDT Registers
  21. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 Analog I/O Digital I/O (AIODIO)
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 Semaphore (SMPH)
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPI Master (SPIM)
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 Comparator A (COMPA)
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 Comparator B (COMPB)
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference Digital-to-Analog Converter (DAC)
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 Current Source (ISRC)
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  22. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 AON_BATMON Registers
  23. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud Rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to µDMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
  24. 23Serial Peripheral Interface (SPI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
          1. 23.4.2.1.1 Repeated Transmit Operation
        2. 23.4.2.2 Receive FIFO
        3. 23.4.2.3 FIFO Flush
      3. 23.4.3 Interrupts
      4. 23.4.4 Data Format
      5. 23.4.5 Delayed Data Sampling
      6. 23.4.6 Frame Formats
        1. 23.4.6.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.6.2 Motorola SPI Frame Format
          1. 23.4.6.2.1 SPO Clock Polarity Bit
          2. 23.4.6.2.2 SPH Phase Control Bit
        3. 23.4.6.3 Motorola SPI Frame Format with SPO = 0 and SPH = 0
        4. 23.4.6.4 Motorola SPI Frame Format with SPO = 0 and SPH = 1
        5. 23.4.6.5 Motorola SPI Frame Format with SPO = 1 and SPH = 0
        6. 23.4.6.6 Motorola SPI Frame Format with SPO = 1 and SPH = 1
        7. 23.4.6.7 MICROWIRE Frame Format
    5. 23.5 μDMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SPI Registers
  25. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format with 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
  26. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
  27. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization with Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command with Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond with Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          19. 26.3.3.2.19 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry from Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries from Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® Low Energy
      1. 26.6.1 Bluetooth® Low Energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® Low Energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® Low Energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Non-connectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  28. 27Revision History

15.10.3 IOC Registers

Table 15-40 lists the memory-mapped registers for the IOC registers. All register offset addresses not listed in Table 15-40 should be considered as reserved locations and the register contents should not be modified.

Table 15-40 IOC Registers
OffsetAcronymRegister NameSection
0hIOCFG0Configuration of DIO0Section 15.10.3.1
4hIOCFG1Configuration of DIO1Section 15.10.3.2
8hIOCFG2Configuration of DIO2Section 15.10.3.3
ChIOCFG3Configuration of DIO3Section 15.10.3.4
10hIOCFG4Configuration of DIO4Section 15.10.3.5
14hIOCFG5Configuration of DIO5Section 15.10.3.6
18hIOCFG6Configuration of DIO6Section 15.10.3.7
1ChIOCFG7Configuration of DIO7Section 15.10.3.8
20hIOCFG8Configuration of DIO8Section 15.10.3.9
24hIOCFG9Configuration of DIO9Section 15.10.3.10
28hIOCFG10Configuration of DIO10Section 15.10.3.11
2ChIOCFG11Configuration of DIO11Section 15.10.3.12
30hIOCFG12Configuration of DIO12Section 15.10.3.13
34hIOCFG13Configuration of DIO13Section 15.10.3.14
38hIOCFG14Configuration of DIO14Section 15.10.3.15
3ChIOCFG15Configuration of DIO15Section 15.10.3.16
40hIOCFG16Configuration of DIO16Section 15.10.3.17
44hIOCFG17Configuration of DIO17Section 15.10.3.18
48hIOCFG18Configuration of DIO18Section 15.10.3.19
4ChIOCFG19Configuration of DIO19Section 15.10.3.20
50hIOCFG20Configuration of DIO20Section 15.10.3.21
54hIOCFG21Configuration of DIO21Section 15.10.3.22
58hIOCFG22Configuration of DIO22Section 15.10.3.23
5ChIOCFG23Configuration of DIO23Section 15.10.3.24
60hIOCFG24Configuration of DIO24Section 15.10.3.25
64hIOCFG25Configuration of DIO25Section 15.10.3.26
68hIOCFG26Configuration of DIO26Section 15.10.3.27
6ChIOCFG27Configuration of DIO27Section 15.10.3.28
70hIOCFG28Configuration of DIO28Section 15.10.3.29
74hIOCFG29Configuration of DIO29Section 15.10.3.30
78hIOCFG30Configuration of DIO30Section 15.10.3.31
7ChIOCFG31Configuration of DIO31Section 15.10.3.32
80hIOCFG32Configuration of DIO32Section 15.10.3.33
84hIOCFG33Configuration of DIO33Section 15.10.3.34
88hIOCFG34Configuration of DIO34Section 15.10.3.35
8ChIOCFG35Configuration of DIO35Section 15.10.3.36
90hIOCFG36Configuration of DIO36Section 15.10.3.37
94hIOCFG37Configuration of DIO37Section 15.10.3.38
98hIOCFG38Configuration of DIO38Section 15.10.3.39
9ChIOCFG39Configuration of DIO39Section 15.10.3.40
A0hIOCFG40Configuration of DIO40Section 15.10.3.41
A4hIOCFG41Configuration of DIO41Section 15.10.3.42
A8hIOCFG42Configuration of DIO42Section 15.10.3.43
AChIOCFG43Configuration of DIO43Section 15.10.3.44
B0hIOCFG44Configuration of DIO44Section 15.10.3.45
B4hIOCFG45Configuration of DIO45Section 15.10.3.46
B8hIOCFG46Configuration of DIO46Section 15.10.3.47
BChIOCFG47Configuration of DIO47Section 15.10.3.48

Complex bit access types are encoded to fit into small table cells. Table 15-41 shows the codes that are used for access types in this section.

Table 15-41 IOC Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

15.10.3.1 IOCFG0 Register (Offset = 0h) [Reset = 0000C000h]

IOCFG0 is shown in Table 15-42.

Return to the Summary Table.

Configuration of DIO0

Table 15-42 IOCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / outut
7h = OPENSRC_INV : Open Source
Inverted input/output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO0
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.2 IOCFG1 Register (Offset = 4h) [Reset = 0000C000h]

IOCFG1 is shown in Table 15-43.

Return to the Summary Table.

Configuration of DIO1

Table 15-43 IOCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO1
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.3 IOCFG2 Register (Offset = 8h) [Reset = 0000C000h]

IOCFG2 is shown in Table 15-44.

Return to the Summary Table.

Configuration of DIO2

Table 15-44 IOCFG2 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO2
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.4 IOCFG3 Register (Offset = Ch) [Reset = 0000C000h]

IOCFG3 is shown in Table 15-45.

Return to the Summary Table.

Configuration of DIO3

Table 15-45 IOCFG3 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO3
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.5 IOCFG4 Register (Offset = 10h) [Reset = 0000C000h]

IOCFG4 is shown in Table 15-46.

Return to the Summary Table.

Configuration of DIO4

Table 15-46 IOCFG4 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO4
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.6 IOCFG5 Register (Offset = 14h) [Reset = 0000C000h]

IOCFG5 is shown in Table 15-47.

Return to the Summary Table.

Configuration of DIO5

Table 15-47 IOCFG5 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO5
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.7 IOCFG6 Register (Offset = 18h) [Reset = 0000C000h]

IOCFG6 is shown in Table 15-48.

Return to the Summary Table.

Configuration of DIO6

Table 15-48 IOCFG6 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO6
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.8 IOCFG7 Register (Offset = 1Ch) [Reset = 0000C000h]

IOCFG7 is shown in Table 15-49.

Return to the Summary Table.

Configuration of DIO7

Table 15-49 IOCFG7 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO7
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.9 IOCFG8 Register (Offset = 20h) [Reset = 0000C000h]

IOCFG8 is shown in Table 15-50.

Return to the Summary Table.

Configuration of DIO8

Table 15-50 IOCFG8 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO8
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.10 IOCFG9 Register (Offset = 24h) [Reset = 0000C000h]

IOCFG9 is shown in Table 15-51.

Return to the Summary Table.

Configuration of DIO9

Table 15-51 IOCFG9 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO9
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.11 IOCFG10 Register (Offset = 28h) [Reset = 0000C000h]

IOCFG10 is shown in Table 15-52.

Return to the Summary Table.

Configuration of DIO10

Table 15-52 IOCFG10 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO10
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.12 IOCFG11 Register (Offset = 2Ch) [Reset = 0000C000h]

IOCFG11 is shown in Table 15-53.

Return to the Summary Table.

Configuration of DIO11

Table 15-53 IOCFG11 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO11
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.13 IOCFG12 Register (Offset = 30h) [Reset = 0000C000h]

IOCFG12 is shown in Table 15-54.

Return to the Summary Table.

Configuration of DIO12

Table 15-54 IOCFG12 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO12
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.14 IOCFG13 Register (Offset = 34h) [Reset = 0000C000h]

IOCFG13 is shown in Table 15-55.

Return to the Summary Table.

Configuration of DIO13

Table 15-55 IOCFG13 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO13
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.15 IOCFG14 Register (Offset = 38h) [Reset = 0000C000h]

IOCFG14 is shown in Table 15-56.

Return to the Summary Table.

Configuration of DIO14

Table 15-56 IOCFG14 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO14
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.16 IOCFG15 Register (Offset = 3Ch) [Reset = 0000C000h]

IOCFG15 is shown in Table 15-57.

Return to the Summary Table.

Configuration of DIO15

Table 15-57 IOCFG15 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO15
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.17 IOCFG16 Register (Offset = 40h) [Reset = 0008C000h]

IOCFG16 is shown in Table 15-58.

Return to the Summary Table.

Configuration of DIO16

Table 15-58 IOCFG16 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO16
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.18 IOCFG17 Register (Offset = 44h) [Reset = 0010C000h]

IOCFG17 is shown in Table 15-59.

Return to the Summary Table.

Configuration of DIO17

Table 15-59 IOCFG17 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO17
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.19 IOCFG18 Register (Offset = 48h) [Reset = 0000C000h]

IOCFG18 is shown in Table 15-60.

Return to the Summary Table.

Configuration of DIO18

Table 15-60 IOCFG18 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO18
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.20 IOCFG19 Register (Offset = 4Ch) [Reset = 0000C000h]

IOCFG19 is shown in Table 15-61.

Return to the Summary Table.

Configuration of DIO19

Table 15-61 IOCFG19 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO19
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.21 IOCFG20 Register (Offset = 50h) [Reset = 0000C000h]

IOCFG20 is shown in Table 15-62.

Return to the Summary Table.

Configuration of DIO20

Table 15-62 IOCFG20 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO20
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.22 IOCFG21 Register (Offset = 54h) [Reset = 0000C000h]

IOCFG21 is shown in Table 15-63.

Return to the Summary Table.

Configuration of DIO21

Table 15-63 IOCFG21 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO21
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.23 IOCFG22 Register (Offset = 58h) [Reset = 0000C000h]

IOCFG22 is shown in Table 15-64.

Return to the Summary Table.

Configuration of DIO22

Table 15-64 IOCFG22 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO22
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.24 IOCFG23 Register (Offset = 5Ch) [Reset = 0000C000h]

IOCFG23 is shown in Table 15-65.

Return to the Summary Table.

Configuration of DIO23

Table 15-65 IOCFG23 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO23
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.25 IOCFG24 Register (Offset = 60h) [Reset = 0000C000h]

IOCFG24 is shown in Table 15-66.

Return to the Summary Table.

Configuration of DIO24

Table 15-66 IOCFG24 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO24
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.26 IOCFG25 Register (Offset = 64h) [Reset = 0000C000h]

IOCFG25 is shown in Table 15-67.

Return to the Summary Table.

Configuration of DIO25

Table 15-67 IOCFG25 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO25
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.27 IOCFG26 Register (Offset = 68h) [Reset = 0000C000h]

IOCFG26 is shown in Table 15-68.

Return to the Summary Table.

Configuration of DIO26

Table 15-68 IOCFG26 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO26
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.28 IOCFG27 Register (Offset = 6Ch) [Reset = 0000C000h]

IOCFG27 is shown in Table 15-69.

Return to the Summary Table.

Configuration of DIO27

Table 15-69 IOCFG27 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO27
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.29 IOCFG28 Register (Offset = 70h) [Reset = 0000C000h]

IOCFG28 is shown in Table 15-70.

Return to the Summary Table.

Configuration of DIO28

Table 15-70 IOCFG28 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO28
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.30 IOCFG29 Register (Offset = 74h) [Reset = 0000C000h]

IOCFG29 is shown in Table 15-71.

Return to the Summary Table.

Configuration of DIO29

Table 15-71 IOCFG29 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO29
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.31 IOCFG30 Register (Offset = 78h) [Reset = 0000C000h]

IOCFG30 is shown in Table 15-72.

Return to the Summary Table.

Configuration of DIO30

Table 15-72 IOCFG30 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO30
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.32 IOCFG31 Register (Offset = 7Ch) [Reset = 0000C000h]

IOCFG31 is shown in Table 15-73.

Return to the Summary Table.

Configuration of DIO31

Table 15-73 IOCFG31 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO31
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
8h = AUX IO
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.33 IOCFG32 Register (Offset = 80h) [Reset = 0000C000h]

IOCFG32 is shown in Table 15-74.

Return to the Summary Table.

Configuration of DIO32

Table 15-74 IOCFG32 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO32
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.34 IOCFG33 Register (Offset = 84h) [Reset = 0000C000h]

IOCFG33 is shown in Table 15-75.

Return to the Summary Table.

Configuration of DIO33

Table 15-75 IOCFG33 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO33
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.35 IOCFG34 Register (Offset = 88h) [Reset = 0000C000h]

IOCFG34 is shown in Table 15-76.

Return to the Summary Table.

Configuration of DIO34

Table 15-76 IOCFG34 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO34
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.36 IOCFG35 Register (Offset = 8Ch) [Reset = 0000C000h]

IOCFG35 is shown in Table 15-77.

Return to the Summary Table.

Configuration of DIO35

Table 15-77 IOCFG35 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO35
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.37 IOCFG36 Register (Offset = 90h) [Reset = 0000C000h]

IOCFG36 is shown in Table 15-78.

Return to the Summary Table.

Configuration of DIO36

Table 15-78 IOCFG36 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO36
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.38 IOCFG37 Register (Offset = 94h) [Reset = 0000C000h]

IOCFG37 is shown in Table 15-79.

Return to the Summary Table.

Configuration of DIO37

Table 15-79 IOCFG37 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO37
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.39 IOCFG38 Register (Offset = 98h) [Reset = 0000C000h]

IOCFG38 is shown in Table 15-80.

Return to the Summary Table.

Configuration of DIO38

Table 15-80 IOCFG38 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO38
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.40 IOCFG39 Register (Offset = 9Ch) [Reset = 0000C000h]

IOCFG39 is shown in Table 15-81.

Return to the Summary Table.

Configuration of DIO39

Table 15-81 IOCFG39 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO39
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.41 IOCFG40 Register (Offset = A0h) [Reset = 0000C000h]

IOCFG40 is shown in Table 15-82.

Return to the Summary Table.

Configuration of DIO40

Table 15-82 IOCFG40 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO40
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.42 IOCFG41 Register (Offset = A4h) [Reset = 0000C000h]

IOCFG41 is shown in Table 15-83.

Return to the Summary Table.

Configuration of DIO41

Table 15-83 IOCFG41 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO41
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.43 IOCFG42 Register (Offset = A8h) [Reset = 0000C000h]

IOCFG42 is shown in Table 15-84.

Return to the Summary Table.

Configuration of DIO42

Table 15-84 IOCFG42 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO42
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.44 IOCFG43 Register (Offset = ACh) [Reset = 0000C000h]

IOCFG43 is shown in Table 15-85.

Return to the Summary Table.

Configuration of DIO43

Table 15-85 IOCFG43 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-18RESERVEDR0hReserved
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO43
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.45 IOCFG44 Register (Offset = B0h) [Reset = 0000C000h]

IOCFG44 is shown in Table 15-86.

Return to the Summary Table.

Configuration of DIO44

Table 15-86 IOCFG44 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO44
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.46 IOCFG45 Register (Offset = B4h) [Reset = 0000C000h]

IOCFG45 is shown in Table 15-87.

Return to the Summary Table.

Configuration of DIO45

Table 15-87 IOCFG45 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO45
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.47 IOCFG46 Register (Offset = B8h) [Reset = 0000C000h]

IOCFG46 is shown in Table 15-88.

Return to the Summary Table.

Configuration of DIO46

Table 15-88 IOCFG46 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO46
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock

15.10.3.48 IOCFG47 Register (Offset = BCh) [Reset = 0000C000h]

IOCFG47 is shown in Table 15-89.

Return to the Summary Table.

Configuration of DIO47

Table 15-89 IOCFG47 Register Field Descriptions
BitFieldTypeResetDescription
31IOEV_MCU_WU_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event
30HYST_ENR/W0h0: Input hysteresis disable
1: Input hysteresis enable
29IER/W0h0: Input disabled
1: Input enabled
Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.
28-27WU_CFGR/W0hIf DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:
00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.
26-24IOMODER/W0hIO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input / output
1h = INV : Inverted input / ouput
4h = OPENDR : Open Drain,
Normal input / output
5h = OPENDR_INV : Open Drain
Inverted input / output
6h = OPENSRC : Open Source
Normal input / output
7h = OPENSRC_INV : Open Source
Inverted input / output
23IOEV_AON_PROG2_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event
22IOEV_AON_PROG1_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event
21IOEV_AON_PROG0_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event
20-19RESERVEDR0hReserved
18EDGE_IRQ_ENR/W0h0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)
17-16EDGE_DETR/W0hEnable generation of edge detection events on this IO
0h = NONE : No edge detection
1h = Negative edge detection
2h = Positive edge detection
3h = Positive and negative edge detection
15-14PULL_CTLR/W3hPull control
1h = DWN : Pull down
2h = UP : Pull up
3h = DIS : No pull
13SLEW_REDR/W0h0: Normal slew rate
1: Enables reduced slew rate in output driver.
12-11IOCURRR/W0hSelects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
10-9IOSTRR/W0hSelect source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
8IOEV_RTC_ENR/W0hEvent asserted by this IO when edge detection is enabled
0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event
7RESERVEDR0hReserved
6-0PORT_IDR/W0hSelects usage for DIO47
Note: This field should not be written other than the times when PORT_ID value is specifically required to change.
0h = General Purpose IO
7h = AON 32 KHz clock (SCLK_LF)
9h = SPI0_RX : SPI0 RX
Ah = SPI0_TX : SPI0 TX
Bh = SPI0_CS : SPI0 CS
Ch = SPI0_CLK : SPI0 CLK
Dh = I2C0_MSSDA : I2C0 Data
Eh = I2C0_MSSCL : I2C0 Clock
Fh = UART0_RX : UART0 RX
10h = UART0_TX : UART0 TX
11h = UART0_CTS : UART0 CTS
12h = UART0_RTS : UART0 RTS
13h = UART1_RX : UART1 RX
14h = UART1_TX : UART1 TX
15h = UART1_CTS : UART1 CTS
16h = UART1_RTS : UART1 RTS
17h = PORT_EVENT0 : PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
18h = PORT_EVENT1 : PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
19h = PORT_EVENT2 : PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ah = PORT_EVENT3 : PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Bh = PORT_EVENT4 : PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Ch = PORT_EVENT5 : PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Dh = PORT_EVENT6 : PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
1Eh = PORT_EVENT7 : PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
20h = CPU_SWV : CPU SWV
21h = SPI1_RX : SPI1 RX
22h = SPI1_TX : SPI1 TX
23h = SPI1_CS : SPI1 CS
24h = SPI1_CLK : SPI1 CLK
25h = I2S_AD0 : I2S Data 0
26h = I2S_AD1 : I2S Data 1
27h = I2S_WCLK : I2S WCLK
28h = I2S_BCLK : I2S BCLK
29h = I2S_MCLK : I2S MCLK
2Eh = RF Core Trace
2Fh = RF Core Data Out 0
30h = RF Core Data Out 1
31h = RF Core Data Out 2
32h = RF Core Data Out 3
33h = RF Core Data In 0
34h = RF Core Data In 1
35h = RF Core SMI Data Link Out
36h = RF Core SMI Data Link In
37h = RF Core SMI Command Link Out
38h = RF Core SMI Command Link In
39h = SPI2_RX : SPI2 RX
3Ah = SPI2_TX : SPI2 TX
3Bh = SPI2_CS : SPI2 CS
3Ch = SPI2_CLK : SPI2 CLK
3Dh = SPI3_RX : SPI3 RX
3Eh = SPI3_TX : SPI3 TX
3Fh = SPI3_CS : SPI3 CS
40h = SPI3_CLK : SPI3 CLK
41h = UART2_RX : UART2 RX
42h = UART2_TX : UART2 TX
43h = UART2_CTS : UART2 CTS
44h = UART2_RTS : UART2 RTS
45h = UART3_RX : UART3 RX
46h = UART3_TX : UART3 TX
47h = UART3_CTS : UART3 CTS
48h = UART3_RTS : UART3 RTS
49h = I2C1_MSSDA : I2C1 Data
4Ah = I2C1_MSSCL : I2C1 Clock