SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
SPI includes a feature to reset TX and RX FIFO pointers to flush FIFOs. This has to be triggered when no SPI transactions are in progress. If a FIFO flush is triggered when a transaction is in progress, a second FIFO flush would be needed when no operations are ongoing, before restarting fresh SPI transfers.
SPI FIFO flush has to follow this sequence:
SPI enable is set low via SPI:CTL1.ENABLE register bit
SPI:CTL1.FIFORST register bit is forced high to trigger FIFO flush
A wait of 4 to 5 CPU clock cycles is included (needed to ensure that the double synchronizers within the async FIFOs are cleared)
SPI:CTL1.FIFORST is released by setting this to zero
SPI enable can be now set high to restart SPI communication