SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The µDMA Channel 7 is dedicated to transfer ADC samples from the ADC FIFO. Use the sequence that follows to set up a µDMA transfer:
The AUX_ADC_IRQ event sets when the µDMA completes data block transfer. AUX_ADC_IRQ is mapped to System CPU interrupt line 32 (for further description, see EVENT:CPUIRQSEL32 in Section 5.8.2).
This event will also set when the ADC FIFO either overflows or underflows, as indicated by AUX_ANAIF:ADCFIFOSTAT.