SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Only two values are supported for PRCM:BUSSECCFG.BUS_CFG; 0xFF and 0xF9. All other values are reserved, and can lead to unpredictable behavior. Table 3-4 through Table 3-6 show the system configuration resulting from PRCM:BUSSECCFG.BUS_CFG. This setting determines the base address of many apertures/peripherals as well as the state of outbound address filtering for bus masters (if they can access all memory (Secure) or are restricted from accessing secure memory ranges (Non-secure)). Some peripherals only have parts of their memory map moved to Secure memory. This is for backwards compatibility.
BUS_CFG | Firewall Enabled | CRYPTO Data Bus Master | CRYPTO Key Bus Master | CRYPTO Address Location | System Management Registers | Flash, PKA, TRNG, SRAM_MMR |
---|---|---|---|---|---|---|
0xFF | Yes | Secure | Secure | Secure(1) | Secure(1) | Secure(1) |
0xF9 | No | Non-secure | Non-secure | Non-secure(2) | Non-secure(2) | Non-secure(2) |
The system management registers affected by the BUS_CFG configuration are all the registers in the apertures listed in Table 3-5 except the ones in the exemption column. Exempted registers are still accessible in the Non-secure offset but all others are secured.
Aperture | Excemption | Non-secure Offset | Secure Alias Offset |
---|---|---|---|
PRCM | RESETSECDMA | 0x40082000 | 0x58082000 |
RESETGPIO | |||
RESETGPT | |||
RESETI2C | |||
RESETUART | |||
RESETSPI | |||
RESETI2S | |||
RAMRETEN | |||
NVMNSCADDR | |||
NVMNSADDR | |||
SRAMNSCADDR | |||
SRAMNSADDR | |||
BUSSECCFG | |||
CPULOCK | |||
MCUSRAMCFG | |||
SECDMACLKGS | |||
SECDMACLKGDS | |||
SECDMACLKGR | |||
AON_PMCTL | AUXSCECLK | 0x40090000 | 0x58090000 |
RAMCFG | |||
PWRSTAT | |||
SHUTDOWN | |||
RECHARGESTAT | |||
AON_RTC | CTL | 0x40092000 | 0x58092000 |
SEC | |||
SUBSEC | |||
AUX_SYSIF | RTCSUBSECINC0 | 0x400C6000 | 0x580C6000 |
RTCSUBSECINC1 | |||
RTCSUBSECINCCTL | |||
AUX_DDI0_OSC | 0x400CA000 | 0x580CA000 | |
AUX_SCE | NONSECDDIACC0 | 0x400E1000 | 0x580E1000 |
NONSECDDIACC1 | |||
NONSECDDIACC2 | |||
NONSECDDIACC3 |
Table 3-6 shows the apertures which have all registers mapped to the Secure address space.
Aperture | Non-secure Offset | Secure Alias Offset | Size |
---|---|---|---|
CRYPTO | 0x40024000 | 0x58024000 | 2 KB |
PKA | 0x40025000 | 0x58025000 | 4 KB |
PKA_RAM | 0x40026000 | 0x58026000 | 2 KB |
PKA_INT | 0x40027000 | 0x58027000 | 4 KB |
TRNG | 0x40028000 | 0x58028000 | 8 KB |
FLASH(1) | 0x58030000 | 8 KB | |
NVMNW(1) | 0x58032000 | 4 KB | |
SRAM_MMR(1) | 0x58035000 | 20 KB | |
AUX_DDI0_OSC | 0x400CA000 | 0x580CA000 | 4 KB |