SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 2-162 lists the memory-mapped registers for the CPU_SAU registers. All register offset addresses not listed in Table 2-162 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | CTRL | Allows enabling of the Security Attribution Unit | Section 2.5.7.1 |
4h | TYPE | Indicates the number of regions implemented by the Security Attribution Unit | Section 2.5.7.2 |
8h | RNR | Selects the region currently accessed by SAU_RBAR and SAU_RLAR | Section 2.5.7.3 |
Ch | RBAR | Provides indirect read and write access to the base address of the currently selected SAU region | Section 2.5.7.4 |
10h | RLAR | Provides indirect read and write access to the limit address of the currently selected SAU region | Section 2.5.7.5 |
14h | SFSR | Provides information about any security related faults | Section 2.5.7.6 |
18h | SFAR | Shows the address of the memory location that caused a Security violation | Section 2.5.7.7 |
Complex bit access types are encoded to fit into small table cells. Table 2-163 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
CTRL is shown in Table 2-164.
Return to the Summary Table.
Allows enabling of the Security Attribution Unit
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
1 | ALLNS | R/W | 0h | When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure |
0 | ENABLE | R/W | 0h | Enables the SAU |
TYPE is shown in Table 2-165.
Return to the Summary Table.
Indicates the number of regions implemented by the Security Attribution Unit
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-0 | SREGION | R | 0h | The number of implemented SAU regions |
RNR is shown in Table 2-166.
Return to the Summary Table.
Selects the region currently accessed by SAU_RBAR and SAU_RLAR
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-0 | REGION | R/W | 0h | Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR |
RBAR is shown in Table 2-167.
Return to the Summary Table.
Provides indirect read and write access to the base address of the currently selected SAU region
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | BADDR | R/W | 0h | Holds bits [31:5] of the base address for the selected SAU region |
4-0 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RLAR is shown in Table 2-168.
Return to the Summary Table.
Provides indirect read and write access to the limit address of the currently selected SAU region
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | LADDR | R/W | 0h | Holds bits [31:5] of the limit address for the selected SAU region |
4-2 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
1 | NSC | R/W | 0h | Controls whether Non-secure state is permitted to execute an SG instruction from this region |
0 | ENABLE | R/W | 0h | SAU region enable |
SFSR is shown in Table 2-169.
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Provides information about any security related faults
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7 | LSERR | R/W | 0h | Sticky flag indicating that an error occurred during lazy state activation or deactivation |
6 | SFARVALID | R/W | 0h | This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault |
5 | LSPERR | R/W | 0h | Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state |
4 | INVTRAN | R/W | 0h | Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory |
3 | AUVIOL | R/W | 0h | Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR |
2 | INVER | R/W | 0h | This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state |
1 | INVIS | R/W | 0h | This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation |
0 | INVEP | R/W | 0h | This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set |
SFAR is shown in Table 2-170.
Return to the Summary Table.
Shows the address of the memory location that caused a Security violation
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ADDRESS | R/W | 0h | The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state |