The following describes the necessary steps to enable and initialize the SPI.
TI recommends using the SPI driver in the SimpleLink™ CC13xx and CC26xx software development kit (SDK) when using the SPI.
Ensure the corresponding power domain is powered up properly. For details, see Chapter 170
Enable the appropriate SPI module in PRCM by writing to PRCM:SPICLKGR, PRCM:SPICLKGS, and PRCM:SPICLKGDS register and load the setting to the clock controller by writing to PRCM:CLKLOADCTL.
Configure the IOC module to route the SPIn_TX, SPIn_RX, SPIn_CS, and SPIn_CLK functionalities from I/Os to the SPI module. IOCFGn.PORT_ID must be written to the correct PORT_IDs. See Section 15.10.3 for details.
For each of the frame formats, the SPI is configured using the following steps:
- Ensure that the ENABLE bit in the SPI:CTL1 register is clear before making any configuration changes.
- Select whether the SPI is a master or slave:
- For master operations, SPI:CTL1.MS should be 1
- For slave mode (output enabled), SPI:CTL1.MS should be 0
- For slave mode (output disabled), set the SPI:CTL1.MS bit to 0x0 and SPI:CTL1.SOD bit to 0x1
- Configure the clock prescale divisor by writing to the SPI:CLKDIV2.RATIO and SPI:CLKCTL.SCR fields
- Write the SPI:CTL0 register with the following configuration:
- Desired clock phase and polarity, if using Motorola™ SPI mode (SPH and SPO)
- The protocol mode: Motorola SPI (4-wire or 3-wire) , TI SSF, MICROWIRE (FRF)
- The data size (DSS)
- Optionally, configure the μDMA channel (see Chapter 423) and enable the DMA options in the SPI:DMACR register.
- Enable the SPI by setting the ENABLE bit in the SPI:CTL1 register.
As an example, assume that the SPI configuration is required to operate with the following parameters:
- Master operation
- Texas Instruments SPI mode
- 1-Mbps bit rate
- 8 data bits
Assuming the system clock is 48 MHz, the bit-rate calculation is shown in Equation 9.
Equation 9. SPIn_CLK = PERDMACLK / [RATIO × (1 + SCR)]
1000000 bps = 48000000 Hz / [2 × (1 + 23)]
In this case, if RATIO = 0x2, SCR must be 0x18.
The configuration sequence is:
- Ensure that the ENABLE bit in the SPI:CTL1 register is clear
- Write the SPI:CTL1 register with a value of 0x00000004
- Write the SPI:CLKDIV2 register with a value of 0x00000002
- Write the SPI:CLKCTL.SCR register with a value of 0x00000018
- Write the SPI:CTL0 register with a value of 0x0000 47
- The SPI is then enabled by setting the ENABLE bit in the SPI:CTL1 register