The SCE clock source gets emulated when it equals SCLK_MF or SCLK_LF and the MCU domain is active. This is done to ensure that access time to peripherals and resources in AUX from System CPU does not scale with the AUX clock rate. Clock emulation results in SCE clock period jitter:
- SCLK_MF clock emulation: The instant SCE clock period jitter equals ±2 SCLK_HF periods.
- SCLK_LF clock emulation: The instant SCE clock period jitter is 2 SCLK_HF periods. A single SCE clock period increases or decreases by 6 to 8 SCLK_HF periods when emulation starts or ends.
Clock emulation has the following implications:
- The small time uncertainty that clock emulation introduces in the clock period affects only modules that operate at the SCE clock rate.
- Frequency configuration of the SPI SCLK may require guard against shorter base clock period to meet I/O timing requirements. The impacted use cases have SCLK frequency of 1 MHz or less, which is rare.
- The SCE clock period jitter is not accumulative.