SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Figure 23-7 and Figure 23-8 show single and continuous transmission signal sequences, respectively, for Motorola SPI format with SPO = 1 and SPH = 0.
In this configuration, the following occurs during idle periods:
If the SPI is enabled and valid data is in the TX FIFO, the SPIn_CS master signal goes low at the start of transmission and transfers slave data onto the SPIn_MISO line of the master immediately. The master SPIn_MOSI output is enabled.
One-half SPIn_CLK period later, valid master data is transferred to the SPIn_MOSI line. When both the master and slave data have been set, the SPIn_CLK master clock pin becomes low after one additional half SPIn_CLK period. Data is captured on the falling edges and propagated on the rising edges of the SPIn_CLK signal.
For a single-word transmission after all bits of the data word are transferred, the SPIn_CS line is returned to its IDLE high state one SPIn_CLK period after the last bit is captured.
For continuous back-to-back transmissions, the SPIn_CS signal must pulse high between each data word transfer as the slave-select pin freezes the data in its serial peripheral register and keeps it from being altered if the SPH bit is clear. The master device must raise the SPIn_CS pin of the slave device between each data transfer to enable the serial peripheral data write. When the continuous transfer completes, the SPIn_CS pin returns to its IDLE state one SPIn_CLK period after the last bit is captured.