SPRUIU1 User guide | 德州仪器 TI.com.cn

Table 12-1823 lists the memory-mapped registers for the CPSW0_MDIO. All register offset addresses not listed in Table 12-1823 should be considered as reserved locations and the register contents should not be modified.

Table 12-1822 CPSW0_MDIO Instances

Instance	Base Address
CPSW0_NUSS_MDIO	0C00 0000h

Table 12-1823 CPSW0_MDIO Registers

Offset⁽¹⁾	Acronym	Register Name	CPSW0_NUSS_MDIO Physical Address
F00h	CPSW_MDIO_VERSION_REG	MDIO Version Register	0C00 0F00h
F04h	CPSW_MDIO_CONTROL_REG	MDIO Control Register	0C00 0F04h
F08h	CPSW_MDIO_ALIVE_REG	MDIO Alive Register	0C00 0F08h
F0Ch	CPSW_MDIO_LINK_REG	MDIO Link Register	0C00 0F0Ch
F10h	CPSW_MDIO_LINK_INT_RAW_REG	MDIO Link Interrupt Raw Register	0C00 0F10h
F14h	CPSW_MDIO_LINK_INT_MASKED_REG	MDIO Link Interrupt Masked Register	0C00 0F14h
F18h	CPSW_MDIO_LINK_INT_MASK_SET_REG	MDIO Link Interrupt Mask Set Register	0C00 0F18h
F1Ch	CPSW_MDIO_LINK_INT_MASK_CLEAR_REG	MDIO Link Interrupt Mask Clear Register	0C00 0F1Ch
F20h	CPSW_MDIO_USER_INT_RAW_REG	MDIO User Interrupt Raw Register	0C00 0F20h
F24h	CPSW_MDIO_USER_INT_MASKED_REG	MDIO User Interrupt Masked Register	0C00 0F24h
F28h	CPSW_MDIO_USER_INT_MASK_SET_REG	MDIO User Interrupt Mask Set Register	0C00 0F28h
F2Ch	CPSW_MDIO_USER_INT_MASK_CLEAR_REG	MDIO User Interrupt Mask Clear Register	0C00 0F2Ch
F30h	CPSW_MDIO_MANUAL_IF_REG	MDIO Manual Interface Register	0C00 0F30h
F34h	CPSW_MDIO_POLL_REG	MDIO Poll Interrupt Register	0C00 0F34h
F38h	CPSW_MDIO_POLL_EN_REG	MDIO Poll Enable Register	0C00 0F38h
F3Ch	CPSW_MDIO_CLAUS45_REG	Clause 45 Enable Register	0C00 0F3Ch
F40h	CPSW_MDIO_USER_ADDR0_REG	MDIO User Address 0 Register	0C00 0F40h
F44h	CPSW_MDIO_USER_ADDR1_REG	MDIO User Address 1 Register	0C00 0F44h
F80h + formula	CPSW_MDIO_USER_ACCESS_REG_k	MDIO User Access k Register	0C00 0F80h + formula
F84h + formula	CPSW_MDIO_USER_PHY_SEL_REG_k	MDIO User PHY Select k Register	0C00 0F84h + formula

(1) k = 0 to 1

2.6.3.1 CPSW_MDIO_VERSION_REG Register (Offset = F00h) [reset = 00070907h]

CPSW_MDIO_VERSION_REG is shown in Figure 12-951 and described in Table 12-1825.

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MDIO Version Register.

Table 12-1824 CPSW_MDIO_VERSION_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F00h

Figure 12-951 CPSW_MDIO_VERSION_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCHEME		BU		MODULE_ID
R-0h		R-0h		R-7h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REVRTL					REVMAJ			CUSTOM		REVMIN
R-1h					R-1h			R-0h		R-7h

LEGEND: R = Read Only; -n = value after reset

Table 12-1825 CPSW_MDIO_VERSION_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	0h	Scheme
29-28	BU	R	0h	bu
27-16	MODULE_ID	R	7h	Module ID
15-11	REVRTL	R	1h	RTL version
10-8	REVMAJ	R	1h	Major version
7-6	CUSTOM	R	0h	Custom version
5-0	REVMIN	R	7h	Minor version

2.6.3.2 CPSW_MDIO_CONTROL_REG Register (Offset = F04h) [reset = X]

CPSW_MDIO_CONTROL_REG is shown in Figure 12-952 and described in Table 12-1827.

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MDIO Control Register

Table 12-1826 CPSW_MDIO_CONTROL_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F04h

Figure 12-952 CPSW_MDIO_CONTROL_REG Register

31	30	29	28	27	26	25	24
IDLE	ENABLE	RESERVED	HIGHEST_USER_CHANNEL
R-1h	R/W-0h	R/W-X	R-1h

23	22	21	20	19	18	17	16
RESERVED			PREAMBLE	FAULT	FAULT_DETECT_ENABLE	INT_TEST_ENABLE	RESERVED
R/W-X			R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-X

15	14	13	12	11	10	9	8
CLKDIV
R/W-FFh

7	6	5	4	3	2	1	0
CLKDIV
R/W-FFh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-1827 CPSW_MDIO_CONTROL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	IDLE	R	1h	MDIO state machine IDLE. Set to 1h when the state machine is in the idle state.
30	ENABLE	R/W	0h	Enable control. Writing a 1h to this bit enables the MDIO state machine, writing a 0h disables it. If the MDIO state machine is active at the time it is disabled, it will complete the current operation before halting and setting the idle bit. If using byte access, the enable bit has to be the last bit written in this register.
29	RESERVED	R/W	X
28-24	HIGHEST_USER_CHANNEL	R	1h	Highest user channel. This field specifies the highest useraccess channel that is available in the module and is currently set to 1h. This implies that MDIOUserAccess1 is the highest available user access channel.
23-21	RESERVED	R/W	X
20	PREAMBLE	R/W	0h	Preamble disable. Writing a 1h to this bit disables this device from sending MDIO frame preambles in clause 22 mode of operation. This bit has no effect in clause 45 mode of operation.
19	FAULT	R/W	0h	Fault indicator. This bit is set to 1h if the MDIO pins fail to read back what the device is driving onto them. This indicates a physical layer fault and the module state machine is reset. Writing a 1h to it clears this bit.
18	FAULT_DETECT_ENABLE	R/W	0h	Fault detect enable. This bit has to be set to 1h to enable the physical layer fault detection.
17	INT_TEST_ENABLE	R/W	0h	Interrupt test enable. This bit can be set to 1h to enable the host to set the userint and linkint bits for test purposes.
16	RESERVED	R/W	X
15-0	CLKDIV	R/W	FFh	Clock Divider. This field specifies the division ratio between CLK and the frequency of MDCLK. MDCLK is disabled when clkdiv is set to 0h. MDCLK frequency = clk frequency/(clkdiv+1).

2.6.3.3 CPSW_MDIO_ALIVE_REG Register (Offset = F08h) [reset = 0h]

CPSW_MDIO_ALIVE_REG is shown in Figure 12-953 and described in Table 12-1829.

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MDIO Alive Register.

Table 12-1828 CPSW_MDIO_ALIVE_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F08h

Figure 12-953 CPSW_MDIO_ALIVE_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ALIVE
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1829 CPSW_MDIO_ALIVE_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ALIVE	R/W	0h	MDIO Alive. Each of the 32-bits of this register is set if the most recent access to the PHY with address corresponding to the register bit number was acknowledged by the PHY, the bit is reset if the PHY fails to acknowledge the access. Both the user and polling accesses to a PHY will cause the corresponding alive bit to be updated. The alive bits are intended to be used to give an indication of the presence or not of the PHY with the corresponding address. Writing a 1h to any bit will clear it, writing a 0h has no effect.

2.6.3.4 CPSW_MDIO_LINK_REG Register (Offset = F0Ch) [reset = 0h]

CPSW_MDIO_LINK_REG is shown in Figure 12-954 and described in Table 12-1831.

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MDIO Link Register.

Table 12-1830 CPSW_MDIO_LINK_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F0Ch

Figure 12-954 CPSW_MDIO_LINK_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LINK
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-1831 CPSW_MDIO_LINK_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LINK	R	0h	MDIO Link state. This register is updated after a read of the Generic Status Register of a PHY. The corresponding bit is set if the PHY with the corresponding address has link and the PHY acknowledges the read transaction. The bit is cleared to 0h if the PHY indicates it does not have link or fails to acknowledge the read transaction. Writes to the register have no effect. In addition, in Normal Mode Operation, the status of the two PHYs specified in the MDIOUserPhySel registers can be determined using the MLINK input pins. This is determined by the linksel bit in the MDIOUserPhySel register. In State Change Mode the MLINK input pins are unused.

2.6.3.5 CPSW_MDIO_LINK_INT_RAW_REG Register (Offset = F10h) [reset = X]

CPSW_MDIO_LINK_INT_RAW_REG is shown in Figure 12-955 and described in Table 12-1833.

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MDIO Link Interrupt Raw Register.

Table 12-1832 CPSW_MDIO_LINK_INT_RAW_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F10h

Figure 12-955 CPSW_MDIO_LINK_INT_RAW_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED						LINKINTRAW
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1833 CPSW_MDIO_LINK_INT_RAW_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R/W	X
1-0	LINKINTRAW	R/W	0h	MDIO link change event raw value. Normal mode operation: When asserted ‘1’, a bit indicates that there was an MDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register. [0]LINKINTRAW and [1]LINKINTRAW correspond to MDIOUserPhySel0 and MDIOUserPhysel1, respectively. Writing a 1h will clear the event and writing 0h has no effect. If the [17] INT_TEST_ENABLE bit in the CPSW_MDIO_CONTROL_REG register is set, the host may set LINKINTRAW bits to a 1h which may be used for test purposes. MDIO link change event raw value. State Change Mode operation: The [0]LINKINTRAW bit will be asserted ‘1’ when any bit (for any PHY) in the MDIOAlive or MDIOLink registers changes due to MDIO operations. The [1]LINKINTRAW bit is unused in State Change Mode. State Change Mode allows any state change in any PHY to issue an interrupt. If the [17] INT_TEST_ENABLE bit in the CPSW_MDIO_CONTROL_REG register is set, the host may set the [0]LINKINTRAW bit to a 1h which may be used for test purposes.

2.6.3.6 CPSW_MDIO_LINK_INT_MASKED_REG Register (Offset = F14h) [reset = X]

CPSW_MDIO_LINK_INT_MASKED_REG is shown in Figure 12-956 and described in Table 12-1835.

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MDIO Link Interrupt Masked Register.

Table 12-1834 CPSW_MDIO_LINK_INT_MASKED_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F14h

Figure 12-956 CPSW_MDIO_LINK_INT_MASKED_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED						LINKINTMASKED
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1835 CPSW_MDIO_LINK_INT_MASKED_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R/W	X
1-0	LINKINTMASKED	R/W	0h	MDIO link change interrupt masked value. Normal mode operation: When asserted ‘1’, a bit indicates that there was an MDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register and the corresponding CPSW_MDIO_USER_PHY_SEL_REG_k[6] LINKINT_ENABLE bit was set. CPSW_MDIO_LINK_INT_MASKED_REG[0] LINKINTMASKED and [1] LINKINTMASKED correspond to MDIOUserPhySel0 and MDIOUserPhysel1, respectively. Writing a 1h will clear the interrupt and writing 0h has no effect. These masked interrupt bits are the MDIO_LINKINT[1:0] pin values. MDIO link change interrupt masked value. State Change Mode operation: The [0] LINKINTMASKED bit will be asserted ‘1’ when CPSW_MDIO_LINK_INT_RAW_REG[0] LINKINTRAW is asserted ‘1’ and when the CPSW_MDIO_LINK_INT_MASK_SET_REG[0] LINKINTMASKSET bit is set to 1h. Writing a 1h will clear [0] LINKINTMASKED (and the MDIO_LINKINT[0] output) and writing 0h has no effect. The [1] LINKINTMASKED bit is not used in State Change Mode (MDIO_LINKINT[1] is therefore also unused in State Change Mode).

2.6.3.7 CPSW_MDIO_LINK_INT_MASK_SET_REG Register (Offset = F18h) [reset = X]

CPSW_MDIO_LINK_INT_MASK_SET_REG is shown in Figure 12-957 and described in Table 12-1837.

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MDIO Link Interrupt Mask Set Register.

Table 12-1836 CPSW_MDIO_LINK_INT_MASK_SET_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F18h

Figure 12-957 CPSW_MDIO_LINK_INT_MASK_SET_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED							LINKINTMASKSET
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1837 CPSW_MDIO_LINK_INT_MASK_SET_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R/W	X
0	LINKINTMASKSET	R/W	0h	MDIO link interrupt mask set. Normal Mode Operation: This register is not used in normal mode. In normal mode the MDIO_LINKINT[1:0] interrupts are enabled with the linkint_enable bit in the associated MDIOUserPhySel0/1 register. MDIO link interrupt mask set. State Change Mode Operation: Writing this bit to 1h will enable the MDIO link status change interrupt (MDIO_LINKINT[0]) to be asserted when [0] LINKINTRAW is asserted.

2.6.3.8 CPSW_MDIO_LINK_INT_MASK_CLEAR_REG Register (Offset = F1Ch) [reset = X]

CPSW_MDIO_LINK_INT_MASK_CLEAR_REG is shown in Figure 12-958 and described in Table 12-1839.

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MDIO Link Interrupt Mask Clear Register.

Table 12-1838 CPSW_MDIO_LINK_INT_MASK_CLEAR_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F1Ch

Figure 12-958 CPSW_MDIO_LINK_INT_MASK_CLEAR_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED							LINKINTMASKCLR
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1839 CPSW_MDIO_LINK_INT_MASK_CLEAR_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R/W	X
0	LINKINTMASKCLR	R/W	0h	MDIO link interrupt mask clear. Normal Mode Operation: This register is not used in normal mode. In normal mode the MDIO_LINKINT[1:0] interrupts are enabled with the linkint_enable bit in the associated MDIOUserPhySel0/1 register. MDIO link interrupt mask clear. State Change Mode Operation: Writing this bit to 1h will disable the MDIO link status change interrupt (MDIO_LINKINT[0]) regardless of the [0] LINKINTRAW bit value.

2.6.3.9 CPSW_MDIO_USER_INT_RAW_REG Register (Offset = F20h) [reset = X]

CPSW_MDIO_USER_INT_RAW_REG is shown in Figure 12-959 and described in Table 12-1841.

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MDIO User Interrupt Raw Register.

Table 12-1840 CPSW_MDIO_USER_INT_RAW_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F20h

Figure 12-959 CPSW_MDIO_USER_INT_RAW_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED						USERINTRAW
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1841 CPSW_MDIO_USER_INT_RAW_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R/W	X
1-0	USERINTRAW	R/W	0h	Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0, respectively. When asserted ‘1’, a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess register has completed. Writing a 1h will clear the event and writing 0h has no effect. If the [17] INT_TEST_ENABLE bit in the CPSW_MDIO_CONTROL_REG register is set, the host may set the userintraw bits to a 1h. This mode may be used for test purposes.

2.6.3.10 CPSW_MDIO_USER_INT_MASKED_REG Register (Offset = F24h) [reset = X]

CPSW_MDIO_USER_INT_MASKED_REG is shown in Figure 12-960 and described in Table 12-1843.

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MDIO User Interrupt Masked Register.

Table 12-1842 CPSW_MDIO_USER_INT_MASKED_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F24h

Figure 12-960 CPSW_MDIO_USER_INT_MASKED_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED						USERINTMASKED
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1843 CPSW_MDIO_USER_INT_MASKED_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R/W	X
1-0	USERINTMASKED	R/W	0h	Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0, respectively. When asserted ‘1’, a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess register has completed and the corresponding userintmaskset bit is set to 1h. Writing a 1h will clear the interrupt and writing 0h has no effect. If the [17] INT_TEST_ENABLE bit in the CPSW_MDIO_CONTROL_REG register is set, the host may set the CPSW_MDIO_USER_INT_MASKED_REG[1-0] USERINTMASKED bits to a 1h. This mode may be used for test purposes.

2.6.3.11 CPSW_MDIO_USER_INT_MASK_SET_REG Register (Offset = F28h) [reset = X]

CPSW_MDIO_USER_INT_MASK_SET_REG is shown in Figure 12-961 and described in Table 12-1845.

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MDIO User Interrupt Mask Set Register.

Table 12-1844 CPSW_MDIO_USER_INT_MASK_SET_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F28h

Figure 12-961 CPSW_MDIO_USER_INT_MASK_SET_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED						USERINTMASKSET
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1845 CPSW_MDIO_USER_INT_MASK_SET_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R/W	X
1-0	USERINTMASKSET	R/W	0h	MDIO user interrupt mask set for CPSW_MDIO_USER_INT_MASKED_REG[1-0] USERINTMASKED, respectively. Writing a bit to 1h will enable MDIO user command complete interrupts for that particular MDIOUserAccess register. MDIO user interrupt for a particular MDIOUserAccess register is disabled if the corresponding bit is 0h. Writing a 0h to this register has no effect.

2.6.3.12 CPSW_MDIO_USER_INT_MASK_CLEAR_REG Register (Offset = F2Ch) [reset = X]

CPSW_MDIO_USER_INT_MASK_CLEAR_REG is shown in Figure 12-962 and described in Table 12-1847.

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MDIO User Interrupt Mask Clear Register

Table 12-1846 CPSW_MDIO_USER_INT_MASK_CLEAR_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F2Ch

Figure 12-962 CPSW_MDIO_USER_INT_MASK_CLEAR_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED						USERINTMASKCLR
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1847 CPSW_MDIO_USER_INT_MASK_CLEAR_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R/W	X
1-0	USERINTMASKCLR	R/W	0h	MDIO user command complete interrupt mask clear for CPSW_MDIO_USER_INT_MASKED_REG[1-0] USERINTMASKED, respectively. Writing a bit to 1h will disable further user command complete interrupts for that particular MDIOUserAccess register. Writing a 0h to this register has no effect.

2.6.3.13 CPSW_MDIO_MANUAL_IF_REG Register (Offset = F30h) [reset = X]

CPSW_MDIO_MANUAL_IF_REG is shown in Figure 12-963 and described in Table 12-1849.

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MDIO Manual Interface Register.

Table 12-1848 CPSW_MDIO_MANUAL_IF_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F30h

Figure 12-963 CPSW_MDIO_MANUAL_IF_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED					MDIO_MDCLK_O	MDIO_OE	MDIO_PIN
R/W-X					R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1849 CPSW_MDIO_MANUAL_IF_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R/W	X
2	MDIO_MDCLK_O	R/W	0h	MDIO Clock Output. This value is the MDCLK_O output value when the [31] MANUALMODE bit is set in the CPSW_MDIO_POLL_REG register.
1	MDIO_OE	R/W	0h	MDIO Output Enable. This value is inverted and output on the MDIO_OE_N output when the [31] MANUALMODE bit is set in the CPSW_MDIO_POLL_REG register.
0	MDIO_PIN	R/W	0h	MDIO Pin Value. This is the external MDIO data pin value when the [31] MANUALMODE bit is set in the CPSW_MDIO_POLL_REG register. That is, this value is driven on the MDIO_O (the MDIO serial data output) when MDIO_OE is asserted ‘1’. The read value for this bit comes from MDIO_I (the MDIO serial data input). If MDIO_OE is asserted ‘1’ and MDIO_PIN is written with a 1h then MDIO_PIN should read a 1h if there are no external devices pulling the MDIO data line low.

2.6.3.14 CPSW_MDIO_POLL_REG Register (Offset = F34h) [reset = X]

CPSW_MDIO_POLL_REG is shown in Figure 12-964 and described in Table 12-1851.

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MDIO Poll Register.

Table 12-1850 CPSW_MDIO_POLL_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F34h

Figure 12-964 CPSW_MDIO_POLL_REG Register

31	30	29	28	27	26	25	24
MANUALMODE	STATECHANGEMODE	RESERVED
R/W-0h	R/W-0h	R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
IPG
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1851 CPSW_MDIO_POLL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	MANUALMODE	R/W	0h	MDIO Manual Mode. When set 1h, the MDIO pins are directly controlled by software through the bits in the CPSW_MDIO_MANUAL_IF_REG register
30	STATECHANGEMODE	R/W	0h	MDIO State Change Mode. When set, the MDIO is operating in State Change Mode. When clear, the MDIO is operating in normal mode. State change mode effects interrupt operations.
29-8	RESERVED	R/W	X
7-0	IPG	R/W	0h	Polling Inter Packet Gap Value. This value is the number of MDCLK_O clocks between each poll when polling is enabled.

2.6.3.15 CPSW_MDIO_POLL_EN_REG Register (Offset = F38h) [reset = FFFFFFFFh]

CPSW_MDIO_POLL_EN_REG is shown in Figure 12-965 and described in Table 12-1853.

Return to Summary Table.

MDIO Poll Enable Register.

Table 12-1852 CPSW_MDIO_POLL_EN_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F38h

Figure 12-965 CPSW_MDIO_POLL_EN_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POLL_EN
R/W-FFFFFFFFh

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1853 CPSW_MDIO_POLL_EN_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	POLL_EN	R/W	FFFFFFFFh	MDIO Poll Enable. When set, the bit indicates that the associated PHY will be included in polling operations. When clear, the associated PHY will not be polled. Each bit in this field is associated with a PHY. Bit zero is associated with PHY 0 and so on. Due to a limitation in the hardware, bit 31 must always be set (regardless of the value of the preamble disable bit ([20] PREAMBLE) in the CPSW_MDIO_CONTROL_REG register. However, there does not have to be a PHY at address 31.

2.6.3.16 CPSW_MDIO_CLAUS45_REG Register (Offset = F3Ch) [reset = 0h]

CPSW_MDIO_CLAUS45_REG is shown in Figure 12-966 and described in Table 12-1855.

Return to Summary Table.

MDIO Clause45 Enable Register.

Table 12-1854 CPSW_MDIO_CLAUS45_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F3Ch

Figure 12-966 CPSW_MDIO_CLAUS45_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLAUSE45
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1855 CPSW_MDIO_CLAUS45_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	CLAUSE45	R/W	0h	MDIO clause 45 mode. When a clause45 bit is cleared 0h, the PHY associated with the clause45 bit is operating in the clause 22 mode. When set 1h, the PHY associated with the clause45 bit is operating in the clause 45 mode. Bit 0 is associated with PHY 0 and so on.

2.6.3.17 CPSW_MDIO_USER_ADDR0_REG Register (Offset = F40h) [reset = X]

CPSW_MDIO_USER_ADDR0_REG is shown in Figure 12-967 and described in Table 12-1857.

Return to Summary Table.

MDIO Address 0 Register.

Table 12-1856 CPSW_MDIO_USER_ADDR0_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F40h

Figure 12-967 CPSW_MDIO_USER_ADDR0_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																USER_ADDR0
R/W-X																R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1857 CPSW_MDIO_USER_ADDR0_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R/W	X
15-0	USER_ADDR0	R/W	0h	MDIO User Address 0. In clause 45 mode, this field value is the address transferred in the address transfer inititated before each MDIOUserAccess0 access. This is not used for PHY’s operating in clause22 mode as there is no address transfer preceeding each MDIOUserAccess0 access.

2.6.3.18 CPSW_MDIO_USER_ADDR1_REG Register (Offset = F44h) [reset = X]

CPSW_MDIO_USER_ADDR1_REG is shown in Figure 12-968 and described in Table 12-1859.

Return to Summary Table.

MDIO Address 1 Register.

Table 12-1858 CPSW_MDIO_USER_ADDR1_REG Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F44h

Figure 12-968 CPSW_MDIO_USER_ADDR1_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																USER_ADDR1
R/W-X																R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1859 CPSW_MDIO_USER_ADDR1_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R/W	X
15-0	USER_ADDR1	R/W	0h	MDIO User Address 1. In clause 45 mode, this field value is the address transferred in the address transfer inititated before each MDIOUserAccess1 access. This is not used for PHY’s operating in clause22 mode as there is no address transfer preceeding each MDIOUserAccess1 access.

2.6.3.19 CPSW_MDIO_USER_ACCESS_REG_k Register (Offset = F80h + formula) [reset = X]

CPSW_MDIO_USER_ACCESS_REG_k is shown in Figure 12-969 and described in Table 12-1861.

Return to Summary Table.

MDIO User Access Register.

Offset = F80h + (k * 8h); where k = 0h to 1h

Table 12-1860 CPSW_MDIO_USER_ACCESS_REG_k Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F80h + formula

Figure 12-969 CPSW_MDIO_USER_ACCESS_REG_k Register

31	30	29	28	27	26	25	24
GO	WRITE	ACK	RESERVED			REGADR
R/W-0h	R/W-0h	R/W-0h	R/W-X			R/W-0h

23	22	21	20	19	18	17	16
REGADR			PHYADR
R/W-0h			R/W-0h

15	14	13	12	11	10	9	8
DATA
R/W-0h

7	6	5	4	3	2	1	0
DATA
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1861 CPSW_MDIO_USER_ACCESS_REG_k Register Field Descriptions

Bit	Field	Type	Reset	Description
31	GO	R/W	0h	Go. Writing a 1h to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0h to this bit has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will self clear when the requested access has been completed. Any writes to the MDIOUserAccess0 register are blocked when the go bit is 1h. If byte access is being used, the go bit should be written last.
30	WRITE	R/W	0h	Write enable. Setting this bit to a 1h causes the MDIO transaction to be a register write, otherwise it is a register read.
29	ACK	R/W	0h	Acknowledge. This bit is set if the PHY acknowledged the read transaction.
28-26	RESERVED	R/W	X
25-21	REGADR	R/W	0h	Register address. This field specifies the PHY register to be accessed for this transaction in clause 22 mode or the MMD value in clause 45 mode.
20-16	PHYADR	R/W	0h	PHY address. This field specifies the PHY to be accessed for this transaction.
15-0	DATA	R/W	0h	User data. The data value read from or to be written to the specified PHY register.

2.6.3.20 CPSW_MDIO_USER_PHY_SEL_REG_k Register (Offset = F84h + formula) [reset = X]

CPSW_MDIO_USER_PHY_SEL_REG_k is shown in Figure 12-970 and described in Table 12-1863.

Return to Summary Table.

MDIO User PHY Select Register

Offset = F84h + (k * 8h); where k = 0h to 1h

Table 12-1862 CPSW_MDIO_USER_PHY_SEL_REG_k Instances

Instance	Physical Address
CPSW0_NUSS_MDIO	0C00 0F84h + formula

Figure 12-970 CPSW_MDIO_USER_PHY_SEL_REG_k Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
LINKSEL	LINKINT_ENABLE	RESERVED	PHYADR_MON
R/W-0h	R/W-0h	R/W-X	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-1863 CPSW_MDIO_USER_PHY_SEL_REG_k Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R/W	X
7	LINKSEL	R/W	0h	Link status determination select. Set to 1h to determine link status using the MLINK pin. Default value is 0h which implies that the link status is determined by the MDIO state machine.
6	LINKINT_ENABLE	R/W	0h	Link change interrupt enable. Set to 1h to enable link change status interrupts for PHY address specified in [4-0] PHYADR_MON. Link change interrupts are disabled if this bit is set to 0h.
5	RESERVED	R/W	X
4-0	PHYADR_MON	R/W	0h	PHY address whose link status is monitored.

12.2.2.6.3 CPSW0_MDIO Registers

2.6.3.1 CPSW_MDIO_VERSION_REG Register (Offset = F00h) [reset = 00070907h]

2.6.3.2 CPSW_MDIO_CONTROL_REG Register (Offset = F04h) [reset = X]

2.6.3.3 CPSW_MDIO_ALIVE_REG Register (Offset = F08h) [reset = 0h]

2.6.3.4 CPSW_MDIO_LINK_REG Register (Offset = F0Ch) [reset = 0h]

2.6.3.5 CPSW_MDIO_LINK_INT_RAW_REG Register (Offset = F10h) [reset = X]

2.6.3.6 CPSW_MDIO_LINK_INT_MASKED_REG Register (Offset = F14h) [reset = X]

2.6.3.7 CPSW_MDIO_LINK_INT_MASK_SET_REG Register (Offset = F18h) [reset = X]

2.6.3.8 CPSW_MDIO_LINK_INT_MASK_CLEAR_REG Register (Offset = F1Ch) [reset = X]

2.6.3.9 CPSW_MDIO_USER_INT_RAW_REG Register (Offset = F20h) [reset = X]

2.6.3.10 CPSW_MDIO_USER_INT_MASKED_REG Register (Offset = F24h) [reset = X]

2.6.3.11 CPSW_MDIO_USER_INT_MASK_SET_REG Register (Offset = F28h) [reset = X]

2.6.3.12 CPSW_MDIO_USER_INT_MASK_CLEAR_REG Register (Offset = F2Ch) [reset = X]

2.6.3.13 CPSW_MDIO_MANUAL_IF_REG Register (Offset = F30h) [reset = X]

2.6.3.14 CPSW_MDIO_POLL_REG Register (Offset = F34h) [reset = X]

2.6.3.15 CPSW_MDIO_POLL_EN_REG Register (Offset = F38h) [reset = FFFFFFFFh]

2.6.3.16 CPSW_MDIO_CLAUS45_REG Register (Offset = F3Ch) [reset = 0h]

2.6.3.17 CPSW_MDIO_USER_ADDR0_REG Register (Offset = F40h) [reset = X]

2.6.3.18 CPSW_MDIO_USER_ADDR1_REG Register (Offset = F44h) [reset = X]

2.6.3.19 CPSW_MDIO_USER_ACCESS_REG_k Register (Offset = F80h + formula) [reset = X]

2.6.3.20 CPSW_MDIO_USER_PHY_SEL_REG_k Register (Offset = F84h + formula) [reset = X]