SPRUIU1D July   2020  – December 2024 DRA821U , DRA821U-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation From Texas Instruments
    3.     Support Resources
    4.     Glossary
    5.     Export Control Notice
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Device Overview
    2. 1.2 Device Block Diagram
    3. 1.3 Device Main Domain
      1. 1.3.1  Arm Cortex-A72 Subsystem
      2. 1.3.2  Arm Cortex-R5F Processor
      3. 1.3.3  Navigator Subsystem
      4. 1.3.4  Region-based Address Translation Module
      5. 1.3.5  Multicore Shared Memory Controller
      6. 1.3.6  DDR Subsystem
      7. 1.3.7  General Purpose Input/Output Interface
      8. 1.3.8  Inter-Integrated Circuit Interface
      9. 1.3.9  Improved Inter-Integrated Circuit Interface
      10. 1.3.10 Multi-channel Serial Peripheral Interface
      11. 1.3.11 Universal Asynchronous Receiver/Transmitter
      12. 1.3.12 Gigabit Ethernet Switch
      13. 1.3.13 Peripheral Component Interconnect Express Subsystem
      14. 1.3.14 Universal Serial Bus (USB) Subsystem
      15. 1.3.15 SerDes
      16. 1.3.16 General Purpose Memory Controller with Error Location Module
      17. 1.3.17 Multimedia Card/Secure Digital Interface
      18. 1.3.18 Enhanced Capture Module
      19. 1.3.19 Enhanced Pulse-Width Modulation Module
      20. 1.3.20 Enhanced Quadrature Encoder Pulse Module
      21. 1.3.21 Controller Area Network
      22. 1.3.22 Audio Tracking Logic
      23. 1.3.23 Multi-channel Audio Serial Port
      24. 1.3.24 Timers
      25. 1.3.25 Internal Diagnostics Modules
    4. 1.4 Device MCU Domain
      1. 1.4.1  MCU Arm Cortex-R5F Processor
      2. 1.4.2  MCU Region-based Address Translation Module
      3. 1.4.3  MCU Navigator Subsystem
      4. 1.4.4  MCU Analog-to-Digital Converter
      5. 1.4.5  MCU Inter-Integrated Circuit Interface
      6. 1.4.6  MCU Improved Inter-Integrated Circuit Interface
      7. 1.4.7  MCU Multi-channel Serial Peripheral Interface
      8. 1.4.8  MCU Universal Asynchronous Receiver/Transmitter
      9. 1.4.9  MCU Gigabit Ethernet Switch
      10. 1.4.10 MCU Octal Serial Peripheral Interface and HyperBus Memory Controller as a Flash Subsystem
      11. 1.4.11 MCU Controller Area Network
      12. 1.4.12 MCU Timers
      13. 1.4.13 MCU Internal Diagnostics Modules
    5. 1.5 Device WKUP Domain
      1. 1.5.1 WKUP Device Management and Security Controller
      2. 1.5.2 WKUP General Purpose Input/Output Interface
      3. 1.5.3 WKUP Inter-Integrated Circuit Interface
      4. 1.5.4 WKUP Universal Asynchronous Receiver/Transmitter
      5. 1.5.5 WKUP Internal Diagnostics Modules
    6. 1.6 Device Identification
  4. 2 Memory Map
    1. 2.1 MAIN Domain Memory Map
    2. 2.2 MCU Domain Memory Map
    3. 2.3 WKUP Domain Memory Map
    4. 2.4 Processors View Memory Map
    5. 2.5 Region-based Address Translation
  5. 3 System Interconnect
    1. 3.1 System Interconnect Overview
    2. 3.2 System Interconnect Integration
      1. 3.2.1 Interconnect Integration in WKUP Domain
      2. 3.2.2 Interconnect Integration in MCU Domain
      3. 3.2.3 Interconnect Integration in MAIN Domain
    3. 3.3 System Interconnect Functional Description
      1. 3.3.1 Master-Slave Connections
      2. 3.3.2 Quality of Service (QoS)
      3. 3.3.3 Route ID
      4. 3.3.4 Initiator-Side Security Controls and Firewalls
        1. 3.3.4.1 Initiator-Side Security Controls (ISC)
          1. 3.3.4.1.1 Special System Level Priv-ID
          2. 3.3.4.1.2 Priv ID and ISC Assignment
        2. 3.3.4.2 Firewalls (FW)
          1. 3.3.4.2.1 Peripheral Firewalls (FW)
          2. 3.3.4.2.2 Memory or Region-based Firewalls
            1. 3.3.4.2.2.1 Region Based Firewall Functional Description
          3. 3.3.4.2.3 Channelized Firewalls
            1. 3.3.4.2.3.1 Channelized Firewall Functional Description
      5. 3.3.5 Null Error Reporting
      6. 3.3.6 VBUSM_TIMEOUT_GASKET (MCU_TIMEOUT_64B2)
        1. 3.3.6.1 Overview and Feature List
          1. 3.3.6.1.1 Features Supported
          2. 3.3.6.1.2 Features Not Supported
        2. 3.3.6.2 Functional Description
          1. 3.3.6.2.1 Functional Operation
            1. 3.3.6.2.1.1  Overview
            2. 3.3.6.2.1.2  FIFOs
            3. 3.3.6.2.1.3  ID Allocator
            4. 3.3.6.2.1.4  Timer
            5. 3.3.6.2.1.5  Timeout Queue
            6. 3.3.6.2.1.6  Write Scoreboard
            7. 3.3.6.2.1.7  Read Scoreboard
            8. 3.3.6.2.1.8  Flush Mode
            9. 3.3.6.2.1.9  Flushing
            10. 3.3.6.2.1.10 Timeout Error Reporting
            11. 3.3.6.2.1.11 Command Timeout Error Reporting
            12. 3.3.6.2.1.12 Unexpected Response Reporting
            13. 3.3.6.2.1.13 Latency and Stalls
            14. 3.3.6.2.1.14 Bypass
            15. 3.3.6.2.1.15 Safety
        3. 3.3.6.3 Interrupt Conditions
          1. 3.3.6.3.1 Transaction Error Interrupt
            1. 3.3.6.3.1.1 Transaction Timeout
            2. 3.3.6.3.1.2 Unexpected Response
            3. 3.3.6.3.1.3 Command Timeout
        4. 3.3.6.4 Memory Map
          1. 3.3.6.4.1  Revision Register (Base Address + 0x00)
          2. 3.3.6.4.2  Configuration Register (Base Address + 0x04)
          3. 3.3.6.4.3  Info Register (Base Address + 0x08)
          4. 3.3.6.4.4  Enable Register (Base Address + 0x0C)
          5. 3.3.6.4.5  Flush Register (Base Address + 0x10)
          6. 3.3.6.4.6  Timeout Value Register (Base Address + 0x14)
          7. 3.3.6.4.7  Timer Register (Base Address + 0x18)
          8. 3.3.6.4.8  Error Interrupt Raw Status/Set Register (Base Address + 0x20)
          9. 3.3.6.4.9  Error Interrupt Enabled Status/Clear Register (Base Address + 0x24)
          10. 3.3.6.4.10 Error Interrupt Mask Set Register (Base Address + 0x28)
          11. 3.3.6.4.11 Error Interrupt Mask Clear Register (Base Address + 0x2C)
          12. 3.3.6.4.12 Timeout Error Info Register (Base Address + 0x30)
          13. 3.3.6.4.13 Unexpected Response Info Register (Base Address + 0x34)
          14. 3.3.6.4.14 Error Transaction Valid/Dir/RouteID Register (Base Address + 0x38)
          15. 3.3.6.4.15 Error Transaction Tag/CommandID Register (Base Address + 0x3C)
          16. 3.3.6.4.16 Error Transaction Bytecnt Register (Base Address + 0x40)
          17. 3.3.6.4.17 Error Transaction Upper Address Register (Base Address + 0x44)
          18. 3.3.6.4.18 Error Transaction Lower Address Register (Base Address + 0x48)
        5. 3.3.6.5 Integration Overview
          1. 3.3.6.5.1 Parameterization Requirements
        6. 3.3.6.6 I/O Description
          1. 3.3.6.6.1 Clockstop Idle
          2. 3.3.6.6.2 Flush
          3. 3.3.6.6.3 Module I/O
        7. 3.3.6.7 User’s Guide
          1. 3.3.6.7.1 Programmer’s Guide
            1. 3.3.6.7.1.1 Initialization
            2. 3.3.6.7.1.2 Software Flush
      7. 3.3.7 Timeout Gasket (TOG)
    4. 3.4 System Interconnect Registers
      1. 3.4.1 QoS Registers
      2. 3.4.2 Firewall Exception Registers
      3. 3.4.3 Firewall Region Registers
      4. 3.4.4 Null Error Reporting Registers
  6. 4 Initialization
    1. 4.1 Initialization Overview
      1. 4.1.1 ROM Code Overview
      2. 4.1.2 Bootloader Modes
      3. 4.1.3 Terminology
    2. 4.2 Boot Process
      1. 4.2.1 MCU ROM Code Architecture
        1. 4.2.1.1 Main Module
        2. 4.2.1.2 X509 Module
        3. 4.2.1.3 Buffer Manager Module
        4. 4.2.1.4 Log and Trace Module
        5. 4.2.1.5 System Module
        6. 4.2.1.6 Protocol Module
        7. 4.2.1.7 Driver Module
      2. 4.2.2 DMSC ROM Description
      3. 4.2.3 Boot Process Flow
      4. 4.2.4 MCU Only vs Normal Boot
    3. 4.3 Boot Mode Pins
      1. 4.3.1  MCU_BOOTMODE Pin Mapping
      2. 4.3.2  BOOTMODE Pin Mapping
        1. 4.3.2.1 Primary Boot Mode Selection
        2. 4.3.2.2 Backup Boot Mode Selection When MCU Only = 0
        3. 4.3.2.3 Primary Boot Mode Configuration
        4. 4.3.2.4 Backup Boot Mode Configuration
      3. 4.3.3  No-boot/Dev-boot Configuration
      4. 4.3.4  Hyperflash Boot Device Configuration
      5. 4.3.5  OSPI Boot Device Configuration
      6. 4.3.6  QSPI Boot Device Configuration
      7. 4.3.7  SPI Boot Device Configuration
      8. 4.3.8  xSPI Boot Device Configuration
      9. 4.3.9  I2C Boot Device Configuration
      10. 4.3.10 MMC/SD Card Boot Device Configuration
      11. 4.3.11 eMMC Boot Device Configuration
        1. 4.3.11.1 eMMC Flash
      12. 4.3.12 Ethernet Boot Device Configuration
      13. 4.3.13 USB Boot Device Configuration
      14. 4.3.14 PCIe Boot Device Configuration
      15. 4.3.15 UART Boot Device Configuration
      16. 4.3.16 PLL Configuration
        1. 4.3.16.1 MCU_PLL0, MCU_PLL2, Main PLL0, and Main PLL3
        2. 4.3.16.2 MCU_PLL1
        3. 4.3.16.3 Main PLL1
        4. 4.3.16.4 Main PLL2
        5. 4.3.16.5 HSDIV Values
        6. 4.3.16.6 191
    4. 4.4 Boot Parameter Tables
      1. 4.4.1  Common Header
      2. 4.4.2  PLL Setup
      3. 4.4.3  PCIe Boot Parameter Table
      4. 4.4.4  I2C Boot Parameter Table
      5. 4.4.5  OSPI/QSPI/SPI Boot Parameter Table
      6. 4.4.6  Ethernet Boot Parameter Table
      7. 4.4.7  USB Boot Parameter Table
      8. 4.4.8  MMCSD Boot Parameter Table
      9. 4.4.9  UART Boot Parameter Table
      10. 4.4.10 Hyperflash Boot Parameter Table
    5. 4.5 Boot Image Format
      1. 4.5.1 Overall Structure
      2. 4.5.2 X.509 Certificate
      3. 4.5.3 Organizational Identifier (OID)
      4. 4.5.4 X.509 Extensions Specific to Boot
        1. 4.5.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
        2. 4.5.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 4.5.5 Extended Boot Info Extension
        1. 4.5.5.1 Impact on HS Device
        2. 4.5.5.2 Extended Boot Info Details
        3. 4.5.5.3 Certificate / Component Types
        4. 4.5.5.4 Extended Boot Encryption Info
        5. 4.5.5.5 Component Ordering
        6. 4.5.5.6 Memory Load Sections Overlap with Executable Components
        7. 4.5.5.7 Device Type and Extended Boot Extension
      6. 4.5.6 Generating X.509 Certificates
        1. 4.5.6.1 Key Generation
          1. 4.5.6.1.1 Degenerate RSA Keys
        2. 4.5.6.2 Configuration Script
      7. 4.5.7 Image Data
    6. 4.6 Boot Modes
      1. 4.6.1 I2C Bootloader Operation
        1. 4.6.1.1 I2C Initialization Process
          1. 4.6.1.1.1 Block Size
          2. 4.6.1.1.2 227
        2. 4.6.1.2 I2C Loading Process
          1. 4.6.1.2.1 Loading a Boot Image From EEPROM
      2. 4.6.2 SPI Bootloader Operation
        1. 4.6.2.1 SPI Initialization Process
        2. 4.6.2.2 SPI Loading Process
      3. 4.6.3 QSPI Bootloader Operation
        1. 4.6.3.1 QSPI Initialization Process
        2. 4.6.3.2 QSPI Loading Process
      4. 4.6.4 OSPI Bootloader Operation
        1. 4.6.4.1 OSPI Initialization Process
        2. 4.6.4.2 OSPI Loading Process
      5. 4.6.5 PCIe Bootloader Operation
        1. 4.6.5.1 PCIe Initialization Process
        2. 4.6.5.2 PCIe Loading Process
      6. 4.6.6 Ethernet Bootloader Operation
        1. 4.6.6.1 Ethernet Initialization Process
        2. 4.6.6.2 Ethernet Loading Process
          1. 4.6.6.2.1 Ethernet Boot Data Formats
            1. 4.6.6.2.1.1 Limitations
            2. 4.6.6.2.1.2 BOOTP Request
              1. 4.6.6.2.1.2.1 MAC Header (DIX)
              2. 4.6.6.2.1.2.2 IPv4 Header
              3. 4.6.6.2.1.2.3 UDP Header
              4. 4.6.6.2.1.2.4 BOOTP Payload
              5. 4.6.6.2.1.2.5 TFTP
        3. 4.6.6.3 Ethernet Hand Over Process
      7. 4.6.7 USB Bootloader Operation
        1. 4.6.7.1 USB-Specific Attributes
          1. 4.6.7.1.1 DFU Device Mode
      8. 4.6.8 MMCSD Bootloader Operation
      9. 4.6.9 UART Bootloader Operation
        1. 4.6.9.1 Initialization Process
        2. 4.6.9.2 UART Loading Process
          1. 4.6.9.2.1 UART XMODEM
        3. 4.6.9.3 UART Hand-Over Process
    7. 4.7 Boot Memory Maps
      1. 4.7.1 Memory Layout/MPU
      2. 4.7.2 Global Memory Addresses Used by ROM Code
      3. 4.7.3 Memory Reserved by ROM Code
  7. 5 Device Configuration
    1. 5.1 Control Module (CTRL_MMR)
      1. 5.1.1 WKUP_CTRL_MMR0
        1. 5.1.1.1 WKUP_CTRL_MMR0 Overview
        2. 5.1.1.2 WKUP_CTRL_MMR0 Integration
        3. 5.1.1.3 WKUP_CTRL_MMR0 Functional Description
          1. 5.1.1.3.1 Description for WKUP_CTRL_MMR0 Register Types
            1. 5.1.1.3.1.1  Pad Configuration Registers
            2. 5.1.1.3.1.2  Kick Protection Registers
            3. 5.1.1.3.1.3  WKUP_CTRL_MMR0 Module Interrupts
            4. 5.1.1.3.1.4  Clock Selection Registers
            5. 5.1.1.3.1.5  Device Feature Registers
            6. 5.1.1.3.1.6  POK Module Registers
            7. 5.1.1.3.1.7  Power and Reset Related Registers
            8. 5.1.1.3.1.8  PRG Related Registers
            9. 5.1.1.3.1.9  Voltage Glitch Detect Control and Status Registers
            10. 5.1.1.3.1.10 I/O Debounce Control Registers
        4. 5.1.1.4 WKUP_CTRL_MMR0 Registers
      2. 5.1.2 MCU_CTRL_MMR0
        1. 5.1.2.1 MCU_CTRL_MMR0 Overview
        2. 5.1.2.2 MCU_CTRL_MMR0 Integration
        3. 5.1.2.3 MCU_CTRL_MMR0 Functional Description
          1. 5.1.2.3.1 Description for MCU_CTRL_MMR0 Register Types
            1. 5.1.2.3.1.1 Kick Protection Registers
            2. 5.1.2.3.1.2 MCU_CTRL_MMR0 Module Interrupts
            3. 5.1.2.3.1.3 Inter-processor Communication Registers
            4. 5.1.2.3.1.4 Timer I/O Muxing Control Registers
            5. 5.1.2.3.1.5 Clock Muxing and Division Registers
            6. 5.1.2.3.1.6 MCU_CPSW0 MAC Address Registers
        4. 5.1.2.4 MCU_CTRL_MMR0 Registers
        5. 5.1.2.5 MCU_SEC_MMR0_DBG_CTRL Registers
        6. 5.1.2.6 MCU_SEC_MMR0_BOOT_CTRL Registers
      3. 5.1.3 CTRL_MMR0
        1. 5.1.3.1 CTRL_MMR0 Overview
        2. 5.1.3.2 CTRL_MMR0 Integration
        3. 5.1.3.3 CTRL_MMR0 Functional Description
          1. 5.1.3.3.1 Description for CTRL_MMR0 Register Types
            1. 5.1.3.3.1.1  Pad Configuration Registers
            2. 5.1.3.3.1.2  Kick Protection Registers
            3. 5.1.3.3.1.3  CTRL_MMR0 Module Interrupts
            4. 5.1.3.3.1.4  Inter-processor Communication Registers
            5. 5.1.3.3.1.5  Timer I/O Muxing Control Registers
            6. 5.1.3.3.1.6  EHRPWM/EQEP Control and Status Registers
            7. 5.1.3.3.1.7  Clock Muxing and Division Registers
            8. 5.1.3.3.1.8  Ethernet Port Operation Control Registers
            9. 5.1.3.3.1.9  SERDES Lane Function Control Registers
            10. 5.1.3.3.1.10 DDRSS Dynamic Frequency Change Registers
        4. 5.1.3.4 CTRL_MMR0 Registers
        5. 5.1.3.5 SEC_MMR0_DBG_CTRL Registers
        6. 5.1.3.6 SEC_MMR0_BOOT_CTRL Registers
    2. 5.2 Power
      1. 5.2.1 Power Management Overview
      2. 5.2.2 Power Management Subsystems
        1. 5.2.2.1 Power Subsystems Overview
          1. 5.2.2.1.1 POK Overview
          2. 5.2.2.1.2 PRG / PRG_PP Overview
          3. 5.2.2.1.3 POR Overview
          4. 5.2.2.1.4 POK / PRG(_PP) /POR Overview
          5. 5.2.2.1.5 Timing
          6. 5.2.2.1.6 Restrictions
        2. 5.2.2.2 Power System Modules
          1. 5.2.2.2.1 Power OK (POK) Modules
            1. 5.2.2.2.1.1 POK Programming Model
              1. 5.2.2.2.1.1.1 POK Threshold Setting Programming Sequence
          2. 5.2.2.2.2 Power on Reset (POR) Module
            1. 5.2.2.2.2.1 POR Overview
            2. 5.2.2.2.2.2 POR Integration
            3. 5.2.2.2.2.3 POR Programming Model
          3. 5.2.2.2.3 PoR/Reset Generator (PRG_PP) Modules
            1. 5.2.2.2.3.1 PRG_PP Overview
            2. 5.2.2.2.3.2 PRG_PP Integration
            3. 5.2.2.2.3.3 PRG_PP Programming Model
          4. 5.2.2.2.4 Power Glitch Detect (PGD) Modules
          5. 5.2.2.2.5 Voltage and Thermal Manager (VTM)
            1. 5.2.2.2.5.1 VTM Overview
              1. 5.2.2.2.5.1.1 VTM Features
              2. 5.2.2.2.5.1.2 VTM Not Supported Features
            2. 5.2.2.2.5.2 VTM Integration
            3. 5.2.2.2.5.3 VTM Functional Description
              1. 5.2.2.2.5.3.1 VTM Temperature Status and Thermal Management
                1. 5.2.2.2.5.3.1.1 10-bit Temperature Values Versus Temperature
              2. 5.2.2.2.5.3.2 VTM Temperature Driven Alerts and Interrupts
              3. 5.2.2.2.5.3.3 VTM VID Voltage Domains
              4. 5.2.2.2.5.3.4 VTM Clocking
              5. 5.2.2.2.5.3.5 VTM Retention Interface
              6. 5.2.2.2.5.3.6 VTM ECC Aggregator
              7. 5.2.2.2.5.3.7 VTM Programming Model
                1. 5.2.2.2.5.3.7.1 VTM Maximum Temperature Outrange Alert
                2. 5.2.2.2.5.3.7.2 Temperature Monitor during Low Power Modes
                3. 5.2.2.2.5.3.7.3 Sensors Programming Sequences
              8. 5.2.2.2.5.3.8 AVS-Class0
          6. 5.2.2.2.6 Distributed Power Clock and Reset Controller (DPCR)
        3. 5.2.2.3 Power Control Modules
          1. 5.2.2.3.1 Power Sleep Controller and Local Power Sleep Controllers
            1. 5.2.2.3.1.1 PSC Terminology
            2. 5.2.2.3.1.2 PSC Features
            3. 5.2.2.3.1.3 PSC: Device Power-Management Layout
              1. 5.2.2.3.1.3.1 WKUP_PSC0 Device-Specific Information
              2. 5.2.2.3.1.3.2 PSC0 Device-Specific Information
              3. 5.2.2.3.1.3.3 LPSC Dependences Overview
            4. 5.2.2.3.1.4 PSC: Power Domain and Module States
              1. 5.2.2.3.1.4.1 Power Domain States
              2. 5.2.2.3.1.4.2 Module States
              3. 5.2.2.3.1.4.3 Local Reset
            5. 5.2.2.3.1.5 PSC: Executing State Transitions
              1. 5.2.2.3.1.5.1 Power Domain State Transitions
              2. 5.2.2.3.1.5.2 Module State Transitions
              3. 5.2.2.3.1.5.3 Concurrent Power Domain/Module State Transitions
              4. 5.2.2.3.1.5.4 Recommendations for Power Domain/Module Sequencing
            6. 5.2.2.3.1.6 PSC: Emulation Support in the PSC
            7. 5.2.2.3.1.7 PSC: A72SS, MSMC, MCU Cortex-R5F, C71SS0, and C66SS Subsystem Power-Up and Power-Down Sequences
              1. 5.2.2.3.1.7.1 ARMi_COREn Power State Transition
              2. 5.2.2.3.1.7.2 A72SS Power State Transition
              3. 5.2.2.3.1.7.3 GIC0 Sequencing to Support A72SS Power Management
              4. 5.2.2.3.1.7.4 MSMC0 Clkstop/Powerdown/Disconnect Sequencing
              5. 5.2.2.3.1.7.5 MCU Cortex-R5F Power Modes
          2. 5.2.2.3.2 Integrated Power Management (DMSC)
            1. 5.2.2.3.2.1 DMSC Power Management Overview
              1. 5.2.2.3.2.1.1 DMSC Power Management Features
      3. 5.2.3 Device Power States
        1. 5.2.3.1 Overview of Device Low-Power Modes
        2. 5.2.3.2 Voltage Domains
        3. 5.2.3.3 Power Domains
        4. 5.2.3.4 Clock Sources States
        5. 5.2.3.5 Wake-up Sources
        6. 5.2.3.6 Device Power States and Transitions
          1. 5.2.3.6.1 LPM Entry Sequences
          2. 5.2.3.6.2 LPM Exit Sequences
          3. 5.2.3.6.3 IO Retention
          4. 5.2.3.6.4 DDRSS Self-Refresh
      4. 5.2.4 Dynamic Power Management
        1. 5.2.4.1 AVS Support
        2. 5.2.4.2 Dynamic Frequency Scaling (DFS) Operations
      5. 5.2.5 Thermal Management
      6. 5.2.6 Registers
        1. 5.2.6.1 WKUP_VTM0 Registers
        2. 5.2.6.2 PSC Registers
    3. 5.3 Reset
      1. 5.3.1 Reset Overview
      2. 5.3.2 Reset Sources
      3. 5.3.3 Reset Status
      4. 5.3.4 Reset Control
      5. 5.3.5 BOOTMODE Pins
      6. 5.3.6 Reset Sequences
        1. 5.3.6.1 MCU_PORz Overview
        2. 5.3.6.2 MCU_PORz Sequence
        3. 5.3.6.3 MCU_RESETz Sequence
        4. 5.3.6.4 PORz Sequence
        5. 5.3.6.5 RESET_REQz Sequence
      7. 5.3.7 PLL Behavior on Reset
    4. 5.4 Clocking
      1. 5.4.1 Overview
      2. 5.4.2 Clock Inputs
        1. 5.4.2.1 Overview
        2. 5.4.2.2 Mapping of Clock Inputs
      3. 5.4.3 Clock Outputs
        1. 5.4.3.1 Observation Clock Pins
          1. 5.4.3.1.1 MCU_OBSCLK0 Pin
          2. 5.4.3.1.2 425
          3. 5.4.3.1.3 OBSCLK0, OBSCLK1, and OBSCLK2 Pins
        2. 5.4.3.2 System Clock Pins
          1. 5.4.3.2.1 MCU_SYSCLKOUT0
          2. 5.4.3.2.2 SYSCLKOUT0
      4. 5.4.4 Device Oscillators
        1. 5.4.4.1 Device Oscillators Integration
          1. 5.4.4.1.1 Oscillators with External Crystal
          2. 5.4.4.1.2 Internal RC Oscillator
        2. 5.4.4.2 Oscillator Clock Loss Detection
      5. 5.4.5 PLLs
        1. 5.4.5.1 WKUP and MCU Domains PLL Overview
        2. 5.4.5.2 MAIN Domain PLLs Overview
        3. 5.4.5.3 PLL Reference Clocks
          1. 5.4.5.3.1 PLLs in MCU Domain
          2. 5.4.5.3.2 PLLs in MAIN Domain
        4. 5.4.5.4 Generic PLL Overview
          1. 5.4.5.4.1 PLLs Output Clocks Parameters
            1. 5.4.5.4.1.1 PLLs Input Clocks
            2. 5.4.5.4.1.2 PLL Output Clocks
              1. 5.4.5.4.1.2.1 PLLTS16FFCLAFRAC2 Type Output Clocks
              2. 5.4.5.4.1.2.2 PLLTS16FFCLAFRACF Type Output Clocks
              3. 5.4.5.4.1.2.3 PLL Lock
              4. 5.4.5.4.1.2.4 HSDIVIDER
              5. 5.4.5.4.1.2.5 ICG Module
              6. 5.4.5.4.1.2.6 PLL Power Down
              7. 5.4.5.4.1.2.7 PLL Calibration
          2. 5.4.5.4.2 PLL Spread Spectrum Modulation Module
            1. 5.4.5.4.2.1 Definition of SSMOD
            2. 5.4.5.4.2.2 SSMOD Configuration
        5. 5.4.5.5 PLLs Device-Specific Information
          1. 5.4.5.5.1 SSMOD Related Bitfields Table
          2. 5.4.5.5.2 Clock Synthesis Inputs to the PLLs
          3. 5.4.5.5.3 Clock Output Parameter
          4. 5.4.5.5.4 Calibration Related Bitfields
        6. 5.4.5.6 PLL and PLL Controller Connection
        7. 5.4.5.7 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
          1. 5.4.5.7.1 PLL Initialization
            1. 5.4.5.7.1.1 Kick Protection Mechanism
            2. 5.4.5.7.1.2 PLL Initialization to PLL Mode
            3. 5.4.5.7.1.3 PLL Programming Requirements
          2. 5.4.5.7.2 HSDIV PLL Programming
          3. 5.4.5.7.3 PLL Controllers Programming - Dividers PLLDIVn and GO Operation
            1. 5.4.5.7.3.1 GO Operation
            2. 5.4.5.7.3.2 Software Steps to Modify PLLDIV Ratios
          4. 5.4.5.7.4 Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
      6. 5.4.6 Registers
        1. 5.4.6.1 MCU_PLL0_CFG Registers
        2. 5.4.6.2 PLL0_CFG Registers
        3. 5.4.6.3 PLLCTRL0 Registers
  8. 6 Processors and Accelerators
    1. 6.1 Compute Cluster
      1. 6.1.1 Compute Cluster Overview
      2. 6.1.2 Compute Cluster Functional Description
        1. 6.1.2.1 Compute Cluster Memory Regions
        2. 6.1.2.2 Compute Cluster Firewalls
        3. 6.1.2.3 Compute Cluster ECC Aggregators
      3. 6.1.3 Compute Cluster Registers
    2. 6.2 Dual-A72 MPU Subsystem
      1. 6.2.1 A72SS Overview
        1. 6.2.1.1 A72SS Introduction
        2. 6.2.1.2 A72SS Features
      2. 6.2.2 A72SS Integration
      3. 6.2.3 A72SS Functional Description
        1. 6.2.3.1  A72SS Block Diagram
        2. 6.2.3.2  A72SS A72 Cluster
        3. 6.2.3.3  A72SS Interfaces and Async Bridges
        4. 6.2.3.4  A72SS Interrupts
          1. 6.2.3.4.1 A72SS Interrupt Inputs
          2. 6.2.3.4.2 A72SS Interrupt Outputs
        5. 6.2.3.5  A72SS Power Management, Clocking and Reset
          1. 6.2.3.5.1 A72SS Power Management
          2. 6.2.3.5.2 A72SS Clocking
        6. 6.2.3.6  A72SS Debug Support
        7. 6.2.3.7  A72SS Timestamps
        8. 6.2.3.8  A72SS Watchdog
        9. 6.2.3.9  A72SS Internal Diagnostics
          1. 6.2.3.9.1 A72SS ECC Aggregators During Low Power States
          2. 6.2.3.9.2 A72SS CBASS Diagnostics
          3. 6.2.3.9.3 A72SS SRAM Diagnostics
          4. 6.2.3.9.4 A72SS SRAM ECC Aggregator Configurations
        10. 6.2.3.10 A72SS Cache Pre-Warming
        11. 6.2.3.11 A72SS Boot
        12. 6.2.3.12 A72SS IPC with Other CPUs
      4. 6.2.4 A72SS Registers
        1. 6.2.4.1 Arm A72 Cluster Registers
        2. 6.2.4.2 A72SS ECC Aggregator Registers
          1. 6.2.4.2.1 A72SS CLUSTER ECC Registers
          2. 6.2.4.2.2 A72SS CORE0 ECC Registers
          3. 6.2.4.2.3 A72SS CORE1 ECC Registers
    3. 6.3 Dual-R5F MCU Subsystem
      1. 6.3.1 R5FSS Overview
        1. 6.3.1.1 R5FSS Features
        2. 6.3.1.2 R5FSS Not Supported Features
      2. 6.3.2 R5FSS Integration
        1. 6.3.2.1 R5FSS Integration in MCU Domain
        2. 6.3.2.2 R5FSS Integration in MAIN Domain
      3. 6.3.3 R5FSS Functional Description
        1. 6.3.3.1  R5FSS Block Diagram
        2. 6.3.3.2  R5FSS Cortex-R5F Core
          1. 6.3.3.2.1 L1 Caches
          2. 6.3.3.2.2 Tightly-Coupled Memories (TCMs)
          3. 6.3.3.2.3 R5FSS Special Signals
        3. 6.3.3.3  R5FSS Interfaces
          1. 6.3.3.3.1 R5FSS Master Interfaces
          2. 6.3.3.3.2 R5FSS Slave Interfaces
        4. 6.3.3.4  R5FSS Power, Clocking and Reset
          1. 6.3.3.4.1 R5FSS Power
          2. 6.3.3.4.2 R5FSS Clocking
            1. 6.3.3.4.2.1 Changing MCU_R5FSS0 CPU Clock Frequency
          3. 6.3.3.4.3 R5FSS Reset
        5. 6.3.3.5  R5FSS Lockstep Error Detection Logic
          1. 6.3.3.5.1 CPU Output Compare Block
            1. 6.3.3.5.1.1 Operating Modes
            2. 6.3.3.5.1.2 Compare Block Active Mode
            3. 6.3.3.5.1.3 Self Test Mode
            4. 6.3.3.5.1.4 Compare Match Test
            5. 6.3.3.5.1.5 Compare Mismatch Test
            6. 6.3.3.5.1.6 Error Forcing Mode
            7. 6.3.3.5.1.7 Self Test Error Forcing Mode
          2. 6.3.3.5.2 Inactivity Monitor Block
            1. 6.3.3.5.2.1 Operating Modes
            2. 6.3.3.5.2.2 Compare Block Active Mode
            3. 6.3.3.5.2.3 Self Test Mode
            4. 6.3.3.5.2.4 Compare Match Test
            5. 6.3.3.5.2.5 Compare Mismatch Test
            6. 6.3.3.5.2.6 Error Forcing Mode
            7. 6.3.3.5.2.7 Self Test Error Forcing Mode
          3. 6.3.3.5.3 Polarity Inversion Logic
        6. 6.3.3.6  R5FSS Vectored Interrupt Manager (VIM)
          1. 6.3.3.6.1 VIM Overview
          2. 6.3.3.6.2 VIM Interrupt Inputs
          3. 6.3.3.6.3 VIM Interrupt Outputs
          4. 6.3.3.6.4 VIM Interrupt Vector Table (VIM RAM)
          5. 6.3.3.6.5 VIM Interrupt Prioritization
          6. 6.3.3.6.6 VIM ECC Support
          7. 6.3.3.6.7 VIM Lockstep Mode
          8. 6.3.3.6.8 VIM IDLE State
          9. 6.3.3.6.9 VIM Interrupt Handling
            1. 6.3.3.6.9.1 Servicing IRQ Through Vector Interface
            2. 6.3.3.6.9.2 Servicing IRQ Through MMR Interface
            3. 6.3.3.6.9.3 Servicing IRQ Through MMR Interface (Alternative)
            4. 6.3.3.6.9.4 Servicing FIQ
            5. 6.3.3.6.9.5 Servicing FIQ (Alternative)
        7. 6.3.3.7  R5FSS Region Address Translation (RAT)
          1. 6.3.3.7.1 RAT Overview
          2. 6.3.3.7.2 RAT Operation
          3. 6.3.3.7.3 RAT Error Logging
          4. 6.3.3.7.4 RAT Protection
        8. 6.3.3.8  R5FSS ECC Support
        9. 6.3.3.9  R5FSS Memory View
        10. 6.3.3.10 R5FSS Interrupts
        11. 6.3.3.11 R5FSS Debug and Trace
        12. 6.3.3.12 R5FSS Boot Options
        13. 6.3.3.13 R5FSS Core Memory ECC Events
      4. 6.3.4 R5FSS Registers
        1. 6.3.4.1 R5FSS_CCMR5 Registers
        2. 6.3.4.2 R5FSS_CPU0_ECC_AGGR_CFG_REGS Registers
        3. 6.3.4.3 R5FSS_CPU1_ECC_AGGR_CFG_REGS Registers
        4. 6.3.4.4 R5FSS_VIM Registers
        5. 6.3.4.5 R5FSS_RAT Registers
        6. 6.3.4.6 R5FSS_EVNT_BUS_VBUSP_MMRS Registers
  9. 7 Interprocessor Communication
    1. 7.1 Mailbox
      1. 7.1.1 Mailbox Overview
        1. 7.1.1.1 Mailbox Features
        2. 7.1.1.2 Mailbox Parameters
        3. 7.1.1.3 Mailbox Not Supported Features
      2. 7.1.2 Mailbox Integration
        1. 7.1.2.1 System Mailbox Integration
      3. 7.1.3 Mailbox Functional Description
        1. 7.1.3.1 Mailbox Block Diagram
        2. 7.1.3.2 Mailbox Software Reset
        3. 7.1.3.3 Mailbox Power Management
        4. 7.1.3.4 Mailbox Interrupt Requests
        5. 7.1.3.5 Mailbox Assignment
          1. 7.1.3.5.1 Description
        6. 7.1.3.6 Sending and Receiving Messages
          1. 7.1.3.6.1 Description
        7. 7.1.3.7 Example of Communication
      4. 7.1.4 Mailbox Programming Guide
        1. 7.1.4.1 Mailbox Low-level Programming Models
          1. 7.1.4.1.1 Global Initialization
            1. 7.1.4.1.1.1 Surrounding Modules Global Initialization
            2. 7.1.4.1.1.2 Mailbox Global Initialization
              1. 7.1.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
          2. 7.1.4.1.2 Mailbox Operational Modes Configuration
            1. 7.1.4.1.2.1 Mailbox Processing modes
              1. 7.1.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
              2. 7.1.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
              3. 7.1.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
              4. 7.1.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
          3. 7.1.4.1.3 Mailbox Events Servicing
            1. 7.1.4.1.3.1 Events Servicing in Sending Mode
            2. 7.1.4.1.3.2 Events Servicing in Receiving Mode
    2. 7.2 Spinlock
      1. 7.2.1 Spinlock Overview
        1. 7.2.1.1 Spinlock Not Supported Features
      2. 7.2.2 Spinlock Integration
      3. 7.2.3 Spinlock Functional Description
        1. 7.2.3.1 Spinlock Software Reset
        2. 7.2.3.2 Spinlock Power Management
        3. 7.2.3.3 About Spinlocks
        4. 7.2.3.4 Spinlock Functional Operation
      4. 7.2.4 Spinlock Programming Guide
        1. 7.2.4.1 Spinlock Low-level Programming Models
          1. 7.2.4.1.1 Surrounding Modules Global Initialization
          2. 7.2.4.1.2 Basic Spinlock Operations
            1. 7.2.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
            2. 7.2.4.1.2.2 Take and Release Spinlock
  10. 8 Memory Controllers
    1. 8.1 Multicore Shared Memory Controller (MSMC)
      1. 8.1.1 MSMC Overview
        1. 8.1.1.1 MSMC Not Supported Features
      2. 8.1.2 MSMC Integration
        1. 8.1.2.1 MSMC Integration in MAIN Domain
        2. 8.1.2.2 641
      3. 8.1.3 MSMC Functional Description
        1. 8.1.3.1  MSMC Block Diagram
        2. 8.1.3.2  MSMC On-Chip Memory Banking
        3. 8.1.3.3  MSMC Snoop Filter and Data Cache
          1. 8.1.3.3.1 Way Partitioning
          2. 8.1.3.3.2 Cache Size Configuration and Associativity
        4. 8.1.3.4  MSMC Access Protection Checks
        5. 8.1.3.5  MSMC Null Slave
        6. 8.1.3.6  MSMC Resource Arbitration
        7. 8.1.3.7  MSMC Error Detection and Correction
          1. 8.1.3.7.1 On-chip SRAM and Pipeline Data Protection
          2. 8.1.3.7.2 On-chip SRAM L3 Cache Tag and Snoop Filter Protection
          3. 8.1.3.7.3 On-chip SRAM Memory Mapped SRAM Snoop Filter Protection
          4. 8.1.3.7.4 Background Parity Refresh (Scrubbing)
        8. 8.1.3.8  MSMC Interrupts
          1. 8.1.3.8.1 Raw Interrupt Registers
          2. 8.1.3.8.2 Interrupt Enable Registers
          3. 8.1.3.8.3 Triggered and Enabled Interrupts
        9. 8.1.3.9  MSMC Memory Regions
        10. 8.1.3.10 MSMC Hardware Coherence
          1. 8.1.3.10.1 Snoop Filter Broadcast Mode
        11. 8.1.3.11 MSMC Quality-of-Service
        12. 8.1.3.12 MSMC Memory Regions Protection
        13. 8.1.3.13 MSMC Cache Tag View
      4. 8.1.4 MSMC Registers
    2. 8.2 DDR Subsystem (DDRSS)
      1. 8.2.1 DDRSS Overview
        1. 8.2.1.1 DDRSS Not Supported Features
      2. 8.2.2 DDRSS Environment
      3. 8.2.3 DDRSS Integration
        1. 8.2.3.1 DDRSS Integration in MAIN Domain
      4. 8.2.4 DDRSS Functional Description
        1. 8.2.4.1 DDRSS MSMC2DDR Bridge
          1. 8.2.4.1.1 VBUSM.C Threads
          2. 8.2.4.1.2 Class of Service (CoS)
          3. 8.2.4.1.3 AXI Write Data All-Strobes
          4. 8.2.4.1.4 Inline ECC for SDRAM Data
            1. 8.2.4.1.4.1 ECC Cache
            2. 8.2.4.1.4.2 ECC Statistics
          5. 8.2.4.1.5 Opcode Checking
          6. 8.2.4.1.6 Address Alias Prevention
          7. 8.2.4.1.7 Data Error Detection and Correction
          8. 8.2.4.1.8 AXI Bus Timeout
        2. 8.2.4.2 DDRSS Interrupts
        3. 8.2.4.3 DDRSS Memory Regions
        4. 8.2.4.4 DDRSS ECC Support
        5. 8.2.4.5 DDRSS Dynamic Frequency Change Interface
        6. 8.2.4.6 DDR Controller Functional Description
          1. 8.2.4.6.1  DDR PHY Interface (DFI)
          2. 8.2.4.6.2  Command Queue
            1. 8.2.4.6.2.1 Placement Logic
            2. 8.2.4.6.2.2 Command Selection Logic
          3. 8.2.4.6.3  Low Power Control
          4. 8.2.4.6.4  Transaction Processing
          5. 8.2.4.6.5  BIST Engine
          6. 8.2.4.6.6  ECC Engine
          7. 8.2.4.6.7  Address Mapping
          8. 8.2.4.6.8  Paging Policy
          9. 8.2.4.6.9  DDR Controller Initialization
          10. 8.2.4.6.10 Programming LPDDR4 Memories
            1. 8.2.4.6.10.1 Frequency Set Point (FSP)
              1. 8.2.4.6.10.1.1 FSP Mode Register Programming During Initialization
              2. 8.2.4.6.10.1.2 FSP Mode Register Programming During Normal Operation
              3. 8.2.4.6.10.1.3 FSP Mode Register Programming During Dynamic Frequency Scaling
            2. 8.2.4.6.10.2 Data Bus Inversion (DBI)
            3. 8.2.4.6.10.3 On-Die Termination
              1. 8.2.4.6.10.3.1 LPDDR4 DQ ODT
              2. 8.2.4.6.10.3.2 LPDDR4 CA ODT
            4. 8.2.4.6.10.4 Byte Lane Swapping
            5. 8.2.4.6.10.5 DQS Interval Oscillator
              1. 8.2.4.6.10.5.1 Oscillator State Machine
            6. 8.2.4.6.10.6 Per-Bank Refresh (PBR)
              1. 8.2.4.6.10.6.1 Normal Operation
              2. 8.2.4.6.10.6.2 Continuous Refresh Request Mode
        7. 8.2.4.7 DDR PHY Functional Description
          1. 8.2.4.7.1  Data Slice
          2. 8.2.4.7.2  Address Slice
            1. 8.2.4.7.2.1 Address Swapping
          3. 8.2.4.7.3  Address/Control Slice
          4. 8.2.4.7.4  Clock Slice
          5. 8.2.4.7.5  DDR PHY Initialization
          6. 8.2.4.7.6  DDR PHY Dynamic Frequency Scaling (DFS)
          7. 8.2.4.7.7  Chip Select and Frequency Based Register Settings
          8. 8.2.4.7.8  Low-Power Modes
          9. 8.2.4.7.9  Training Support
            1. 8.2.4.7.9.1 Write Leveling
            2. 8.2.4.7.9.2 Read Gate Training
            3. 8.2.4.7.9.3 Read Data Eye Training
            4. 8.2.4.7.9.4 Write DQ Training
            5. 8.2.4.7.9.5 CA Training
            6. 8.2.4.7.9.6 CS Training
          10. 8.2.4.7.10 Data Bus Inversion (DBI)
          11. 8.2.4.7.11 I/O Pad Calibration
          12. 8.2.4.7.12 DQS Error
        8. 8.2.4.8 PI Functional Description
          1. 8.2.4.8.1 PI Initialization
      5. 8.2.5 DDRSS Registers
        1. 8.2.5.1 DDR Subsystem Registers
        2. 8.2.5.2 DDR Controller Registers
        3. 8.2.5.3 PI Registers
        4. 8.2.5.4 DDR PHY Registers
        5. 8.2.5.5 DDRSS0_ECC_AGGR_CTL Registers
        6. 8.2.5.6 DDRSS0_ECC_AGGR_VBUS Registers
        7. 8.2.5.7 DDRSS0_ECC_AGGR_CFG Registers
    3. 8.3 Peripheral Virtualization Unit (PVU)
      1. 8.3.1 PVU Overview
        1. 8.3.1.1 PVU Features
        2. 8.3.1.2 PVU Parameters
        3. 8.3.1.3 PVU Not Supported Features
      2. 8.3.2 PVU Integration
      3. 8.3.3 PVU Functional Description
        1. 8.3.3.1  Functional Operation Overview
        2. 8.3.3.2  PVU Channels
        3. 8.3.3.3  TLB
        4. 8.3.3.4  TLB Entry
        5. 8.3.3.5  TLB Selection
        6. 8.3.3.6  DMA Classes
        7. 8.3.3.7  General virtIDs
        8. 8.3.3.8  TLB Lookup
        9. 8.3.3.9  TLB Miss
        10. 8.3.3.10 Multiple Matching Entries
        11. 8.3.3.11 TLB Disable
        12. 8.3.3.12 TLB Chaining
        13. 8.3.3.13 TLB Permissions
        14. 8.3.3.14 Translation
        15. 8.3.3.15 Memory Attributes
        16. 8.3.3.16 Faulted Transactions
        17. 8.3.3.17 Non-Virtual Transactions
        18. 8.3.3.18 Allowed virtIDs
        19. 8.3.3.19 Software Control
        20. 8.3.3.20 Fault Logging
        21. 8.3.3.21 Alignment Restrictions
      4. 8.3.4 PVU Registers
        1. 8.3.4.1 NAVSS_PVU_CFG Registers
        2. 8.3.4.2 NAVSS0_PVU_CFG_TLBIF Registers
    4. 8.4 Region-based Address Translation (RAT) Module
      1. 8.4.1 RAT Functional Description
        1. 8.4.1.1 RAT Availability
        2. 8.4.1.2 RAT Operation
        3. 8.4.1.3 RAT Error Logging
      2. 8.4.2 RAT Registers
  11. 9 Interrupts
    1. 9.1 Interrupt Architecture
    2. 9.2 Interrupt Controllers
      1. 9.2.1 Generic Interrupt Controller (GIC)
        1. 9.2.1.1 GIC Overview
          1. 9.2.1.1.1 GIC Features
          2. 9.2.1.1.2 GIC Not Supported Features
        2. 9.2.1.2 GIC Integration
        3. 9.2.1.3 GIC Functional Description
          1. 9.2.1.3.1 GIC Block Diagram
          2. 9.2.1.3.2 Arm GIC-500
          3. 9.2.1.3.3 GIC Interrupt Types
          4. 9.2.1.3.4 GIC Interfaces
          5. 9.2.1.3.5 GIC Interrupt Outputs
          6. 9.2.1.3.6 GIC ECC Support
          7. 9.2.1.3.7 GIC AXI2VBUSM and VBUSM2AXI Bridges
        4. 9.2.1.4 GIC Registers
          1. 9.2.1.4.1 Arm GIC-500 Registers
          2. 9.2.1.4.2 GIC_ECC_AGGR Registers
      2. 9.2.2 Other Interrupt Controllers
    3. 9.3 Interrupt Routers
      1. 9.3.1 INTRTR Overview
      2. 9.3.2 INTRTR Integration
        1. 9.3.2.1 WKUP_GPIOMUX_INTRTR0 Integration
        2. 9.3.2.2 GPIOMUX_INTRTR0 Integration
        3. 9.3.2.3 MAIN2MCU_LVL_INTRTR0 Integration
        4. 9.3.2.4 MAIN2MCU_PLS_INTRTR0 Integration
      3. 9.3.3 INTRTR Registers
        1. 9.3.3.1 WKUP_GPIOMUX_INTRTR0 Registers
        2. 9.3.3.2 GPIOMUX_INTRTR0 Registers
        3. 9.3.3.3 MAIN2MCU_LVL_INTRTR0 Registers
        4. 9.3.3.4 MAIN2MCU_PLS_INTRTR0 Registers
    4. 9.4 Interrupt Sources
      1. 9.4.1 WKUP Domain Interrupt Maps
        1. 9.4.1.1 WKUP_DMSC0 Interrupt Map
        2. 9.4.1.2 WKUP_GPIOMUX_INTRTR0 Interrupt Map
        3. 9.4.1.3 WKUP_GPIO0_VIRT Interrupt Map
        4. 9.4.1.4 WKUP_ESM0 Interrupt Map
      2. 9.4.2 MCU Domain Interrupt Maps
        1. 9.4.2.1 MCU_R5FSS0_CORE0 Interrupt Map
        2. 9.4.2.2 MCU_R5FSS0_CORE1 Interrupt Map
        3. 9.4.2.3 MCU_ESM0 Interrupt Map
      3. 9.4.3 MAIN Domain Interrupt Maps
        1. 9.4.3.1 COMPUTE_CLUSTER0 Interrupt Map
          1. 9.4.3.1.1 GIC500 PPI Interrupt Map
          2. 9.4.3.1.2 GIC500 SPI Interrupt Map
          3. 9.4.3.1.3 SoC Event Output Interrupt Map
        2. 9.4.3.2 R5FSS0_CORE0 Interrupt Map
        3. 9.4.3.3 R5FSS0_CORE1 Interrupt Map
        4. 9.4.3.4 MAIN2MCU_LVL_INTRTR0 Interrupt Map
        5. 9.4.3.5 MAIN2MCU_PLS_INTRTR0 Interrupt Map
        6. 9.4.3.6 GPIOMUX_INTRTR0 Interrupt Map
        7. 9.4.3.7 GPIO0_VIRT Interrupt Map
        8. 9.4.3.8 ESM0 Interrupt Map
  12. 10Data Movement Architecture (DMA)
    1. 10.1 DMA Architecture
      1. 10.1.1 Overview
        1. 10.1.1.1  Navigator Subsystem
        2. 10.1.1.2  Ring Accelerator (RA)
        3. 10.1.1.3  Proxy
        4. 10.1.1.4  Secure Proxy
        5. 10.1.1.5  Interrupt Aggregator (INTA)
        6. 10.1.1.6  Interrupt Router (IR)
        7. 10.1.1.7  Unified DMA – Third Party Channel Controller (UDMA-C)
        8. 10.1.1.8  Unified Transfer Controller (UTC)
        9. 10.1.1.9  Data Routing Unit (DRU)
        10. 10.1.1.10 Unified DMA – Peripheral Root Complex (UDMA-P)
          1. 10.1.1.10.1 Channel Classes
        11. 10.1.1.11 Peripheral DMA (PDMA)
        12. 10.1.1.12 Embedded DMA
        13. 10.1.1.13 Definition of Terms
      2. 10.1.2 DMA Hardware/Software Interface
        1. 10.1.2.1 Data Buffers
        2. 10.1.2.2 Descriptors
          1. 10.1.2.2.1 Host Packet Descriptor
          2. 10.1.2.2.2 Host Buffer Descriptor
          3. 10.1.2.2.3 Monolithic Packet Descriptor
          4. 10.1.2.2.4 Transfer Request Descriptor
        3. 10.1.2.3 Transfer Request Record
          1. 10.1.2.3.1 Overview
          2. 10.1.2.3.2 Addressing Algorithm
            1. 10.1.2.3.2.1 Linear Addressing (Forward)
          3. 10.1.2.3.3 Transfer Request Formats
          4. 10.1.2.3.4 Flags Field Definition
            1. 10.1.2.3.4.1 Type: TR Type Field
            2. 10.1.2.3.4.2 STATIC: Static Field Definition
            3. 10.1.2.3.4.3 EVENT_SIZE: Event Generation Definition
            4. 10.1.2.3.4.4 TRIGGER INFO: TR Triggers
            5. 10.1.2.3.4.5 TRIGGERX_TYPE: Trigger Type
            6. 10.1.2.3.4.6 TRIGGERX: Trigger Selection
            7. 10.1.2.3.4.7 CMD ID: Command ID Field Definition
            8. 10.1.2.3.4.8 Configuration Specific Flags Definition
          5. 10.1.2.3.5 TR Address and Size Attributes
            1. 10.1.2.3.5.1  ICNT0
            2. 10.1.2.3.5.2  ICNT1
            3. 10.1.2.3.5.3  ADDR
            4. 10.1.2.3.5.4  DIM1
            5. 10.1.2.3.5.5  ICNT2
            6. 10.1.2.3.5.6  ICNT3
            7. 10.1.2.3.5.7  DIM2
            8. 10.1.2.3.5.8  DIM3
            9. 10.1.2.3.5.9  DDIM1
            10. 10.1.2.3.5.10 DADDR
            11. 10.1.2.3.5.11 DDIM2
            12. 10.1.2.3.5.12 DDIM3
            13. 10.1.2.3.5.13 DICNT0
            14. 10.1.2.3.5.14 DICNT1
            15. 10.1.2.3.5.15 DICNT2
            16. 10.1.2.3.5.16 DICNT3
          6. 10.1.2.3.6 FMTFLAGS
            1. 10.1.2.3.6.1 AMODE: Addressing Mode Definition
              1. 10.1.2.3.6.1.1 Linear Addressing
              2. 10.1.2.3.6.1.2 Circular Addressing
            2. 10.1.2.3.6.2 DIR: Addressing Mode Direction Definition
            3. 10.1.2.3.6.3 ELTYPE: Element Type Definition
            4. 10.1.2.3.6.4 DFMT: Data Formatting Algorithm Definition
            5. 10.1.2.3.6.5 SECTR: Secondary Transfer Request Definition
              1. 10.1.2.3.6.5.1 Secondary TR Formats
              2. 10.1.2.3.6.5.2 Secondary TR FLAGS
                1. 10.1.2.3.6.5.2.1 SEC_TR_TYPE: Secondary TR Type Field
                2. 10.1.2.3.6.5.2.2 Multiple Buffer Interleave
            6. 10.1.2.3.6.6 AMODE SPECIFIC: Addressing Mode Field
              1. 10.1.2.3.6.6.1 Circular Address Mode Specific Flags
                1. 10.1.2.3.6.6.1.1 CBK0 and CBK1: Circular Block Size Selection
                2. 10.1.2.3.6.6.1.2 Amx: Addressing Mode Selection
            7. 10.1.2.3.6.7 Cache Flags
        4. 10.1.2.4 Transfer Response Record
          1. 10.1.2.4.1 STATUS Field Definition
            1. 10.1.2.4.1.1 STATUS_TYPE Definition
              1. 10.1.2.4.1.1.1 Transfer Error
              2. 10.1.2.4.1.1.2 Aborted Error
              3. 10.1.2.4.1.1.3 Submission Error
              4. 10.1.2.4.1.1.4 Unsupported Feature
              5. 10.1.2.4.1.1.5 Transfer Exception
              6. 10.1.2.4.1.1.6 Teardown Flush
        5. 10.1.2.5 Queues
          1. 10.1.2.5.1 Queue Types
            1. 10.1.2.5.1.1 Transmit Queues (Pass By Reference)
            2. 10.1.2.5.1.2 Transmit Queues (Pass By Value)
            3. 10.1.2.5.1.3 Transmit Completion Queues (Pass By Reference)
            4. 10.1.2.5.1.4 Transmit Completion Queues (Pass By Value)
            5. 10.1.2.5.1.5 Receive Queues
            6. 10.1.2.5.1.6 Free Descriptor Queues
            7. 10.1.2.5.1.7 Free Descriptor/Buffer Queues
          2. 10.1.2.5.2 Ring Accelerator Queues Implementation
      3. 10.1.3 Operational Description
        1. 10.1.3.1  Resource Allocation
        2. 10.1.3.2  Ring Accelerator Operation
          1. 10.1.3.2.1 Queue Initialization
          2. 10.1.3.2.2 Queuing packets (Exposed Ring Mode)
          3. 10.1.3.2.3 De-queuing packets (Exposed Ring Mode)
          4. 10.1.3.2.4 Queuing packets (Queue Mode)
          5. 10.1.3.2.5 De-queuing packets (Queue Mode)
        3. 10.1.3.3  UDMA Internal Transmit Channel Setup (All Packet Types)
        4. 10.1.3.4  UDMA Internal Transmit Channel Teardown (All Packet Types)
        5. 10.1.3.5  UDMA External Transmit Channel Setup
        6. 10.1.3.6  UDMA Transmit External Channel Teardown
        7. 10.1.3.7  UDMA-P Transmit Channel Pause
        8. 10.1.3.8  UDMA-P Transmit Operation (Host Packet Type)
        9. 10.1.3.9  UDMA-P Transmit Operation (Monolithic Packet)
        10. 10.1.3.10 UDMA Transmit Operation (TR Packet)
        11. 10.1.3.11 UDMA Transmit Operation (Direct TR)
        12. 10.1.3.12 UDMA Transmit Error/Exception Handling
          1. 10.1.3.12.1 Null Icnt0 Error
          2. 10.1.3.12.2 Unsupported TR Type
          3. 10.1.3.12.3 Bus Errors
        13. 10.1.3.13 UDMA Receive Channel Setup (All Packet Types)
        14. 10.1.3.14 UDMA Receive Channel Teardown
        15. 10.1.3.15 UDMA-P Receive Channel Pause
        16. 10.1.3.16 UDMA-P Receive Free Descriptor/Buffer Queue Setup (Host Packets)
        17. 10.1.3.17 UDMA-P Receive FlowID Firewall Operation
        18. 10.1.3.18 UDMA-P Receive Operation (Host Packet)
        19. 10.1.3.19 UDMA-P Receive Operation (Monolithic Packet)
        20. 10.1.3.20 UDMA Receive Operation (TR Packet)
        21. 10.1.3.21 UDMA Receive Operation (Direct TR)
        22. 10.1.3.22 UDMA Receive Error/Exception Handling
          1. 10.1.3.22.1 Error Conditions
            1. 10.1.3.22.1.1 Bus Errors
            2. 10.1.3.22.1.2 Null Icnt0 Error
            3. 10.1.3.22.1.3 Unsupported TR Type
          2. 10.1.3.22.2 Exception Conditions Exception Conditions
            1. 10.1.3.22.2.1 Descriptor Starvation
            2. 10.1.3.22.2.2 Protocol Errors
            3. 10.1.3.22.2.3 Dropped Packets
            4. 10.1.3.22.2.4 Reception of EOL Delimiter
            5. 10.1.3.22.2.5 EOP Asserted Prematurely (Short Packet)
            6. 10.1.3.22.2.6 EOP Asserted Late (Long Packets)
        23. 10.1.3.23 UTC Operation
        24. 10.1.3.24 UTC Receive Error/Exception Handling
          1. 10.1.3.24.1 Error Handling
            1. 10.1.3.24.1.1 Null Icnt0 Error
            2. 10.1.3.24.1.2 Unsupported TR Type
          2. 10.1.3.24.2 Exception Conditions
            1. 10.1.3.24.2.1 Reception of EOL Delimiter
            2. 10.1.3.24.2.2 EOP Asserted Prematurely (Short Packet)
            3. 10.1.3.24.2.3 EOP Asserted Late (Long Packets)
    2. 10.2 Navigator Subsystem (NAVSS)
      1. 10.2.1  Main Navigator Subsystem (NAVSS)
        1. 10.2.1.1 NAVSS Overview
        2. 10.2.1.2 NAVSS Integration
          1. 10.2.1.2.1 NAVSS Interrupt Router Configuration
          2. 10.2.1.2.2 Global Event Map
          3. 10.2.1.2.3 PSI-L System Thread Map (All NAVSS)
          4. 10.2.1.2.4 NAVSS VBUSM Route ID Table
        3. 10.2.1.3 NAVSS Functional Description
        4. 10.2.1.4 NAVSS Interrupt Configuration
          1. 10.2.1.4.1 NAVSS Event and Interrupt Flow
            1. 10.2.1.4.1.1 NAVSS Interrupts Description
            2. 10.2.1.4.1.2 Application Example
        5. 10.2.1.5 NAVSS Top-level Registers
          1. 10.2.1.5.1 NAVSS0_CFG Registers
          2. 10.2.1.5.2 INTR0_INTR_ROUTER_CFG Registers
          3. 10.2.1.5.3 VIRTID_CFG_MMRS Registers
      2. 10.2.2  MCU Navigator Subsystem (MCU NAVSS)
        1. 10.2.2.1 MCU NAVSS Overview
        2. 10.2.2.2 MCU NAVSS Integration
          1. 10.2.2.2.1  MCU NAVSS Interrupt Router Configuration
          2. 10.2.2.2.2  MCU NAVSS UDMASS Interrupt Aggregator Configuration
          3. 10.2.2.2.3  MCU NAVSS UDMA Configuration
          4. 10.2.2.2.4  MCU NAVSS Ring Accelerator Configuration
          5. 10.2.2.2.5  MCU NAVSS Proxy Configuration
          6. 10.2.2.2.6  MCU NAVSS Secure Proxy Configuration
          7. 10.2.2.2.7  Global Event Map
          8. 10.2.2.2.8  PSI-L System Thread Map (All NAVSS)
          9. 10.2.2.2.9  MCU NAVSS VBUSM Route ID Table
          10. 10.2.2.2.10 1008
        3. 10.2.2.3 MCU NAVSS Functional Description
        4. 10.2.2.4 MCU NAVSS Top-Level Registers
          1. 10.2.2.4.1 MCU_NAVSS0_CFG Registers
          2. 10.2.2.4.2 MCU_NAVSS0_UDMASS_ECCAGGR0 Registers
      3. 10.2.3  Unified DMA Controller (UDMA)
        1. 10.2.3.1 UDMA Overview
          1. 10.2.3.1.1 UDMA Features
          2. 10.2.3.1.2 UDMA Parameters
        2. 10.2.3.2 UDMA Integration
        3. 10.2.3.3 UDMA Functional Description
          1. 10.2.3.3.1 Block Diagram
          2. 10.2.3.3.2 General Functionality
            1. 10.2.3.3.2.1  Operational States
            2. 10.2.3.3.2.2  Tx Channel Allocation
            3. 10.2.3.3.2.3  Rx Channel Allocation
            4. 10.2.3.3.2.4  Tx Teardown
            5. 10.2.3.3.2.5  Rx Teardown
            6. 10.2.3.3.2.6  Tx Clock Stop
            7. 10.2.3.3.2.7  Rx Clock Stop
            8. 10.2.3.3.2.8  Rx Thread Enables
            9. 10.2.3.3.2.9  Events
              1. 10.2.3.3.2.9.1 Local Event Inputs
              2. 10.2.3.3.2.9.2 Inbound Tx PSI-L Events
              3. 10.2.3.3.2.9.3 Outbound Rx PSI-L Events
            10. 10.2.3.3.2.10 Emulation Control
          3. 10.2.3.3.3 Packet Oriented Transmit Operation
            1. 10.2.3.3.3.1 Packet Mode VBUSM Master Interface Command ID Selection
          4. 10.2.3.3.4 Packet Oriented Receive Operation
            1. 10.2.3.3.4.1 Rx Packet Drop
            2. 10.2.3.3.4.2 Rx Starvation and the Starvation Timer
          5. 10.2.3.3.5 Third Party Mode Operation
            1. 10.2.3.3.5.1 Events and Flow Control
              1. 10.2.3.3.5.1.1 Channel Triggering
              2. 10.2.3.3.5.1.2 Internal TR Completion Events
            2. 10.2.3.3.5.2 Transmit Operation
              1. 10.2.3.3.5.2.1 Transfer Request
              2. 10.2.3.3.5.2.2 Transfer Response
              3. 10.2.3.3.5.2.3 Data Transfer
              4. 10.2.3.3.5.2.4 Memory Interface Transactions
              5. 10.2.3.3.5.2.5 Error Handling
            3. 10.2.3.3.5.3 Receive Operation
              1. 10.2.3.3.5.3.1 Transfer Request
              2. 10.2.3.3.5.3.2 Transfer Response
              3. 10.2.3.3.5.3.3 Error Handling
            4. 10.2.3.3.5.4 Data Transfer
              1. 10.2.3.3.5.4.1 Memory Interface Transactions
              2. 10.2.3.3.5.4.2 Rx Packet Drop
        4. 10.2.3.4 UDMA Registers
          1. 10.2.3.4.1 UDMASS_UDMAP0_CFG Registers
          2. 10.2.3.4.2 UDMASS_UDMAP0_CFG_TCHAN Registers
          3. 10.2.3.4.3 UDMASS_UDMAP0_CFG_RCHAN Registers
          4. 10.2.3.4.4 UDMASS_UDMAP0_CFG_RFLOW Registers
          5. 10.2.3.4.5 UDMASS_UDMAP0_CFG_RCHANRT Registers
          6. 10.2.3.4.6 UDMASS_UDMAP0_CFG_TCHANRT Registers
      4. 10.2.4  Ring Accelerator (RINGACC)
        1. 10.2.4.1 RINGACC Overview
          1. 10.2.4.1.1 RINGACC Features
          2. 10.2.4.1.2 RINGACC Not Supported Features
          3. 10.2.4.1.3 RINGACC Parameters
        2. 10.2.4.2 RINGACC Integration
        3. 10.2.4.3 RINGACC Functional Description
          1. 10.2.4.3.1 Block Diagram
            1. 10.2.4.3.1.1  Configuration Registers
            2. 10.2.4.3.1.2  Source Command FIFO
            3. 10.2.4.3.1.3  Source Write Data FIFO
            4. 10.2.4.3.1.4  Source Read Data FIFO
            5. 10.2.4.3.1.5  Source Write Status FIFO
            6. 10.2.4.3.1.6  Main State Machine
            7. 10.2.4.3.1.7  Destination Command FIFO
            8. 10.2.4.3.1.8  Destination Write Data FIFO
            9. 10.2.4.3.1.9  Destination Read Data FIFO
            10. 10.2.4.3.1.10 Destination Write Status FIFO
          2. 10.2.4.3.2 RINGACC Functional Operation
            1. 10.2.4.3.2.1 Queue Modes
              1. 10.2.4.3.2.1.1 Ring Mode
              2. 10.2.4.3.2.1.2 Messaging Mode
              3. 10.2.4.3.2.1.3 Credentials Mode
              4. 10.2.4.3.2.1.4 Queue Manager Mode
              5. 10.2.4.3.2.1.5 Peek Support
              6. 10.2.4.3.2.1.6 Index Register Operation
            2. 10.2.4.3.2.2 VBUSM Slave Ring Operations
            3. 10.2.4.3.2.3 VBUSM Master Interface Command ID Selection
            4. 10.2.4.3.2.4 Ring Push Operation (VBUSM Write to Source Interface)
            5. 10.2.4.3.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
            6. 10.2.4.3.2.6 Host Doorbell Access
            7. 10.2.4.3.2.7 Queue Push Operation (VBUSM Write to Source Interface)
            8. 10.2.4.3.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
            9. 10.2.4.3.2.9 Mismatched Element Size Handling
          3. 10.2.4.3.3 Events
          4. 10.2.4.3.4 Bus Error Handling
          5. 10.2.4.3.5 Monitors
            1. 10.2.4.3.5.1 Threshold Monitor
            2. 10.2.4.3.5.2 Watermark Monitor
            3. 10.2.4.3.5.3 Starvation Monitor
            4. 10.2.4.3.5.4 Statistics Monitor
            5. 10.2.4.3.5.5 Overflow
            6. 10.2.4.3.5.6 Ring Update Port
            7. 10.2.4.3.5.7 Tracing
        4. 10.2.4.4 RINGACC Registers
          1. 10.2.4.4.1 NAVSS0_UDMASS_RINGACC0_CFG Registers
          2. 10.2.4.4.2 NAVSS0_UDMASS_RINGACC0_GCFG Registers
          3. 10.2.4.4.3 NAVSS0_UDMASS_RINGACC0_CFG_MON Registers
          4. 10.2.4.4.4 NAVSS0_UDMASS_RINGACC0_CFG_RT Registers
          5. 10.2.4.4.5 NAVSS0_UDMASS_RINGACC0_SRC_FIFOS Registers
      5. 10.2.5  Proxy
        1. 10.2.5.1 Proxy Overview
          1. 10.2.5.1.1 Proxy Features
          2. 10.2.5.1.2 Proxy Parameters
          3. 10.2.5.1.3 Proxy Not Supported Features
        2. 10.2.5.2 Proxy Integration
        3. 10.2.5.3 Proxy Functional Description
          1. 10.2.5.3.1  Targets
            1. 10.2.5.3.1.1 Ring Accelerator
          2. 10.2.5.3.2  Proxy Sizes
          3. 10.2.5.3.3  Proxy Interleaving
          4. 10.2.5.3.4  Proxy Host States
          5. 10.2.5.3.5  Proxy Host Channel Selection
          6. 10.2.5.3.6  Proxy Host Access
            1. 10.2.5.3.6.1 Proxy Host Writes
            2. 10.2.5.3.6.2 Proxy Host Reads
          7. 10.2.5.3.7  Permission Inheritance
          8. 10.2.5.3.8  Buffer Size
          9. 10.2.5.3.9  Error Events
          10. 10.2.5.3.10 Debug Reads
        4. 10.2.5.4 Proxy Registers
          1. 10.2.5.4.1 NAVSS0_PROXY0_CFG_BUF_CFG Registers
          2. 10.2.5.4.2 NAVSS0_PROXY0_BUF_CFG Registers
          3. 10.2.5.4.3 NAVSS0_PROXY_BUF Registers
          4. 10.2.5.4.4 NAVSS0_PROXY_TARGET0_DATA Registers
      6. 10.2.6  Secure Proxy
        1. 10.2.6.1 Secure Proxy Overview
          1. 10.2.6.1.1 Secure Proxy Features
          2. 10.2.6.1.2 Secure Proxy Parameters
          3. 10.2.6.1.3 Secure Proxy Not Supported Features
        2. 10.2.6.2 Secure Proxy Integration
        3. 10.2.6.3 Secure Proxy Functional Description
          1. 10.2.6.3.1  Targets
            1. 10.2.6.3.1.1 Ring Accelerator
          2. 10.2.6.3.2  Buffers
            1. 10.2.6.3.2.1 Proxy Credits
            2. 10.2.6.3.2.2 Proxy Private Word
            3. 10.2.6.3.2.3 Completion Byte
          3. 10.2.6.3.3  Proxy Thread Sizes
          4. 10.2.6.3.4  Proxy Thread Interleaving
          5. 10.2.6.3.5  Proxy States
          6. 10.2.6.3.6  Proxy Host Access
            1. 10.2.6.3.6.1 Proxy Host Writes
            2. 10.2.6.3.6.2 Proxy Host Reads
            3. 10.2.6.3.6.3 Buffer Accesses
            4. 10.2.6.3.6.4 Target Access
            5. 10.2.6.3.6.5 Error State
          7. 10.2.6.3.7  Permission Inheritance
          8. 10.2.6.3.8  Resource Association
          9. 10.2.6.3.9  Direction
          10. 10.2.6.3.10 Threshold Events
          11. 10.2.6.3.11 Error Events
          12. 10.2.6.3.12 Bus Errors and Credits
          13. 10.2.6.3.13 Debug
        4. 10.2.6.4 Secure Proxy Registers
          1. 10.2.6.4.1 NAVSS0_SEC_PROXY0_CFG_MMRS Registers
          2. 10.2.6.4.2 NAVSS0_SEC_PROXY0_CFG_RT Registers
          3. 10.2.6.4.3 NAVSS0_SEC_PROXY0_CFG_SCFG Registers
          4. 10.2.6.4.4 NAVSS0_SEC_PROXY0_SRC_TARGET_DATA Registers
      7. 10.2.7  Interrupt Aggregator (INTR_AGGR)
        1. 10.2.7.1 INTR_AGGR Overview
          1. 10.2.7.1.1 INTR_AGGR Features
          2. 10.2.7.1.2 INTR_AGGR Parameters
        2. 10.2.7.2 INTR_AGGR Integration
        3. 10.2.7.3 INTR_AGGR Functional Description
          1. 10.2.7.3.1 Submodule Descriptions
            1. 10.2.7.3.1.1 Status/Mask Registers
            2. 10.2.7.3.1.2 Interrupt Mapping Block
            3. 10.2.7.3.1.3 Global Event Input (GEVI) Counters
            4. 10.2.7.3.1.4 Local Event Input (LEVI) to Global Event Conversion
            5. 10.2.7.3.1.5 Global Event Multicast
          2. 10.2.7.3.2 General Functionality
            1. 10.2.7.3.2.1 Event to Interrupt Bit Steering
            2. 10.2.7.3.2.2 Interrupt Status
            3. 10.2.7.3.2.3 Interrupt Masked Status
            4. 10.2.7.3.2.4 Enabling/Disabling Individual Interrupt Source Bits
            5. 10.2.7.3.2.5 Interrupt Output Generation
            6. 10.2.7.3.2.6 Global Event Counting
            7. 10.2.7.3.2.7 Local Event to Global Event Conversion
            8. 10.2.7.3.2.8 Global Event Multicast
        4. 10.2.7.4 INTR_AGGR Registers
          1. 10.2.7.4.1  MODSS_INTA_CFG Registers
          2. 10.2.7.4.2  MODSS_INTA_CFG_IMAP Registers
          3. 10.2.7.4.3  MODSS_INTA_CFG_INTR Registers
          4. 10.2.7.4.4  UDMASS_INTA0_CFG Registers
          5. 10.2.7.4.5  UDMASS_INTA0_CFG_INTR Registers
          6. 10.2.7.4.6  UDMASS_INTA0_CFG_IMAP Registers
          7. 10.2.7.4.7  UDMASS_INTA0_CFG_L2G Registers
          8. 10.2.7.4.8  UDMASS_INTA0_CFG_MCAST Registers
          9. 10.2.7.4.9  UDMASS_INTA0_CFG_GCNTCFG Registers
          10. 10.2.7.4.10 UDMASS_INTA0_CFG_GCNTRTI Registers
      8. 10.2.8  Packet Streaming Interface Link (PSI-L)
        1. 10.2.8.1 PSI-L Overview
        2. 10.2.8.2 PSI-L Functional Description
          1. 10.2.8.2.1 PSI-L Introduction
          2. 10.2.8.2.2 PSI-L Operation
            1. 10.2.8.2.2.1 Event Transport
            2. 10.2.8.2.2.2 Threads
            3. 10.2.8.2.2.3 Arbitration Protocol
            4. 10.2.8.2.2.4 Thread Configuration
              1. 10.2.8.2.2.4.1 Thread Pairing
                1. 10.2.8.2.2.4.1.1 Configuration Transaction Pairing
              2. 10.2.8.2.2.4.2 Configuration Registers Region
        3. 10.2.8.3 PSI-L Configuration Registers
        4. 10.2.8.4 PSI-L CFG_PROXY Registers
      9. 10.2.9  PSIL Subsystem (PSILSS)
        1. 10.2.9.1 PSILSS Overview
          1. 10.2.9.1.1 PSILSS Features
        2. 10.2.9.2 PSILSS Functional Description
          1. 10.2.9.2.1 PSILSS Basic Operation
          2. 10.2.9.2.2 PSILSS Event Routing
          3. 10.2.9.2.3 PSILSS Link Down Detection
          4. 10.2.9.2.4 PSILSS Configuration
        3. 10.2.9.3 PSILSS Registers
          1. 10.2.9.3.1 PDMA_USART_PSILSS0 Registers
          2. 10.2.9.3.2 PDMA_SPI_PSILSS0 Registers
      10. 10.2.10 NAVSS North Bridge (NB)
        1. 10.2.10.1 NB Overview
          1. 10.2.10.1.1 Features Supported
          2. 10.2.10.1.2 NB Parameters
            1. 10.2.10.1.2.1 Compliance to Standards
            2. 10.2.10.1.2.2 Features Not Supported
        2. 10.2.10.2 NB Functional Description
          1. 10.2.10.2.1  VBUSM Slave Interfaces
          2. 10.2.10.2.2  VBUSM Master Interface
          3. 10.2.10.2.3  VBUSM.C Interfaces
            1. 10.2.10.2.3.1 Multi-Threading
            2. 10.2.10.2.3.2 Write Command Crediting
            3. 10.2.10.2.3.3 Early Credit Response
            4. 10.2.10.2.3.4 Priority Escalation
          4. 10.2.10.2.4  Source M2M Bridges
          5. 10.2.10.2.5  Destination M2M Bridge
          6. 10.2.10.2.6  M2C Bridge
          7. 10.2.10.2.7  Memory Attribute Tables
          8. 10.2.10.2.8  Outstanding Read Data Limiter
          9. 10.2.10.2.9  Ordering
          10. 10.2.10.2.10 Quality of Service
          11. 10.2.10.2.11 IDLE Behavior
          12. 10.2.10.2.12 Clock Power Management
        3. 10.2.10.3 NB Registers
          1. 10.2.10.3.1 NAVSS0_NBSS_CFG_REGS0_MMRS Registers
          2. 10.2.10.3.2 NAVSS0_NBSS_NB_CFG_MMRS Registers
    3. 10.3 Peripheral DMA (PDMA)
      1. 10.3.1 PDMA Controller
        1. 10.3.1.1 PDMA Overview
          1. 10.3.1.1.1 PDMA Features
            1. 10.3.1.1.1.1  MCU_PDMA0 (MCU_PDMA_MISC_G0) Features
            2. 10.3.1.1.1.2  MCU_PDMA1 (MCU_PDMA_MISC_G1) Features
            3. 10.3.1.1.1.3  MCU_PDMA2 (MCU_PDMA_MISC_G2) Features
            4. 10.3.1.1.1.4  MCU_PDMA3 (MCU_PDMA_ADC) Features
            5. 10.3.1.1.1.5  PDMA2 (PDMA_DEBUG_CCMCU) Features
            6. 10.3.1.1.1.6  PDMA5 (PDMA_MCAN) Features
            7. 10.3.1.1.1.7  PDMA6 (PDMA_MCASP_G0) Features
            8. 10.3.1.1.1.8  PDMA9 (PDMA_SPI_G0) Features
            9. 10.3.1.1.1.9  PDMA10 (PDMA_SPI_G1) Features
            10. 10.3.1.1.1.10 PDMA13 (PDMA_USART_G0) Features
            11. 10.3.1.1.1.11 PDMA14 (PDMA_USART_G1) Features
            12. 10.3.1.1.1.12 PDMA15 (PDMA_USART_G2) Features
        2. 10.3.1.2 PDMA Integration
          1. 10.3.1.2.1 PDMA Integration in MCU Domain
          2. 10.3.1.2.2 PDMA Integration in MAIN Domain
        3. 10.3.1.3 PDMA Functional Description
          1. 10.3.1.3.1 PDMA Functional Blocks
            1. 10.3.1.3.1.1 Scheduler
            2. 10.3.1.3.1.2 Tx Per-Channel Buffers (TCP FIFO)
            3. 10.3.1.3.1.3 Tx DMA Unit (Tx Engine)
            4. 10.3.1.3.1.4 Rx Per-Channel Buffers (RCP FIFO)
            5. 10.3.1.3.1.5 Rx DMA Unit (Rx Engine)
          2. 10.3.1.3.2 PDMA General Functionality
            1. 10.3.1.3.2.1 Operational States
            2. 10.3.1.3.2.2 Clock Stop
            3. 10.3.1.3.2.3 Emulation Control
          3. 10.3.1.3.3 PDMA Events and Flow Control
            1. 10.3.1.3.3.1 Channel Types
              1. 10.3.1.3.3.1.1 X-Y FIFO Mode
              2. 10.3.1.3.3.1.2 MCAN Mode
              3. 10.3.1.3.3.1.3 AASRC Mode
              4. 10.3.1.3.3.1.4 1290
            2. 10.3.1.3.3.2 Channel Triggering
            3. 10.3.1.3.3.3 Completion Events
          4. 10.3.1.3.4 PDMA Transmit Operation
            1. 10.3.1.3.4.1 Destination (Tx) Channel Allocation
            2. 10.3.1.3.4.2 Destination (Tx) Channel Out-of-Band Signals
            3. 10.3.1.3.4.3 Destination Channel Initialization
              1. 10.3.1.3.4.3.1 PSI-L Destination Thread Pairing
              2. 10.3.1.3.4.3.2 Static Transfer Request Setup
              3. 10.3.1.3.4.3.3 1299
              4. 10.3.1.3.4.3.4 PSI-L Destination Thread Enables
            4. 10.3.1.3.4.4 Data Transfer
              1. 10.3.1.3.4.4.1 X-Y FIFO Mode Channel
                1. 10.3.1.3.4.4.1.1 X-Y FIFO Burst Mode
              2. 10.3.1.3.4.4.2 MCAN Mode Channel
                1. 10.3.1.3.4.4.2.1 MCAN Burst Mode
              3. 10.3.1.3.4.4.3 AASRC Mode Channel
            5. 10.3.1.3.4.5 Tx Pause
            6. 10.3.1.3.4.6 Tx Teardown
            7. 10.3.1.3.4.7 Tx Channel Reset
            8. 10.3.1.3.4.8 Tx Debug/State Registers
          5. 10.3.1.3.5 PDMA Receive Operation
            1. 10.3.1.3.5.1 Source (Rx) Channel Allocation
            2. 10.3.1.3.5.2 Source Channel Initialization
              1. 10.3.1.3.5.2.1 PSI-L Source Thread Pairing
              2. 10.3.1.3.5.2.2 Static Transfer Request Setup
              3. 10.3.1.3.5.2.3 PSI-L Source Thread Enables
            3. 10.3.1.3.5.3 Data Transfer
              1. 10.3.1.3.5.3.1 X-Y FIFO Mode Channel
              2. 10.3.1.3.5.3.2 MCAN Mode Channel
                1. 10.3.1.3.5.3.2.1 MCAN Burst Mode
              3. 10.3.1.3.5.3.3 AASRC Mode Channel
            4. 10.3.1.3.5.4 Rx Pause
            5. 10.3.1.3.5.5 Rx Teardown
            6. 10.3.1.3.5.6 Rx Channel Reset
            7. 10.3.1.3.5.7 Rx Debug/State Register
          6. 10.3.1.3.6 PDMA ECC Support
        4. 10.3.1.4 PDMA Registers
          1. 10.3.1.4.1 PDMA5 ECC Registers
          2. 10.3.1.4.2 PDMA9 ECC Registers
          3. 10.3.1.4.3 PDMA10 ECC Registers
          4. 10.3.1.4.4 PDMA PSI-L TX Configuration Registers
          5. 10.3.1.4.5 PDMA PSI-L RX Configuration Registers
      2. 10.3.2 PDMA Sources
        1. 10.3.2.1 MCU Domain PDMA Event Maps
          1. 10.3.2.1.1 MCU_PDMA_MISC_G0 Event Map
          2. 10.3.2.1.2 MCU_PDMA_MISC_G1 Event Map
          3. 10.3.2.1.3 MCU_PDMA_MISC_G2 Event Map
          4. 10.3.2.1.4 MCU_PDMA_ADC Event Map
        2. 10.3.2.2 MAIN Domain PDMA Event Maps
          1. 10.3.2.2.1 PDMA_DEBUG_CCMCU Event Map
          2. 10.3.2.2.2 PDMA_MCAN Event Map
          3. 10.3.2.2.3 PDMA_MCASP_G0 Event Map
          4. 10.3.2.2.4 PDMA_SPI_G0 Event Map
          5. 10.3.2.2.5 PDMA_SPI_G1 Event Map
          6. 10.3.2.2.6 PDMA_USART_G0 Event Map
          7. 10.3.2.2.7 PDMA_USART_G1 Event Map
          8. 10.3.2.2.8 PDMA_USART_G2 Event Map
  13. 11Time Sync
    1. 11.1 Time Sync Module (CPTS)
      1. 11.1.1 CPTS Overview
        1. 11.1.1.1 CPTS Features
        2. 11.1.1.2 CPTS Not Supported Features
      2. 11.1.2 CPTS Integration
      3. 11.1.3 CPTS Functional Description
        1. 11.1.3.1  CPTS Architecture
        2. 11.1.3.2  CPTS Initialization
        3. 11.1.3.3  32-bit Time Stamp Value
        4. 11.1.3.4  64-bit Time Stamp Value
          1. 11.1.3.4.1 64-Bit Timestamp Nudge
          2. 11.1.3.4.2 64-bit Timestamp PPM
        5. 11.1.3.5  Event FIFO
        6. 11.1.3.6  Timestamp Compare Output
          1. 11.1.3.6.1 Non-Toggle Mode
          2. 11.1.3.6.2 Toggle Mode
        7. 11.1.3.7  Timestamp Sync Output
        8. 11.1.3.8  Timestamp GENF Output
          1. 11.1.3.8.1 GENFn Nudge
          2. 11.1.3.8.2 GENFn PPM
        9. 11.1.3.9  Time Sync Events
          1. 11.1.3.9.1 Time Stamp Push Event
          2. 11.1.3.9.2 Time Stamp Counter Rollover Event (32-bit mode only)
          3. 11.1.3.9.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
          4. 11.1.3.9.4 Hardware Time Stamp Push Event
        10. 11.1.3.10 Timestamp Compare Event
        11. 11.1.3.11 CPTS Interrupt Handling
      4. 11.1.4 CPTS Registers
    2. 11.2 Timer Manager
      1. 11.2.1 Timer Manager Overview
        1. 11.2.1.1 Timer Manager Features
        2. 11.2.1.2 Timer Manager Not Supported Features
      2. 11.2.2 Timer Manager Integration
      3. 11.2.3 Timer Manager Functional Description
        1. 11.2.3.1 Timer Manager Function Overview
        2. 11.2.3.2 Timer Counter
          1. 11.2.3.2.1 Timer Counter Rollover
        3. 11.2.3.3 Timer Control Module (FSM)
        4. 11.2.3.4 Timer Reprogramming
          1. 11.2.3.4.1 Periodic Hardware Timers
        5. 11.2.3.5 Event FIFO
        6. 11.2.3.6 Output Event Lookup (OES RAM)
      4. 11.2.4 Timer Manager Programming Guide
        1. 11.2.4.1 Timer Manager Low-level Programming Models
          1. 11.2.4.1.1 Surrounding Modules Global Initialization
          2. 11.2.4.1.2 Initialization Sequence
          3. 11.2.4.1.3 Real-time Operating Requirements
            1. 11.2.4.1.3.1 Timer Touch
            2. 11.2.4.1.3.2 Timer Disable
            3. 11.2.4.1.3.3 Timer Enable
          4. 11.2.4.1.4 Power Up/Power Down Sequence
      5. 11.2.5 Timer Manager Registers
        1. 11.2.5.1 TIMERMGR_CFG_CFG Registers
        2. 11.2.5.2 TIMERMGR_CFG_OES Registers
        3. 11.2.5.3 TIMERMGR_CFG_TIMERS Registers
    3. 11.3 Time Sync and Compare Events
      1. 11.3.1 Time Sync Architecture
        1. 11.3.1.1 Time Sync Architecture Overview
      2. 11.3.2 Time Sync Routers
        1. 11.3.2.1 Time Sync Routers Overview
        2. 11.3.2.2 Time Sync Routers Integration
          1. 11.3.2.2.1 TIMESYNC_INTRTR0 Integration
          2. 11.3.2.2.2 CMPEVT_INTRTR0 Integration
        3. 11.3.2.3 Time Sync Routers Registers
          1. 11.3.2.3.1 TIMESYNC_INTRTR0 Registers
          2. 11.3.2.3.2 CMPEVT_INTRTR0 Registers
      3. 11.3.3 Time Sync Event Sources
        1. 11.3.3.1 CMPEVT_INTRTR0 Event Map
        2. 11.3.3.2 TIMESYNC_INTRTR0 Event Map
        3. 11.3.3.3 DMSS0 Sync Event Map
        4. 11.3.3.4 PCIE1 Sync Event Map
        5. 11.3.3.5 MCU_CPSW0 Sync Event Map
        6. 11.3.3.6 CPSW0 Sync Event Map
        7. 11.3.3.7 I/O Sync Event Map
  14. 12Peripherals
    1. 12.1 General Connectivity Peripherals
      1. 12.1.1 Analog-to-Digital Converter (ADC)
        1. 12.1.1.1 ADC Overview
          1. 12.1.1.1.1 ADC Features
          2. 12.1.1.1.2 ADC Not Supported Features
        2. 12.1.1.2 ADC Environment
          1. 12.1.1.2.1 ADC Interface Signals
        3. 12.1.1.3 ADC Integration
          1. 12.1.1.3.1 ADC Integration in MCU Domain
        4. 12.1.1.4 ADC Functional Description
          1. 12.1.1.4.1 ADC FSM Sequencer Functional Description
            1. 12.1.1.4.1.1 Step Enable
            2. 12.1.1.4.1.2 Step Configuration
              1. 12.1.1.4.1.2.1 One-Shot (Single) or Continuous Mode
              2. 12.1.1.4.1.2.2 Software- or Hardware-Enabled Steps
              3. 12.1.1.4.1.2.3 Averaging of Samples
              4. 12.1.1.4.1.2.4 Analog Multiplexer Input Select
              5. 12.1.1.4.1.2.5 Differential Control
              6. 12.1.1.4.1.2.6 FIFO Select
              7. 12.1.1.4.1.2.7 Range Check Interrupt Enable
            3. 12.1.1.4.1.3 Open Delay and Sample Delay
              1. 12.1.1.4.1.3.1 Open Delay
              2. 12.1.1.4.1.3.2 Sample Delay
            4. 12.1.1.4.1.4 Interrupts
            5. 12.1.1.4.1.5 Power Management
            6. 12.1.1.4.1.6 DMA Requests
          2. 12.1.1.4.2 ADC AFE Functional Description
            1. 12.1.1.4.2.1 AFE Functional Block Diagram
            2. 12.1.1.4.2.2 ADC GPI Integration
          3. 12.1.1.4.3 ADC FIFOs and DMA
            1. 12.1.1.4.3.1 FIFOs
            2. 12.1.1.4.3.2 DMA
          4. 12.1.1.4.4 ADC Error Correcting Code (ECC)
            1. 12.1.1.4.4.1 Testing ECC Error Injection
          5. 12.1.1.4.5 ADC Functional Internal Diagnostic Debug Mode
        5. 12.1.1.5 ADC Programming Guide
          1. 12.1.1.5.1 ADC Low-Level Programming Models
            1. 12.1.1.5.1.1 Global Initialization
              1. 12.1.1.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.1.5.1.1.2 General Programming Model
            2. 12.1.1.5.1.2 During Operation
        6. 12.1.1.6 ADC Registers
      2. 12.1.2 General-Purpose Interface (GPIO)
        1. 12.1.2.1 GPIO Overview
          1. 12.1.2.1.1 GPIO Features
          2. 12.1.2.1.2 GPIO Not Supported Features
        2. 12.1.2.2 GPIO Environment
          1. 12.1.2.2.1 GPIO Interface Signals
        3. 12.1.2.3 GPIO Integration
          1. 12.1.2.3.1 GPIO Integration in WKUP Domain
          2. 12.1.2.3.2 GPIO Integration in MAIN Domain
        4. 12.1.2.4 GPIO Functional Description
          1. 12.1.2.4.1 GPIO Block Diagram
          2. 12.1.2.4.2 GPIO Function
          3. 12.1.2.4.3 GPIO Interrupt and Event Generation
            1. 12.1.2.4.3.1 Interrupt Enable (per Bank)
            2. 12.1.2.4.3.2 Trigger Configuration (per Bit)
            3. 12.1.2.4.3.3 Interrupt Status and Clear (per Bit)
          4. 12.1.2.4.4 GPIO Interrupt Connectivity
          5. 12.1.2.4.5 GPIO DeepSleep Mode
          6. 12.1.2.4.6 GPIO Emulation Halt Operation
        5. 12.1.2.5 GPIO Programming Guide
          1. 12.1.2.5.1 GPIO Low-Level Programming Models
            1. 12.1.2.5.1.1 Global Initialization
              1. 12.1.2.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.2.5.1.1.2 GPIO Module Global Initialization
            2. 12.1.2.5.1.2 GPIO Operational Modes Configuration
              1. 12.1.2.5.1.2.1 GPIO Read Input Register
              2. 12.1.2.5.1.2.2 GPIO Set Bit Function
              3. 12.1.2.5.1.2.3 GPIO Clear Bit Function
        6. 12.1.2.6 GPIO Registers
      3. 12.1.3 Inter-Integrated Circuit (I2C) Interface
        1. 12.1.3.1 I2C Overview
          1. 12.1.3.1.1 I2C Features
          2. 12.1.3.1.2 I2C Not Supported Features
        2. 12.1.3.2 I2C Environment
          1. 12.1.3.2.1 I2C Typical Application
            1. 12.1.3.2.1.1 I2C Pins for Typical Connections in I2C Mode
            2. 12.1.3.2.1.2 I2C Interface Typical Connections
            3. 12.1.3.2.1.3 1503
          2. 12.1.3.2.2 I2C Typical Connection Protocol and Data Format
            1. 12.1.3.2.2.1  I2C Serial Data Format
            2. 12.1.3.2.2.2  I2C Data Validity
            3. 12.1.3.2.2.3  I2C Start and Stop Conditions
            4. 12.1.3.2.2.4  I2C Addressing
              1. 12.1.3.2.2.4.1 Data Transfer Formats in F/S Mode
              2. 12.1.3.2.2.4.2 Data Transfer Format in HS Mode
            5. 12.1.3.2.2.5  I2C Controller Transmitter
            6. 12.1.3.2.2.6  I2C Controller Receiver
            7. 12.1.3.2.2.7  I2C Target Transmitter
            8. 12.1.3.2.2.8  I2C Target Receiver
            9. 12.1.3.2.2.9  I2C Bus Arbitration
            10. 12.1.3.2.2.10 I2C Clock Generation and Synchronization
        3. 12.1.3.3 I2C Integration
          1. 12.1.3.3.1 I2C Integration in WKUP Domain
          2. 12.1.3.3.2 I2C Integration in MCU Domain
          3. 12.1.3.3.3 I2C Integration in MAIN Domain
        4. 12.1.3.4 I2C Functional Description
          1. 12.1.3.4.1 I2C Block Diagram
          2. 12.1.3.4.2 I2C Clocks
            1. 12.1.3.4.2.1 I2C Clocking
            2. 12.1.3.4.2.2 I2C Automatic Blocking of the I2C Clock Feature
          3. 12.1.3.4.3 I2C Software Reset
          4. 12.1.3.4.4 I2C Power Management
          5. 12.1.3.4.5 I2C Interrupt Requests
          6. 12.1.3.4.6 I2C Programmable Multitarget Channel Feature
          7. 12.1.3.4.7 I2C FIFO Management
            1. 12.1.3.4.7.1 I2C FIFO Interrupt Mode
            2. 12.1.3.4.7.2 I2C FIFO Polling Mode
            3. 12.1.3.4.7.3 I2C Draining Feature
          8. 12.1.3.4.8 I2C Noise Filter
          9. 12.1.3.4.9 I2C System Test Mode
        5. 12.1.3.5 I2C Programming Guide
          1. 12.1.3.5.1 I2C Low-Level Programming Models
            1. 12.1.3.5.1.1 I2C Programming Model
              1. 12.1.3.5.1.1.1 Main Program
                1. 12.1.3.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                2. 12.1.3.5.1.1.1.2 Initialize the I2C Controller
                3. 12.1.3.5.1.1.1.3 Configure Target Address and the Data Control Register
                4. 12.1.3.5.1.1.1.4 Initiate a Transfer
                5. 12.1.3.5.1.1.1.5 Receive Data
                6. 12.1.3.5.1.1.1.6 Transmit Data
              2. 12.1.3.5.1.1.2 Interrupt Subroutine Sequence
              3. 12.1.3.5.1.1.3 Programming Flow-Diagrams
        6. 12.1.3.6 I2C Registers
      4. 12.1.4 Improved Inter-Integrated Circuit (I3C) Interface
        1. 12.1.4.1 I3C Overview
          1. 12.1.4.1.1 I3C Features
          2. 12.1.4.1.2 I3C Not Supported Features
        2. 12.1.4.2 I3C Environment
          1. 12.1.4.2.1 I3C Typical Application
            1. 12.1.4.2.1.1 I3C Pins for Typical Connections
            2. 12.1.4.2.1.2 I3C Interface Typical Connections
            3. 12.1.4.2.1.3 1557
        3. 12.1.4.3 I3C Integration
          1. 12.1.4.3.1 I3C Integration in MCU Domain
          2. 12.1.4.3.2 I3C Integration in MAIN Domain
        4. 12.1.4.4 I3C Functional Description
          1. 12.1.4.4.1  I3C Block Diagram
          2. 12.1.4.4.2  I3C Clock Configuration
            1. 12.1.4.4.2.1 Setting Base Frequencies
            2. 12.1.4.4.2.2 Asymmetric Push-Pull SCL Timing
            3. 12.1.4.4.2.3 Open-Drain SCL Timing
            4. 12.1.4.4.2.4 Changing Programmed Frequencies
          3. 12.1.4.4.3  I3C Interrupt Requests
          4. 12.1.4.4.4  I3C Power Configuration
          5. 12.1.4.4.5  I3C Dynamic Address Management
          6. 12.1.4.4.6  I3C Retaining Registers Space
          7. 12.1.4.4.7  I3C Dynamic Address Assignment Procedure
          8. 12.1.4.4.8  I3C Sending CCC Messages
          9. 12.1.4.4.9  I3C In-Band Interrupt
            1. 12.1.4.4.9.1 Regular I3C Slave In-Band Interrupt
            2. 12.1.4.4.9.2 Current Master Takeover In-Band Interrupt
          10. 12.1.4.4.10 I3C Hot-Join Request
          11. 12.1.4.4.11 I3C Immediate Commands
          12. 12.1.4.4.12 I3C Host Commands
          13. 12.1.4.4.13 I3C Sending Private Data in SDR Messages
            1. 12.1.4.4.13.1 SDR Private Write Message
            2. 12.1.4.4.13.2 SDR Private Read Message
            3. 12.1.4.4.13.3 SDR Payload Length Adjustment
        5. 12.1.4.5 I3C Programming Guide
          1. 12.1.4.5.1 I3C Power-On Programming Model
          2. 12.1.4.5.2 I3C Static Devices Programming
          3. 12.1.4.5.3 I3C DAA Procedure Initiation
          4. 12.1.4.5.4 I3C SDR Write Message Programming Model
          5. 12.1.4.5.5 I3C SDR Read Message Programming Model
          6. 12.1.4.5.6 I3C DDR Write Message Programming Model
          7. 12.1.4.5.7 I3C DDR Read Message Programming Model
        6. 12.1.4.6 I3C Registers
      5. 12.1.5 Multichannel Serial Peripheral Interface (MCSPI)
        1. 12.1.5.1 MCSPI Overview
          1. 12.1.5.1.1 SPI Features
          2. 12.1.5.1.2 MCSPI Not Supported Features
        2. 12.1.5.2 MCSPI Environment
          1. 12.1.5.2.1 Basic MCSPI Pins for Master Mode
          2. 12.1.5.2.2 Basic MCSPI Pins for Slave Mode
          3. 12.1.5.2.3 MCSPI Internal Connectivity
          4. 12.1.5.2.4 MCSPI Protocol and Data Format
            1. 12.1.5.2.4.1 Transfer Format
          5. 12.1.5.2.5 MCSPI in Controller Mode
          6. 12.1.5.2.6 MCSPI in Peripheral Mode
        3. 12.1.5.3 MCSPI Integration
          1. 12.1.5.3.1 MCSPI Integration in MCU Domain
          2. 12.1.5.3.2 MCSPI Integration in MAIN Domain
        4. 12.1.5.4 MCSPI Functional Description
          1. 12.1.5.4.1 SPI Block Diagram
          2. 12.1.5.4.2 MCSPI Reset
          3. 12.1.5.4.3 MCSPI Controller Mode
            1. 12.1.5.4.3.1 Controller Mode Features
            2. 12.1.5.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 12.1.5.4.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 12.1.5.4.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 12.1.5.4.3.5 Single-Channel Controller Mode
              1. 12.1.5.4.3.5.1 Programming Tips When Switching to Another Channel
              2. 12.1.5.4.3.5.2 Force SPIEN[i] Mode
              3. 12.1.5.4.3.5.3 Turbo Mode
            6. 12.1.5.4.3.6 Start-Bit Mode
            7. 12.1.5.4.3.7 Chip-Select Timing Control
            8. 12.1.5.4.3.8 Programmable MCSPI Clock (SPICLK)
              1. 12.1.5.4.3.8.1 Clock Ratio Granularity
          4. 12.1.5.4.4 MCSPI Peripheral Mode
            1. 12.1.5.4.4.1 Dedicated Resources
            2. 12.1.5.4.4.2 Peripheral Transmit-and-Receive Mode
            3. 12.1.5.4.4.3 Peripheral Transmit-Only Mode
            4. 12.1.5.4.4.4 Peripheral Receive-Only Mode
          5. 12.1.5.4.5 MCSPI 3-Pin or 4-Pin Mode
          6. 12.1.5.4.6 MCSPI FIFO Buffer Management
            1. 12.1.5.4.6.1 Buffer Almost Full
            2. 12.1.5.4.6.2 Buffer Almost Empty
            3. 12.1.5.4.6.3 End of Transfer Management
            4. 12.1.5.4.6.4 Multiple MCSPI Word Access
            5. 12.1.5.4.6.5 First MCSPI Word Delay
          7. 12.1.5.4.7 MCSPI Interrupts
            1. 12.1.5.4.7.1 Interrupt Events in Controller Mode
              1. 12.1.5.4.7.1.1 TXx_EMPTY
              2. 12.1.5.4.7.1.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.1.3 RXx_ FULL
              4. 12.1.5.4.7.1.4 End Of Word Count
            2. 12.1.5.4.7.2 Interrupt Events in Peripheral Mode
              1. 12.1.5.4.7.2.1 TXx_EMPTY
              2. 12.1.5.4.7.2.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.2.3 RXx_FULL
              4. 12.1.5.4.7.2.4 RX0_OVERFLOW
              5. 12.1.5.4.7.2.5 End Of Word Count
            3. 12.1.5.4.7.3 Interrupt-Driven Operation
            4. 12.1.5.4.7.4 Polling
          8. 12.1.5.4.8 MCSPI DMA Requests
          9. 12.1.5.4.9 MCSPI Power Saving Management
            1. 12.1.5.4.9.1 Normal Mode
            2. 12.1.5.4.9.2 Idle Mode
              1. 12.1.5.4.9.2.1 Force-Idle Mode
        5. 12.1.5.5 MCSPI Programming Guide
          1. 12.1.5.5.1 MCSPI Global Initialization
            1. 12.1.5.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.5.5.1.2 MCSPI Global Initialization
              1. 12.1.5.5.1.2.1 Main Sequence – MCSPI Global Initialization
          2. 12.1.5.5.2 MCSPI Operational Mode Configuration
            1. 12.1.5.5.2.1 MCSPI Operational Modes
              1. 12.1.5.5.2.1.1 Common Transfer Sequence
              2. 12.1.5.5.2.1.2 End of Transfer Sequences
              3. 12.1.5.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 12.1.5.5.2.1.4 Transmit-Only (Controller and Peripheral)
                1. 12.1.5.5.2.1.4.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.4.2 Based on DMA Write Requests
              5. 12.1.5.5.2.1.5 Controller Normal Receive-Only
                1. 12.1.5.5.2.1.5.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.5.2 Based on DMA Read Requests
              6. 12.1.5.5.2.1.6 Controller Turbo Receive-Only
                1. 12.1.5.5.2.1.6.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.6.2 Based on DMA Read Requests
              7. 12.1.5.5.2.1.7 Peripheral Receive-Only
              8. 12.1.5.5.2.1.8 Transfer Procedures With FIFO
                1. 12.1.5.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 12.1.5.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 12.1.5.5.2.1.8.3 Transmit-and-Receive With Word Count
                4. 12.1.5.5.2.1.8.4 Transmit-and-Receive Without Word Count
                5. 12.1.5.5.2.1.8.5 Transmit-Only
                6. 12.1.5.5.2.1.8.6 Receive-Only With Word Count
                7. 12.1.5.5.2.1.8.7 Receive-Only Without Word Count
              9. 12.1.5.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.5.5.2.1.9.1 Receive-Only Procedure – Polling Method
                2. 12.1.5.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.5.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                4. 12.1.5.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
        6. 12.1.5.6 MCSPI Registers
      6. 12.1.6 Universal Asynchronous Receiver/Transmitter (UART)
        1. 12.1.6.1 UART Overview
          1. 12.1.6.1.1 UART Features
          2. 12.1.6.1.2 IrDA Features
          3. 12.1.6.1.3 CIR Features
          4. 12.1.6.1.4 UART Not Supported Features
        2. 12.1.6.2 UART Environment
          1. 12.1.6.2.1 UART Functional Interfaces
            1. 12.1.6.2.1.1 System Using UART Communication With Hardware Handshake
            2. 12.1.6.2.1.2 UART Interface Description
            3. 12.1.6.2.1.3 UART Protocol and Data Format
            4. 12.1.6.2.1.4 UART 9-bit Mode Data Format
          2. 12.1.6.2.2 RS-485 Functional Interfaces
            1. 12.1.6.2.2.1 System Using RS-485 Communication
            2. 12.1.6.2.2.2 RS-485 Interface Description
          3. 12.1.6.2.3 IrDA Functional Interfaces
            1. 12.1.6.2.3.1 System Using IrDA Communication Protocol
            2. 12.1.6.2.3.2 IrDA Interface Description
            3. 12.1.6.2.3.3 IrDA Protocol and Data Format
              1. 12.1.6.2.3.3.1 SIR Mode
                1. 12.1.6.2.3.3.1.1 Frame Format
                2. 12.1.6.2.3.3.1.2 Asynchronous Transparency
                3. 12.1.6.2.3.3.1.3 Abort Sequence
                4. 12.1.6.2.3.3.1.4 Pulse Shaping
                5. 12.1.6.2.3.3.1.5 Encoder
                6. 12.1.6.2.3.3.1.6 Decoder
                7. 12.1.6.2.3.3.1.7 IR Address Checking
              2. 12.1.6.2.3.3.2 SIR Free-Format Mode
              3. 12.1.6.2.3.3.3 MIR Mode
                1. 12.1.6.2.3.3.3.1 MIR Encoder/Decoder
                2. 12.1.6.2.3.3.3.2 SIP Generation
              4. 12.1.6.2.3.3.4 FIR Mode
          4. 12.1.6.2.4 CIR Functional Interfaces
            1. 12.1.6.2.4.1 System Using CIR Communication Protocol With Remote Control
            2. 12.1.6.2.4.2 CIR Interface Description
            3. 12.1.6.2.4.3 CIR Protocol and Data Format
              1. 12.1.6.2.4.3.1 Carrier Modulation
              2. 12.1.6.2.4.3.2 Pulse Duty Cycle
              3. 12.1.6.2.4.3.3 Consumer IR Encoding/Decoding
        3. 12.1.6.3 UART Integration
          1. 12.1.6.3.1 UART Integration in WKUP Domain
          2. 12.1.6.3.2 UART Integration in MCU Domain
          3. 12.1.6.3.3 UART Integration in MAIN Domain
        4. 12.1.6.4 UART Functional Description
          1. 12.1.6.4.1 UART Block Diagram
          2. 12.1.6.4.2 UART Clock Configuration
          3. 12.1.6.4.3 UART Software Reset
            1. 12.1.6.4.3.1 Independent TX/RX
          4. 12.1.6.4.4 UART Power Management
            1. 12.1.6.4.4.1 UART Mode Power Management
              1. 12.1.6.4.4.1.1 Module Power Saving
              2. 12.1.6.4.4.1.2 System Power Saving
            2. 12.1.6.4.4.2 IrDA Mode Power Management
              1. 12.1.6.4.4.2.1 Module Power Saving
              2. 12.1.6.4.4.2.2 System Power Saving
            3. 12.1.6.4.4.3 CIR Mode Power Management
              1. 12.1.6.4.4.3.1 Module Power Saving
              2. 12.1.6.4.4.3.2 System Power Saving
            4. 12.1.6.4.4.4 Local Power Management
          5. 12.1.6.4.5 UART Interrupt Requests
            1. 12.1.6.4.5.1 UART Mode Interrupt Management
              1. 12.1.6.4.5.1.1 UART Interrupts
              2. 12.1.6.4.5.1.2 Wake-Up Interrupt
            2. 12.1.6.4.5.2 IrDA Mode Interrupt Management
              1. 12.1.6.4.5.2.1 IrDA Interrupts
              2. 12.1.6.4.5.2.2 Wake-Up Interrupts
            3. 12.1.6.4.5.3 CIR Mode Interrupt Management
              1. 12.1.6.4.5.3.1 CIR Interrupts
              2. 12.1.6.4.5.3.2 Wake-Up Interrupts
          6. 12.1.6.4.6 UART FIFO Management
            1. 12.1.6.4.6.1 FIFO Trigger
              1. 12.1.6.4.6.1.1 Transmit FIFO Trigger
              2. 12.1.6.4.6.1.2 Receive FIFO Trigger
            2. 12.1.6.4.6.2 FIFO Interrupt Mode
            3. 12.1.6.4.6.3 FIFO Polled Mode Operation
            4. 12.1.6.4.6.4 FIFO DMA Mode Operation
              1. 12.1.6.4.6.4.1 DMA sequence to disable TX DMA
              2. 12.1.6.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 12.1.6.4.6.4.3 DMA Transmission
              4. 12.1.6.4.6.4.4 DMA Reception
          7. 12.1.6.4.7 UART Mode Selection
            1. 12.1.6.4.7.1 Register Access Modes
              1. 12.1.6.4.7.1.1 Operational Mode and Configuration Modes
              2. 12.1.6.4.7.1.2 Register Access Submode
              3. 12.1.6.4.7.1.3 Registers Available for the Register Access Modes
            2. 12.1.6.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 12.1.6.4.7.2.1 Registers Available for the UART Function
              2. 12.1.6.4.7.2.2 Registers Available for the IrDA Function
              3. 12.1.6.4.7.2.3 Registers Available for the CIR Function
          8. 12.1.6.4.8 UART Protocol Formatting
            1. 12.1.6.4.8.1 UART Mode
              1. 12.1.6.4.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 12.1.6.4.8.1.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.1.3 UART Data Formatting
                1. 12.1.6.4.8.1.3.1 Frame Formatting
                2. 12.1.6.4.8.1.3.2 Hardware Flow Control
                3. 12.1.6.4.8.1.3.3 Software Flow Control
                  1. 1.6.4.8.1.3.3.1 Receive (RX)
                  2. 1.6.4.8.1.3.3.2 Transmit (TX)
                4. 12.1.6.4.8.1.3.4 Autobauding Modes
                5. 12.1.6.4.8.1.3.5 Error Detection
                6. 12.1.6.4.8.1.3.6 Overrun During Receive
                7. 12.1.6.4.8.1.3.7 Time-Out and Break Conditions
                  1. 1.6.4.8.1.3.7.1 Time-Out Counter
                  2. 1.6.4.8.1.3.7.2 Break Condition
            2. 12.1.6.4.8.2 RS-485 Mode
              1. 12.1.6.4.8.2.1 RS-485 External Transceiver Direction Control
            3. 12.1.6.4.8.3 IrDA Mode
              1. 12.1.6.4.8.3.1 IrDA Clock Generation: Baud Generator
              2. 12.1.6.4.8.3.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.3.3 IrDA Data Formatting
                1. 12.1.6.4.8.3.3.1  IR RX Polarity Control
                2. 12.1.6.4.8.3.3.2  IrDA Reception Control
                3. 12.1.6.4.8.3.3.3  IR Address Checking
                4. 12.1.6.4.8.3.3.4  Frame Closing
                5. 12.1.6.4.8.3.3.5  Store and Controlled Transmission
                6. 12.1.6.4.8.3.3.6  Error Detection
                7. 12.1.6.4.8.3.3.7  Underrun During Transmission
                8. 12.1.6.4.8.3.3.8  Overrun During Receive
                9. 12.1.6.4.8.3.3.9  Status FIFO
                10. 12.1.6.4.8.3.3.10 Multi-drop Parity Mode with Address Match
                11. 12.1.6.4.8.3.3.11 Time-guard
              4. 12.1.6.4.8.3.4 SIR Mode Data Formatting
                1. 12.1.6.4.8.3.4.1 Abort Sequence
                2. 12.1.6.4.8.3.4.2 Pulse Shaping
                3. 12.1.6.4.8.3.4.3 SIR Free Format Programming
              5. 12.1.6.4.8.3.5 MIR and FIR Mode Data Formatting
            4. 12.1.6.4.8.4 CIR Mode
              1. 12.1.6.4.8.4.1 CIR Mode Clock Generation
              2. 12.1.6.4.8.4.2 CIR Data Formatting
                1. 12.1.6.4.8.4.2.1 IR RX Polarity Control
                2. 12.1.6.4.8.4.2.2 CIR Transmission
                3. 12.1.6.4.8.4.2.3 CIR Reception
        5. 12.1.6.5 UART Programming Guide
          1. 12.1.6.5.1 UART Global Initialization
            1. 12.1.6.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.6.5.1.2 UART Module Global Initialization
          2. 12.1.6.5.2 UART Mode selection
          3. 12.1.6.5.3 UART Submode selection
          4. 12.1.6.5.4 UART Load FIFO trigger and DMA mode settings
            1. 12.1.6.5.4.1 DMA mode Settings
            2. 12.1.6.5.4.2 FIFO Trigger Settings
          5. 12.1.6.5.5 UART Protocol, Baud rate and interrupt settings
            1. 12.1.6.5.5.1 Baud rate settings
            2. 12.1.6.5.5.2 Interrupt settings
            3. 12.1.6.5.5.3 Protocol settings
            4. 12.1.6.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 12.1.6.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
          6. 12.1.6.5.6 UART Hardware and Software Flow Control Configuration
            1. 12.1.6.5.6.1 Hardware Flow Control Configuration
            2. 12.1.6.5.6.2 Software Flow Control Configuration
          7. 12.1.6.5.7 IrDA Programming Model
            1. 12.1.6.5.7.1 SIR mode
              1. 12.1.6.5.7.1.1 Receive
              2. 12.1.6.5.7.1.2 Transmit
            2. 12.1.6.5.7.2 MIR mode
              1. 12.1.6.5.7.2.1 Receive
              2. 12.1.6.5.7.2.2 Transmit
            3. 12.1.6.5.7.3 FIR mode
              1. 12.1.6.5.7.3.1 Receive
              2. 12.1.6.5.7.3.2 Transmit
        6. 12.1.6.6 UART Registers
    2. 12.2 High-speed Serial Interfaces
      1. 12.2.1 Gigabit Ethernet MAC (MCU_CPSW0)
        1. 12.2.1.1 MCU_CPSW0 Overview
          1. 12.2.1.1.1 MCU_CPSW0 Features
          2. 12.2.1.1.2 MCU_CPSW0 Not Supported Features
          3. 12.2.1.1.3 Terminology
        2. 12.2.1.2 MCU_CPSW0 Environment
          1. 12.2.1.2.1 MCU_CPSW0 RMII Interface
          2. 12.2.1.2.2 MCU_CPSW0 RGMII Interface
        3. 12.2.1.3 MCU_CPSW0 Integration
        4. 12.2.1.4 MCU_CPSW0 Functional Description
          1. 12.2.1.4.1 Functional Block Diagram
          2. 12.2.1.4.2 CPSW Ports
            1. 12.2.1.4.2.1 Interface Mode Selection
          3. 12.2.1.4.3 Clocking
            1. 12.2.1.4.3.1 Subsystem Clocking
            2. 12.2.1.4.3.2 Interface Clocking
              1. 12.2.1.4.3.2.1 RGMII Interface Clocking
              2. 12.2.1.4.3.2.2 RMII Interface Clocking
              3. 12.2.1.4.3.2.3 MDIO Clocking
          4. 12.2.1.4.4 Software IDLE
          5. 12.2.1.4.5 Interrupt Functionality
            1. 12.2.1.4.5.1 EVNT_PEND Interrupt
            2. 12.2.1.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.1.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.1.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.1.4.5.5 MDIO Interrupts
          6. 12.2.1.4.6 CPSW_2G
            1. 12.2.1.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.1.4.6.1.1  Error Handling
              2. 12.2.1.4.6.1.2  Bypass Operations
              3. 12.2.1.4.6.1.3  OUI Deny or Accept
              4. 12.2.1.4.6.1.4  Statistics Counting
              5. 12.2.1.4.6.1.5  Automotive Security Features
              6. 12.2.1.4.6.1.6  CPSW Switching Solutions
                1. 12.2.1.4.6.1.6.1 Basics of 2-port Switch Type
              7. 12.2.1.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.1.4.6.1.7.1 InterVLAN Routing
                2. 12.2.1.4.6.1.7.2 OAM Operations
              8. 12.2.1.4.6.1.8  Supervisory packets
              9. 12.2.1.4.6.1.9  Address Table Entry
                1. 12.2.1.4.6.1.9.1 Free Table Entry
                2. 12.2.1.4.6.1.9.2 Multicast Address Table Entry
                3. 12.2.1.4.6.1.9.3 VLAN/Multicast Address Table Entry
                4. 12.2.1.4.6.1.9.4 Unicast Address Table Entry
                5. 12.2.1.4.6.1.9.5 OUI Unicast Address Table Entry
                6. 12.2.1.4.6.1.9.6 VLAN/Unicast Address Table Entry
                7. 12.2.1.4.6.1.9.7 VLAN Table Entry
              10. 12.2.1.4.6.1.10 ALE Policing and Classification
                1. 12.2.1.4.6.1.10.1 ALE Classification
                  1. 2.1.4.6.1.10.1.1 Classifier to CPPI Transmit Flow ID Mapping
              11. 12.2.1.4.6.1.11 DSCP
              12. 12.2.1.4.6.1.12 Packet Forwarding Processes
                1. 12.2.1.4.6.1.12.1 Ingress Filtering Process
                2. 12.2.1.4.6.1.12.2 VLAN_Aware Lookup Process
                3. 12.2.1.4.6.1.12.3 Egress Process
                4. 12.2.1.4.6.1.12.4 Learning/Updating/Touching Processes
                  1. 2.1.4.6.1.12.4.1 Learning Process
                  2. 2.1.4.6.1.12.4.2 Updating Process
                  3. 2.1.4.6.1.12.4.3 Touching Process
              13. 12.2.1.4.6.1.13 VLAN Aware Mode
              14. 12.2.1.4.6.1.14 VLAN Unaware Mode
            2. 12.2.1.4.6.2  Packet Priority Handling
              1. 12.2.1.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.1.4.6.3  CPPI Port Ingress
            4. 12.2.1.4.6.4  Packet CRC Handling
              1. 12.2.1.4.6.4.1 Transmit VLAN Processing
                1. 12.2.1.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.1.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.1.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.1.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.1.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.1.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.1.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.1.4.6.5  FIFO Memory Control
            6. 12.2.1.4.6.6  FIFO Transmit Queue Control
              1. 12.2.1.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.1.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.1.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.1.4.6.7.1 IET Configuration
            8. 12.2.1.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
              7. 12.2.1.4.6.8.7 Enhanced Scheduled Traffic Packets Per Priority
            9. 12.2.1.4.6.9  Audio Video Bridging
              1. 12.2.1.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.1.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.1.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.1.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.1.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.1.4.6.10 Ethernet MAC Sliver
              1. 12.2.1.4.6.10.1 1947
                1. 12.2.1.4.6.10.1.1 1948
                  1. 2.1.4.6.10.1.1.1 CRC Insertion
                  2. 2.1.4.6.10.1.1.2 MTXER
                  3. 2.1.4.6.10.1.1.3 Adaptive Performance Optimization (APO)
                  4. 2.1.4.6.10.1.1.4 Inter-Packet-Gap Enforcement
                  5. 2.1.4.6.10.1.1.5 Back Off
                  6. 2.1.4.6.10.1.1.6 Programmable Transmit Inter-Packet Gap
                  7. 2.1.4.6.10.1.1.7 Speed, Duplex and Pause Frame Support Negotiation
              2. 12.2.1.4.6.10.2 RMII Interface
                1. 12.2.1.4.6.10.2.1 Features
                2. 12.2.1.4.6.10.2.2 RMII Receive (RX)
                3. 12.2.1.4.6.10.2.3 RMII Transmit (TX)
              3. 12.2.1.4.6.10.3 RGMII Interface
                1. 12.2.1.4.6.10.3.1 Features
                2. 12.2.1.4.6.10.3.2 RGMII Receive (RX)
                3. 12.2.1.4.6.10.3.3 In-Band Mode of Operation
                4. 12.2.1.4.6.10.3.4 Forced Mode of Operation
                5. 12.2.1.4.6.10.3.5 RGMII Transmit (TX)
              4. 12.2.1.4.6.10.4 Frame Classification
              5. 12.2.1.4.6.10.5 Receive FIFO Architecture
            11. 12.2.1.4.6.11 Embedded Memories
            12. 12.2.1.4.6.12 Memory Error Detection and Correction
              1. 12.2.1.4.6.12.1 Packet Header ECC
              2. 12.2.1.4.6.12.2 Packet Protect CRC
              3. 12.2.1.4.6.12.3 Aggregator RAM Control
            13. 12.2.1.4.6.13 Ethernet Port Flow Control
              1. 12.2.1.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.1.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.1.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.1.4.6.13.2 Flow Control Trigger
              3. 12.2.1.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 12.2.1.4.6.15 Ethernet Switch Latency
            16. 12.2.1.4.6.16 MAC Emulation Control
            17. 12.2.1.4.6.17 MAC Command IDLE
            18. 12.2.1.4.6.18 CPSW Network Statistics
              1. 12.2.1.4.6.18.1  Rx-only Statistics Descriptions
                1. 12.2.1.4.6.18.1.1  Good Rx Frames (Offset = 3A000h - Port 0 or Offset = 3A200h - Port 1)
                2. 12.2.1.4.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h - Port 0 or Offset = 3A204h - Port 1)
                3. 12.2.1.4.6.18.1.3  Multicast Rx Frames (Offset = 3A008h - Port 0 or Offset = 3A208h - Port 1)
                4. 12.2.1.4.6.18.1.4  Pause Rx Frames (Offset = 3A20Ch - Port 1)
                5. 12.2.1.4.6.18.1.5  Rx CRC Errors (Offset = 3A010h - Port 0 or Offset = 3A210h - Port 1)
                6. 12.2.1.4.6.18.1.6  Rx Align/Code Errors (Offset = 3A214h - Port 1)
                7. 12.2.1.4.6.18.1.7  Oversize Rx Frames (Offset = 3A018h - Port 0 or Offset = 3A218h - Port 1)
                8. 12.2.1.4.6.18.1.8  Rx Jabbers (Offset = 3A21Ch - Port 1)
                9. 12.2.1.4.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h- Port 0 or Offset = 3A220h - Port 1)
                10. 12.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h - Port 0 or Offset = 3A224h - Port 1)
                11. 12.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A25Ch - Port 1)
                12. 12.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h - Port 0 or Offset = 3A228h - Port 1)
                13. 12.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch - Port 0 or Offset = 3A22Ch - Port 1)
                14. 12.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h - Port 0 or Offset = 3A230h - Port 1)
                15. 12.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h - Port 0 or Offset = 3A284h - Port 1)
                16. 12.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h - Port 0 or Offset = 3A288h - Port 1)
                17. 12.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch - Port 0 or Offset = 3A28Ch - Port 1)
                18. 12.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h - Port 0 or Offset = 3A290h - Port 1)
                19. 12.2.1.4.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h - Port 0 or Offset = 3A294h - Port 1)
                  1. 2.1.4.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h - Port 0 or Offset = 3A298h - Port 1)
                  2. 2.1.4.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch - Port 0 or Offset = 3A29Ch - Port 1)
                  3. 2.1.4.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h - Port 0 or Offset = 3A2A0h - Port 1)
                  4. 2.1.4.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h - Port 0 or Offset = 3A2A4h - Port 1)
                  5. 2.1.4.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h - Port 0 or Offset = 3A2A8h - Port 1)
                  6. 2.1.4.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh - Port 0 or Offset = 3A2ACh - Port 1)
                  7. 2.1.4.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h - Port 0 or Offset = 3A2B0h - Port 1)
                  8. 2.1.4.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h - Port 0 or Offset = 3A2B4h - Port 1)
                  9. 2.1.4.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h - Port 0 or Offset = 3A2B8h - Port 1)
                  10. 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh - Port 0 or Offset = 3A2BCh - Port 1)
                  11. 2.1.4.6.18.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h - Port 0 or Offset = 3A2C0h - Port 1)
              2. 12.2.1.4.6.18.2  ALE Policer Match Red (Offset = 3A0C4h - Port 0 or Offset = 3A2C4h - Port 1)
              3. 12.2.1.4.6.18.3  ALE Policer Match Yellow (Offset = 3A0C8h - Port 0 or Offset = 3A2C8h - Port 1)
              4. 12.2.1.4.6.18.4  IET Receive Assembly Error (Offset = 3A140h - Port 0 or Offset = 3A340h - Port 1)
              5. 12.2.1.4.6.18.5  IET Receive Assembly OK (Offset = 3A144h - Port 0 or Offset = 3A344h - Port 1)
              6. 12.2.1.4.6.18.6  IET Receive SMD Error (Offset = 3A148h - Port 0 or Offset = 3A348h - Port 1)
              7. 12.2.1.4.6.18.7  IET Receive Merge Fragment Count (Offset = 3A14Ch - Port 0 or Offset = 3A34Ch - Port 1)
              8. 12.2.1.4.6.18.8  Tx-only Statistics Descriptions
                1. 12.2.1.4.6.18.8.1  Good Tx Frames (Offset = 3A034h - Port 0 or Offset = 3A234h - Port 1)
                2. 12.2.1.4.6.18.8.2  Broadcast Tx Frames (Offset = 3A038h - Port 0 or Offset = 3A238h - Port 1)
                3. 12.2.1.4.6.18.8.3  Multicast Tx Frames (Offset = 3A03Ch - Port 0 or Offset = 3A23Ch - Port 1)
                4. 12.2.1.4.6.18.8.4  Pause Tx Frames (Offset = 3A240h - Port 1)
                5. 12.2.1.4.6.18.8.5  Deferred Tx Frames (Offset = 3A244h - Port 1)
                6. 12.2.1.4.6.18.8.6  Collisions (Offset = 3A248h - Port 1)
                7. 12.2.1.4.6.18.8.7  Single Collision Tx Frames (Offset = 3A24Ch - Port 1)
                8. 12.2.1.4.6.18.8.8  Multiple Collision Tx Frames (Offset = 3A250h - Port 1)
                9. 12.2.1.4.6.18.8.9  Excessive Collisions (Offset = 3A254h - Port 1)
                10. 12.2.1.4.6.18.8.10 Late Collisions (Offset = 3A258h - Port 1)
                11. 12.2.1.4.6.18.8.11 Carrier Sense Errors (Offset = 3A260h - Port 1)
                12. 12.2.1.4.6.18.8.12 Tx Octets (Offset = 3A064h - Port 0 or Offset = 3A264h - Port 1 )
                13. 12.2.1.4.6.18.8.13 Transmit Priority 0-7 (Offset = 3A380h to 3A3A8h - Port 1)
                14. 12.2.1.4.6.18.8.14 Transmit Priority 0-7 Drop (Offset = 3A3C0h to 3A3E8 - Port 1)
                15. 12.2.1.4.6.18.8.15 Tx Memory Protect Errors (Offset = 3A17Ch - Port 0 or Offset = 3A37Ch - Port 1)
                16. 12.2.1.4.6.18.8.16 IET Transmit Merge Hold Count (Offset = 3A350h - Port 1)
                17. 12.2.1.4.6.18.8.17 IET Transmit Merge Fragment Count (Offset = 3A154h - Port 0 or Offset = 3A354h - Port 1)
              9. 12.2.1.4.6.18.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.1.4.6.18.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h - Port 0 or Offset = 3A268h - Port 1)
                2. 12.2.1.4.6.18.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch - Port 0 or Offset = 3A26Ch - Port 1)
                3. 12.2.1.4.6.18.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h - Port 0 or Offset = 3A270h - Port 1)
                4. 12.2.1.4.6.18.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h - Port 0 or Offset = 3A274h - Port 1)
                5. 12.2.1.4.6.18.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h - Port 0 or Offset = 3A278h - Port 1)
                6. 12.2.1.4.6.18.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch - Port 0 or Offset = 3A27Ch - Port 1)
                7. 12.2.1.4.6.18.9.7 Net Octets (Offset = 3A080h - Port 0 or Offset = 3A280h - Port 1)
              10. 12.2.1.4.6.18.10 2047
          7. 12.2.1.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.1.4.7.1  MCU_CPSW0 CPTS Integration
            2. 12.2.1.4.7.2  CPTS Architecture
            3. 12.2.1.4.7.3  CPTS Initialization
            4. 12.2.1.4.7.4  32-bit Time Stamp Value
            5. 12.2.1.4.7.5  64-bit Time Stamp Value
            6. 12.2.1.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.1.4.7.7  64-bit Timestamp PPM
            8. 12.2.1.4.7.8  Event FIFO
            9. 12.2.1.4.7.9  Timestamp Compare Output
              1. 12.2.1.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.1.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.1.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.1.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.1.4.7.10 Timestamp Sync Output
            11. 12.2.1.4.7.11 Timestamp GENFn Output
              1. 12.2.1.4.7.11.1 GENFn Nudge
              2. 12.2.1.4.7.11.2 GENFn PPM
            12. 12.2.1.4.7.12 Timestamp ESTFn
            13. 12.2.1.4.7.13 Time Sync Events
              1. 12.2.1.4.7.13.1 Time Stamp Push Event
              2. 12.2.1.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.1.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.1.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.1.4.7.13.5 Ethernet Port Events
                1. 12.2.1.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.1.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.1.4.7.13.5.3 2075
            14. 12.2.1.4.7.14 Timestamp Compare Event
              1. 12.2.1.4.7.14.1 32-Bit Mode
              2. 12.2.1.4.7.14.2 64-Bit Mode
            15. 12.2.1.4.7.15 Host Transmit Event
            16. 12.2.1.4.7.16 CPTS Interrupt Handling
          8. 12.2.1.4.8 CPPI Streaming Packet Interface
            1. 12.2.1.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_2G Egress)
            2. 12.2.1.4.8.2 Port 0 CPPI Receive Packet Streaming Interface (CPSW_2G Ingress)
            3. 12.2.1.4.8.3 CPPI Checksum Offload
              1. 12.2.1.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.1.4.8.3.1.1 IPV4 UDP
                2. 12.2.1.4.8.3.1.2 IPV4 TCP
                3. 12.2.1.4.8.3.1.3 IPV6 UDP
                4. 12.2.1.4.8.3.1.4 IPV6 TCP
            4. 12.2.1.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.1.4.8.5 Egress Packet Operations
          9. 12.2.1.4.9 MII Management Interface (MDIO)
            1. 12.2.1.4.9.1 MDIO Frame Formats
            2. 12.2.1.4.9.2 MDIO Functional Description
        5. 12.2.1.5 MCU_CPSW0 Programming Guide
          1. 12.2.1.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.1.5.2 CPSW Reset
          3. 12.2.1.5.3 MDIO Software Interface
            1. 12.2.1.5.3.1 Initializing the MDIO Module
            2. 12.2.1.5.3.2 Writing Data To a PHY Register
            3. 12.2.1.5.3.3 Reading Data From a PHY Register
        6. 12.2.1.6 MCU_CPSW0 Registers
          1. 12.2.1.6.1  MCU_CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.1.6.2  MCU_CPSW0_SGMII Registers
          3. 12.2.1.6.3  MCU_CPSW0_MDIO Registers
          4. 12.2.1.6.4  MCU_CPSW0_CPTS Registers
          5. 12.2.1.6.5  MCU_CPSW0_CONTROL Registers
          6. 12.2.1.6.6  MCU_CPSW0_CPINT Registers
          7. 12.2.1.6.7  MCU_CPSW0_RAM Registers
          8. 12.2.1.6.8  MCU_CPSW0_STAT0 Registers
          9. 12.2.1.6.9  MCU_CPSW0_STAT1 Registers
          10. 12.2.1.6.10 MCU_CPSW0_ALE Registers
          11. 12.2.1.6.11 MCU_CPSW0_ECC Registers
      2. 12.2.2 Gigabit Ethernet Switch (CPSW0)
        1. 12.2.2.1 CPSW0 Overview
          1. 12.2.2.1.1 CPSW0 Features
          2. 12.2.2.1.2 CPSW0 Not Supported Features
          3. 12.2.2.1.3 Terminology
        2. 12.2.2.2 CPSW0 Environment
          1. 12.2.2.2.1 CPSW0 RMII Interface
          2. 12.2.2.2.2 CPSW0 RGMII Interface
        3. 12.2.2.3 CPSW0 Integration
        4. 12.2.2.4 CPSW0 Functional Description
          1. 12.2.2.4.1 Functional Block Diagram
          2. 12.2.2.4.2 CPSW Ports
            1. 12.2.2.4.2.1 Interface Mode Selection
          3. 12.2.2.4.3 Clocking
            1. 12.2.2.4.3.1 Subsystem Clocking
            2. 12.2.2.4.3.2 Interface Clocking
              1. 12.2.2.4.3.2.1 RGMII Interface Clocking
              2. 12.2.2.4.3.2.2 RMII Interface Clocking
              3. 12.2.2.4.3.2.3 MDIO Clocking
          4. 12.2.2.4.4 Software IDLE
          5. 12.2.2.4.5 Interrupt Functionality
            1. 12.2.2.4.5.1 EVNT_PEND Interrupt
            2. 12.2.2.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.2.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.2.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.2.4.5.5 MDIO Interrupts
          6. 12.2.2.4.6 CPSW_5X
            1. 12.2.2.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.2.4.6.1.1  Error Handling
              2. 12.2.2.4.6.1.2  Bypass Operations
              3. 12.2.2.4.6.1.3  OUI Deny or Accept
              4. 12.2.2.4.6.1.4  Statistics Counting
              5. 12.2.2.4.6.1.5  Automotive Security Features
              6. 12.2.2.4.6.1.6  CPSW Switching Solutions
                1. 12.2.2.4.6.1.6.1 Basics of 5-port Switch Type
              7. 12.2.2.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.2.4.6.1.7.1 InterVLAN Routing
                2. 12.2.2.4.6.1.7.2 OAM Operations
              8. 12.2.2.4.6.1.8  Supervisory packets
              9. 12.2.2.4.6.1.9  Address Table Entry
                1. 12.2.2.4.6.1.9.1  Free Table Entry
                2. 12.2.2.4.6.1.9.2  Multicast Address Table Entry (Bit 40 == 0)
                3. 12.2.2.4.6.1.9.3  Multicast Address Table Entry (Bit 40 == 1)
                4. 12.2.2.4.6.1.9.4  VLAN Unicast Address Table Entry (Bit 40 == 0)
                5. 12.2.2.4.6.1.9.5  OUI Unicast Address Table Entry
                6. 12.2.2.4.6.1.9.6  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                7. 12.2.2.4.6.1.9.7  VLAN/ Multicast Address Table Entry (Bit 40 == 1)
                8. 12.2.2.4.6.1.9.8  Inner VLAN Table Entry
                9. 12.2.2.4.6.1.9.9  Outer VLAN Table Entry
                10. 12.2.2.4.6.1.9.10 EtherType Table Entry
                11. 12.2.2.4.6.1.9.11 IPv4 Table Entry
                12. 12.2.2.4.6.1.9.12 IPv6 Table Entry High
                13. 12.2.2.4.6.1.9.13 IPv6 Table Entry Low
              10. 12.2.2.4.6.1.10 Multicast Address
                1. 12.2.2.4.6.1.10.1 Multicast Ranges
              11. 12.2.2.4.6.1.11 Supervisory Packets
              12. 12.2.2.4.6.1.12 Aging and Auto Aging
              13. 12.2.2.4.6.1.13 ALE Policing and Classification
                1. 12.2.2.4.6.1.13.1 ALE Policing
                2. 12.2.2.4.6.1.13.2 Classifier to Host Thread Mapping
                3. 12.2.2.4.6.1.13.3 ALE Classification
                  1. 2.2.4.6.1.13.3.1 Classifier to CPPI Transmit Flow ID Mapping
              14. 12.2.2.4.6.1.14 Mirroring
              15. 12.2.2.4.6.1.15 Trunking
              16. 12.2.2.4.6.1.16 DSCP
              17. 12.2.2.4.6.1.17 Packet Forwarding Processes
                1. 12.2.2.4.6.1.17.1 Ingress Filtering Process
                2. 12.2.2.4.6.1.17.2 VLAN_Aware Lookup Process
                3. 12.2.2.4.6.1.17.3 Egress Process
                4. 12.2.2.4.6.1.17.4 Learning/Updating/Touching Processes
                  1. 2.2.4.6.1.17.4.1 Learning Process
                  2. 2.2.4.6.1.17.4.2 Updating Process
                  3. 2.2.4.6.1.17.4.3 Touching Process
              18. 12.2.2.4.6.1.18 VLAN Aware Mode
              19. 12.2.2.4.6.1.19 VLAN Unaware Mode
            2. 12.2.2.4.6.2  Packet Priority Handling
              1. 12.2.2.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.2.4.6.3  CPPI Port Ingress
            4. 12.2.2.4.6.4  Packet CRC Handling
              1. 12.2.2.4.6.4.1 Transmit VLAN Processing
                1. 12.2.2.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.2.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.2.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.2.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.2.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.2.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.2.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.2.4.6.5  FIFO Memory Control
            6. 12.2.2.4.6.6  FIFO Transmit Queue Control
              1. 12.2.2.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.2.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.2.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.2.4.6.7.1 IET Configuration
            8. 12.2.2.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.2.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.2.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.2.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.2.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.2.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.2.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
            9. 12.2.2.4.6.9  Audio Video Bridging
              1. 12.2.2.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.2.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.2.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.2.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.2.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.2.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.2.4.6.10 Ethernet MAC Sliver
              1. 12.2.2.4.6.10.1  CRC Insertion
              2. 12.2.2.4.6.10.2  MTXER
              3. 12.2.2.4.6.10.3  Adaptive Performance Optimization (APO)
              4. 12.2.2.4.6.10.4  Inter-Packet-Gap Enforcement
              5. 12.2.2.4.6.10.5  Back Off
              6. 12.2.2.4.6.10.6  Programmable Transmit Inter-Packet Gap
              7. 12.2.2.4.6.10.7  Speed, Duplex and Pause Frame Support Negotiation
              8. 12.2.2.4.6.10.8  RMII Interface
                1. 12.2.2.4.6.10.8.1 Features
                2. 12.2.2.4.6.10.8.2 RMII Receive (RX)
                3. 12.2.2.4.6.10.8.3 RMII Transmit (TX)
              9. 12.2.2.4.6.10.9  RGMII Interface
                1. 12.2.2.4.6.10.9.1 Features
                2. 12.2.2.4.6.10.9.2 RGMII Receive (RX)
                3. 12.2.2.4.6.10.9.3 In-Band Mode of Operation
                4. 12.2.2.4.6.10.9.4 Forced Mode of Operation
                5. 12.2.2.4.6.10.9.5 RGMII Transmit (TX)
              10. 12.2.2.4.6.10.10 Frame Classification
              11. 12.2.2.4.6.10.11 Receive FIFO Architecture
            11. 12.2.2.4.6.11 Embedded Memories
            12. 12.2.2.4.6.12 Memory Error Detection and Correction
              1. 12.2.2.4.6.12.1 Packet Header ECC
              2. 12.2.2.4.6.12.2 Packet Protect CRC
              3. 12.2.2.4.6.12.3 Aggregator RAM Control
            13. 12.2.2.4.6.13 Ethernet Port Flow Control
              1. 12.2.2.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.2.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.2.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.2.4.6.13.2 Qbb (10/100/1G/10G) Receive Priority Based Flow Control (PFC)
              3. 12.2.2.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.2.4.6.14 PFC Trigger Rules
              1. 12.2.2.4.6.14.1 Destination Based Rule
              2. 12.2.2.4.6.14.2 Sum of Outflows Rule
              3. 12.2.2.4.6.14.3 Sum of Blocks Per Port Rule
              4. 12.2.2.4.6.14.4 Sum of Blocks Total Rule
              5. 12.2.2.4.6.14.5 Top of Receive FIFO Rule
            15. 12.2.2.4.6.15 Energy Efficient Ethernet Support (802.3az)
            16. 12.2.2.4.6.16 Ethernet Switch Latency
            17. 12.2.2.4.6.17 MAC Emulation Control
            18. 12.2.2.4.6.18 MAC Command IDLE
            19. 12.2.2.4.6.19 CPSW Network Statistics
              1. 12.2.2.4.6.19.1  Rx-only Statistics Descriptions
                1. 12.2.2.4.6.19.1.1  Good Rx Frames (Offset = 3A000h)
                2. 12.2.2.4.6.19.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 12.2.2.4.6.19.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 12.2.2.4.6.19.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 12.2.2.4.6.19.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 12.2.2.4.6.19.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 12.2.2.4.6.19.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 12.2.2.4.6.19.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 12.2.2.4.6.19.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 12.2.2.4.6.19.1.10 Rx Fragments (Offset = 3A024h)
                11. 12.2.2.4.6.19.1.11 RX IPG Error
                12. 12.2.2.4.6.19.1.12 ALE Drop (Offset = 3A028h)
                13. 12.2.2.4.6.19.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 12.2.2.4.6.19.1.14 Rx Octets (Offset = 3A030h)
                15. 12.2.2.4.6.19.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 12.2.2.4.6.19.1.16 Portmask Drop (Offset = 3A088h)
                17. 12.2.2.4.6.19.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 12.2.2.4.6.19.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 12.2.2.4.6.19.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.2.4.6.19.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.2.4.6.19.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.2.4.6.19.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.2.4.6.19.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.2.4.6.19.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.2.4.6.19.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.2.4.6.19.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.2.4.6.19.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.2.4.6.19.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.2.4.6.19.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.2.4.6.19.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h)
              2. 12.2.2.4.6.19.2  ALE Policer Match Red (Offset = 3A0C4h)
              3. 12.2.2.4.6.19.3  ALE Policer Match Yellow (Offset = 3A0C8h)
              4. 12.2.2.4.6.19.4  IET Receive Assembly Error (Offset = 3A140h)
              5. 12.2.2.4.6.19.5  IET Receive Assembly OK (Offset = 3A144h)
              6. 12.2.2.4.6.19.6  IET Receive SMD Error (Offset = 3A148h)
              7. 12.2.2.4.6.19.7  IET Receive Merge Fragment Count (Offset = 3A14Ch)
              8. 12.2.2.4.6.19.8  Tx-only Statistics Descriptions
                1. 12.2.2.4.6.19.8.1  Good Tx Frames (Offset = 3A034h)
                2. 12.2.2.4.6.19.8.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 12.2.2.4.6.19.8.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 12.2.2.4.6.19.8.4  Pause Tx Frames (Offset = 3A040h)
                5. 12.2.2.4.6.19.8.5  Deferred Tx Frames (Offset = 3A044h)
                6. 12.2.2.4.6.19.8.6  Collisions (Offset = 3A048h)
                7. 12.2.2.4.6.19.8.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 12.2.2.4.6.19.8.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 12.2.2.4.6.19.8.9  Excessive Collisions (Offset = 3A054h)
                10. 12.2.2.4.6.19.8.10 Late Collisions (Offset = 3A058h)
                11. 12.2.2.4.6.19.8.11 Carrier Sense Errors (Offset = 3A060h)
                12. 12.2.2.4.6.19.8.12 Tx Octets (Offset = 3A064h)
                13. 12.2.2.4.6.19.8.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 12.2.2.4.6.19.8.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8h)
                15. 12.2.2.4.6.19.8.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 12.2.2.4.6.19.8.16 IET Transmit Merge Fragment Count (Offset = 3A14Ch)
                17. 12.2.2.4.6.19.8.17 IET Transmit Merge Hold Count (Offset = 3A150h)
              9. 12.2.2.4.6.19.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.2.4.6.19.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 12.2.2.4.6.19.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 12.2.2.4.6.19.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 12.2.2.4.6.19.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 12.2.2.4.6.19.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 12.2.2.4.6.19.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 12.2.2.4.6.19.9.7 Net Octets (Offset = 3A080h)
              10. 12.2.2.4.6.19.10 2326
          7. 12.2.2.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.2.4.7.1  CPSW0 CPTS Integration
            2. 12.2.2.4.7.2  CPTS Architecture
            3. 12.2.2.4.7.3  CPTS Initialization
            4. 12.2.2.4.7.4  32-bit Time Stamp Value
            5. 12.2.2.4.7.5  64-bit Time Stamp Value
            6. 12.2.2.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.2.4.7.7  64-bit Timestamp PPM
            8. 12.2.2.4.7.8  Event FIFO
            9. 12.2.2.4.7.9  Timestamp Compare Output
              1. 12.2.2.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.2.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.2.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.2.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.2.4.7.10 Timestamp Sync Output
            11. 12.2.2.4.7.11 Timestamp GENFn Output
              1. 12.2.2.4.7.11.1 GENFn Nudge
              2. 12.2.2.4.7.11.2 GENFn PPM
            12. 12.2.2.4.7.12 Timestamp ESTFn
            13. 12.2.2.4.7.13 Time Sync Events
              1. 12.2.2.4.7.13.1 Time Stamp Push Event
              2. 12.2.2.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.2.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.2.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.2.4.7.13.5 Ethernet Port Events
                1. 12.2.2.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.2.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.2.4.7.13.5.3 2354
            14. 12.2.2.4.7.14 Timestamp Compare Event
              1. 12.2.2.4.7.14.1 32-Bit Mode
              2. 12.2.2.4.7.14.2 64-Bit Mode
            15. 12.2.2.4.7.15 Host Transmit Event
            16. 12.2.2.4.7.16 CPTS Interrupt Handling
          8. 12.2.2.4.8 CPPI Streaming Packet Interface
            1. 12.2.2.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_5X Egress)
            2. 12.2.2.4.8.2 CPPI Receive Packet Streaming Interface (CPSW Ingress)
            3. 12.2.2.4.8.3 CPPI Checksum Offload
              1. 12.2.2.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.2.4.8.3.1.1 IPV4 UDP
                2. 12.2.2.4.8.3.1.2 IPV4 TCP
                3. 12.2.2.4.8.3.1.3 IPV6 UDP
                4. 12.2.2.4.8.3.1.4 IPV6 TCP
            4. 12.2.2.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.2.4.8.5 Egress Packet Operations
          9. 12.2.2.4.9 MII Management Interface (MDIO)
            1. 12.2.2.4.9.1 MDIO Frame Formats
            2. 12.2.2.4.9.2 MDIO Functional Description
        5. 12.2.2.5 CPSW0 Programming Guide
          1. 12.2.2.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.2.5.2 Ethernet MAC Reset or XGMII/GMII Mode Change Configuration
          3. 12.2.2.5.3 MDIO Software Interface
            1. 12.2.2.5.3.1 Initializing the MDIO Module
            2. 12.2.2.5.3.2 Writing Data To a PHY Register
            3. 12.2.2.5.3.3 Reading Data From a PHY Register
        6. 12.2.2.6 CPSW0 Registers
          1. 12.2.2.6.1  CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.2.6.2  CPSW0_SGMII Registers
          3. 12.2.2.6.3  CPSW0_MDIO Registers
          4. 12.2.2.6.4  CPSW0_CPTS Registers
          5. 12.2.2.6.5  CPSW0_CONTROL Registers
          6. 12.2.2.6.6  CPSW0_CPINT Registers
          7. 12.2.2.6.7  CPSW0_RAM Registers
          8. 12.2.2.6.8  CPSW0_STAT Registers
          9. 12.2.2.6.9  CPSW0_ALE Registers
          10. 12.2.2.6.10 CPSW0_PCSR Registers
          11. 12.2.2.6.11 CPSW0_ECC Registers
      3. 12.2.3 Peripheral Component Interconnect Express (PCIe) Subsystem
        1. 12.2.3.1 PCIe Subsystem Overview
          1. 12.2.3.1.1 PCIe Subsystem Features
          2. 12.2.3.1.2 PCIe Subsystem Not Supported Features
        2. 12.2.3.2 PCIe Subsystem Environment
        3. 12.2.3.3 PCIe Subsystem Integration
        4. 12.2.3.4 PCIe Subsystem Functional Description
          1. 12.2.3.4.1  PCIe Subsystem Block Diagram
            1. 12.2.3.4.1.1 PCIe Core Module
            2. 12.2.3.4.1.2 PCIe PHY Interface
            3. 12.2.3.4.1.3 CBA Infrastructure
            4. 12.2.3.4.1.4 VBUSM to AXI Bridges
            5. 12.2.3.4.1.5 AXI to VBUSM Bridges
            6. 12.2.3.4.1.6 VBUSP to APB Bridge
            7. 12.2.3.4.1.7 Custom Logic
          2. 12.2.3.4.2  PCIe Subsystem Reset Schemes
            1. 12.2.3.4.2.1 PCIe Conventional Reset
            2. 12.2.3.4.2.2 PCIe Function Level Reset
            3. 12.2.3.4.2.3 PCIe Reset Isolation
              1. 12.2.3.4.2.3.1 Root Port Reset with Device Not Reset
              2. 12.2.3.4.2.3.2 Device Reset with Root Port Not Reset
              3. 12.2.3.4.2.3.3 End Point Device Reset with Root Port Not Reset
              4. 12.2.3.4.2.3.4 Device Reset with End Point Device Not Reset
            4. 12.2.3.4.2.4 PCIe Reset Limitations
            5. 12.2.3.4.2.5 PCIe Reset Requirements
          3. 12.2.3.4.3  PCIe Subsystem Power Management
            1. 12.2.3.4.3.1 CBA Power Management
          4. 12.2.3.4.4  PCIe Subsystem Interrupts
            1. 12.2.3.4.4.1 Interrupts Aggregation
            2. 12.2.3.4.4.2 Interrupt Generation in EP Mode
              1. 12.2.3.4.4.2.1 Legacy Interrupt Generation in EP Mode
              2. 12.2.3.4.4.2.2 MSI and MSI-X Interrupt Generation
            3. 12.2.3.4.4.3 Interrupt Reception in EP Mode
              1. 12.2.3.4.4.3.1 PCIe Core Downstream Interrupts
              2. 12.2.3.4.4.3.2 PCIe Core Function Level Reset Interrupts
              3. 12.2.3.4.4.3.3 PCIe Core Power Management Event Interrupts
              4. 12.2.3.4.4.3.4 PCIe Core Hot Reset Request Interrupt
              5. 12.2.3.4.4.3.5 PTM Valid Interrupt
            4. 12.2.3.4.4.4 Interrupt Generation in RP Mode
            5. 12.2.3.4.4.5 Interrupt Reception in RP Mode
              1. 12.2.3.4.4.5.1 PCIe Legacy Interrupt Reception in RP Mode
              2. 12.2.3.4.4.5.2 MSI/MSI-X Interrupt Reception in RP Mode
              3. 12.2.3.4.4.5.3 Advanced Error Reporting Interrupt
            6. 12.2.3.4.4.6 Common Interrupt Reception in RP and EP Modes
              1. 12.2.3.4.4.6.1 PCIe Local Interrupt
              2. 12.2.3.4.4.6.2 PHY Interrupt
              3. 12.2.3.4.4.6.3 Link down Interrupt
              4. 12.2.3.4.4.6.4 Transaction Error Interrupts
              5. 12.2.3.4.4.6.5 Power Management Event Interrupt
              6. 12.2.3.4.4.6.6 Active Internal Diagnostics Interrupts
            7. 12.2.3.4.4.7 ECC Aggregator Interrupts
            8. 12.2.3.4.4.8 CPTS Interrupt
          5. 12.2.3.4.5  PCIe Subsystem DMA Support
            1. 12.2.3.4.5.1 PCIe DMA Support in RP Mode
            2. 12.2.3.4.5.2 PCIe DMA Support in EP Mode
          6. 12.2.3.4.6  PCIe Subsystem Transactions
            1. 12.2.3.4.6.1 PCIe Supported Transactions
            2. 12.2.3.4.6.2 PCIe Transaction Limitations
          7. 12.2.3.4.7  PCIe Subsystem Address Translation
            1. 12.2.3.4.7.1 PCIe Inbound Address Translation
              1. 12.2.3.4.7.1.1 Root Port Inbound PCIe to AXI Address Translation
              2. 12.2.3.4.7.1.2 End Point Inbound PCIe to AXI Address Translation
            2. 12.2.3.4.7.2 PCIe Outbound Address Translation
              1. 12.2.3.4.7.2.1 PCIe Outbound Address Translation Bypass
          8. 12.2.3.4.8  PCIe Subsystem Virtualization Support
            1. 12.2.3.4.8.1 End Point SR-IOV Support
            2. 12.2.3.4.8.2 Root Port ATS Support
            3. 12.2.3.4.8.3 VirtID Mapping
          9. 12.2.3.4.9  PCIe Subsystem Quality-of-Service (QoS)
          10. 12.2.3.4.10 PCIe Subsystem Precision Time Measurement (PTM)
          11. 12.2.3.4.11 PCIe Subsystem Loopback
            1. 12.2.3.4.11.1 PCIe PIPE Loopback
              1. 12.2.3.4.11.1.1 PIPE Loopback Master Mode
              2. 12.2.3.4.11.1.2 PIPE Loopback Slave Mode
          12. 12.2.3.4.12 PCIe Subsystem Error Handling
            1. 12.2.3.4.12.1 PCIe AXI to/from VBUSM Bus Error Mapping
          13. 12.2.3.4.13 PCIe Subsystem Internal Diagnostics Features
            1. 12.2.3.4.13.1 PCIe Parity
            2. 12.2.3.4.13.2 ECC Aggregators
            3. 12.2.3.4.13.3 RAM ECC Inversion
          14. 12.2.3.4.14 LTSSM State Encoding
        5. 12.2.3.5 PCIe Subsystem Registers
          1. 12.2.3.5.1  PCIE_CORE_EP_PF Registers
          2. 12.2.3.5.2  PCIE_CORE_EP_VF Registers
          3. 12.2.3.5.3  PCIE_CORE_RP Registers
          4. 12.2.3.5.4  PCIE_CORE_LM Registers
          5. 12.2.3.5.5  PCIE_CORE_AXI Registers
          6. 12.2.3.5.6  PCIE_INTD Registers
          7. 12.2.3.5.7  PCIE_VMAP Registers
          8. 12.2.3.5.8  PCIE_CPTS Registers
          9. 12.2.3.5.9  PCIE_USER_CFG Registers
          10. 12.2.3.5.10 PCIE_ECC_AGGR0 Registers
          11. 12.2.3.5.11 PCIE_ECC_AGGR1 Registers
          12. 12.2.3.5.12 PCIE_DAT0 Registers
          13. 12.2.3.5.13 PCIE_DAT1 Registers
      4. 12.2.4 Universal Serial Bus (USB) Subsystem
        1. 12.2.4.1 USB Overview
          1. 12.2.4.1.1 USB Features
          2. 12.2.4.1.2 USB Not Supported Features
          3. 12.2.4.1.3 USB Terminology
        2. 12.2.4.2 USB Environment
        3. 12.2.4.3 USB Integration
        4. 12.2.4.4 USB Functional Description
          1. 12.2.4.4.1 USB Type-C Connector Support
          2. 12.2.4.4.2 USB Controller Reset
          3. 12.2.4.4.3 Overcurrent Detection
          4. 12.2.4.4.4 Top-Level Initialization Sequence
        5. 12.2.4.5 USB Registers
          1. 12.2.4.5.1 USB3P0SS_MMR_MMRVBP_USBSS_CMN Registers
          2. 12.2.4.5.2 USB_ECC_AGGR_CFG Registers
          3. 12.2.4.5.3 USB_RAMS_INJ_CFG Registers
      5. 12.2.5 Serializer/Deserializer (SerDes)
        1. 12.2.5.1 SerDes Overview
          1. 12.2.5.1.1 SerDes Features
          2. 12.2.5.1.2 Industry Standards Compatibility
        2. 12.2.5.2 SerDes Environment
          1. 12.2.5.2.1 SerDes I/Os
        3. 12.2.5.3 SerDes Integration
          1. 12.2.5.3.1 WIZ Settings
            1. 12.2.5.3.1.1 Interface Selection
            2. 12.2.5.3.1.2 Reference Clock Distribution
            3. 12.2.5.3.1.3 Internal Reference Clock Selection
        4. 12.2.5.4 SerDes Functional Description
          1. 12.2.5.4.1 SerDes Block Diagram
          2. 12.2.5.4.2 SerDes Programming Guide
    3. 12.3 Memory Interfaces
      1. 12.3.1 Flash Subsystem (FSS)
        1. 12.3.1.1 FSS Overview
          1. 12.3.1.1.1 FSS Features
          2. 12.3.1.1.2 FSS Not Supported Features
        2. 12.3.1.2 FSS Environment
          1. 12.3.1.2.1 FSS Typical Application
        3. 12.3.1.3 FSS Integration
          1. 12.3.1.3.1 FSS Integration in MCU Domain
        4. 12.3.1.4 FSS Functional Description
          1. 12.3.1.4.1 FSS Block Diagram
          2. 12.3.1.4.2 FSS ECC Support
            1. 12.3.1.4.2.1 FSS ECC Calculation
          3. 12.3.1.4.3 FSS Modes of Operation
          4. 12.3.1.4.4 FSS Regions
            1. 12.3.1.4.4.1 FSS Regions Boot Size Configuration
          5. 12.3.1.4.5 FSS Memory Regions
        5. 12.3.1.5 FSS Programming Guide
          1. 12.3.1.5.1 FSS Initialization Sequence
          2. 12.3.1.5.2 FSS Real-Time Operation
          3. 12.3.1.5.3 FSS Power Up/Down Sequence
        6. 12.3.1.6 FSS Registers
      2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
        1. 12.3.2.1 OSPI Overview
          1. 12.3.2.1.1 OSPI Features
          2. 12.3.2.1.2 OSPI Not Supported Features
        2. 12.3.2.2 OSPI Environment
        3. 12.3.2.3 OSPI Integration
          1. 12.3.2.3.1 OSPI Integration in MCU Domain
        4. 12.3.2.4 OSPI Functional Description
          1. 12.3.2.4.1  OSPI Block Diagram
            1. 12.3.2.4.1.1 Data Target Interface
            2. 12.3.2.4.1.2 Configuration Target Interface
            3. 12.3.2.4.1.3 OSPI Clock Domains
          2. 12.3.2.4.2  OSPI Modes
            1. 12.3.2.4.2.1 Read Data Capture
              1. 12.3.2.4.2.1.1 Mechanisms of Data Capturing
              2. 12.3.2.4.2.1.2 Data Capturing Mechanism Using Taps
              3. 12.3.2.4.2.1.3 Data Capturing Mechanism Using PHY Module
            2. 12.3.2.4.2.2 External Pull Down on DQS
          3. 12.3.2.4.3  OSPI Power Management
          4. 12.3.2.4.4  Auto HW Polling
          5. 12.3.2.4.5  Flash Reset
          6. 12.3.2.4.6  OSPI Memory Regions
          7. 12.3.2.4.7  OSPI Interrupt Requests
          8. 12.3.2.4.8  OSPI Data Interface
            1. 12.3.2.4.8.1 Data Interface Address Remapping
            2. 12.3.2.4.8.2 Write Protection
            3. 12.3.2.4.8.3 Access Forwarding
          9. 12.3.2.4.9  OSPI Direct Access Controller (DAC)
          10. 12.3.2.4.10 OSPI Indirect Access Controller (INDAC)
            1. 12.3.2.4.10.1 Indirect Read Controller
              1. 12.3.2.4.10.1.1 Indirect Read Transfer Process
            2. 12.3.2.4.10.2 Indirect Write Controller
              1. 12.3.2.4.10.2.1 Indirect Write Transfer Process
            3. 12.3.2.4.10.3 Indirect Access Queuing
            4. 12.3.2.4.10.4 Consecutive Writes and Reads Using Indirect Transfers
            5. 12.3.2.4.10.5 Accessing the SRAM
          11. 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG)
            1. 12.3.2.4.11.1 Servicing a STIG Request
            2. 12.3.2.4.11.2 2578
          12. 12.3.2.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
          13. 12.3.2.4.13 OSPI Command Translation
          14. 12.3.2.4.14 Selecting the Flash Instruction Type
          15. 12.3.2.4.15 OSPI Data Integrity
          16. 12.3.2.4.16 OSPI PHY Module
            1. 12.3.2.4.16.1 PHY Pipeline Mode
            2. 12.3.2.4.16.2 Read Data Capturing by the PHY Module
        5. 12.3.2.5 OSPI Programming Guide
          1. 12.3.2.5.1 Configuring the OSPI Controller for Use After Reset
          2. 12.3.2.5.2 Configuring the OSPI Controller for Optimal Use
          3. 12.3.2.5.3 Using the Flash Command Control Register (STIG Operation)
          4. 12.3.2.5.4 Using SPI Legacy Mode
          5. 12.3.2.5.5 Entering XIP Mode from POR
          6. 12.3.2.5.6 Entering XIP Mode Otherwise
          7. 12.3.2.5.7 Exiting XIP Mode
        6. 12.3.2.6 OSPI Registers
      3. 12.3.3 HyperBus Interface
        1. 12.3.3.1 HyperBus Overview
          1. 12.3.3.1.1 HyperBus Features
          2. 12.3.3.1.2 HyperBus Not Supported Features
        2. 12.3.3.2 HyperBus Environment
        3. 12.3.3.3 HyperBus Integration
          1. 12.3.3.3.1 HyperBus Integration in MCU Domain
        4. 12.3.3.4 HyperBus Functional Description
          1. 12.3.3.4.1 HyperBus Interrupts
          2. 12.3.3.4.2 HyperBus ECC Support
            1. 12.3.3.4.2.1 ECC Aggregator
          3. 12.3.3.4.3 HyperBus Internal FIFOs
          4. 12.3.3.4.4 HyperBus Data Regions
          5. 12.3.3.4.5 HyperBus True Continuous Read (TCR) Mode
        5. 12.3.3.5 HyperBus Programming Guide
          1. 12.3.3.5.1 HyperBus Initialization Sequence
            1. 12.3.3.5.1.1 HyperFlash Access
            2. 12.3.3.5.1.2 HyperRAM Access
          2. 12.3.3.5.2 HyperBus Real-time Operating Requirements
          3. 12.3.3.5.3 HyperBus Power Up/Down Sequence
        6. 12.3.3.6 HyperBus Registers
      4. 12.3.4 General-Purpose Memory Controller (GPMC)
        1. 12.3.4.1 GPMC Overview
          1. 12.3.4.1.1 GPMC Features
          2. 12.3.4.1.2 GPMC Not Supported Features
        2. 12.3.4.2 GPMC Environment
          1. 12.3.4.2.1 GPMC Modes
          2. 12.3.4.2.2 GPMC I/O Signals
        3. 12.3.4.3 GPMC Integration
          1. 12.3.4.3.1 GPMC Integration in MAIN Domain
        4. 12.3.4.4 GPMC Functional Description
          1. 12.3.4.4.1  GPMC Block Diagram
          2. 12.3.4.4.2  GPMC Clock Configuration
          3. 12.3.4.4.3  GPMC Power Management
          4. 12.3.4.4.4  GPMC Interrupt Requests
          5. 12.3.4.4.5  GPMC Interconnect Port Interface
          6. 12.3.4.4.6  GPMC Address and Data Bus
            1. 12.3.4.4.6.1 GPMC I/O Configuration Setting
          7. 12.3.4.4.7  GPMC Address Decoder and Chip-Select Configuration
            1. 12.3.4.4.7.1 Chip-Select Base Address and Region Size
            2. 12.3.4.4.7.2 Access Protocol
              1. 12.3.4.4.7.2.1 Supported Devices
              2. 12.3.4.4.7.2.2 Access Size Adaptation and Device Width
              3. 12.3.4.4.7.2.3 Address/Data-Multiplexing Interface
            3. 12.3.4.4.7.3 External Signals
              1. 12.3.4.4.7.3.1 WAIT Pin Monitoring Control
                1. 12.3.4.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 12.3.4.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 12.3.4.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 12.3.4.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 12.3.4.4.7.3.1.5 Wait With NAND Device
                6. 12.3.4.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.4.4.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.4.4.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.4.4.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 12.3.4.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 12.3.4.4.7.3.2 DIR Pin
              3. 12.3.4.4.7.3.3 Reset
              4. 12.3.4.4.7.3.4 Write Protect Signal (nWP)
              5. 12.3.4.4.7.3.5 Byte Enable (nBE1/nBE0)
            4. 12.3.4.4.7.4 Error Handling
          8. 12.3.4.4.8  GPMC Timing Setting
            1. 12.3.4.4.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 12.3.4.4.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 12.3.4.4.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 12.3.4.4.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 12.3.4.4.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 12.3.4.4.8.6  GPMC_CLKOUT
            7. 12.3.4.4.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 12.3.4.4.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 12.3.4.4.8.8.1 Access Time on Read Access
              2. 12.3.4.4.8.8.2 Access Time on Write Access
            9. 12.3.4.4.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 12.3.4.4.8.9.1 Page Burst Access Time on Read Access
              2. 12.3.4.4.8.9.2 Page Burst Access Time on Write Access
            10. 12.3.4.4.8.10 Bus Keeping Support
          9. 12.3.4.4.9  GPMC NOR Access Description
            1. 12.3.4.4.9.1 Asynchronous Access Description
              1. 12.3.4.4.9.1.1 Access on Address/Data Multiplexed Devices
                1. 12.3.4.4.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 12.3.4.4.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 12.3.4.4.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 12.3.4.4.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 12.3.4.4.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 12.3.4.4.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 12.3.4.4.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 12.3.4.4.9.2 Synchronous Access Description
              1. 12.3.4.4.9.2.1 Synchronous Single Read
              2. 12.3.4.4.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 12.3.4.4.9.2.3 Synchronous Single Write
              4. 12.3.4.4.9.2.4 Synchronous Multiple (Burst) Write
            3. 12.3.4.4.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 12.3.4.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 12.3.4.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 12.3.4.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 12.3.4.4.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 12.3.4.4.9.4 Page and Burst Support
            5. 12.3.4.4.9.5 System Burst vs External Device Burst Support
          10. 12.3.4.4.10 GPMC pSRAM Access Specificities
          11. 12.3.4.4.11 GPMC NAND Access Description
            1. 12.3.4.4.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 12.3.4.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 12.3.4.4.11.1.2 NAND Device Command and Address Phase Control
              3. 12.3.4.4.11.1.3 Command Latch Cycle
              4. 12.3.4.4.11.1.4 Address Latch Cycle
              5. 12.3.4.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 12.3.4.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 12.3.4.4.11.1.7 Read and Write Access Size Adaptation
                1. 12.3.4.4.11.1.7.1 8-Bit-Wide NAND Device
                2. 12.3.4.4.11.1.7.2 16-Bit-Wide NAND Device
            2. 12.3.4.4.11.2 NAND Device-Ready Pin
              1. 12.3.4.4.11.2.1 Ready Pin Monitored by Software Polling
              2. 12.3.4.4.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 12.3.4.4.11.3 ECC Calculator
              1. 12.3.4.4.11.3.1 Hamming Code
                1. 12.3.4.4.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 12.3.4.4.11.3.1.2 ECC Enabling
                3. 12.3.4.4.11.3.1.3 ECC Computation
                4. 12.3.4.4.11.3.1.4 ECC Comparison and Correction
                5. 12.3.4.4.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 12.3.4.4.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 12.3.4.4.11.3.2 BCH Code
                1. 12.3.4.4.11.3.2.1 Requirements
                2. 12.3.4.4.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.4.4.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.4.4.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.4.4.11.3.2.2.3 Wrapping Modes
                    1. 4.4.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 4.4.11.3.2.2.3.2  Mode 0x1
                    3. 4.4.11.3.2.2.3.3  Mode 0xA (10)
                    4. 4.4.11.3.2.2.3.4  Mode 0x2
                    5. 4.4.11.3.2.2.3.5  Mode 0x3
                    6. 4.4.11.3.2.2.3.6  Mode 0x7
                    7. 4.4.11.3.2.2.3.7  Mode 0x8
                    8. 4.4.11.3.2.2.3.8  Mode 0x4
                    9. 4.4.11.3.2.2.3.9  Mode 0x9
                    10. 4.4.11.3.2.2.3.10 Mode 0x5
                    11. 4.4.11.3.2.2.3.11 Mode 0xB (11)
                    12. 4.4.11.3.2.2.3.12 Mode 0x6
                3. 12.3.4.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.4.4.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.4.4.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.4.4.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 12.3.4.4.11.4 Prefetch and Write-Posting Engine
              1. 12.3.4.4.11.4.1 General Facts About the Engine Configuration
              2. 12.3.4.4.11.4.2 Prefetch Mode
              3. 12.3.4.4.11.4.3 FIFO Control in Prefetch Mode
              4. 12.3.4.4.11.4.4 Write-Posting Mode
              5. 12.3.4.4.11.4.5 FIFO Control in Write-Posting Mode
              6. 12.3.4.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 12.3.4.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 12.3.4.4.12 GPMC Use Cases and Tips
            1. 12.3.4.4.12.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 12.3.4.4.12.1.1 External Memory Attached to the GPMC Module
              2. 12.3.4.4.12.1.2 Typical GPMC Setup
                1. 12.3.4.4.12.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 12.3.4.4.12.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 12.3.4.4.12.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 12.3.4.4.12.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 12.3.4.4.12.2.1 Supported Memories or Devices
                1. 12.3.4.4.12.2.1.1 Memory Pin Multiplexing
                2. 12.3.4.4.12.2.1.2 NAND Interface Protocol
                3. 12.3.4.4.12.2.1.3 NOR Interface Protocol
                4. 12.3.4.4.12.2.1.4 Other Technologies
        5. 12.3.4.5 GPMC Basic Programming Model
          1. 12.3.4.5.1 GPMC High-Level Programming Model Overview
          2. 12.3.4.5.2 GPMC Initialization
          3. 12.3.4.5.3 GPMC Configuration in NOR Mode
          4. 12.3.4.5.4 GPMC Configuration in NAND Mode
          5. 12.3.4.5.5 Set Memory Access
          6. 12.3.4.5.6 GPMC Timing Parameters
            1. 12.3.4.5.6.1 GPMC Timing Parameters Formulas
              1. 12.3.4.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 12.3.4.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 12.3.4.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
        6. 12.3.4.6 GPMC Registers
      5. 12.3.5 Error Location Module (ELM)
        1. 12.3.5.1 ELM Overview
          1. 12.3.5.1.1 ELM Features
          2. 12.3.5.1.2 ELM Not Supported Features
        2. 12.3.5.2 ELM Integration
          1. 12.3.5.2.1 ELM Integration in MAIN Domain
        3. 12.3.5.3 ELM Functional Description
          1. 12.3.5.3.1 ELM Software Reset
          2. 12.3.5.3.2 ELM Power Management
          3. 12.3.5.3.3 ELM Interrupt Requests
          4. 12.3.5.3.4 ELM Processing Initialization
          5. 12.3.5.3.5 ELM Processing Sequence
          6. 12.3.5.3.6 ELM Processing Completion
        4. 12.3.5.4 ELM Basic Programming Model
          1. 12.3.5.4.1 ELM Low-Level Programming Model
            1. 12.3.5.4.1.1 Processing Initialization
            2. 12.3.5.4.1.2 Read Results
            3. 12.3.5.4.1.3 2788
          2. 12.3.5.4.2 Use Case: ELM Used in Continuous Mode
          3. 12.3.5.4.3 Use Case: ELM Used in Page Mode
        5. 12.3.5.5 ELM Registers
      6. 12.3.6 Multi-Media Card Secure Digital (MMCSD) Interface
        1. 12.3.6.1 MMCSD Overview
          1. 12.3.6.1.1 MMCSD Features
          2. 12.3.6.1.2 MMCSD Not Supported Features
        2. 12.3.6.2 MMCSD Environment
          1. 12.3.6.2.1 Protocol and Data Format
            1. 12.3.6.2.1.1 Protocol
            2. 12.3.6.2.1.2 Data Format
              1. 12.3.6.2.1.2.1 Coding Scheme for Command Token
              2. 12.3.6.2.1.2.2 Coding Scheme for Response Token
              3. 12.3.6.2.1.2.3 Coding Scheme for Data Token
        3. 12.3.6.3 MMCSD Integration
          1. 12.3.6.3.1 MMCSD Integration in MAIN Domain
        4. 12.3.6.4 MMCSD Functional Description
          1. 12.3.6.4.1 Block Diagram
          2. 12.3.6.4.2 Memory Regions
          3. 12.3.6.4.3 Interrupt Requests
          4. 12.3.6.4.4 ECC Support
            1. 12.3.6.4.4.1 ECC Aggregator
          5. 12.3.6.4.5 Advanced DMA
          6. 12.3.6.4.6 eMMC PHY BIST
            1. 12.3.6.4.6.1 BIST Overview
            2. 12.3.6.4.6.2 BIST Modes
              1. 12.3.6.4.6.2.1 DS Mode
              2. 12.3.6.4.6.2.2 HS Mode with TXDLY using DLL
              3. 12.3.6.4.6.2.3 HS Mode with TXDLY using Delay Chain
              4. 12.3.6.4.6.2.4 DDR50 Mode with TXDLY using DLL
              5. 12.3.6.4.6.2.5 DDR50 Mode with TXDLY using Delay Chain
              6. 12.3.6.4.6.2.6 HS200 Mode with TX/RXDLY using DLL
              7. 12.3.6.4.6.2.7 HS200 Mode with TX/RXDLY using Delay Chain
              8. 12.3.6.4.6.2.8 HS400 Mode
            3. 12.3.6.4.6.3 BIST Functionality
            4. 12.3.6.4.6.4 Signal Interface
            5. 12.3.6.4.6.5 Programming Flow
              1. 12.3.6.4.6.5.1 DS Mode
                1. 12.3.6.4.6.5.1.1 Configuration
                2. 12.3.6.4.6.5.1.2 BIST Programming
              2. 12.3.6.4.6.5.2 HS Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.2.1 Configuration
                2. 12.3.6.4.6.5.2.2 BIST Programming
              3. 12.3.6.4.6.5.3 HS Mode with DLL
                1. 12.3.6.4.6.5.3.1 Configuration
                2. 12.3.6.4.6.5.3.2 BIST Programming
              4. 12.3.6.4.6.5.4 DDR52 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.4.1 Configuration
                2. 12.3.6.4.6.5.4.2 BIST Programming
              5. 12.3.6.4.6.5.5 DDR52 Mode with DLL
                1. 12.3.6.4.6.5.5.1 Configuration
                2. 12.3.6.4.6.5.5.2 BIST Programming
              6. 12.3.6.4.6.5.6 HS200 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.6.1 Configuration
                2. 12.3.6.4.6.5.6.2 BIST Programming
              7. 12.3.6.4.6.5.7 HS200 Mode with DLL
                1. 12.3.6.4.6.5.7.1 Configuration
                2. 12.3.6.4.6.5.7.2 BIST Programming
              8. 12.3.6.4.6.5.8 HS400 Mode with DLL
                1. 12.3.6.4.6.5.8.1 Configuration
                2. 12.3.6.4.6.5.8.2 BIST Programming
            6. 12.3.6.4.6.6 HS200 BIST Result Check Procedure
        5. 12.3.6.5 MMCSD Programming Guide
          1. 12.3.6.5.1 Sequences
            1. 12.3.6.5.1.1  SD Card Detection
            2. 12.3.6.5.1.2  SD Clock Control
              1. 12.3.6.5.1.2.1 Internal Clock Setup Sequence
              2. 12.3.6.5.1.2.2 SD Clock Supply and Stop Sequence
              3. 12.3.6.5.1.2.3 SD Clock Frequency Change Sequence
            3. 12.3.6.5.1.3  SD Bus Power Control
            4. 12.3.6.5.1.4  Changing Bus Width
            5. 12.3.6.5.1.5  Timeout Setting on DAT Line
            6. 12.3.6.5.1.6  Card Initialization and Identification (for SD I/F)
              1. 12.3.6.5.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
            7. 12.3.6.5.1.7  SD Transaction Generation
              1. 12.3.6.5.1.7.1 Transaction Control without Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.1.1 The Sequence to Issue a SD Command
                2. 12.3.6.5.1.7.1.2 The Sequence to Finalize a Command
                3. 12.3.6.5.1.7.1.3 2867
              2. 12.3.6.5.1.7.2 Transaction Control with Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.2.1 Not using DMA
                2. 12.3.6.5.1.7.2.2 Using SDMA
                3. 12.3.6.5.1.7.2.3 Using ADMA
            8. 12.3.6.5.1.8  Abort Transaction
              1. 12.3.6.5.1.8.1 Asynchronous Abort
              2. 12.3.6.5.1.8.2 Synchronous Abort
            9. 12.3.6.5.1.9  Changing Bus Speed Mode
            10. 12.3.6.5.1.10 Error Recovery
              1. 12.3.6.5.1.10.1 Error Interrupt Recovery
              2. 12.3.6.5.1.10.2 Auto CMD12 Error Recovery
            11. 12.3.6.5.1.11 Wakeup Control (Optional)
            12. 12.3.6.5.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
              1. 12.3.6.5.1.12.1 Suspend Sequence
              2. 12.3.6.5.1.12.2 Resume Sequence
              3. 12.3.6.5.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
              4. 12.3.6.5.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
          2. 12.3.6.5.2 Driver Flow Sequence
            1. 12.3.6.5.2.1 Host Controller Setup and Card Detection
              1. 12.3.6.5.2.1.1 Host Controller Setup Sequence
              2. 12.3.6.5.2.1.2 Card Interface Detection Sequence
            2. 12.3.6.5.2.2 Boot Operation
              1. 12.3.6.5.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
              2. 12.3.6.5.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
              3. 12.3.6.5.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
            3. 12.3.6.5.2.3 Retuning procedure (For Legacy Interface)
              1. 12.3.6.5.2.3.1 Sampling Clock Tuning
              2. 12.3.6.5.2.3.2 Tuning Modes
              3. 12.3.6.5.2.3.3 Re-Tuning Mode 2
            4. 12.3.6.5.2.4 Command Queuing Driver Flow Sequence
              1. 12.3.6.5.2.4.1 Command Queuing Initialization Sequence
              2. 12.3.6.5.2.4.2 Task Issuance Sequence
              3. 12.3.6.5.2.4.3 Task Execution and Completion Sequence
              4. 12.3.6.5.2.4.4 Task Discard and Clear Sequence
              5. 12.3.6.5.2.4.5 Error Detect and Recovery when CQ is enabled
        6. 12.3.6.6 MMCSD Registers
          1. 12.3.6.6.1 MMCSD0 Subsystem Registers
          2. 12.3.6.6.2 MMCSD0 RX RAM ECC Aggregator Registers
          3. 12.3.6.6.3 MMCSD0 TX RAM ECC Aggregator Registers
          4. 12.3.6.6.4 MMCSD0 Host Controller Registers
          5. 12.3.6.6.5 MMCSD1 Subsystem Registers
          6. 12.3.6.6.6 MMCSD1 RX RAM ECC Aggregator Registers
          7. 12.3.6.6.7 MMCSD1 TX RAM ECC Aggregator Registers
          8. 12.3.6.6.8 MMCSD1 Host Controller Registers
    4. 12.4 Industrial and Control Interfaces
      1. 12.4.1 Enhanced Capture (ECAP) Module
        1. 12.4.1.1 ECAP Overview
          1. 12.4.1.1.1 ECAP Features
        2. 12.4.1.2 ECAP Environment
          1. 12.4.1.2.1 ECAP I/O Interface
        3. 12.4.1.3 ECAP Integration
          1. 12.4.1.3.1 Daisy-Chain Connectivity between ECAP Modules
        4. 12.4.1.4 ECAP Functional Description
          1. 12.4.1.4.1 Capture and APWM Operating Modes
            1. 12.4.1.4.1.1 ECAP Capture Mode Description
              1. 12.4.1.4.1.1.1 ECAP Event Prescaler
              2. 12.4.1.4.1.1.2 ECAP Edge Polarity Select and Qualifier
              3. 12.4.1.4.1.1.3 ECAP Continuous/One-Shot Control
              4. 12.4.1.4.1.1.4 ECAP 32-Bit Counter and Phase Control
              5. 12.4.1.4.1.1.5 CAP1-CAP4 Registers
              6. 12.4.1.4.1.1.6 ECAP Interrupt Control
              7. 12.4.1.4.1.1.7 ECAP Shadow Load and Lockout Control
            2. 12.4.1.4.1.2 ECAP APWM Mode Operation
          2. 12.4.1.4.2 Summary of ECAP Functional Registers
        5. 12.4.1.5 ECAP Use Cases
          1. 12.4.1.5.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
            1. 12.4.1.5.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
          2. 12.4.1.5.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
          3. 12.4.1.5.3 Time Difference (Delta) Operation Rising Edge Trigger Example
            1. 12.4.1.5.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
          4. 12.4.1.5.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
          5. 12.4.1.5.5 Application of the APWM Mode
            1. 12.4.1.5.5.1 Simple PWM Generation (Independent Channel/s) Example
              1. 12.4.1.5.5.1.1 Code Snippet for APWM Mode
            2. 12.4.1.5.5.2 Multichannel PWM Generation with Synchronization Example
              1. 12.4.1.5.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
            3. 12.4.1.5.5.3 Multichannel PWM Generation with Phase Control Example
              1. 12.4.1.5.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
        6. 12.4.1.6 ECAP Registers
      2. 12.4.2 Enhanced Pulse Width Modulation (EPWM) Module
        1. 12.4.2.1 EPWM Overview
          1. 12.4.2.1.1 EPWM Features
          2. 12.4.2.1.2 EPWM Not Supported Features
          3. 12.4.2.1.3 2953
        2. 12.4.2.2 EPWM Environment
          1. 12.4.2.2.1 EPWM I/O Interface
        3. 12.4.2.3 EPWM Integration
          1. 12.4.2.3.1 Device Specific EPWM Features
          2. 12.4.2.3.2 Daisy-Chain Connectivity between EPWM Modules
          3. 12.4.2.3.3 ADC start of conversion signals (PWM_SOCA and PWM_SOCB)
          4. 12.4.2.3.4 EPWM Modules Time Base Clock Gating
        4. 12.4.2.4 EPWM Functional Description
          1. 12.4.2.4.1  EPWM Submodule Features
            1. 12.4.2.4.1.1 Constant Definitions Used in the EPWM Code Examples
          2. 12.4.2.4.2  EPWM Time-Base (TB) Submodule
            1. 12.4.2.4.2.1 Overview
            2. 12.4.2.4.2.2 2966
            3. 12.4.2.4.2.3 Controlling and Monitoring the EPWM Time-Base Submodule
            4. 12.4.2.4.2.4 Calculating PWM Period and Frequency
              1. 12.4.2.4.2.4.1 EPWM Time-Base Period Shadow Register
              2. 12.4.2.4.2.4.2 EPWM Time-Base Counter Synchronization
            5. 12.4.2.4.2.5 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
            6. 12.4.2.4.2.6 EPWM Time-Base Counter Modes and Timing Waveforms
          3. 12.4.2.4.3  EPWM Counter-Compare (CC) Submodule
            1. 12.4.2.4.3.1 Overview
            2. 12.4.2.4.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
            3. 12.4.2.4.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
            4. 12.4.2.4.3.4 EPWM Counter-Compare Submodule Timing Waveforms
          4. 12.4.2.4.4  EPWM Action-Qualifier (AQ) Submodule
            1. 12.4.2.4.4.1 Overview
            2. 12.4.2.4.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
            3. 12.4.2.4.4.3 EPWM Action-Qualifier Event Priority
            4. 12.4.2.4.4.4 Waveforms for Common EPWM Configurations
          5. 12.4.2.4.5  EPWM Dead-Band Generator (DB) Submodule
            1. 12.4.2.4.5.1 Overview
            2. 12.4.2.4.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
            3. 12.4.2.4.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
          6. 12.4.2.4.6  EPWM-Chopper (PC) Submodule
            1. 12.4.2.4.6.1 Overview
            2. 12.4.2.4.6.2 2989
            3. 12.4.2.4.6.3 Controlling the EPWM-Chopper Submodule
            4. 12.4.2.4.6.4 Operational Highlights for the EPWM-Chopper Submodule
            5. 12.4.2.4.6.5 EPWM-Chopper Waveforms
              1. 12.4.2.4.6.5.1 EPWM-Chopper One-Shot Pulse
              2. 12.4.2.4.6.5.2 EPWM-Chopper Duty Cycle Control
          7. 12.4.2.4.7  EPWM Trip-Zone (TZ) Submodule
            1. 12.4.2.4.7.1 Overview
            2. 12.4.2.4.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
            3. 12.4.2.4.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
            4. 12.4.2.4.7.4 Generating EPWM Trip-Event Interrupts
          8. 12.4.2.4.8  EPWM Event-Trigger (ET) Submodule
            1. 12.4.2.4.8.1 Overview
            2. 12.4.2.4.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
            3. 12.4.2.4.8.3 Operational Overview of the EPWM Event-Trigger Submodule
            4. 12.4.2.4.8.4 3004
          9. 12.4.2.4.9  EPWM High Resolution (HRPWM) Submodule
            1. 12.4.2.4.9.1 Overview
            2. 12.4.2.4.9.2 Architecture of the High-Resolution PWM Submodule
            3. 12.4.2.4.9.3 Controlling and Monitoring the High-Resolution PWM Submodule
            4. 12.4.2.4.9.4 Configuring the High-Resolution PWM Submodule
            5. 12.4.2.4.9.5 Operational Highlights for the High-Resolution PWM Submodule
              1. 12.4.2.4.9.5.1 HRPWM Edge Positioning
              2. 12.4.2.4.9.5.2 HRPWM Scaling Considerations
              3. 12.4.2.4.9.5.3 HRPWM Duty Cycle Range Limitation
          10. 12.4.2.4.10 EPWM / HRPWM Functional Register Groups
          11. 12.4.2.4.11 Proper EPWM Interrupt Initialization Procedure
        5. 12.4.2.5 EPWM Registers
      3. 12.4.3 Enhanced Quadrature Encoder Pulse (EQEP) Module
        1. 12.4.3.1 EQEP Overview
          1. 12.4.3.1.1 EQEP Features
          2. 12.4.3.1.2 EQEP Not Supported Features
        2. 12.4.3.2 EQEP Environment
          1. 12.4.3.2.1 EQEP I/O Interface
        3. 12.4.3.3 EQEP Integration
          1. 12.4.3.3.1 Device Specific EQEP Features
        4. 12.4.3.4 EQEP Functional Description
          1. 12.4.3.4.1 EQEP Inputs
          2. 12.4.3.4.2 EQEP Quadrature Decoder Unit (QDU)
            1. 12.4.3.4.2.1 EQEP Position Counter Input Modes
              1. 12.4.3.4.2.1.1 Quadrature Count Mode
              2. 12.4.3.4.2.1.2 EQEP Direction-count Mode
              3. 12.4.3.4.2.1.3 EQEP Up-Count Mode
              4. 12.4.3.4.2.1.4 EQEP Down-Count Mode
            2. 12.4.3.4.2.2 EQEP Input Polarity Selection
            3. 12.4.3.4.2.3 EQEP Position-Compare Sync Output
          3. 12.4.3.4.3 EQEP Position Counter and Control Unit (PCCU)
            1. 12.4.3.4.3.1 EQEP Position Counter Operating Modes
              1. 12.4.3.4.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
              2. 12.4.3.4.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
              3. 12.4.3.4.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
              4. 12.4.3.4.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
            2. 12.4.3.4.3.2 EQEP Position Counter Latch
              1. 12.4.3.4.3.2.1 Index Event Latch
              2. 12.4.3.4.3.2.2 EQEP Strobe Event Latch
            3. 12.4.3.4.3.3 EQEP Position Counter Initialization
            4. 12.4.3.4.3.4 EQEP Position-Compare Unit
          4. 12.4.3.4.4 EQEP Edge Capture Unit
          5. 12.4.3.4.5 EQEP Watchdog
          6. 12.4.3.4.6 Unit Timer Base
          7. 12.4.3.4.7 EQEP Interrupt Structure
          8. 12.4.3.4.8 Summary of EQEP Functional Registers
        5. 12.4.3.5 EQEP Registers
      4. 12.4.4 Controller Area Network (MCAN)
        1. 12.4.4.1 MCAN Overview
          1. 12.4.4.1.1 MCAN Features
          2. 12.4.4.1.2 MCAN Not Supported Features
        2. 12.4.4.2 MCAN Environment
          1. 12.4.4.2.1 CAN Network Basics
        3. 12.4.4.3 MCAN Integration
          1. 12.4.4.3.1 MCAN Integration in MCU Domain
          2. 12.4.4.3.2 MCAN Integration in MAIN Domain
        4. 12.4.4.4 MCAN Functional Description
          1. 12.4.4.4.1  Module Clocking Requirements
          2. 12.4.4.4.2  Interrupt and DMA Requests
            1. 12.4.4.4.2.1 Interrupt Requests
            2. 12.4.4.4.2.2 DMA Requests
            3. 12.4.4.4.2.3 3066
          3. 12.4.4.4.3  Operating Modes
            1. 12.4.4.4.3.1 Software Initialization
            2. 12.4.4.4.3.2 Normal Operation
            3. 12.4.4.4.3.3 CAN FD Operation
            4. 12.4.4.4.3.4 Transmitter Delay Compensation
              1. 12.4.4.4.3.4.1 Description
              2. 12.4.4.4.3.4.2 Transmitter Delay Compensation Measurement
            5. 12.4.4.4.3.5 Restricted Operation Mode
            6. 12.4.4.4.3.6 Bus Monitoring Mode
            7. 12.4.4.4.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 12.4.4.4.3.7.1 Frame Transmission in DAR Mode
            8. 12.4.4.4.3.8 Power Down (Sleep Mode)
              1. 12.4.4.4.3.8.1 External Clock Stop Mode
              2. 12.4.4.4.3.8.2 Suspend Mode
              3. 12.4.4.4.3.8.3 Wakeup request
            9. 12.4.4.4.3.9 Test Modes
              1. 12.4.4.4.3.9.1 Internal Loopback Mode
          4. 12.4.4.4.4  Timestamp Generation
            1. 12.4.4.4.4.1 External Timestamp Counter
          5. 12.4.4.4.5  Timeout Counter
          6. 12.4.4.4.6  ECC Support
            1. 12.4.4.4.6.1 ECC Wrapper
            2. 12.4.4.4.6.2 ECC Aggregator
          7. 12.4.4.4.7  Rx Handling
            1. 12.4.4.4.7.1 Acceptance Filtering
              1. 12.4.4.4.7.1.1 Range Filter
              2. 12.4.4.4.7.1.2 Filter for specific IDs
              3. 12.4.4.4.7.1.3 Classic Bit Mask Filter
              4. 12.4.4.4.7.1.4 Standard Message ID Filtering
              5. 12.4.4.4.7.1.5 Extended Message ID Filtering
            2. 12.4.4.4.7.2 Rx FIFOs
              1. 12.4.4.4.7.2.1 Rx FIFO Blocking Mode
              2. 12.4.4.4.7.2.2 Rx FIFO Overwrite Mode
            3. 12.4.4.4.7.3 Dedicated Rx Buffers
              1. 12.4.4.4.7.3.1 Rx Buffer Handling
            4. 12.4.4.4.7.4 Debug on CAN Support
          8. 12.4.4.4.8  Tx Handling
            1. 12.4.4.4.8.1 Transmit Pause
            2. 12.4.4.4.8.2 Dedicated Tx Buffers
            3. 12.4.4.4.8.3 Tx FIFO
            4. 12.4.4.4.8.4 Tx Queue
            5. 12.4.4.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 12.4.4.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 12.4.4.4.8.7 Transmit Cancellation
            8. 12.4.4.4.8.8 Tx Event Handling
          9. 12.4.4.4.9  FIFO Acknowledge Handling
          10. 12.4.4.4.10 Message RAM
            1. 12.4.4.4.10.1 Message RAM Configuration
            2. 12.4.4.4.10.2 Rx Buffer and FIFO Element
            3. 12.4.4.4.10.3 Tx Buffer Element
            4. 12.4.4.4.10.4 Tx Event FIFO Element
            5. 12.4.4.4.10.5 Standard Message ID Filter Element
            6. 12.4.4.4.10.6 Extended Message ID Filter Element
        5. 12.4.4.5 MCAN Registers
          1. 12.4.4.5.1 MCAN Subsystem Registers
          2. 12.4.4.5.2 MCAN Core Registers
          3. 12.4.4.5.3 MCAN ECC Aggregator Registers
    5. 12.5 Audio Interfaces
      1. 12.5.1 Audio Tracking Logic (ATL)
        1. 12.5.1.1 ATL Overview
          1. 12.5.1.1.1 ATL Features Overview
          2. 12.5.1.1.2 ATL Not Supported Features
    6. 12.6 Timer Modules
      1. 12.6.1 Global Timebase Counter (GTC)
        1. 12.6.1.1 GTC Overview
          1. 12.6.1.1.1 GTC Features
          2. 12.6.1.1.2 GTC Not Supported Features
        2. 12.6.1.2 GTC Integration
        3. 12.6.1.3 GTC Functional Description
          1. 12.6.1.3.1 GTC Block Diagram
          2. 12.6.1.3.2 GTC Counter
          3. 12.6.1.3.3 GTC Gray Encoder
          4. 12.6.1.3.4 GTC Push Event Generation
          5. 12.6.1.3.5 GTC Register Partitioning
        4. 12.6.1.4 GTC Registers
          1. 12.6.1.4.1 GTC0_GTC_CFG0 Registers
          2. 12.6.1.4.2 GTC0_GTC_CFG1 Registers
          3. 12.6.1.4.3 GTC0_GTC_CFG2 Registers
          4. 12.6.1.4.4 GTC0_GTC_CFG3 Registers
      2. 12.6.2 Windowed Watchdog Timer (WWDT)
        1. 12.6.2.1 RTI Overview
          1. 12.6.2.1.1 RTI Features
          2. 12.6.2.1.2 RTI Not Supported Features
        2. 12.6.2.2 RTI Integration
          1. 12.6.2.2.1 RTI Integration in MCU Domain
          2. 12.6.2.2.2 RTI Integration in MAIN Domain
        3. 12.6.2.3 RTI Functional Description
          1. 12.6.2.3.1 RTI Counter Operation
          2. 12.6.2.3.2 RTI Digital Watchdog
          3. 12.6.2.3.3 RTI Digital Windowed Watchdog
          4. 12.6.2.3.4 RTI Low Power Mode Operation
          5. 12.6.2.3.5 RTI Debug Mode Behavior
        4. 12.6.2.4 RTI Registers
      3. 12.6.3 Timers
        1. 12.6.3.1 Timers Overview
          1. 12.6.3.1.1 Timers Features
          2. 12.6.3.1.2 Timers Not Supported Features
        2. 12.6.3.2 Timers Environment
          1. 12.6.3.2.1 Timer External System Interface
        3. 12.6.3.3 Timers Integration
          1. 12.6.3.3.1 Timers Integration in MCU Domain
          2. 12.6.3.3.2 Timers Integration in MAIN Domain
        4. 12.6.3.4 Timers Functional Description
          1. 12.6.3.4.1  Timer Block Diagram
          2. 12.6.3.4.2  Timer Power Management
            1. 12.6.3.4.2.1 Wake-Up Capability
          3. 12.6.3.4.3  Timer Software Reset
          4. 12.6.3.4.4  Timer Interrupts
          5. 12.6.3.4.5  Timer Mode Functionality
            1. 12.6.3.4.5.1 1-ms Tick Generation
          6. 12.6.3.4.6  Timer Capture Mode Functionality
          7. 12.6.3.4.7  Timer Compare Mode Functionality
          8. 12.6.3.4.8  Timer Prescaler Functionality
          9. 12.6.3.4.9  Timer Pulse-Width Modulation
          10. 12.6.3.4.10 Timer Counting Rate
          11. 12.6.3.4.11 Timer Under Emulation
          12. 12.6.3.4.12 Accessing Timer Registers
            1. 12.6.3.4.12.1 Writing to Timer Registers
              1. 12.6.3.4.12.1.1 Write Posting Synchronization Mode
              2. 12.6.3.4.12.1.2 Write Nonposting Synchronization Mode
            2. 12.6.3.4.12.2 Reading From Timer Counter Registers
              1. 12.6.3.4.12.2.1 Read Posted
              2. 12.6.3.4.12.2.2 Read Non-Posted
          13. 12.6.3.4.13 Timer Posted Mode Selection
        5. 12.6.3.5 Timers Low-Level Programming Models
          1. 12.6.3.5.1 Timer Global Initialization
            1. 12.6.3.5.1.1 Global Initialization of Surrounding Modules
            2. 12.6.3.5.1.2 Timer Module Global Initialization
              1. 12.6.3.5.1.2.1 Main Sequence – Timer Module Global Initialization
          2. 12.6.3.5.2 Timer Operational Mode Configuration
            1. 12.6.3.5.2.1 Timer Mode
              1. 12.6.3.5.2.1.1 Main Sequence – Timer Mode Configuration
            2. 12.6.3.5.2.2 Timer Compare Mode
              1. 12.6.3.5.2.2.1 Main Sequence – Timer Compare Mode Configuration
            3. 12.6.3.5.2.3 Timer Capture Mode
              1. 12.6.3.5.2.3.1 Main Sequence – Timer Capture Mode Configuration
              2. 12.6.3.5.2.3.2 Subsequence – Initialize Capture Mode
              3. 12.6.3.5.2.3.3 Subsequence – Detect Event
            4. 12.6.3.5.2.4 Timer PWM Mode
              1. 12.6.3.5.2.4.1 Main Sequence – Timer PWM Mode Configuration
        6. 12.6.3.6 Timers Registers
    7. 12.7 Internal Diagnostics Modules
      1. 12.7.1 Dual Clock Comparator (DCC)
        1. 12.7.1.1 DCC Overview
          1. 12.7.1.1.1 DCC Features
          2. 12.7.1.1.2 DCC Not Supported Features
        2. 12.7.1.2 DCC Integration
          1. 12.7.1.2.1 DCC Integration in MCU Domain
          2. 12.7.1.2.2 DCC Integration in MAIN Domain
        3. 12.7.1.3 DCC Functional Description
          1. 12.7.1.3.1 DCC Counter Operation
          2. 12.7.1.3.2 DCC Low Power Mode Operation
          3. 12.7.1.3.3 DCC Suspend Mode Behavior
          4. 12.7.1.3.4 DCC Single-Shot Mode
          5. 12.7.1.3.5 DCC Continuous mode
            1. 12.7.1.3.5.1 DCC Continue on Error
            2. 12.7.1.3.5.2 DCC Error Count
          6. 12.7.1.3.6 DCC Control and count hand-off across clock domains
          7. 12.7.1.3.7 DCC Error Trajectory record
            1. 12.7.1.3.7.1 DCC FIFO capturing for Errors
            2. 12.7.1.3.7.2 DCC FIFO in continuous capture mode
            3. 12.7.1.3.7.3 DCC FIFO Details
            4. 12.7.1.3.7.4 DCC FIFO Debug mode behavior
          8. 12.7.1.3.8 DCC Count read registers
        4. 12.7.1.4 DCC Registers
      2. 12.7.2 Error Signaling Module (ESM)
        1. 12.7.2.1 ESM Overview
          1. 12.7.2.1.1 ESM Features
        2. 12.7.2.2 ESM Environment
        3. 12.7.2.3 ESM Integration
          1. 12.7.2.3.1 ESM Integration in WKUP Domain
          2. 12.7.2.3.2 ESM Integration in MCU Domain
          3. 12.7.2.3.3 ESM Integration in MAIN Domain
        4. 12.7.2.4 ESM Functional Description
          1. 12.7.2.4.1 ESM Interrupt Requests
            1. 12.7.2.4.1.1 ESM Configuration Error Interrupt
            2. 12.7.2.4.1.2 ESM Low Priority Error Interrupt
              1. 12.7.2.4.1.2.1 ESM Low Priority Error Level Event
              2. 12.7.2.4.1.2.2 ESM Low Priority Error Pulse Event
            3. 12.7.2.4.1.3 ESM High Priority Error Interrupt
              1. 12.7.2.4.1.3.1 ESM High Priority Error Level Event
              2. 12.7.2.4.1.3.2 ESM High Priority Error Pulse Event
          2. 12.7.2.4.2 ESM Error Event Inputs
          3. 12.7.2.4.3 ESM Error Pin Output
          4. 12.7.2.4.4 ESM Minimum Time Interval
          5. 12.7.2.4.5 ESM Protection for Registers
          6. 12.7.2.4.6 ESM Clock Stop
        5. 12.7.2.5 ESM Registers
      3. 12.7.3 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 12.7.3.1 MCRC Overview
          1. 12.7.3.1.1 MCRC Features
          2. 12.7.3.1.2 MCRC Not Supported Features
        2. 12.7.3.2 MCRC Integration
        3. 12.7.3.3 MCRC Functional Description
          1. 12.7.3.3.1  MCRC Block Diagram
          2. 12.7.3.3.2  MCRC General Operation
          3. 12.7.3.3.3  MCRC Modes of Operation
            1. 12.7.3.3.3.1 AUTO Mode
            2. 12.7.3.3.3.2 Semi-CPU Mode
            3. 12.7.3.3.3.3 Full-CPU Mode
          4. 12.7.3.3.4  PSA Signature Register
          5. 12.7.3.3.5  PSA Sector Signature Register
          6. 12.7.3.3.6  CRC Value Register
          7. 12.7.3.3.7  Raw Data Register
          8. 12.7.3.3.8  Example DMA Controller Setup
            1. 12.7.3.3.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 12.7.3.3.8.2 AUTO Mode Using Software Trigger
            3. 12.7.3.3.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 12.7.3.3.9  Pattern Count Register
          10. 12.7.3.3.10 Sector Count Register/Current Sector Register
          11. 12.7.3.3.11 Interrupts
            1. 12.7.3.3.11.1 Compression Complete Interrupt
            2. 12.7.3.3.11.2 CRC Fail Interrupt
            3. 12.7.3.3.11.3 Overrun Interrupt
            4. 12.7.3.3.11.4 Underrun Interrupt
            5. 12.7.3.3.11.5 Timeout Interrupt
            6. 12.7.3.3.11.6 Interrupt Offset Register
            7. 12.7.3.3.11.7 Error Handling
          12. 12.7.3.3.12 Power Down Mode
          13. 12.7.3.3.13 Emulation
        4. 12.7.3.4 MCRC Programming Examples
          1. 12.7.3.4.1 Example: Auto Mode Using Time Based Event Triggering
            1. 12.7.3.4.1.1 DMA Setup
            2. 12.7.3.4.1.2 Timer Setup
            3. 12.7.3.4.1.3 CRC Setup
          2. 12.7.3.4.2 Example: Auto Mode Without Using Time Based Triggering
            1. 12.7.3.4.2.1 DMA Setup
            2. 12.7.3.4.2.2 CRC Setup
          3. 12.7.3.4.3 Example: Semi-CPU Mode
            1. 12.7.3.4.3.1 DMA Setup
            2. 12.7.3.4.3.2 Timer Setup
            3. 12.7.3.4.3.3 CRC Setup
          4. 12.7.3.4.4 Example: Full-CPU Mode
            1. 12.7.3.4.4.1 CRC Setup
        5. 12.7.3.5 MCRC Registers
      4. 12.7.4 ECC Aggregator
        1. 12.7.4.1 ECC Aggregator Overview
          1. 12.7.4.1.1 ECC Aggregator Features
        2. 12.7.4.2 ECC Aggregator Integration
        3. 12.7.4.3 ECC Aggregator Functional Description
          1. 12.7.4.3.1 ECC Aggregator Block Diagram
          2. 12.7.4.3.2 ECC Aggregator Register Groups
          3. 12.7.4.3.3 Read Access to the ECC Control and Status Registers
          4. 12.7.4.3.4 Serial Write Operation
          5. 12.7.4.3.5 Interrupts
          6. 12.7.4.3.6 Inject Only Mode
        4. 12.7.4.4 ECC Aggregator Registers
  15. 13On-Chip Debug
  16. 14Revision History
12.2.3.5.4 PCIE_CORE_LM Registers

Table 12-3128 lists the PCIE_CORE_LM registers. All register offset addresses not listed in Table 12-3128 should be considered as reserved locations and the register contents should not be modified.

PCIE core local management (LM) registers. The local management registers are used to configure various operational parameters associated with the core, and for a local processor to monitor its status. These registers are accessible only from the local management bus.

Table 12-3127 PCIE_CORE_LM Instances
InstanceBase Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D80 0000h
Table 12-3128 PCIE_CORE_LM Registers
Offset Acronym Register Name PCIE1_CORE_DBN_CFG_PCIE_CORE
Physical Address
00100000h PCIE_CORE_LM_I_PL_CONFIG_0_REG 0D90 0000h
00100004h PCIE_CORE_LM_I_PL_CONFIG_1_REG 0D90 0004h
00100008h PCIE_CORE_LM_I_DLL_TMR_CONFIG_REG 0D90 0008h
0010000Ch PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG 0D90 000Ch
00100010h PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG 0D90 0010h
00100014h PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG 0D90 0014h
00100018h PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG 0D90 0018h
0010001Ch PCIE_CORE_LM_I_TRANSM_CRED_UPDATE_INT_CONFIG_0_REG 0D90 001Ch
00100020h PCIE_CORE_LM_I_TRANSM_CRED_UPDATE_INT_CONFIG_1_REG 0D90 0020h
00100024h PCIE_CORE_LM_I_L0S_TIMEOUT_LIMIT_REG 0D90 0024h
00100028h PCIE_CORE_LM_I_TRANSMIT_TLP_COUNT_REG 0D90 0028h
0010002Ch PCIE_CORE_LM_I_TRANSMIT_TLP_PAYLOAD_DWORD_COUNT_REG 0D90 002Ch
00100030h PCIE_CORE_LM_I_RECEIVE_TLP_COUNT_REG 0D90 0030h
00100034h PCIE_CORE_LM_I_RECEIVE_TLP_PAYLOAD_DWORD_COUNT_REG 0D90 0034h
00100038h PCIE_CORE_LM_I_COMPLN_TMOUT_LIM_0_REG 0D90 0038h
0010003Ch PCIE_CORE_LM_I_COMPLN_TMOUT_LIM_1_REG 0D90 003Ch
00100040h PCIE_CORE_LM_I_L1_ST_REENTRY_DELAY_REG 0D90 0040h
00100044h PCIE_CORE_LM_I_VENDOR_ID_REG 0D90 0044h
00100048h PCIE_CORE_LM_I_ASPM_L1_ENTRY_TMOUT_DELAY_REG 0D90 0048h
0010004Ch PCIE_CORE_LM_I_PME_TURNOFF_ACK_DELAY_REG 0D90 004Ch
00100050h PCIE_CORE_LM_I_LINKWIDTH_CONTROL_REG 0D90 0050h
00100054h PCIE_CORE_LM_I_PL_CONFIG_2_REG 0D90 0054h
00100070h PCIE_CORE_LM_I_MULTI_VC_CONROL_REG 0D90 0070h
00100074h PCIE_CORE_LM_I_SRIS_CONTROL_REG 0D90 0074h
00100080h PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC1 0D90 0080h
00100084h PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC1 0D90 0084h
00100088h PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC1 0D90 0088h
0010008Ch PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC1 0D90 008Ch
00100090h PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC2 0D90 0090h
00100094h PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC2 0D90 0094h
00100098h PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC2 0D90 0098h
0010009Ch PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC2 0D90 009Ch
001000A0h PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC3 0D90 00A0h
001000A4h PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC3 0D90 00A4h
001000A8h PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC3 0D90 00A8h
001000ACh PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC3 0D90 00ACh
001000F0h PCIE_CORE_LM_I_FC_INIT_DELAY_REG 0D90 00F0h
00100100h PCIE_CORE_LM_I_SHDW_HDR_LOG_0_REG 0D90 0100h
00100104h PCIE_CORE_LM_I_SHDW_HDR_LOG_1_REG 0D90 0104h
00100108h PCIE_CORE_LM_I_SHDW_HDR_LOG_2_REG 0D90 0108h
0010010Ch PCIE_CORE_LM_I_SHDW_HDR_LOG_3_REG 0D90 010Ch
00100110h PCIE_CORE_LM_I_SHDW_FUNC_NUM_REG 0D90 0110h
00100114h PCIE_CORE_LM_I_SHDW_UR_ERR_REG 0D90 0114h
00100140h PCIE_CORE_LM_I_PM_CLK_FREQUENCY_REG 0D90 0140h
00100144h PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN1_REG 0D90 0144h
00100148h PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN2_REG 0D90 0148h
0010014Ch PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN3_REG 0D90 014Ch
00100150h PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN4_REG 0D90 0150h
00100158h PCIE_CORE_LM_I_VENDOR_DEFINED_MESSAGE_TAG_REG 0D90 0158h
00100200h PCIE_CORE_LM_I_NEGOTIATED_LANE_MAP_REG 0D90 0200h
00100204h PCIE_CORE_LM_I_RECEIVE_FTS_COUNT_REG 0D90 0204h
00100208h PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_REG 0D90 0208h
0010020Ch PCIE_CORE_LM_I_LOCAL_ERROR_STATUS_REGISTER 0D90 020Ch
00100210h PCIE_CORE_LM_I_LOCAL_INTRPT_MASK_REG 0D90 0210h
00100214h PCIE_CORE_LM_I_LCRC_ERR_COUNT_REG 0D90 0214h
00100218h PCIE_CORE_LM_I_ECC_CORR_ERR_COUNT_REG 0D90 0218h
0010021Ch PCIE_CORE_LM_I_LTR_SNOOP_LAT_REG 0D90 021Ch
00100220h PCIE_CORE_LM_I_LTR_MSG_GEN_CTL_REG 0D90 0220h
00100224h PCIE_CORE_LM_I_PME_SERVICE_TIMEOUT_DELAY_REG 0D90 0224h
00100228h PCIE_CORE_LM_I_ROOT_PORT_REQUESTOR_ID_REG 0D90 0228h
0010022Ch PCIE_CORE_LM_I_EP_BUS_DEVICE_NUMBER_REG 0D90 022Ch
00100234h PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_2_REG 0D90 0234h
00100238h PCIE_CORE_LM_I_PHY_STATUS_1_REG 0D90 0238h
0010023Ch PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_3_REG 0D90 023Ch
00100240h PCIE_CORE_LM_I_PF_0_BAR_CONFIG_0_REG 0D90 0240h
00100244h PCIE_CORE_LM_I_PF_0_BAR_CONFIG_1_REG 0D90 0244h
00100248h PCIE_CORE_LM_I_PF_1_BAR_CONFIG_0_REG 0D90 0248h
0010024Ch PCIE_CORE_LM_I_PF_1_BAR_CONFIG_1_REG 0D90 024Ch
00100250h PCIE_CORE_LM_I_PF_2_BAR_CONFIG_0_REG 0D90 0250h
00100254h PCIE_CORE_LM_I_PF_2_BAR_CONFIG_1_REG 0D90 0254h
00100258h PCIE_CORE_LM_I_PF_3_BAR_CONFIG_0_REG 0D90 0258h
0010025Ch PCIE_CORE_LM_I_PF_3_BAR_CONFIG_1_REG 0D90 025Ch
00100260h PCIE_CORE_LM_I_PF_4_BAR_CONFIG_0_REG 0D90 0260h
00100264h PCIE_CORE_LM_I_PF_4_BAR_CONFIG_1_REG 0D90 0264h
00100268h PCIE_CORE_LM_I_PF_5_BAR_CONFIG_0_REG 0D90 0268h
0010026Ch PCIE_CORE_LM_I_PF_5_BAR_CONFIG_1_REG 0D90 026Ch
00100280h PCIE_CORE_LM_I_PF_0_VF_BAR_CONFIG_0_REG 0D90 0280h
00100284h PCIE_CORE_LM_I_PF_0_VF_BAR_CONFIG_1_REG 0D90 0284h
00100288h PCIE_CORE_LM_I_PF_1_VF_BAR_CONFIG_0_REG 0D90 0288h
0010028Ch PCIE_CORE_LM_I_PF_1_VF_BAR_CONFIG_1_REG 0D90 028Ch
00100290h PCIE_CORE_LM_I_PF_2_VF_BAR_CONFIG_0_REG 0D90 0290h
00100294h PCIE_CORE_LM_I_PF_2_VF_BAR_CONFIG_1_REG 0D90 0294h
00100298h PCIE_CORE_LM_I_PF_3_VF_BAR_CONFIG_0_REG 0D90 0298h
0010029Ch PCIE_CORE_LM_I_PF_3_VF_BAR_CONFIG_1_REG 0D90 029Ch
001002A0h PCIE_CORE_LM_I_PF_4_VF_BAR_CONFIG_0_REG 0D90 02A0h
001002A4h PCIE_CORE_LM_I_PF_4_VF_BAR_CONFIG_1_REG 0D90 02A4h
001002A8h PCIE_CORE_LM_I_PF_5_VF_BAR_CONFIG_0_REG 0D90 02A8h
001002ACh PCIE_CORE_LM_I_PF_5_VF_BAR_CONFIG_1_REG 0D90 02ACh
001002C0h PCIE_CORE_LM_I_PF_CONFIG_REG 0D90 02C0h
00100300h PCIE_CORE_LM_I_RC_BAR_CONFIG_REG 0D90 0300h
00100360h PCIE_CORE_LM_I_GEN3_DEFAULT_PRESET_REG 0D90 0360h
00100364h PCIE_CORE_LM_I_GEN3_GEN4_LINK_EQ_TIMEOUT_2MS_REG 0D90 0364h
00100368h PCIE_CORE_LM_I_PIPE_FIFO_LATENCY_CTRL_REG 0D90 0368h
00100374h PCIE_CORE_LM_I_GEN4_DEFAULT_PRESET_REG 0D90 0374h
00100378h PCIE_CORE_LM_I_PHY_CONFIG_REG3 0D90 0378h
0010037Ch PCIE_CORE_LM_I_GEN3_GEN4_LINK_EQ_CTRL_REG 0D90 037Ch
00100380h PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE0 0D90 0380h
00100384h PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE1 0D90 0384h
00100388h PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE2 0D90 0388h
0010038Ch PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE3 0D90 038Ch
001003C0h PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE0 0D90 03C0h
001003C4h PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE1 0D90 03C4h
001003C8h PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE2 0D90 03C8h
001003CCh PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE3 0D90 03CCh
00100C80h PCIE_CORE_LM_I_ECC_CORR_ERR_COUNT_REG_AXI 0D90 0C80h
00100C88h PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL0 0D90 0C88h
00100C8Ch PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL1 0D90 0C8Ch
00100C90h PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL2 0D90 0C90h
00100C94h PCIE_CORE_LM_TL_INTERNAL_CONTROL 0D90 0C94h
00100C98h PCIE_CORE_LM_I_DTI_ATS_STATUS 0D90 0C98h
00100C9Ch PCIE_CORE_LM_I_DTI_ATS_CTRL 0D90 0C9Ch
00100CC0h PCIE_CORE_LM_I_SCALED_FLOW_CONTROL_MGMT_VC_SELECT_REG 0D90 0CC0h
00100CC4h PCIE_CORE_LM_I_SCALED_FLOW_CONTROL_MGMT_REG 0D90 0CC4h
00100CD0h PCIE_CORE_LM_I_MARGINING_PARAMETERS_1_REG 0D90 0CD0h
00100CD4h PCIE_CORE_LM_I_MARGINING_PARAMETERS_2_REG 0D90 0CD4h
00100CD8h PCIE_CORE_LM_I_MARGINING_LOCAL_CONTROL_REG 0D90 0CD8h
00100CDCh PCIE_CORE_LM_I_MARGINING_ERROR_STATUS1_REG 0D90 0CDCh
00100CE0h PCIE_CORE_LM_I_MARGINING_ERROR_STATUS2_REG 0D90 0CE0h
00100D00h PCIE_CORE_LM_I_LOCAL_ERROR_STATUS_2_REGISTER 0D90 0D00h
00100D04h PCIE_CORE_LM_I_LOCAL_INTRPT_MASK_2_REG 0D90 0D04h
00100D10h PCIE_CORE_LM_MSI_MASK_CLEARED_STATUS_1 0D90 0D10h
00100D14h PCIE_CORE_LM_MSI_MASK_SET_STATUS_1 0D90 0D14h
00100D18h PCIE_CORE_LM_MSIX_FUNCTION_MASK_CLEARED_STATUS_1 0D90 0D18h
00100D1Ch PCIE_CORE_LM_MSIX_FUNCTION_MASK_SET_STATUS_1 0D90 0D1Ch
00100DA0h PCIE_CORE_LM_I_LD_CTRL 0D90 0DA0h
00100DA4h PCIE_CORE_LM_RX_ELEC_IDLE_FILTER_CONTROL 0D90 0DA4h
00100DA8h PCIE_CORE_LM_I_PTM_LOCAL_CONTROL_REG 0D90 0DA8h
00100DACh PCIE_CORE_LM_I_PTM_LOCAL_STATUS_REG 0D90 0DACh
00100DB0h PCIE_CORE_LM_I_PTM_LATENCY_PARAMETERS_INDEX_REG 0D90 0DB0h
00100DB4h PCIE_CORE_LM_I_PTM_LATENCY_PARAMETERS_REG 0D90 0DB4h
00100DB8h PCIE_CORE_LM_I_PTM_CONTEXT_1_REG 0D90 0DB8h
00100DBCh PCIE_CORE_LM_I_PTM_CONTEXT_2_REG 0D90 0DBCh
00100DC0h PCIE_CORE_LM_I_PTM_CONTEXT_3_REG 0D90 0DC0h
00100DC4h PCIE_CORE_LM_I_PTM_CONTEXT_4_REG 0D90 0DC4h
00100DC8h PCIE_CORE_LM_I_PTM_CONTEXT_5_REG 0D90 0DC8h
00100DCCh PCIE_CORE_LM_I_PTM_CONTEXT_6_REG 0D90 0DCCh
00100DD0h PCIE_CORE_LM_I_PTM_CONTEXT_7_REG 0D90 0DD0h
00100DD4h PCIE_CORE_LM_I_PTM_CONTEXT_8_REG 0D90 0DD4h
00100DD8h PCIE_CORE_LM_I_PTM_CONTEXT_9_REG 0D90 0DD8h
00100DDCh PCIE_CORE_LM_I_PTM_CONTEXT_10_REG 0D90 0DDCh
00100DE0h PCIE_CORE_LM_I_PTM_CONTEXT_11_REG 0D90 0DE0h
00100DECh PCIE_CORE_LM_I_ASF_INTRPT_STATUS 0D90 0DECh
00100DF0h PCIE_CORE_LM_I_ASF_INTRPT_RAW_STATUS 0D90 0DF0h
00100DF4h PCIE_CORE_LM_I_ASF_INTRPT_MASK_REG 0D90 0DF4h
00100DF8h PCIE_CORE_LM_I_ASF_INTRPT_TEST 0D90 0DF8h
00100DFCh PCIE_CORE_LM_I_ASF_INTRPT_FATAL_NONFATAL_SEL 0D90 0DFCh
00100E00h PCIE_CORE_LM_I_ASF_SRAM_CORR_FAULT_STATUS 0D90 0E00h
00100E04h PCIE_CORE_LM_I_ASF_SRAM_UNCORR_FAULT_STATUS 0D90 0E04h
00100E08h PCIE_CORE_LM_I_ASF_SRAM_FAULT_STATSTICS 0D90 0E08h
00100E0Ch PCIE_CORE_LM_I_ASF_TRANS_TO_CTRL 0D90 0E0Ch
00100E10h PCIE_CORE_LM_I_ASF_TRANS_TO_FAULT_MASK 0D90 0E10h
00100E14h PCIE_CORE_LM_I_ASF_TRANS_TO_FAULT_STATUS 0D90 0E14h
00100E18h PCIE_CORE_LM_I_ASF_PROTOCOL_FAULT_MASK 0D90 0E18h
00100E1Ch PCIE_CORE_LM_I_ASF_PROTOCOL_FAULT_STATUS_REG 0D90 0E1Ch
00100E20h PCIE_CORE_LM_DUAL_TL_CTRL 0D90 0E20h
00100E40h PCIE_CORE_LM_I_ASF_MAGIC_NUM_CTRLLER_VER_REG 0D90 0E40h
00100E4Ch PCIE_CORE_LM_I_EQ_DEBUG_MON_CONTROL_REG 0D90 0E4Ch
00100E50h PCIE_CORE_LM_I_EQ_DEBUG_MON_STATUS0_REG 0D90 0E50h
00100E54h PCIE_CORE_LM_I_EQ_DEBUG_MON_STATUS_REG 0D90 0E54h
00100E5Ch PCIE_CORE_LM_I_AXI_FEATURE_REG 0D90 0E5Ch
00100E60h PCIE_CORE_LM_I_LINK_EQ_CONTROL_2_REG 0D90 0E60h
00100E64h PCIE_CORE_LM_I_CORE_FEATURE_REG 0D90 0E64h
00100E68h PCIE_CORE_LM_I_DTI_ATS_CTRL_2 0D90 0E68h
00100E88h PCIE_CORE_LM_I_RX_INVERT_POLARITY_REG 0D90 0E88h

3.5.4.1 PCIE_CORE_LM_I_PL_CONFIG_0_REG Register (Offset = 00100000h) [reset = 24h]

PCIE_CORE_LM_I_PL_CONFIG_0_REG is shown in Figure 12-1593 and described in Table 12-3130.

Return to the Summary Table.

This register contains the configured parameters at the Physical Layer of the link, and
status information from the Physical Layer.

Table 12-3129 PCIE_CORE_LM_I_PL_CONFIG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0000h
Figure 12-1593 PCIE_CORE_LM_I_PL_CONFIG_0_REG Register
3130292827262524
MLER0LTSSM
R/W-0hR-0hR-0h
2322212019181716
RLID
R-0h
15141312111098
RFC
R-0h
76543210
TSSAPERLTDNSNLCLS
R/W-0hR/W-0hR-1hR-0hR-2hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3130 PCIE_CORE_LM_I_PL_CONFIG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31MLER/W0hWhen the Controller is operating as a Root Port, setting this to 1 causes the LTSSM to
initiate a loopback and become the loopback master.
This bit is not used in the EndPoint
Mode.
30R0R0hA 1 in this field indicates that the remote node advertised Linkwidth Upconfigure
Capability in the training sequences in the Configuration.Complete state when the link came
up.
A 0 indicates that the remote node did not set the Link Upconfigure bit.
29-24LTSSMR0hCurrent state of the LTSSM.
The encoding of the states is given in Appendix C.
23-16RLIDR0hLink ID received from other side during link training.
15-8RFCR0hFTS count received from the other side during link training for use at the 2.5 GT/s
link speed.
The Controller transmits this many FTS sequences while exiting the L0S state,
when operating at the 2.5 GT/s speed.
7TSSR/W0hThis bit drives the PIPE_TX_SWING output of the Controller.
6APERR/W0hThis bit controls the reporting of Errors Detected by the PHY.
The Errors Detected by the PHY include:-
- Received errors indicated on PIPE RxStatus interface,
- 8.0 GT/s Invalid Sync Header received error,
- 16.0 GT/s Invalid Sync Header received error,
If PHY Error Reporting bit is set to 0, the Controller will only report those errors that caused a TLP or DLLP to be
dropped because of a Detected PHY Error.

If PHY Error Reporting bit is set to 1, the Controller will report all Detected PHY Errors regardless of whether a TLP or DLLP was dropped.


The following registers report PHY error in conjunction with this bit:
- Correctable Error Status Register, i_corr_err_status, bit-0, Receiver Error Status
- Local Error and Status Register, PCIE_CORE_LM_I_LOCAL_ERROR_STATUS_REGISTER, bit-7, Phy Error

In addition to the Errors Detected by the PHY[PCS], the Controller detects the following Physical Layer Protocol Framing Errors:
- Framing Errors in the received DLLP and TLP
- Ordered Set Block Received Without EDS
- Data Block Received After EDS
- Illegal Ordered Set Block Received After EDS
- Ordered Set Block Received After Skip OS
Note: These Errors are always reported independent of the setting of this bit.

5LTDR1hThe state of this bit indicates whether the Controller completed
link training as an upstream port[EndPoint][=0] or a downstream port[Root Port][=1].

Default value depends on CORE_TYPE strap pin.
4-3NSR0hCurrent operating speed of link
[00 = 2.5G,
01 = 5G,
10 = 8G,
11 = 16G].
2-1NLCR2hLane count negotiated with other side during link training


[00 = x1,
01 = x2,
10 = x4,
11 = x8].

0LSR0hCurrent state of link
[1 = link training complete,
0 = link training not complete].

3.5.4.2 PCIE_CORE_LM_I_PL_CONFIG_1_REG Register (Offset = 00100004h) [reset = 80808000h]

PCIE_CORE_LM_I_PL_CONFIG_1_REG is shown in Figure 12-1594 and described in Table 12-3132.

Return to the Summary Table.

This register contains additional configured parameters at the Physical Layer of the
link, and command bits for various Physical Layer functions.

Table 12-3131 PCIE_CORE_LM_I_PL_CONFIG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0004h
Figure 12-1594 PCIE_CORE_LM_I_PL_CONFIG_1_REG Register
313029282726252423222120191817161514131211109876543210
TFC3TFC2TFC1TLI
R/W-80hR/W-80hR/W-80hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3132 PCIE_CORE_LM_I_PL_CONFIG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-24TFC3R/W80hFTS count transmitted by the Controller in TS1/TS2 sequences during link training.
This
value must be set based on the time needed by the receiver to acquire sync
while exiting from L0S state.
23-16TFC2R/W80hFTS count transmitted by the Controller in TS1/TS2 sequences during link training.
This
value must be set based on the time needed by the receiver to acquire sync
while exiting from L0S state.
15-8TFC1R/W80hFTS count transmitted by the Controller in TS1/TS2 sequences during link training.
This
value must be set based on the time needed by the receiver to acquire sync
while exiting from L0S state.
7-0TLIR/W0hLink ID transmitted by the device in training sequences in the Root Port mode.

3.5.4.3 PCIE_CORE_LM_I_DLL_TMR_CONFIG_REG Register (Offset = 00100008h) [reset = 0h]

PCIE_CORE_LM_I_DLL_TMR_CONFIG_REG is shown in Figure 12-1595 and described in Table 12-3134.

Return to the Summary Table.

This register defines the replay timeout values used by the DL receive and transmit
sides of the link. It can be read or written via the local management APB bus.

Table 12-3133 PCIE_CORE_LM_I_DLL_TMR_CONFIG_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0008h
Figure 12-1595 PCIE_CORE_LM_I_DLL_TMR_CONFIG_REG Register
313029282726252423222120191817161514131211109876543210
R25RSARTR9TSRT
R-0hR/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3134 PCIE_CORE_LM_I_DLL_TMR_CONFIG_REG Register Field Descriptions
BitFieldTypeResetDescription
31-25R25R0hReserved
24-16RSARTR/W0hAdditional receive side ACK-NAK timer timeout interval.
This
9-bit value is
added as a signed 2's complement number to the internal ACK-NAK timer timeout value
computed by the Controller based on the PCI Express Specifications.
This enables the user
to make minor adjustments to the spec-defined replay timer settings.Its value is in multiples of [2 Symbol Times]
At Gen1 adjustment range = [+2040 ns to -2048 ns].
At Gen2 adjustment range = [+1020 ns to -1024 ns].
At Gen3 adjustment range = [+510 ns to -512 ns].
15-9R9R0hReserved
8-0TSRTR/W0hAdditional transmit-side replay timer timeout interval.
This
9-bit value is
added as a signed 2's complement number to the internal replay timer timeout value
computed by the Controller based on the PCI Express Specifications.
This enables the user to
make minor adjustments to the spec-defined replay timer settings.
Its value is in multiples of [2 Symbol Times]
At Gen1 adjustment range = [+2040 ns to -2048 ns].
At Gen2 adjustment range = [+1020 ns to -1024 ns].
At Gen3 adjustment range = [+510 ns to -512 ns].

3.5.4.4 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG Register (Offset = 0010000Ch) [reset = 02020080h]

PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG is shown in Figure 12-1596 and described in Table 12-3136.

Return to the Summary Table.

This register contains the initial credit limits advertised by the Controller during th DL
initialization. If the fields of this register are modified, the link must be re-trained to
re-initialize the DL for the modified settings to take effect.
The credit limit fields in this register can be programmed to any value lesser than or equal to the respective default values.
The default values are set to advertise the full size of the receive buffers.
If a value of 0x00 is programmed, it implies infinite credit.
Note: This may result in receiver overflow if received data is back pressured on the Client interface.

Table 12-3135 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 000Ch
Figure 12-1596 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG Register
313029282726252423222120191817161514131211109876543210
NPPCPHCPPC
R/W-20hR/W-20hR/W-80h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3136 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20NPPCR/W20hNon-Posted payload credit limit advertised by the Controller for VC 0 .



This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 0.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of 4 DW and then advertised in the InitFC DLLPs.

Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
19-12PHCR/W20hPosted header credit limit advertised by the Controller for VC 0.

This field is in units of 1, 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 0.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of [1 Packet Header] and then advertised in the InitFC DLLPs.

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
11-0PPCR/W80hPosted payload credit limit advertised by the Controller for VC 0.

This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 0.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of 4 DW and then advertised in the InitFC DLLPs.

Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

3.5.4.5 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG Register (Offset = 00100010h) [reset = 20h]

PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG is shown in Figure 12-1597 and described in Table 12-3138.

Return to the Summary Table.

This register contains the initial credit limits advertised by the Controller during the DL
initialization. If the fields of this register are modified, the link must be re-trained to
re-initialize the DL for the modified settings to take effect.
The credit limit fields in this register can be programmed to any value lesser than or equal to the respective default values.
The default values are set to advertise the full size of the receive buffers.
If a value of 0x00 is programmed, it implies infinite credit.
Note: This may result in receiver overflow if received data is back pressured on the Client interface.

Table 12-3137 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0010h
Figure 12-1597 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG Register
313029282726252423222120191817161514131211109876543210
CHCR2CPCNPHCL
R/W-0hR-0hR/W-0hR/W-20h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3138 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-24CHCR/W0hCompletion header credit limit advertised by the Controller for VC 0 [in number of packets].


This field is in units of 1, 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 0.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of [1 Packet Header] and then advertised in the InitFC DLLPs.

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
23-20R2R0hReserved
19-8CPCR/W0hCompletion payload credit limit advertised by the Controller for VC 0 .


This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 0.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of 4 DW and then advertised in the InitFC DLLPs.

Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
7-0NPHCLR/W20hNon-Posted header credit limit advertised by the Controller for VC 0 [in number of packets].


This field is in units of 1, 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 0.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of [1 Packet Header] and then advertised in the InitFC DLLPs.

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

3.5.4.6 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG Register (Offset = 00100014h) [reset = 0h]

PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG is shown in Figure 12-1598 and described in Table 12-3140.

Return to the Summary Table.

This register contains the initial credit limits received from the opposite node during
the DL initialization. It is a read-only register.

Table 12-3139 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0014h
Figure 12-1598 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG Register
313029282726252423222120191817161514131211109876543210
NPPCPHCPPC
R-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3140 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20NPPCR0hNon-Posted payload credit limit received by the Controller for Link 0 .


This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 0.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]


19-12PHCR0hPosted header credit limit received by the Controller for this link .

This field is in units of 1, 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 0.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
11-0PPCR0hPosted payload credit limit received by the Controller for this link .

This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 0.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]

3.5.4.7 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG Register (Offset = 00100018h) [reset = 0h]

PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG is shown in Figure 12-1599 and described in Table 12-3142.

Return to the Summary Table.

This register contains the initial credit limits received from the opposite node during
the DL initialization. It is a read-only register.

Table 12-3141 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0018h
Figure 12-1599 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG Register
313029282726252423222120191817161514131211109876543210
CHCR3CPCNPHC
R-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3142 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-24CHCR0hCompletion header credit limit received by the Controller for VC 0 .

This field is in units of 1, 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 0.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
23-20R3R0hReserved
19-8CPCR0hCompletion payload credit limit received by the Controller for VC 0 .


This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 0.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]


7-0NPHCR0hNon-Posted header credit limit received by the Controller for VC 0 .


This field is in units of 1, 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 0.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]


Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.

3.5.4.8 PCIE_CORE_LM_I_TRANSM_CRED_UPDATE_INT_CONFIG_0_REG Register (Offset = 0010001Ch) [reset = 00040004h]

PCIE_CORE_LM_I_TRANSM_CRED_UPDATE_INT_CONFIG_0_REG is shown in Figure 12-1600 and described in Table 12-3144.

Return to the Summary Table.

This register contains parameters that control how frequently the Controller sends a credit
update to the opposite node.

Table 12-3143 PCIE_CORE_LM_I_TRANSM_CRED_UPDATE_INT_CONFIG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 001Ch
Figure 12-1600 PCIE_CORE_LM_I_TRANSM_CRED_UPDATE_INT_CONFIG_0_REG Register
313029282726252423222120191817161514131211109876543210
MNUIMPUI
R/W-4hR/W-4h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3144 PCIE_CORE_LM_I_TRANSM_CRED_UPDATE_INT_CONFIG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16MNUIR/W4hMinimum credit update interval for non-posted transactions.
The Controller follows this
minimum interval between issuing posted credit updates on the link.
This is to limit the
bandwidth use of credit updates.
If new credit becomes available in the receive FIFO since the
last update was sent, the Controller will issue a new update only after this interval has elapsed
since the last update.
The value is in units of 16 ns.
This field is re-written by the internal
logic when the negotiated link width or link speed changes, to correspond to the default
values defined in defines.h.
The user may override this default value by writing into this
register field.
The value written will be lost on a change in the negotiated link width/speed.
15-0MPUIR/W4hMinimum credit update interval for posted transactions.
The Controller follows this minimum
interval between issuing posted credit updates on the link.
This is to limit the bandwidth use
of credit updates.
If new credit becomes available in the receive FIFO since the last update
was sent, the Controller will issue a new update only after this interval has elapsed since the last
update.
The value is in units of 16 ns.
This field is re-written by the internal logic when the
negotiated link width or link speed changes, to correspond to the default values defined in
defines.h.
The user may override this default value by writing into this register field.
The
value written will be lost on a change in the negotiated link width/speed.

3.5.4.9 PCIE_CORE_LM_I_TRANSM_CRED_UPDATE_INT_CONFIG_1_REG Register (Offset = 00100020h) [reset = 03AA0004h]

PCIE_CORE_LM_I_TRANSM_CRED_UPDATE_INT_CONFIG_1_REG is shown in Figure 12-1601 and described in Table 12-3146.

Return to the Summary Table.

This register contains parameters that control how frequently the Controller sends a credit
update to the opposite node.

Table 12-3145 PCIE_CORE_LM_I_TRANSM_CRED_UPDATE_INT_CONFIG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0020h
Figure 12-1601 PCIE_CORE_LM_I_TRANSM_CRED_UPDATE_INT_CONFIG_1_REG Register
313029282726252423222120191817161514131211109876543210
MUICUI
R/W-3AAhR/W-4h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3146 PCIE_CORE_LM_I_TRANSM_CRED_UPDATE_INT_CONFIG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16MUIR/W3AAhMaximum credit update interval for all transactions.
If no new credit has become
available since the last update, the Controller will repeat the last update after this interval.
This is to recover from any losses of credit update packets.
The value is in units of 16 ns.
This field could be re-written by the internal logic when the negotiated link width or link
speed changes, to correspond to the default values defined in defines.h.
The user may override
this default value by writing into this register field.
The value written will be lost on a
change in the negotiated link width/speed.
15-0CUIR/W4hMinimum credit update interval for Completion packets.
The Controller follows this minimum
interval between issuing completion credit updates on the link.
This is to limit the bandwidth use
of credit updates.
If new credit becomes available in the receive FIFO since the last update
was sent, the Controller will issue a new update only after this interval has elapsed since the last
update.
The value is in units of 16 ns.
This parameter is not used when the Completion credit
is infinity.

3.5.4.10 PCIE_CORE_LM_I_L0S_TIMEOUT_LIMIT_REG Register (Offset = 00100024h) [reset = 177h]

PCIE_CORE_LM_I_L0S_TIMEOUT_LIMIT_REG is shown in Figure 12-1602 and described in Table 12-3148.

Return to the Summary Table.

This register defines the timeout value for transitioning to the L0S power state. If the
transmit side has been idle for this interval, the Controller will transmit the idle sequence on the
link and transition the state of the link to L0S .

Table 12-3147 PCIE_CORE_LM_I_L0S_TIMEOUT_LIMIT_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0024h
Figure 12-1602 PCIE_CORE_LM_I_L0S_TIMEOUT_LIMIT_REG Register
313029282726252423222120191817161514131211109876543210
R4LT
R-0hR/W-177h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3148 PCIE_CORE_LM_I_L0S_TIMEOUT_LIMIT_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R4R0hReserved
15-0LTR/W177hContains the timeout value [in units of 16 ns] for transitioning to the L0S power
state.
Setting this parameter to 0 permanently disables the transition to the L0S power state.

3.5.4.11 PCIE_CORE_LM_I_TRANSMIT_TLP_COUNT_REG Register (Offset = 00100028h) [reset = 0h]

PCIE_CORE_LM_I_TRANSMIT_TLP_COUNT_REG is shown in Figure 12-1603 and described in Table 12-3150.

Return to the Summary Table.

This register contains the number of Transaction-Layer packets transmitted by the Controller
on the link since the register was last reset. This counter saturates on reaching a count of all
1's. Writing all 1's to this register causes it to be reset to 0.

Table 12-3149 PCIE_CORE_LM_I_TRANSMIT_TLP_COUNT_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0028h
Figure 12-1603 PCIE_CORE_LM_I_TRANSMIT_TLP_COUNT_REG Register
313029282726252423222120191817161514131211109876543210
TTC
R/W1C-0h
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3150 PCIE_CORE_LM_I_TRANSMIT_TLP_COUNT_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0TTCR/W1C0hCount of TLPs transmitted

3.5.4.12 PCIE_CORE_LM_I_TRANSMIT_TLP_PAYLOAD_DWORD_COUNT_REG Register (Offset = 0010002Ch) [reset = 0h]

PCIE_CORE_LM_I_TRANSMIT_TLP_PAYLOAD_DWORD_COUNT_REG is shown in Figure 12-1604 and described in Table 12-3152.

Return to the Summary Table.

This register contains the aggregate number of payload double-words transmitted in
Transaction-Layer Packets by the Controller on the link since the register was last reset. This
counter saturates on reaching a count of all 1's. Writing all 1's to this register causes it
to be reset to 0.

Table 12-3151 PCIE_CORE_LM_I_TRANSMIT_TLP_PAYLOAD_DWORD_COUNT_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 002Ch
Figure 12-1604 PCIE_CORE_LM_I_TRANSMIT_TLP_PAYLOAD_DWORD_COUNT_REG Register
313029282726252423222120191817161514131211109876543210
TTPBC
R/W1C-0h
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3152 PCIE_CORE_LM_I_TRANSMIT_TLP_PAYLOAD_DWORD_COUNT_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0TTPBCR/W1C0hCount of TLPs payload Dwords transmitted

3.5.4.13 PCIE_CORE_LM_I_RECEIVE_TLP_COUNT_REG Register (Offset = 00100030h) [reset = 0h]

PCIE_CORE_LM_I_RECEIVE_TLP_COUNT_REG is shown in Figure 12-1605 and described in Table 12-3154.

Return to the Summary Table.

This register contains the number of Transaction-Layer packets received by the Controller
from the link since the register was last reset. This counter saturates on reaching a count
of all 1's. Writing all 1's to this register causes it to be reset to 0.

Table 12-3153 PCIE_CORE_LM_I_RECEIVE_TLP_COUNT_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0030h
Figure 12-1605 PCIE_CORE_LM_I_RECEIVE_TLP_COUNT_REG Register
313029282726252423222120191817161514131211109876543210
RTC
R/W1C-0h
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3154 PCIE_CORE_LM_I_RECEIVE_TLP_COUNT_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0RTCR/W1C0hCount of TLPs received

3.5.4.14 PCIE_CORE_LM_I_RECEIVE_TLP_PAYLOAD_DWORD_COUNT_REG Register (Offset = 00100034h) [reset = 0h]

PCIE_CORE_LM_I_RECEIVE_TLP_PAYLOAD_DWORD_COUNT_REG is shown in Figure 12-1606 and described in Table 12-3156.

Return to the Summary Table.

This register contains the aggregate number of payload double-words received in
Transaction-Layer packets by the Controller from the link since the register was last reset. This
counter saturates on reaching a count of all 1's. Writing all 1's to this register causes it
to be reset to 0.

Table 12-3155 PCIE_CORE_LM_I_RECEIVE_TLP_PAYLOAD_DWORD_COUNT_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0034h
Figure 12-1606 PCIE_CORE_LM_I_RECEIVE_TLP_PAYLOAD_DWORD_COUNT_REG Register
313029282726252423222120191817161514131211109876543210
RTPDC
R/W1C-0h
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3156 PCIE_CORE_LM_I_RECEIVE_TLP_PAYLOAD_DWORD_COUNT_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0RTPDCR/W1C0hCount of TLP payload Dwords received

3.5.4.15 PCIE_CORE_LM_I_COMPLN_TMOUT_LIM_0_REG Register (Offset = 00100038h) [reset = 00BEBC20h]

PCIE_CORE_LM_I_COMPLN_TMOUT_LIM_0_REG is shown in Figure 12-1607 and described in Table 12-3158.

Return to the Summary Table.

This register contains the timeout value used to detect a completion timeout event for a
request originated by the Controller from it master interface, when sub-range 1 is programmed in
the Device Control 2 Register.

Table 12-3157 PCIE_CORE_LM_I_COMPLN_TMOUT_LIM_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0038h
Figure 12-1607 PCIE_CORE_LM_I_COMPLN_TMOUT_LIM_0_REG Register
313029282726252423222120191817161514131211109876543210
R5CTL
R-0hR/W-00BEBC20h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3158 PCIE_CORE_LM_I_COMPLN_TMOUT_LIM_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-24R5R0hReserved
23-0CTLR/W00BEBC20hTimeout limit for completion timers [in 4 ns cycles].
Default value is 50 ms in 4 ns cycles.
Please note that there could be a variation of 0 to +8us on the programmed Completion Timeout.

3.5.4.16 PCIE_CORE_LM_I_COMPLN_TMOUT_LIM_1_REG Register (Offset = 0010003Ch) [reset = 02FAF080h]

PCIE_CORE_LM_I_COMPLN_TMOUT_LIM_1_REG is shown in Figure 12-1608 and described in Table 12-3160.

Return to the Summary Table.

This register contains the timeout value used to detect a completion timeout event for a
request originated by the Controller from its master interface, when sub-range 2 is programmed in
the Device Control 2 Register.

Table 12-3159 PCIE_CORE_LM_I_COMPLN_TMOUT_LIM_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 003Ch
Figure 12-1608 PCIE_CORE_LM_I_COMPLN_TMOUT_LIM_1_REG Register
313029282726252423222120191817161514131211109876543210
R6CTL
R-0hR/W-02FAF080h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3160 PCIE_CORE_LM_I_COMPLN_TMOUT_LIM_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-28R6R0hReserved
27-0CTLR/W02FAF080hTimeout limit for completion timers [in 4 ns cycles].
Default value is 200ms in 4ns cycles.
Please note that there could be a variation of 0 to +8us on the programmed Completion Timeout.

3.5.4.17 PCIE_CORE_LM_I_L1_ST_REENTRY_DELAY_REG Register (Offset = 00100040h) [reset = 0h]

PCIE_CORE_LM_I_L1_ST_REENTRY_DELAY_REG is shown in Figure 12-1609 and described in Table 12-3162.

Return to the Summary Table.

This register specifies the time the Controller will wait before it re-enters the L1 state if
its link partner transitions the link to L0 while all the Functions of the Controller are in D3 power
state. The Controller will change the power state of the link from L0 to L1 if no activity is detected
both on the transmit and receive sides before this interval, while all Functions are in D3 state
and the link is in L0. Setting this register to 0 disables re-entry to L1 state if the link
partner returns the link to L0 from L1 when all the Functions of the Controller are in D3 state. This
register controls only the re-entry to L1. The initial transition to L1 always occurs when all
of the Functions of the Controller are set to the D3 state.

Table 12-3161 PCIE_CORE_LM_I_L1_ST_REENTRY_DELAY_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0040h
Figure 12-1609 PCIE_CORE_LM_I_L1_ST_REENTRY_DELAY_REG Register
313029282726252423222120191817161514131211109876543210
L1RD
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3162 PCIE_CORE_LM_I_L1_ST_REENTRY_DELAY_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0L1RDR/W0hDelay to re-enter L1 after no activity [in units of 16 ns].

3.5.4.18 PCIE_CORE_LM_I_VENDOR_ID_REG Register (Offset = 00100044h) [reset = 17CD17CDh]

PCIE_CORE_LM_I_VENDOR_ID_REG is shown in Figure 12-1610 and described in Table 12-3164.

Return to the Summary Table.

This register contains the Vendor ID and Subsystem Vendor ID that the device advertises
during its enumeration of the PCI configuration space.

Table 12-3163 PCIE_CORE_LM_I_VENDOR_ID_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0044h
Figure 12-1610 PCIE_CORE_LM_I_VENDOR_ID_REG Register
313029282726252423222120191817161514131211109876543210
SVIDVID
R/W-17CDhR/W-17CDh
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3164 PCIE_CORE_LM_I_VENDOR_ID_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16SVIDR/W17CDhSubsystem Vendor ID
15-0VIDR/W17CDhVendor ID

3.5.4.19 PCIE_CORE_LM_I_ASPM_L1_ENTRY_TMOUT_DELAY_REG Register (Offset = 00100048h) [reset = 2EEh]

PCIE_CORE_LM_I_ASPM_L1_ENTRY_TMOUT_DELAY_REG is shown in Figure 12-1611 and described in Table 12-3166.

Return to the Summary Table.

This register defines the timeout value for transitioning to the L1 power state under
Active State Power management. If the transmit side has been idle for this interval, the Controller
will initiate a transition of its link to the L1 power state.

Table 12-3165 PCIE_CORE_LM_I_ASPM_L1_ENTRY_TMOUT_DELAY_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0048h
Figure 12-1611 PCIE_CORE_LM_I_ASPM_L1_ENTRY_TMOUT_DELAY_REG Register
3130292827262524
DISLNRXCHKR7
R/W-0hR-0h
2322212019181716
R7L1T
R-0hR/W-2EEh
15141312111098
L1T
R/W-2EEh
76543210
L1T
R/W-2EEh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3166 PCIE_CORE_LM_I_ASPM_L1_ENTRY_TMOUT_DELAY_REG Register Field Descriptions
BitFieldTypeResetDescription
31DISLNRXCHKR/W0hThis bit is used to configure the ASPM L1 Entry mechanism:

1: Link is checked for IDLE only on the TX to determine ASPM L1 Entry.
ASPM L1 entry is initiated if no TLP is transmitted for the L1 timeout period.

0: Link is checked for IDLE both on the TX and RX to determine ASPM L1 Entry.
ASPM L1 entry is initiated if no TLP is transmitted/received for the L1 timeout period.
30-20R7R0hReserved
19-0L1TR/W2EEhContains the timeout value[in units of 16 ns] for transitioning to the L1 power state.
Setting it to 0 permanently disables the transition to the L1 power state.

3.5.4.20 PCIE_CORE_LM_I_PME_TURNOFF_ACK_DELAY_REG Register (Offset = 0010004Ch) [reset = 64h]

PCIE_CORE_LM_I_PME_TURNOFF_ACK_DELAY_REG is shown in Figure 12-1612 and described in Table 12-3168.

Return to the Summary Table.

Defines the time interval between the Controller receiving a PME_Turn_Off message from the
link and generating an ack for it.

Table 12-3167 PCIE_CORE_LM_I_PME_TURNOFF_ACK_DELAY_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 004Ch
Figure 12-1612 PCIE_CORE_LM_I_PME_TURNOFF_ACK_DELAY_REG Register
313029282726252423222120191817161514131211109876543210
R7PTOAD
R-0hR/W-64h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3168 PCIE_CORE_LM_I_PME_TURNOFF_ACK_DELAY_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R7R0hReserved
15-0PTOADR/W64hTime in microseconds between the Controller receiving a PME_TurnOff message TLP and the
Controller sending a PME_TO_Ack response to it.
This field must be set to a non-zero value in order
for the Controller to send a response.
Setting this field to 0 suppresses the Controller's response to
PME_TurnOff message, so that the client may transmit the PME_TO_Ack message through the
master interface.

3.5.4.21 PCIE_CORE_LM_I_LINKWIDTH_CONTROL_REG Register (Offset = 00100050h) [reset = Fh]

PCIE_CORE_LM_I_LINKWIDTH_CONTROL_REG is shown in Figure 12-1613 and described in Table 12-3170.

Return to the Summary Table.

This register can be used to retrain the link to a different width, without bringing the link down.
This register can also be used to retrain the link to a different speed, without bringing the link down.

Table 12-3169 PCIE_CORE_LM_I_LINKWIDTH_CONTROL_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0050h
Figure 12-1613 PCIE_CORE_LM_I_LINKWIDTH_CONTROL_REG Register
3130292827262524
EPLSCRLR2EPTLS
R/W-0hR-0hR/W-0h
2322212019181716
R20DSAG4SCDSAG3SCDSAG2SCRL
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
R0
R-0h
76543210
R0TLM
R-0hR/W-Fh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3170 PCIE_CORE_LM_I_LINKWIDTH_CONTROL_REG Register Field Descriptions
BitFieldTypeResetDescription
31EPLSCRLR/W0hWriting a 1 into this field results in the Controller re-training the link to change its
speed.
When setting this bit to 1, the software must also set the EP Target Link Speed field to
indicate the speed that the EP desires to change on the link.
The EP Controller will attempt to change the link
to this speed.
This bit is cleared by the internal logic of the Controller after the
re-training has been completed and link has reached the L0 state.
Software must wait for the
bit to be clear before setting it again to change the link speed.
30-26R2R0hReserved
25-24EPTLSR/W0hThis field contains the Link Speed that the EP intends to change to during the re-training.
Client needs to ensure that this field is programmed to a speed which is lesser than or equal to
the Target Link Speed field of PF0 Configuration Link Control 2 Register.
Client also needs to ensure that this does not exceed PCIE_GENERATION_SEL strap input.
Defined encodings of this field are:
00 - GEN1
01 - GEN2
10 - GEN3
11 - GEN4
23-20R1R0hReserved
19DSAG4SCR/W0hThis bit is used Only in RP mode.
This bit is not used in EP mode of the Controller.
During initial link training, if both components advertise Gen4 capability and if Gen3 speed change, equalization was successful,
the Controller [RP] autonomously initiates Gen3 to Gen4 speed change, equalization.
If Gen4 autonomous speed change/equalization was unsuccessful, then the Link transitions back to Gen3 L0.
Software can re-initiate Gen4 speed change.
Autonomous Speed Change to Gen4 can be disabled by programming this bit to 1.
Note: If Disable Auto Gen3 Speed Change is disabled, then Auto Gen4 Speed Change must also be
disabled by setting this bit to 1.
18DSAG3SCR/W0hThis bit is used Only in RP mode.
This bit is not used in EP mode of the Controller.
During initial link training, if both components advertise Gen3 capability,
the Controller [RP] autonomously initiates Gen1 to Gen3 speed change, equalization.
If Gen3 autonomous speed change/equalization was unsuccessful, then the Link transitions back to Gen1 L0.
Software can re-initiate Gen3 speed change.
Autonomous Speed Change to Gen3 can be disabled by programming this bit to 1.
17DSAG2SCR/W0hThis bit is used Only in RP mode.
This bit is not used in EP mode of the Controller.
During initial link training, if both components advertise Gen2 capability and if Gen2 is the highest common supported speed
the Controller [RP] autonomously initiates Gen1 to Gen2 speed change.
If Gen2 autonomous speed change was unsuccessful, then the Link transitions back to Gen1 L0.
Software can re-initiate Gen2 speed change.
Autonomous Speed Change to Gen2 can be disabled by programming this bit to 1.
16RLR/W0hWriting a 1 into this field results in the Controller re-training the link to change its
width.
When setting this bit to 1, the software must also set the target lane-map field to
indicate the lanes it desires to be part of the link.
The Controller will attempt to form a link
with this set of lanes.
The link formed at the end of the retraining may include all of these
lanes [if both nodes agree on them during re-training], or the largest subset that both sides
were able to activate.
This bit is cleared by the internal logic of the Controller after the
re-training has been completed and link has reached the L0 state.
Software must wait for the
bit to be clear before setting it again to change the link width.
15-4R0R0hReserved
3-0TLMR/WFhThis field contains the bitmap of the lanes to be included in forming the link during
the re-training.
01 - Retrain to a x1 link

11 - Retrain to a x2 link
1111 - Retrain to a x4 link
If the target lane map includes lanes that were inactive when retraining is initiated, then
both the Controller and its link partner must support the LinkWidth Upconfigure Capability to be
able to activate those lanes.
In RC Mode, the user can check if the remote node has this capability by
reading the Remote Link Upconfigure Capability Status bit in Physical Layer Configuration
Register 0 after the link first came up.

3.5.4.22 PCIE_CORE_LM_I_PL_CONFIG_2_REG Register (Offset = 00100054h) [reset = 1h]

PCIE_CORE_LM_I_PL_CONFIG_2_REG is shown in Figure 12-1614 and described in Table 12-3172.

Return to the Summary Table.

This register controls various LTSSM related capabilities.

Table 12-3171 PCIE_CORE_LM_I_PL_CONFIG_2_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0054h
Figure 12-1614 PCIE_CORE_LM_I_PL_CONFIG_2_REG
3130292827262524
R3
R-0h
2322212019181716
R3
R-0h
15141312111098
R3
R-0h
76543210
R3DQMDCLK_TRN
R-0hR/W-0hR/W-1h
Table 12-3172 PCIE_CORE_LM_I_PL_CONFIG_2_REG Register Field Descriptions
BitFieldTypeResetDescription
31-3R3R0hReserved
2-1DQMDCR/W0hAs per PCIe specification, All Receivers must meet the the Z-RX-DC specification for 2.5 GT/s within 1ms of
entering Detect.Quiet LTSSM substate.
The LTSSM must stay in this substate until the ZRX-DC specification for
2.5 GT/s is met.
This register field can be used to program the minimum time that LTSSM waits on entering Detect.Quiet state.

00 : 0us minimum wait time in Detect.Quiet state.

01 : 100us minimum wait time in Detect.Quiet state.

10 : 1ms minimum wait time in Detect.Quiet state.

11 : 2ms minimum wait time in Detect.Quiet state.
0LK_TRNR/W1hThis bit is AND'ed with the input LINK_TRAINING_ENABLE strap to enable Link Training.

3.5.4.23 PCIE_CORE_LM_I_MULTI_VC_CONROL_REG Register (Offset = 00100070h) [reset = 2h]

PCIE_CORE_LM_I_MULTI_VC_CONROL_REG is shown in Figure 12-1615 and described in Table 12-3174.

Return to the Summary Table.

This register contains control bits to control certain multi VC features

Table 12-3173 PCIE_CORE_LM_I_MULTI_VC_CONROL_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0070h
Figure 12-1615 PCIE_CORE_LM_I_MULTI_VC_CONROL_REG Register
3130292827262524
R31
R-0h
2322212019181716
R31
R-0h
15141312111098
R31
R-0h
76543210
R31RES4RES2WAIT_4_ALL_VC_CC_RDYDMAAM
R-0hR-0hR-0hR/W-1hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3174 PCIE_CORE_LM_I_MULTI_VC_CONROL_REG Register Field Descriptions
BitFieldTypeResetDescription
31-5R31R0hReserved
4RES4R0hReserved
3-2RES2R0hReserved
1WAIT_4_ALL_VC_CC_RDYR/W1hWhen this bit is set, the controller waits for credits to be available to be able to send atleast 1 max payload TLP in all enabled VCs.
When this bit is not set, the controller waits for credits to be available to be able to send atleast 1 max payload TLP in any of the enabled VCs [PCI-SIG recommedned].
0DMAAMR0hReserved

3.5.4.24 PCIE_CORE_LM_I_SRIS_CONTROL_REG Register (Offset = 00100074h) [reset = 0h]

PCIE_CORE_LM_I_SRIS_CONTROL_REG is shown in Figure 12-1616 and described in Table 12-3176.

Return to the Summary Table.

This register contains control bits to enable the SRIS operation in the PHY Layer

Table 12-3175 PCIE_CORE_LM_I_SRIS_CONTROL_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0074h
Figure 12-1616 PCIE_CORE_LM_I_SRIS_CONTROL_REG Register
3130292827262524
R31
R-0h
2322212019181716
R31
R-0h
15141312111098
R31
R-0h
76543210
R31SRISE
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3176 PCIE_CORE_LM_I_SRIS_CONTROL_REG Register Field Descriptions
BitFieldTypeResetDescription
31-1R31R0hReserved
0SRISER/W0hSetting this bit enables SRIS mode in the PHY layer.
This bit should be changed before
link training begins by holding the LINK_TRAINING_ENABLE input to 1'b0.
When SRIS is disabled using this bit the Lower SKP OS Generation Supported Speeds Vector and Lower SKP OS Reception
Supported Speeds Vector in the Link Capabilities Register 2 will be forced to ZERO.
The default value of this register can be controlled using the SRIS_ENABLE strap input.

3.5.4.25 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC1 Register (Offset = 00100080h) [reset = 02020080h]

PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC1 is shown in Figure 12-1617 and described in Table 12-3178.

Return to the Summary Table.

This register contains the initial credit limits advertised by the Controller during th DL
initialization. If the fields of this register are modified, the link must be re-trained to
re-initialize the DL for the modified settings to take effect.
The credit limit fields in this register can be programmed to any value lesser than or equal to the respective default values.
The default values are set to advertise the full size of the receive buffers.
If a value of 0x00 is programmed, it implies infinite credit.
Note: This may result in receiver overflow if received data is back pressured on the Client interface.

Table 12-3177 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0080h
Figure 12-1617 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC1 Register
313029282726252423222120191817161514131211109876543210
NPPCPHCPPC
R/W-20hR/W-20hR/W-80h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3178 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC1 Register Field Descriptions
BitFieldTypeResetDescription
31-20NPPCR/W20hNon-Posted payload credit limit advertised by the Controller for VC 1 .



This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 1.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of 4 DW and then advertised in the InitFC DLLPs.

Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
19-12PHCR/W20hPosted header credit limit advertised by the Controller for VC 1.

This field is in units of 1, 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 1.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of [1 Packet Header] and then advertised in the InitFC DLLPs.

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
11-0PPCR/W80hPosted payload credit limit advertised by the Controller for VC 1.

This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 1.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of 4 DW and then advertised in the InitFC DLLPs.

Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

3.5.4.26 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC1 Register (Offset = 00100084h) [reset = 20h]

PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC1 is shown in Figure 12-1618 and described in Table 12-3180.

Return to the Summary Table.

This register contains the initial credit limits advertised by the Controller during the DL
initialization. If the fields of this register are modified, the link must be re-trained to
re-initialize the DL for the modified settings to take effect.
The credit limit fields in this register can be programmed to any value lesser than or equal to the respective default values.
The default values are set to advertise the full size of the receive buffers.
If a value of 0x00 is programmed, it implies infinite credit.
Note: This may result in receiver overflow if received data is back pressured on the Client interface.

Table 12-3179 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0084h
Figure 12-1618 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC1 Register
313029282726252423222120191817161514131211109876543210
CHCR2CPCNPHCL
R/W-0hR-0hR/W-0hR/W-20h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3180 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC1 Register Field Descriptions
BitFieldTypeResetDescription
31-24CHCR/W0hCompletion header credit limit advertised by the Controller for VC 1 [in number of packets].


This field is in units of 1, 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 1.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of [1 Packet Header] and then advertised in the InitFC DLLPs.

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
23-20R2R0hReserved
19-8CPCR/W0hCompletion payload credit limit advertised by the Controller for VC 1 .


This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 1.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of 4 DW and then advertised in the InitFC DLLPs.

Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
7-0NPHCLR/W20hNon-Posted header credit limit advertised by the Controller for VC 1 [in number of packets].


This field is in units of 1, 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 1.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of [1 Packet Header] and then advertised in the InitFC DLLPs.

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

3.5.4.27 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC1 Register (Offset = 00100088h) [reset = 0h]

PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC1 is shown in Figure 12-1619 and described in Table 12-3182.

Return to the Summary Table.

This register contains the initial credit limits received from the opposite node during
the DL initialization. It is a read-only register.

Table 12-3181 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0088h
Figure 12-1619 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC1 Register
313029282726252423222120191817161514131211109876543210
NPPCPHCPPC
R-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3182 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC1 Register Field Descriptions
BitFieldTypeResetDescription
31-20NPPCR0hNon-Posted payload credit limit received by the Controller for Link 0 .


This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 1.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]


19-12PHCR0hPosted header credit limit received by the Controller for this link .

This field is in units of 1, 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 1.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
11-0PPCR0hPosted payload credit limit received by the Controller for this link .

This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 1.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]

3.5.4.28 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC1 Register (Offset = 0010008Ch) [reset = 0h]

PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC1 is shown in Figure 12-1620 and described in Table 12-3184.

Return to the Summary Table.

This register contains the initial credit limits received from the opposite node during
the DL initialization. It is a read-only register.

Table 12-3183 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 008Ch
Figure 12-1620 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC1 Register
313029282726252423222120191817161514131211109876543210
CHCR3CPCNPHC
R-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3184 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC1 Register Field Descriptions
BitFieldTypeResetDescription
31-24CHCR0hCompletion header credit limit received by the Controller for VC 1 .

This field is in units of 1, 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 1.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
23-20R3R0hReserved
19-8CPCR0hCompletion payload credit limit received by the Controller for VC 1 .


This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 1.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]


7-0NPHCR0hNon-Posted header credit limit received by the Controller for VC 1 .


This field is in units of 1, 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 1.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]


Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.

3.5.4.29 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC2 Register (Offset = 00100090h) [reset = 02020080h]

PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC2 is shown in Figure 12-1621 and described in Table 12-3186.

Return to the Summary Table.

This register contains the initial credit limits advertised by the Controller during th DL
initialization. If the fields of this register are modified, the link must be re-trained to
re-initialize the DL for the modified settings to take effect.
The credit limit fields in this register can be programmed to any value lesser than or equal to the respective default values.
The default values are set to advertise the full size of the receive buffers.
If a value of 0x00 is programmed, it implies infinite credit.
Note: This may result in receiver overflow if received data is back pressured on the Client interface.

Table 12-3185 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0090h
Figure 12-1621 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC2 Register
313029282726252423222120191817161514131211109876543210
NPPCPHCPPC
R/W-20hR/W-20hR/W-80h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3186 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC2 Register Field Descriptions
BitFieldTypeResetDescription
31-20NPPCR/W20hNon-Posted payload credit limit advertised by the Controller for VC 2 .



This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 2.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of 4 DW and then advertised in the InitFC DLLPs.

Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
19-12PHCR/W20hPosted header credit limit advertised by the Controller for VC 2.

This field is in units of 1, 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 2.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of [1 Packet Header] and then advertised in the InitFC DLLPs.

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
11-0PPCR/W80hPosted payload credit limit advertised by the Controller for VC 2.

This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 2.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of 4 DW and then advertised in the InitFC DLLPs.

Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

3.5.4.30 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC2 Register (Offset = 00100094h) [reset = 20h]

PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC2 is shown in Figure 12-1622 and described in Table 12-3188.

Return to the Summary Table.

This register contains the initial credit limits advertised by the Controller during the DL
initialization. If the fields of this register are modified, the link must be re-trained to
re-initialize the DL for the modified settings to take effect.
The credit limit fields in this register can be programmed to any value lesser than or equal to the respective default values.
The default values are set to advertise the full size of the receive buffers.
If a value of 0x00 is programmed, it implies infinite credit.
Note: This may result in receiver overflow if received data is back pressured on the Client interface.

Table 12-3187 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0094h
Figure 12-1622 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC2 Register
313029282726252423222120191817161514131211109876543210
CHCR2CPCNPHCL
R/W-0hR-0hR/W-0hR/W-20h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3188 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC2 Register Field Descriptions
BitFieldTypeResetDescription
31-24CHCR/W0hCompletion header credit limit advertised by the Controller for VC 2 [in number of packets].


This field is in units of 1, 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 2.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of [1 Packet Header] and then advertised in the InitFC DLLPs.

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
23-20R2R0hReserved
19-8CPCR/W0hCompletion payload credit limit advertised by the Controller for VC 2 .


This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 2.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of 4 DW and then advertised in the InitFC DLLPs.

Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
7-0NPHCLR/W20hNon-Posted header credit limit advertised by the Controller for VC 2 [in number of packets].


This field is in units of 1, 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 2.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of [1 Packet Header] and then advertised in the InitFC DLLPs.

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

3.5.4.31 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC2 Register (Offset = 00100098h) [reset = 0h]

PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC2 is shown in Figure 12-1623 and described in Table 12-3190.

Return to the Summary Table.

This register contains the initial credit limits received from the opposite node during
the DL initialization. It is a read-only register.

Table 12-3189 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0098h
Figure 12-1623 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC2 Register
313029282726252423222120191817161514131211109876543210
NPPCPHCPPC
R-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3190 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC2 Register Field Descriptions
BitFieldTypeResetDescription
31-20NPPCR0hNon-Posted payload credit limit received by the Controller for Link 0 .


This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 2.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]


19-12PHCR0hPosted header credit limit received by the Controller for this link .

This field is in units of 1, 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 2.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
11-0PPCR0hPosted payload credit limit received by the Controller for this link .

This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 2.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]

3.5.4.32 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC2 Register (Offset = 0010009Ch) [reset = 0h]

PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC2 is shown in Figure 12-1624 and described in Table 12-3192.

Return to the Summary Table.

This register contains the initial credit limits received from the opposite node during
the DL initialization. It is a read-only register.

Table 12-3191 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 009Ch
Figure 12-1624 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC2 Register
313029282726252423222120191817161514131211109876543210
CHCR3CPCNPHC
R-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3192 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC2 Register Field Descriptions
BitFieldTypeResetDescription
31-24CHCR0hCompletion header credit limit received by the Controller for VC 2 .

This field is in units of 1, 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 2.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
23-20R3R0hReserved
19-8CPCR0hCompletion payload credit limit received by the Controller for VC 2 .


This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 2.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]


7-0NPHCR0hNon-Posted header credit limit received by the Controller for VC 2 .


This field is in units of 1, 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 2.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]


Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.

3.5.4.33 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC3 Register (Offset = 001000A0h) [reset = 02020080h]

PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC3 is shown in Figure 12-1625 and described in Table 12-3194.

Return to the Summary Table.

This register contains the initial credit limits advertised by the Controller during th DL
initialization. If the fields of this register are modified, the link must be re-trained to
re-initialize the DL for the modified settings to take effect.
The credit limit fields in this register can be programmed to any value lesser than or equal to the respective default values.
The default values are set to advertise the full size of the receive buffers.
If a value of 0x00 is programmed, it implies infinite credit.
Note: This may result in receiver overflow if received data is back pressured on the Client interface.

Table 12-3193 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 00A0h
Figure 12-1625 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC3 Register
313029282726252423222120191817161514131211109876543210
NPPCPHCPPC
R/W-20hR/W-20hR/W-80h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3194 PCIE_CORE_LM_I_RCV_CRED_LIM_0_REG_VC3 Register Field Descriptions
BitFieldTypeResetDescription
31-20NPPCR/W20hNon-Posted payload credit limit advertised by the Controller for VC 3 .



This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 3.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of 4 DW and then advertised in the InitFC DLLPs.

Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
19-12PHCR/W20hPosted header credit limit advertised by the Controller for VC 3.

This field is in units of 1, 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 3.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of [1 Packet Header] and then advertised in the InitFC DLLPs.

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
11-0PPCR/W80hPosted payload credit limit advertised by the Controller for VC 3.

This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 3.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of 4 DW and then advertised in the InitFC DLLPs.

Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

3.5.4.34 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC3 Register (Offset = 001000A4h) [reset = 20h]

PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC3 is shown in Figure 12-1626 and described in Table 12-3196.

Return to the Summary Table.

This register contains the initial credit limits advertised by the Controller during the DL
initialization. If the fields of this register are modified, the link must be re-trained to
re-initialize the DL for the modified settings to take effect.
The credit limit fields in this register can be programmed to any value lesser than or equal to the respective default values.
The default values are set to advertise the full size of the receive buffers.
If a value of 0x00 is programmed, it implies infinite credit.
Note: This may result in receiver overflow if received data is back pressured on the Client interface.

Table 12-3195 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 00A4h
Figure 12-1626 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC3 Register
313029282726252423222120191817161514131211109876543210
CHCR2CPCNPHCL
R/W-0hR-0hR/W-0hR/W-20h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3196 PCIE_CORE_LM_I_RCV_CRED_LIM_1_REG_VC3 Register Field Descriptions
BitFieldTypeResetDescription
31-24CHCR/W0hCompletion header credit limit advertised by the Controller for VC 3 [in number of packets].


This field is in units of 1, 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 3.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of [1 Packet Header] and then advertised in the InitFC DLLPs.

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
23-20R2R0hReserved
19-8CPCR/W0hCompletion payload credit limit advertised by the Controller for VC 3 .


This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Local Posted Payload Credit Scale for VC 3.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of 4 DW and then advertised in the InitFC DLLPs.

Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
7-0NPHCLR/W20hNon-Posted header credit limit advertised by the Controller for VC 3 [in number of packets].


This field is in units of 1, 4 or 16 Packet Headers based on the Local Posted Header Credit Scale for VC 3.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]
Note: When Scaled FLow Control is Activated, the programmed credit value is advertised in the InitFC DLLPs.
Else, the programmed credit value is internally normalized to units of [1 Packet Header] and then advertised in the InitFC DLLPs.

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

3.5.4.35 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC3 Register (Offset = 001000A8h) [reset = 0h]

PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC3 is shown in Figure 12-1627 and described in Table 12-3198.

Return to the Summary Table.

This register contains the initial credit limits received from the opposite node during
the DL initialization. It is a read-only register.

Table 12-3197 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 00A8h
Figure 12-1627 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC3 Register
313029282726252423222120191817161514131211109876543210
NPPCPHCPPC
R-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3198 PCIE_CORE_LM_I_TRANSM_CRED_LIM_0_REG_VC3 Register Field Descriptions
BitFieldTypeResetDescription
31-20NPPCR0hNon-Posted payload credit limit received by the Controller for Link 0 .


This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 3.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]


19-12PHCR0hPosted header credit limit received by the Controller for this link .

This field is in units of 1, 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 3.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
11-0PPCR0hPosted payload credit limit received by the Controller for this link .

This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 3.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]

3.5.4.36 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC3 Register (Offset = 001000ACh) [reset = 0h]

PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC3 is shown in Figure 12-1628 and described in Table 12-3200.

Return to the Summary Table.

This register contains the initial credit limits received from the opposite node during
the DL initialization. It is a read-only register.

Table 12-3199 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 00ACh
Figure 12-1628 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC3 Register
313029282726252423222120191817161514131211109876543210
CHCR3CPCNPHC
R-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3200 PCIE_CORE_LM_I_TRANSM_CRED_LIM_1_REG_VC3 Register Field Descriptions
BitFieldTypeResetDescription
31-24CHCR0hCompletion header credit limit received by the Controller for VC 3 .

This field is in units of 1, 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 3.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]

Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.
23-20R3R0hReserved
19-8CPCR0hCompletion payload credit limit received by the Controller for VC 3 .


This field is in units of 4 DWords, 16 DWords or 64 DWords based on the Remote Posted Payload Credit Scale for VC 3.
00b => [units of 4 DWords]
01b => [units of 4 DWords]
10b => [units of 16 DWords]
11b => [units of 64 DWords]


7-0NPHCR0hNon-Posted header credit limit received by the Controller for VC 3 .


This field is in units of 1, 4 or 16 Packet Headers based on the Remote Posted Header Credit Scale for VC 3.
00b => [units of 1 Packet Header]
01b => [units of 1 Packet Header]
10b => [units of 4 Packet Headers]
11b => [units of 16 Packet Headers]


Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of EndEnd TLP Prefixes permitted in a TLP.

3.5.4.37 PCIE_CORE_LM_I_FC_INIT_DELAY_REG Register (Offset = 001000F0h) [reset = 64h]

PCIE_CORE_LM_I_FC_INIT_DELAY_REG is shown in Figure 12-1629 and described in Table 12-3202.

Return to the Summary Table.

This register defines the delay value in between successive FC_INIT DLLPs for VCx.

Table 12-3201 PCIE_CORE_LM_I_FC_INIT_DELAY_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 00F0h
Figure 12-1629 PCIE_CORE_LM_I_FC_INIT_DELAY_REG Register
313029282726252423222120191817161514131211109876543210
R4FCINITDLY
R-0hR/W-64h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3202 PCIE_CORE_LM_I_FC_INIT_DELAY_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R4R0hReserved
15-0FCINITDLYR/W64hDelay between successive sets of P, NP, CPL FC_INIT DLLP transmissions for VCx.

3.5.4.38 PCIE_CORE_LM_I_SHDW_HDR_LOG_0_REG Register (Offset = 00100100h) [reset = 0h]

PCIE_CORE_LM_I_SHDW_HDR_LOG_0_REG is shown in Figure 12-1630 and described in Table 12-3204.

Return to the Summary Table.

N/A

Table 12-3203 PCIE_CORE_LM_I_SHDW_HDR_LOG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0100h
Figure 12-1630 PCIE_CORE_LM_I_SHDW_HDR_LOG_0_REG Register
313029282726252423222120191817161514131211109876543210
SHDW_HDR_LOG_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3204 PCIE_CORE_LM_I_SHDW_HDR_LOG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0SHDW_HDR_LOG_0R/W0hThe value here will be reflected in the target function's header log register when f/w sets any bit in the
the shadow error register.
If the header log is already set in the function's AER space, the value here may not get written and a header log overflow
bit would get set.
This register holds [31:0] value of the TLP header.

3.5.4.39 PCIE_CORE_LM_I_SHDW_HDR_LOG_1_REG Register (Offset = 00100104h) [reset = 0h]

PCIE_CORE_LM_I_SHDW_HDR_LOG_1_REG is shown in Figure 12-1631 and described in Table 12-3206.

Return to the Summary Table.

N/A

Table 12-3205 PCIE_CORE_LM_I_SHDW_HDR_LOG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0104h
Figure 12-1631 PCIE_CORE_LM_I_SHDW_HDR_LOG_1_REG Register
313029282726252423222120191817161514131211109876543210
SHDW_HDR_LOG_1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3206 PCIE_CORE_LM_I_SHDW_HDR_LOG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0SHDW_HDR_LOG_1R/W0hThe value here will be reflected in the target function's header log register when f/w sets any bit in the
the shadow error register.
If the header log is already set in the function's AER space, the value here may not get written and a header log overflow
bit would get set.
This register holds [63:32] value of the TLP header.

3.5.4.40 PCIE_CORE_LM_I_SHDW_HDR_LOG_2_REG Register (Offset = 00100108h) [reset = 0h]

PCIE_CORE_LM_I_SHDW_HDR_LOG_2_REG is shown in Figure 12-1632 and described in Table 12-3208.

Return to the Summary Table.

N/A

Table 12-3207 PCIE_CORE_LM_I_SHDW_HDR_LOG_2_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0108h
Figure 12-1632 PCIE_CORE_LM_I_SHDW_HDR_LOG_2_REG Register
313029282726252423222120191817161514131211109876543210
SHDW_HDR_LOG_2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3208 PCIE_CORE_LM_I_SHDW_HDR_LOG_2_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0SHDW_HDR_LOG_2R/W0hThe value here will be reflected in the target function's header log register when f/w sets any bit in the
the shadow error register.
If the header log is already set in the function's AER space, the value here may not get written and a header log overflow
bit would get set.
This register holds [95:64] value of the TLP header.

3.5.4.41 PCIE_CORE_LM_I_SHDW_HDR_LOG_3_REG Register (Offset = 0010010Ch) [reset = 0h]

PCIE_CORE_LM_I_SHDW_HDR_LOG_3_REG is shown in Figure 12-1633 and described in Table 12-3210.

Return to the Summary Table.

N/A

Table 12-3209 PCIE_CORE_LM_I_SHDW_HDR_LOG_3_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 010Ch
Figure 12-1633 PCIE_CORE_LM_I_SHDW_HDR_LOG_3_REG Register
313029282726252423222120191817161514131211109876543210
SHDW_HDR_LOG_3
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3210 PCIE_CORE_LM_I_SHDW_HDR_LOG_3_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0SHDW_HDR_LOG_3R/W0hThe value here will be reflected in the target function's header log register when f/w sets any bit in the
the shadow error register.
If the header log is already set in the function's AER space, the value here may not get written and a header log overflow
bit would get set.
This register holds [127:96] value of the TLP header.

3.5.4.42 PCIE_CORE_LM_I_SHDW_FUNC_NUM_REG Register (Offset = 00100110h) [reset = 0h]

PCIE_CORE_LM_I_SHDW_FUNC_NUM_REG is shown in Figure 12-1634 and described in Table 12-3212.

Return to the Summary Table.

N/A

Table 12-3211 PCIE_CORE_LM_I_SHDW_FUNC_NUM_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0110h
Figure 12-1634 PCIE_CORE_LM_I_SHDW_FUNC_NUM_REG Register
31302928272625242322212019181716
R0
R-0h
1514131211109876543210
R0SHDW_FUNC_NUM
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3212 PCIE_CORE_LM_I_SHDW_FUNC_NUM_REG Register Field Descriptions
BitFieldTypeResetDescription
31-8R0R0hReserved
7-0SHDW_FUNC_NUMR/W0hThe value here will be the target function number when f/w sets any bit in the shadow error register.

3.5.4.43 PCIE_CORE_LM_I_SHDW_UR_ERR_REG Register (Offset = 00100114h) [reset = 0h]

PCIE_CORE_LM_I_SHDW_UR_ERR_REG is shown in Figure 12-1635 and described in Table 12-3214.

Return to the Summary Table.

Shadow register to create UR error via local f/w. Please make sure this register is written to last, after
writing to all the header log and function number registers. A write to this register with any bits set, will
internally create a single cycle pulse with the corresponding error type and the header log will reflect the value
written in the shadow header log registers.

Table 12-3213 PCIE_CORE_LM_I_SHDW_UR_ERR_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0114h
Figure 12-1635 PCIE_CORE_LM_I_SHDW_UR_ERR_REG Register
3130292827262524
R0
R-0h
2322212019181716
R0
R-0h
15141312111098
R0
R-0h
76543210
R0NP_UR_ERRP_UR_ERR
R-0hW-0hW-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3214 PCIE_CORE_LM_I_SHDW_UR_ERR_REG Register Field Descriptions
BitFieldTypeResetDescription
31-2R0R0hReserved
1NP_UR_ERRW0hIf this bit is set, the corresponding non-posted UR error bits will be set in the AER and device status registers of the target function.
0P_UR_ERRW0hIf this bit is set, the corresponding posted UR error bits will be set in the AER and device status registers of the target function.

3.5.4.44 PCIE_CORE_LM_I_PM_CLK_FREQUENCY_REG Register (Offset = 00100140h) [reset = 19h]

PCIE_CORE_LM_I_PM_CLK_FREQUENCY_REG is shown in Figure 12-1636 and described in Table 12-3216.

Return to the Summary Table.

This register should be programmed with the frequency of the PM_CLK input to the Controller.
The Controller supports the frequency range of 2MHz to 60MHz for PM_CLK.
The reset value reflects the PM_CLK frequency chosen during Controller configuration.
NOTE: PM_CLK will be timed at 60Mhz and the Controller SDC file will be generated accordingly.
If timing is to be closed at a different frequency, then the user needs to update the SDC accordingly.

Table 12-3215 PCIE_CORE_LM_I_PM_CLK_FREQUENCY_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0140h
Figure 12-1636 PCIE_CORE_LM_I_PM_CLK_FREQUENCY_REG Register
313029282726252423222120191817161514131211109876543210
R0PMCLKFRQ
R-0hR/W-19h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3216 PCIE_CORE_LM_I_PM_CLK_FREQUENCY_REG Register Field Descriptions
BitFieldTypeResetDescription
31-8R0R0hReserved
7-0PMCLKFRQR/W19hThis field specifies the PM_CLK Frequency selected.
The encoding is described below:

000000: Reserved

000001: Reserved

000010: PM_CLK is 2 MHz

000011: PM_CLK is 3 MHz

000100: PM_CLK is 4 MHz

000101: PM_CLK is 5 MHz
..

111010: PM_CLK is 58 MHz

111011: PM_CLK is 59 MHz

111100: PM_CLK is 60 MHz

111101 : Reserved

111110 : Reserved

111111 : Reserved
.

3.5.4.45 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN1_REG Register (Offset = 00100144h) [reset = 0h]

PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN1_REG is shown in Figure 12-1637 and described in Table 12-3218.

Return to the Summary Table.

This register indicates the total number of DLLPs received by the Controller in GEN1.
This counter rolls over back to 0 after 4G DLLPs are received.
This register can be used for Debug purposes.

Table 12-3217 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0144h
Figure 12-1637 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN1_REG Register
313029282726252423222120191817161514131211109876543210
DLLPCNT1
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3218 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0DLLPCNT1R0hReflects the total number of DLLPs received by the Controller at GEN1 speed.

3.5.4.46 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN2_REG Register (Offset = 00100148h) [reset = 0h]

PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN2_REG is shown in Figure 12-1638 and described in Table 12-3220.

Return to the Summary Table.

This register indicates the total number of DLLPs received by the Controller in GEN2.
This counter rolls over back to 0 after 4G DLLPs are received.
This register can be used for Debug purposes.

Table 12-3219 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN2_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0148h
Figure 12-1638 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN2_REG Register
313029282726252423222120191817161514131211109876543210
DLLPCNT2
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3220 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN2_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0DLLPCNT2R0hReflects the total number of DLLPs received by the Controller at GEN2 speed.

3.5.4.47 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN3_REG Register (Offset = 0010014Ch) [reset = 0h]

PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN3_REG is shown in Figure 12-1639 and described in Table 12-3222.

Return to the Summary Table.

This register indicates the total number of DLLPs received by the Controller in GEN3.
This counter rolls over back to 0 after 4G DLLPs are received.
This register can be used for Debug purposes.

Table 12-3221 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN3_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 014Ch
Figure 12-1639 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN3_REG Register
313029282726252423222120191817161514131211109876543210
DLLPCNT3
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3222 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN3_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0DLLPCNT3R0hReflects the total number of DLLPs received by the Controller at GEN3 speed.

3.5.4.48 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN4_REG Register (Offset = 00100150h) [reset = 0h]

PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN4_REG is shown in Figure 12-1640 and described in Table 12-3224.

Return to the Summary Table.

This register indicates the total number of DLLPs received by the Controller in GEN4.
This counter rolls over back to 0 after 4G DLLPs are received.
This register can be used for Debug purposes.

Table 12-3223 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN4_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0150h
Figure 12-1640 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN4_REG Register
313029282726252423222120191817161514131211109876543210
DLLPCNT4
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3224 PCIE_CORE_LM_I_DEBUG_DLLP_COUNT_GEN4_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0DLLPCNT4R0hReflects the total number of DLLPs received by the Controller at GEN4 speed.

3.5.4.49 PCIE_CORE_LM_I_VENDOR_DEFINED_MESSAGE_TAG_REG Register (Offset = 00100158h) [reset = X]

PCIE_CORE_LM_I_VENDOR_DEFINED_MESSAGE_TAG_REG is shown in Figure 12-1641 and described in Table 12-3226.

Return to the Summary Table.

The 8-bit Tag field of the Outbound Vendor Defined Messages, transmitted by the Controller, can be programmed in this register.

Table 12-3225 PCIE_CORE_LM_I_VENDOR_DEFINED_MESSAGE_TAG_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0158h
Figure 12-1641 PCIE_CORE_LM_I_VENDOR_DEFINED_MESSAGE_TAG_REG Register
313029282726252423222120191817161514131211109876543210
RESERVEDVDMTAG
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3226 PCIE_CORE_LM_I_VENDOR_DEFINED_MESSAGE_TAG_REG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/WX
7-0VDMTAGR/W0hThe Controller will use the tag programed in this register for all Outbound Vendor Defined Messages.

3.5.4.50 PCIE_CORE_LM_I_NEGOTIATED_LANE_MAP_REG Register (Offset = 00100200h) [reset = 0h]

PCIE_CORE_LM_I_NEGOTIATED_LANE_MAP_REG is shown in Figure 12-1642 and described in Table 12-3228.

Return to the Summary Table.

This register contains a map of the active lanes used by the Controller to form the link
during link training. It also contains a bit to indicate whether the Controller reversed the lane
number on its lanes during link training.

Table 12-3227 PCIE_CORE_LM_I_NEGOTIATED_LANE_MAP_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0200h
Figure 12-1642 PCIE_CORE_LM_I_NEGOTIATED_LANE_MAP_REG Register
31302928272625242322212019181716
R71LRS
R-0hR-0h
1514131211109876543210
R70NLM
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3228 PCIE_CORE_LM_I_NEGOTIATED_LANE_MAP_REG Register Field Descriptions
BitFieldTypeResetDescription
31-17R71R0hReserved
16LRSR0hThis bit set by the Controller at the end of link training if the LTSSM had to reverse the
lane numbers to form the link.
15-4R70R0hReserved
3-0NLMR0hBit i of this field is set to 1 at the end of link training if Lane i is part of the
PCIe link.
The value of this field is valid only when the link is in L0 or L0s states.

3.5.4.51 PCIE_CORE_LM_I_RECEIVE_FTS_COUNT_REG Register (Offset = 00100204h) [reset = 0h]

PCIE_CORE_LM_I_RECEIVE_FTS_COUNT_REG is shown in Figure 12-1643 and described in Table 12-3230.

Return to the Summary Table.

This register contains the FTS count values received from the link partner during link
training for use at the 5 GT/s 8
GT/s and 16 GT/s speeds. These values determine the number of Fast
Training Sequences transmitted by the Controller when it exits the L0s link power state.

Table 12-3229 PCIE_CORE_LM_I_RECEIVE_FTS_COUNT_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0204h
Figure 12-1643 PCIE_CORE_LM_I_RECEIVE_FTS_COUNT_REG Register
313029282726252423222120191817161514131211109876543210
R24RFC16SRFC8SRFC5S
R-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3230 PCIE_CORE_LM_I_RECEIVE_FTS_COUNT_REG Register Field Descriptions
BitFieldTypeResetDescription
31-24R24R0hReserved
23-16RFC16SR0hFTS count received from the other side during link training for use at the 16 GT/s
link speed.
The Controller transmits this many FTS sequences while exiting the L0S state, when
operating at the 16 GT/s speed.
15-8RFC8SR0hFTS count received from the other side during link training for use at the 8 GT/s
link speed.
The Controller transmits this many FTS sequences while exiting the L0S state, when
operating at the 8 GT/s speed.
7-0RFC5SR0hFTS count received from the other side during link training for use at the 5 GT/s
link speed.
The Controller transmits this many FTS sequences while exiting the L0S state, when
operating at the 5 GT/s speed.

3.5.4.52 PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_REG Register (Offset = 00100208h) [reset = 80000000h]

PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_REG is shown in Figure 12-1644 and described in Table 12-3232.

Return to the Summary Table.

N/A

Table 12-3231 PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0208h
Figure 12-1644 PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_REG Register
3130292827262524
EFSRTCADOCDFCUTDEIDGLUSIEDPPEESPCEFLT
R/W-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
DLUCDLRFEDSHECDCIVMCDIOAEFCDOASFCHPRSUPPAWRPRI
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
FDSDSSPLMR1313R1212R1111R1010MSIVCMSDIDBOC
R/W-0hR/W-0hR-0hR-0hR/W-0hR-0hR/W-0hR/W-0h
76543210
R77R6MS
R/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3232 PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_REG Register Field Descriptions
BitFieldTypeResetDescription
31EFSRTCAR/W1hSetting this bit to 0 causes all the enabled Functions to report an error when a
Type-1 configuration access is received by the Controller, targeted at any Function.
Setting it to 1
limits the error reporting to the type-0 Function whose number matches with the Function
number specified in the request.
If the Function number in the request refers to an
unimplemented or disabled Function, all enabled Functions report the error regardless of the
setting of this bit.
30DOCR/W0hSetting this bit to 1 disables the ordering check in the Controller between Completions and
Posted requests received from the link.
29DFCUTR/W0hWhen this bit is 0, the Controller will time out and re-train the link when no Flow Control
Update DLLPs are received from the link within an interval of 128 us.
Setting this bit to 1
disables this timeout.
When the advertised receive credit of the link partner is infinity for
the header and payload of all credit types, this timeout is always suppressed.
The setting of
this bit has no effect in this case.
This bit should not be set during normal operation, but
is useful for testing.
28DEIR/W0hSetting this bit to 1 disables the inferring of electrical idle in the L0 state.
Electrical idle is inferred when no flow control updates and no SKP sequences are received
within an interval of 128 us.
This bit should not be set during normal operation, but is
useful for testing.
27DGLUSR/W0hSetting this bit to 1 disables the update of the LFSRs in the Gen3 descramblers of the
Controller, from the values received in SKP sequences.
This bit should not be set during normal
operation, but is useful for testing.
26IEDPPER/W0hWhen set to 1, this bit inverts the parity bits generated by the Controller for end-to-end
data protection.
This will result in the inversion of parity bits for data payloads delivered
through the HAL Target Interface request descriptor.
This bit is to be used for diagnostics only, and should not be set
during normal operation.
25ESPCR/W0hWhen this bit is set to 1, the Controller will capture the Slot Power Limit Value and Slot
Power Limit Scale parameters from a Set_Slot_Power_Limit message received in the Device
Capabilities Register.
When this bit is 0, the capture is disabled.
This bit is valid only
when the Controller is configured as an EndPoint.
It has no effect when the Controller is a Root
Complex.
24EFLTR/W0hThis bit is provided to shorten the link training time to facilitate fast simulation
of the design, especially at the gate level.
Enabling this bit has the following effects:
1.
The 1 ms, 2 ms, 12 ms, 24 ms, 32 ms and 48 ms timeout intervals in the LTSSM are shortened
by a factor of 500.
2.
In the Polling.Active state of the LTSSM, only 16 training sequences are required to be
transmitted [Instead of 1024] to make the transition to the Configuration state.
This bit should not be set during normal operation of the Controller.
23DLUCR/W0hThe user may set this bit to turn off the link upconfigure capability of the Controller.
Setting this bit prevents the Controller from advertising the link upconfigure capability in
training sequences transmitted in the Configuration.Complete state.
In addition, setting this bit causes the Controller to put the unused lanes into Turn Off mode.
When disable_link_upconfigure_capability==
1:
Controller drives PIPE_TX_ELEC_IDLE==1 AND PIPE_TX_COMPLIANCE==1 for the Unused upper lanes.
The Unused upper lanes are put into Turn Off mode by the PHY as per PIPE specification.

When disable_link_upconfigure_capability==
0:
Controller drives PIPE_TX_ELEC_IDLE==1 AND PIPE_TX_COMPLIANCE==0 for the Unused upper lanes.
The Unused upper lanes are put into Electrical Idle by the PHY.
22DLRFER/W0hWhen this bit is 1, the Controller will not transition its LTSSM into the Recovery state
when it detects a Framing Error at 8 GT/s or 16 GT/s speed [as defined in Section 4.2.2.3.3 of the PCIe
Base Specification 3.0.
This bit must normally be set to 0 so that a Framing Error will cause
the LTSSM to enter Recovery.
The setting of this bit has no effect on the operation of the
Controller at 2.5 and 5 GT/s speeds.
21DSHECR/W0hWhen this bit is 0, the Controller will signal a framing error if it detects a sync header
error in the received blocks at 8 GT/s or 16 GT/s speed [A 00 or 11 binary setting of the sync header on
the received blocks in any lane constitutes a framing error].
Setting this bit to 1 suppresses
this error check.
This bit should normally be set to 0, as the sync header check is mandatory
in the PCIe 3.0 Specifications.
20DCIVMCR/W0hWhen this bit is 1, the Controller will not check for invalid message codes.
This bit
should normally set to 0, as the invalid message code checking is mandatory in the PCIe 3.0
specifications.
19DIOAEFCR/W0hWhen this bit is 1, the Controller will not check for illegal OS after EDS as part of Gen3 Framing Error Checks.

This bit should normally set to 0, as this is a mandatory Gen3 Framing Error check in the PCIe 3.0 specifications.
18DOASFCR/W0hWhen this bit is 1, the Controller will not check for OS after SKIP OS as part of Gen3 Framing Error Checks.

This bit should normally set to 0, as this is a mandatory Gen3 Framing Error check in the PCIe 3.0 specifications.
17HPRSUPPR/W0hWhen this bit is 1, data path parity check is disabled on the TX side of the Controller.
16AWRPRIR/W0hWhen this bit is 1, the AXI bridge places a write request on the HAL Master interface
in preference over a read request if both AXI write and AXI read requests are available to be
asserted on the same clock cycle.
15FDSR/W0hDisable Scrambling/Descrambling in Gen1/Gen2.
14DSSPLMR/W0hDisable sending Set Slot Power Limit Message if the Slot Capabilitied register is configured
13R1313R0hN/A
12R1212R0hN/A
11R1111R/W0hWhen this bit is 1, Disable Client TX MUX Completion and PNP request arbitartion,roundrobin priority logic added to prevent PNP requests from starving when completions are present
10R1010R0hReserved
9MSIVCMSR/W0hSets the mode of generating MSI_VECTOR_COUNT output for all functions.

0 - MSI_VECTOR_COUNT always outputs the configured value of MSI Multiple Message Enable
[2:0] register.

1 - MSI_VECTOR_COUNT outputs the lesser of the MSI Multiple Message Enable
[2:0] and MSI Multiple Message Capable
[2:0]
This mode can be used to handle any programming error form the Host software.
8DIDBOCR/W0hSetting this bit to 1 disables the ID Based Ordering check in the Controller between Completions and
Posted requests received from the link.
7R77R/W0hThis bit should be set to 0 for backward compatibility.
6-5R6R0hN/A
4-0MSR/W0hBits
4:3 select the module and bits
2:0 select the group of signals within the module
that are driven on the debug bus.
The assignments of signals on the debug outputs of the Controller
are given in Appendix B.

3.5.4.53 PCIE_CORE_LM_I_LOCAL_ERROR_STATUS_REGISTER Register (Offset = 0010020Ch) [reset = 0h]

PCIE_CORE_LM_I_LOCAL_ERROR_STATUS_REGISTER is shown in Figure 12-1645 and described in Table 12-3234.

Return to the Summary Table.

This register contains the status of the various events, errors and abnormal conditions in the
Controller. Any of the status bits can be reset by writing a 1 into the bit position. This register
does not capture any errors signaled by remote devices using PCIe error messages when the Controller
is operating in the RC mode. Unless masked by the setting of the Local Interrupt Mask Register,
the occurrence of any of these conditions causes the Controller to activate the LOCAL_INTERRUPT
output.

Table 12-3233 PCIE_CORE_LM_I_LOCAL_ERROR_STATUS_REGISTER Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 020Ch
Figure 12-1645 PCIE_CORE_LM_I_LOCAL_ERROR_STATUS_REGISTER Register
3130292827262524
REORDER_ER_UNAXISLAVE_WFIFO_ER_UNAXIMASTER_RFIFO_ER_UNAXIMASTER_DIB_ER_UNR27MSIXMSKSTR24
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR-0hR/W1C-0hR-0h
2322212019181716
R24HAWCDR22MMVCUTCEEPER13
R-0hR/W1C-0hR-0hR/W1C-0hR/W1C-0hR/W1C-0hR-0h
15141312111098
R13R12CTFCEUCRMTR
R-0hR-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
PERTRRTCRFOPRFORRPECRFPEPRFPE
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3234 PCIE_CORE_LM_I_LOCAL_ERROR_STATUS_REGISTER Register Field Descriptions
BitFieldTypeResetDescription
31REORDER_ER_UNR/W1C0hThis indicates an uncorrectbale axi slave reorder ram parity/ecc error
30AXISLAVE_WFIFO_ER_UNR/W1C0hThis indicates an uncorrectbale axi slave write fifo ram parity/ecc error
29AXIMASTER_RFIFO_ER_UNR/W1C0hThis indicates an uncorrectbale axi master write fifo ram parity/ecc error
28AXIMASTER_DIB_ER_UNR/W1C0hThis indicates an uncorrectbale axi slave write fifo ram parity/ecc error
27-26R27R0hReserved
25MSIXMSKSTR/W1C0h

This interrupt status bit is used when MSIX Function Mask Enhanced Interrupt Enable bit is set to 0 by the User.

This status bit indicates that the MSIX Function Mask bit of any function, PF or VF, was programmed or configured by Local Firmware Or Host SW.
24-22R24R0hReserved
21HAWCDR/W1C0hThis interrupt status bit indicates that the Host toggled the Hardware Autonomous Width Change bit in the Link Control Register through a Config Write.
Upon this interrupt, the Client firmware must read the Link Control Register to check the value set by Host in the Hardware Autonomous Width Change bit.
The Host Software may disable autonomous width change by setting Hardware Autonomous Width Disable bit in the Link Control register.
If disabled by the Host and if the Endpoint firmware had initiated an autonomous width downsizing prior to this interrupt, then the local Client firmware is responsible
to upconfigure the Link to go to its full functional width by initiating the link_upconfigure_retrain_link within 1 ms of this interrupt.
20R22R0hReserved
19MMVCR/W1C0hThis status bit is set whenever the MSI mask register value in the MSI capability
register changes value in ANY of the functions in the controller
18UTCR/W1C0hUnmapped TC error.

17EEPER/W1C0hThe Controller detected an End to End Parity Error
16-13R13R0hReserved
12R12R0hReserved
11CTR/W1C0hA request timed out waiting for completion.
10FCER/W1C0hAn error was observed in the flow control advertisements from the other side.
9UCRR/W1C0hUnexpected Completion received from the link.
8MTRR/W1C0hMalformed TLP received from the link.
7PER/W1C0hPhy error detected on receive side.
This bit is set when an error is detected in the receive side of the Physical Layer of
the Controller [e.g.
a bit error or coding violation].

This bit is set upon any of the following errors:
[1] PHY reported 8B10B error, Disparity Error, Elastic Buffer Overflow Error, Underflow Error
[2] GEN3 TLP, DLLP Framing Errors
[3] OS Block Received Without EDS
[4] Data Block Received After EDS
[5] Illegal OS Block After EDS
[6] OS Block Received After SKIP OS
[7] OS Block Received After SDS
[8] Sync Header Error
[9] Loss of Gen3 Block Alignment
This error is not Function-specific..
6RTRR/W1C0hReplay timer rolled over after 4 transmissions of the same TLP.
5RTR/W1C0hReplay timer timed out
4CRFOR/W1C0hOverflow occurred in the Completion Receive FIFO.
3PRFOR/W1C0hOverflow occurred in the PNP Receive FIFO.
2RRPER/W1C0hParity error detected while reading from Replay Buffer RAM.
1CRFPER/W1C0hParity error detected while reading from the Completion Receive FIFO RAM.
0PRFPER/W1C0hParity error detected while reading from the PNP Receive FIFO RAM.

3.5.4.54 PCIE_CORE_LM_I_LOCAL_INTRPT_MASK_REG Register (Offset = 00100210h) [reset = 022E0FFFh]

PCIE_CORE_LM_I_LOCAL_INTRPT_MASK_REG is shown in Figure 12-1646 and described in Table 12-3236.

Return to the Summary Table.

This register contains a mask bit for each interrupting condition. Setting the bit to 1
prevents the corresponding condition in the Local Error Status Register from activating the
LOCAL_INTERRUPT output.

Table 12-3235 PCIE_CORE_LM_I_LOCAL_INTRPT_MASK_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0210h
Figure 12-1646 PCIE_CORE_LM_I_LOCAL_INTRPT_MASK_REG Register
3130292827262524
REORDER_ER_UNAXISLAVE_WFIFO_ER_UNAXIMASTER_RFIFO_ER_UNAXIMASTER_DIB_ER_UNR27MSIXMSKR24
R/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-1hR-0h
2322212019181716
R24HAWCDR45MMVCUTCEEPER13
R-0hR/W-1hR-0hR/W-1hR/W-1hR/W-1hR-0h
15141312111098
R13R12CTFCEUCRMTR
R-0hR-0hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
PERTRRTCRFOPRFORRPECRFPEPRFPE
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3236 PCIE_CORE_LM_I_LOCAL_INTRPT_MASK_REG Register Field Descriptions
BitFieldTypeResetDescription
31REORDER_ER_UNR/W0hmask for uncorrectbale axi slave reorder ram parity/ecc error
30AXISLAVE_WFIFO_ER_UNR/W0hmask for uncorrectbale axi slave write fifo ram parity/ecc error
29AXIMASTER_RFIFO_ER_UNR/W0hmask for uncorrectbale axi master write fifo ram parity/ecc error
28AXIMASTER_DIB_ER_UNR/W0hmask for uncorrectbale axi slave write fifo ram parity/ecc error
27-26R27R0hReserved
25MSIXMSKR/W1hThis bit is used to mask interrupt that indicates that the MSIX Function Mask bit of any function, PF or VF, was programmed or configured by Local Firmware Or Host SW.
24-22R24R0hReserved
21HAWCDR/W1hThis bit is used to mask interrupt that indicates that the Host toggled the Hardware Autonomous Width Change in the Endpoint Link Control Register through a Config Write.
20R45R0hReserved
19MMVCR/W1hMSI mask register value in the MSI capability register changes value in
ANY of the functions in the controller
18UTCR/W1hUnmapped TC error
17EEPER/W1hThe Controller detected an End to End Parity Error
16-13R13R0hReserved
12R12R0hReserved
11CTR/W1hA request timed out waiting for completion.
10FCER/W1hAn error was observed in the flow control advertisements from the other side.
9UCRR/W1hUnexpected Completion received from the link.
8MTRR/W1hMalformed TLP received from the link.
7PER/W1hPhy error detected on receive side.
6RTRR/W1hReplay timer rolled over after 4 transmissions of the same TLP.
5RTR/W1hReplay timer timed out
4CRFOR/W1hOverflow occurred in the Completion Receive FIFO.
3PRFOR/W1hOverflow occurred in the PNP Receive FIFO.
2RRPER/W1hParity error detected while reading from Replay Buffer RAM.
1CRFPER/W1hParity error detected while reading from the Completion Receive FIFO RAM.
0PRFPER/W1hParity error detected while reading from the PNP Receive FIFO RAM.

3.5.4.55 PCIE_CORE_LM_I_LCRC_ERR_COUNT_REG Register (Offset = 00100214h) [reset = 0h]

PCIE_CORE_LM_I_LCRC_ERR_COUNT_REG is shown in Figure 12-1647 and described in Table 12-3238.

Return to the Summary Table.

This register contains the count of the number of TLPs received by the Controller with LCRC
errors in them. This is a 16-bit saturating counter that can be reset to 0 by writing all 1's
into it.

Table 12-3237 PCIE_CORE_LM_I_LCRC_ERR_COUNT_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0214h
Figure 12-1647 PCIE_CORE_LM_I_LCRC_ERR_COUNT_REG Register
313029282726252423222120191817161514131211109876543210
R11LEC
R-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3238 PCIE_CORE_LM_I_LCRC_ERR_COUNT_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R11R0hReserved
15-0LECR/W1C0hNumber of TLPs received with LCRC errors.

3.5.4.56 PCIE_CORE_LM_I_ECC_CORR_ERR_COUNT_REG Register (Offset = 00100218h) [reset = 0h]

PCIE_CORE_LM_I_ECC_CORR_ERR_COUNT_REG is shown in Figure 12-1648 and described in Table 12-3240.

Return to the Summary Table.

This register contains the count of the number of ECC errors detected and corrected
during reads from the PCIe core external RAMs.

Table 12-3239 PCIE_CORE_LM_I_ECC_CORR_ERR_COUNT_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0218h
Figure 12-1648 PCIE_CORE_LM_I_ECC_CORR_ERR_COUNT_REG Register
313029282726252423222120191817161514131211109876543210
R31_2RRCERSFRCERPFRCER
R-0hR/W1C-0hR/W1C-0hR/W1C-0h
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3240 PCIE_CORE_LM_I_ECC_CORR_ERR_COUNT_REG Register Field Descriptions
BitFieldTypeResetDescription
31-24R31_2R0hReserved
23-16RRCERR/W1C0hNumber of correctable errors detected while reading from the Replay Buffer RAM.
This
is an
8-bit saturating counter that can be cleared by writing all 1's into it.
15-8SFRCERR/W1C0hNumber of correctable errors detected while reading from the SC FIFO RAM.
This is an

8-bit saturating counter that can be cleared by writing all 1's into it.
7-0PFRCERR/W1C0hNumber of correctable errors detected while reading from the PNP FIFO RAM.
This is an

8-bit saturating counter that can be cleared by writing all 1's into it.

3.5.4.57 PCIE_CORE_LM_I_LTR_SNOOP_LAT_REG Register (Offset = 0010021Ch) [reset = 0h]

PCIE_CORE_LM_I_LTR_SNOOP_LAT_REG is shown in Figure 12-1649 and described in Table 12-3242.

Return to the Summary Table.

This register contains the Snoop and No-Snoop Latency parameters used by the Controller when
sending Latency Tolerance Reporting (LTR) Message. When the Controller is configured in the EndPoint
mode, client software can program these fields to the desired latency settings and then set the
Send LTR Message bit in the LTR Message Generation Control Register to send an LTR message to
the Root Complex. The fields in this register should not be changed when the Send LTR Message
bit in the LTR Message Generation Control Register is 1, which indicates that an LTR message is
pending to be transmitted.

Table 12-3241 PCIE_CORE_LM_I_LTR_SNOOP_LAT_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 021Ch
Figure 12-1649 PCIE_CORE_LM_I_LTR_SNOOP_LAT_REG Register
3130292827262524
SLR13SLSSLV
R/W-0hR-0hR/W-0hR/W-0h
2322212019181716
SLV
R/W-0h
15141312111098
NSLRR12NSLSNSLV
R/W-0hR-0hR/W-0hR/W-0h
76543210
NSLV
R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3242 PCIE_CORE_LM_I_LTR_SNOOP_LAT_REG Register Field Descriptions
BitFieldTypeResetDescription
31SLR/W0hThe client software must set this bit to 1 to set the Snoop Latency Requirement bit in the LTR
message to be sent.
30-29R13R0hReserved
28-26SLSR/W0hThe client software must program this field with the value to be sent in the Snoop
Latency Scale field of the LTR message.
25-16SLVR/W0hThe client software must program this field with the value to be sent in the Snoop
Latency Value field of the LTR message.
15NSLRR/W0hThe client software must set this bit to 1 to set the No-Snoop Latency Requirement bit
in the LTR message to be sent.
14-13R12R0hN/A
12-10NSLSR/W0hThe client software must program this field with the value to be sent in the No-Snoop
Latency Scale field of the LTR message.
9-0NSLVR/W0hThe client software must program this field with the value to be sent in the No-Snoop
Latency Value field of the LTR message.

3.5.4.58 PCIE_CORE_LM_I_LTR_MSG_GEN_CTL_REG Register (Offset = 00100220h) [reset = X]

PCIE_CORE_LM_I_LTR_MSG_GEN_CTL_REG is shown in Figure 12-1650 and described in Table 12-3244.

Return to the Summary Table.

This register contains fields for the generation of Latency Tolerance Reporting (LTR)
Messages. This register is to be used only when the Controller is configured in the EndPoint mode.

Table 12-3243 PCIE_CORE_LM_I_LTR_MSG_GEN_CTL_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0220h
Figure 12-1650 PCIE_CORE_LM_I_LTR_MSG_GEN_CTL_REG Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDTMFPSCTMLMETSLMMLI
R/W-XR/W-1hR/W-1hR-0hR/W-FAh
76543210
MLI
R/W-FAh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3244 PCIE_CORE_LM_I_LTR_MSG_GEN_CTL_REG Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR/WX
12TMFPSCR/W1hWhen this bit is set to 1, the Controller will automatically transmit an LTR message when
all the Functions in the Controller have transitioned to a non-D0 power state, provided that the
following conditions are both true: 1.
The Controller sent at least one LTR message since the Data
Link layer last transitioned from down to up state.
2.
The most recent LTR message
transmitted by the Controller had as least one of the Requirement bits set.
The Controller will set the
Requirement bits in this LTR message to 0.
When this bit 12 is 0, the Controller will not, by
itself, send any LTR messages in response to Function Power State changes.
Client logic may
monitor the FUNCTION_POWER_STATE outputs of the Controller and transmit LTR messages through the
master interface, in response to changes in their states.
11TMLMETR/W1hWhen this bit is set to 1, the Controller will automatically transmit an LTR message
whenever the LTR Mechanism Enable bit in the Device Control 2 Register changes from 0 to 1,
with the parameters specified in the LTR Snoop/No-Snoop Latency Register.
When this bit is 1,
the Controller will also transmit an LTR message whenever the LTR Mechanism Enable bit is cleared,
if the following conditions are both true:
1.
The Controller sent at least one LTR message since the LTR Mechanism Enable bit was last set.
2.
The most recent LTR message transmitted by the Controller had as least one of the Requirement
bits set.
The Controller will set the Requirement bits in this LTR message to 0.
When this bit 11 is 0, the Controller will not, by itself, send any LTR messages in response to
state changes of the LTR Mechanism Enable bit.
Client logic may monitor the state of the
LTR_MECHANISM_ ENABLE output of the Controller and transmit LTR messages through the master
interface, in response to its state changes.
10SLMR0hSetting this bit causes the Controller to transmit an LTR message with the parameters
specified in the LTR Snoop/No-Snoop Latency Register.
This bit is cleared by
the Controller on transmitting the LTR message, and stays set until then.
Client software must read
this register and verify that this bit is 0 before setting it again to send a new message.
This field becomes writable when LTR mechanism is enabled in device control-2 register.
9-0MLIR/WFAhThis field specifies the minimum spacing between LTR messages transmitted by the Controller
in units of microseconds.
The PCI Express Specifications recommend sending no more than two
LTR messages within a 500 microsecond interval.
The Controller will wait for the minimum delay
specified by this field after sending an LTR message, before transmitting a new LTR message.
NOTE: The LINK can be in low power states[L0s and L1] when send LTR Message is trigered.
So, the user has to consider the exit latencies while programming this field.
It is recommended to program this field with about 2 us higher than the required interval to
account for the L0s/L1 exit latencies.

3.5.4.59 PCIE_CORE_LM_I_PME_SERVICE_TIMEOUT_DELAY_REG Register (Offset = 00100224h) [reset = 000186A0h]

PCIE_CORE_LM_I_PME_SERVICE_TIMEOUT_DELAY_REG is shown in Figure 12-1651 and described in Table 12-3246.

Return to the Summary Table.

This register stores the timeout delay parameter for the service timeout mechanism
associated with the generation of PM_PME messages. In the EndPoint mode, the Controller will
retransmit a PM_PME message after the expiration of this delay, if the Root Complex did not
clear the PME Status bit in the Power Management Control and Status Register. This register is
not used when the Controller is configured as Root Complex.

Table 12-3245 PCIE_CORE_LM_I_PME_SERVICE_TIMEOUT_DELAY_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0224h
Figure 12-1651 PCIE_CORE_LM_I_PME_SERVICE_TIMEOUT_DELAY_REG Register
3130292827262524
R21
R-0h
2322212019181716
R21DPMOPSPSTD
R-0hR/W-0hR/W-000186A0h
15141312111098
PSTD
R/W-000186A0h
76543210
PSTD
R/W-000186A0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3246 PCIE_CORE_LM_I_PME_SERVICE_TIMEOUT_DELAY_REG Register Field Descriptions
BitFieldTypeResetDescription
31-21R21R0hReserved
20DPMOPSR/W0hWhen this bit is set, Controller will not automatically send a PME message, when PM Status
bit in PMCSR register is set
19-0PSTDR/W000186A0hSpecifies the timeout delay for retransmission of PM_PME messages.
The value is in
units of microseconds.
The actual time elapsed has a +1 microseconds tolerance from the value programmed.

3.5.4.60 PCIE_CORE_LM_I_ROOT_PORT_REQUESTOR_ID_REG Register (Offset = 00100228h) [reset = 0h]

PCIE_CORE_LM_I_ROOT_PORT_REQUESTOR_ID_REG is shown in Figure 12-1652 and described in Table 12-3248.

Return to the Summary Table.

When the Controller is configured as Root Complex, this ID will be used for all internally
generated messages.

Table 12-3247 PCIE_CORE_LM_I_ROOT_PORT_REQUESTOR_ID_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0228h
Figure 12-1652 PCIE_CORE_LM_I_ROOT_PORT_REQUESTOR_ID_REG Register
313029282726252423222120191817161514131211109876543210
R0RPRI
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3248 PCIE_CORE_LM_I_ROOT_PORT_REQUESTOR_ID_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R0R0hReserved
15-0RPRIR/W0hRID [bus, device and function numbers] for all TLPs internally generated by Root Port

3.5.4.61 PCIE_CORE_LM_I_EP_BUS_DEVICE_NUMBER_REG Register (Offset = 0010022Ch) [reset = 0h]

PCIE_CORE_LM_I_EP_BUS_DEVICE_NUMBER_REG is shown in Figure 12-1653 and described in Table 12-3250.

Return to the Summary Table.

When the Controller is configured as End Point, this register holds the Bus and Device number
captured for Function 0

Table 12-3249 PCIE_CORE_LM_I_EP_BUS_DEVICE_NUMBER_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 022Ch
Figure 12-1653 PCIE_CORE_LM_I_EP_BUS_DEVICE_NUMBER_REG Register
313029282726252423222120191817161514131211109876543210
R16EPBNR5EPDN
R-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3250 PCIE_CORE_LM_I_EP_BUS_DEVICE_NUMBER_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R16R0hReserved
15-8EPBNR0hBus Number captured by Function 0 in End Point mode
7-5R5R0hReserved
4-0EPDNR0hDevice Number captured by Function 0 in End Point mode

3.5.4.62 PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_2_REG Register (Offset = 00100234h) [reset = 10040850h]

PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_2_REG is shown in Figure 12-1654 and described in Table 12-3252.

Return to the Summary Table.

N/A

Table 12-3251 PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_2_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0234h
Figure 12-1654 PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_2_REG Register
3130292827262524
HRLTR30DRXRMFRDFLRTRBDTAE2EPR26MSIXMSKENMSIMSKEN
R/W-0hR-0hR/W-0hR/W-1hR/W-0hR-0hR/W-0hR/W-0h
2322212019181716
VARCCLKENMAXNPREQ
R/W-0hR/W-20h
15141312111098
MAXNPREQAXINPSPEN_RSVDCMPTOADVPSNADVMSIPIMSENG4REV05
R/W-20hR-0hR/W-1hR/W-0hR/W-0hR/W-0h
76543210
BLKALNWINBLKALNCHKARICAPMODENLNCHKDISSDSCHKEXTSNPDLFFS
R/W-1hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3252 PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_2_REG Register Field Descriptions
BitFieldTypeResetDescription
31HRLTR/W0hIf set this bit makes the HOT_RESET_OUT signal behave as a level signal rather than a
pulse.
When set , the HOT_RESET_OUT will be asserted as long as the controller is in the HOT
Reset state.
30R30R0hReserved
29DRXRMFRR/W0hBy default, when an Uncorrectable error is detected on a receive FIFO RAM,
then no packets are read out of the RAM subsequent to the error and the RAMs
are frozen.
0 : Receive FIFO RAMs are frozen after an uncorrectable error.
1 : Receive FIFO RAMs continue to read subsequent packets after an uncorrectable error.
28DFLRTRBR/W1h
1 : NP Termination due to FLR/Completion Timeout is delayed till the RX Completion FIFO is Empty.


0 : NP Termination due to FLR is done immediately on receiving FLR/Completion Timeout.

27DTAE2EPR/W0hBy default, when End to End Parity error is detected on inbound/outbound data streams,
then all the transmitted outbound packets will be Nullified by the Controller.
This bit can be used to turn off nullifying Tx packets on End to End Parity Error.
26R26R0hReserved
25MSIXMSKENR/W0hBy default, the Controller provides a single status bit when any function's MSIX Function Mask
is programmed or configured by Local firmware or Host SW.
Controller also implements an enhanced MSIX Function Mask Interrupt mechanism, which provides
per-function set/clear status when a function's MSIX Function Mask is updated by SW.

This Local Management programmable bit allows user to choose between the Default and
Enhanced MSIX Function Mask Change Interrupt mechanisms.
24MSIMSKENR/W0hBy default, the Controller provides a single status bit when any function's MSI Mask
is programmed or configured by Local firmware or Host SW.
Controller also implements an enhanced MSI Mask Interrupt mechanism, which provides
per-function set/clear status when a function's MSI Mask is updated by SW.

This Local Management programmable bit allows user to choose between the Default and
Enhanced MSI Mask Change Interrupt mechanisms.
23VARCCLKENR/W0hIf this bit is set the CORE_CLK input can be driven with Variable Clock depending on
the Link Speed,similar to the PIPE_PCLK.
22-13MAXNPREQR/W20hThe Controller supports 32 outstanding NP requests that can be initiated by the User.
However, the number of split completion TLPs that can be stored in the Controller is limited to 128.
The Completion FIFO will overflow if more than 128 split completion packets are pending.
If the User interface can accept inbound Posted and Completion packets at the same rate as received from PCIe link,
then the split completion FIFO will never reach the FULL condition.
However, if the User cannot guarantee this,
then this register needs to be programmed as described in the Programming Guide section of the Controller User guide.
The Controller will limit the maximum number of outstanding NP requests to the value programmed in this register.
Example:

8 : Controller will limit maximum number of outstanding NP requests to 8.

0-
7 : Reserved
Default Value is 32
12AXINPSPEN_RSVDR0hRESERVED
11CMPTOADVR/W1hAs per PCIe specification on Error Signaling, the Requester detecting a Completion
Timeout is allowed to handle this as an Advisory Non Fatal Error.

1: Completion Timeout is handled as Advisory Non-Fatal Error.

0: Completion Timeout is handled as normally as a Non-Fatal Error.
10PSNADVR/W0hAs per PCIe specification 2.7.2.2, the following Poisoned TLP requests must be handled as Uncorrectable and not as Advisory:
I/O Write Request, Memory Write Request, or non-vendor-defined Message with data that target a Control structure.
Since it is not possible for the Controller to determine if the target is a Control or
a non-Control strusture, the Controller implements this bit for the user to determine
the required handling.

1: Poisoned TLP of type IOWr, MemWr, MsgD will be handled as Advisory Non-Fatal Error.

0: Poisoned TLP of type IOWr, MemWr, MsgD will be handled as Uncorrectable Error.
Note: Poisoned CplD will always be reported as Advisory Non-Fatal and is not controlled by this register setting.
9MSIPIMSR/W0hIf the Client wishes to use the MSI_PENDING_STATUS_IN Signal to Update the MSI pending
Bits register, this bit needs to be set to 1.
Otherwise the Pending Bits register
is updated via the APB Interface
8ENG4REV05R/W0hWhen operating in Gen4 16GT/s , This Enables Gen4 Spec Revision 0.5 EIEOS and SKP features.
When disabled, the Gen4 1.0 features are enabled, by default this bit is ZERO.

1: Enable Gen4 0.5 Features

0: Disable Gen4 0.5 Features [This enabled the Gen4 1.0 Features] .
7-6BLKALNWINR/W1hWhen in the data stream at Gen3 or higher speeds, the pipe_rx_valid is asserted by the PHY.
If the block alignment is lost, then the PHY may deassert pipe_rx_valid.
Controller reports loss of block alignment if pipe_rx_valid or pipe_rx_data_valid=0
for a period consecutive clock cycles as programmed in this field.

00: 8 CORE_CLK cycles

01: 16 CORE_CLK cycles

10: 64 CORE_CLK cycles

11: 256 CORE_CLK cycles
5BLKALNCHKR/W0hWhen in the data stream at Gen3 or higher speeds, the pipe_rx_valid is asserted by the PHY.
If the block alignment is lost, then the PHY may deassert pipe_rx_valid.
Block Alignment may be lost if the received sync header is invalid.
Controller supports detecting loss of block alignment while in a data stream in Gen3.

0: Enable check for loss of Gen3 Block Alignment during data stream.

1: Disable check for loss of Gen3 Block Alignment.
4ARICAPMODR/W1hAs per SR IOC specification, ARI Capable Hierarchy bit is only present in the lowest numbered PF of a Device.
The Controller has two modes to determine the lowest numbered PF.

0: the first PF which is enabled [PF0] is taken as the lowest numbered PF.

1: the first PF which has a non-zero TOTAL_VF_COUNT field is taken as the lowest numbered PF.[Default Mode]
3ENLNCHKR/W0hAs per PCIe specification, LTSSM should transition to Disabled after any Lanes that are transmitting TS1 Ordered Sets receive two
consecutive TS1 Ordered Sets with the Disable Link bit asserted.
Similarly, LTSSM should transition to Loopback after all Lanes that are transmitting TS1 Ordered Sets, that are also
receiving TS1 Ordered Sets, receive the Loopback bit asserted in two consecutive TS1 Ordered Sets.
Controller ignores the Link and Lane Number in the Received TS1s with Loopback/Disable bit set.
Setting this bit to 1 turns on the check for link number [assigned by RC in Recovery.Idle] and lane number [PAD in Config.LW.Start or as assigned by RC in Recovery.Idle].
This bit is recommended to be kept at the default value of 0.
2DISSDSCHKR/W0hAs per PCIe specification, When using 128b/130b encoding, next state is L0 if eight consecutive Symbol Times of Idle
data are received on all configured Lanes.
The Controller checks to ensure that the Idle symbols of data are received in Data Blocks after SDS OS.
This check is enabled by default.
Setting this bit to 1 turns off this check.
This bit is recommended to be kept at the default value of 0.
1EXTSNPR/W0hThis bit can be set if an extra clock cycle is required by the Client Application logic
to respond with the Read Data on Configuration Snoop Interface.
Please refer to the
user guide section on Configuration Snoop Interface for timing diagrams.
0DLFFSR/W0hAs per PIPE 4.2 specification, the LOCALLF, LOCALFS outputs from PHY can be sampled uponf PHYSTATUS pulse after Reset# OR
upon the first PHYSTATUS pulse after speed change to GEN3.
This bit can be set to 1 to disable sampling after speed change to GEN3 or higher

3.5.4.63 PCIE_CORE_LM_I_PHY_STATUS_1_REG Register (Offset = 00100238h) [reset = 0h]

PCIE_CORE_LM_I_PHY_STATUS_1_REG is shown in Figure 12-1655 and described in Table 12-3254.

Return to the Summary Table.

This status register provides additional debug information about the PHY. Bits 8:0
provide information to debug Receiver Errors.

Table 12-3253 PCIE_CORE_LM_I_PHY_STATUS_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0238h
Figure 12-1655 PCIE_CORE_LM_I_PHY_STATUS_1_REG Register
3130292827262524
R31
R-0h
2322212019181716
R31
R-0h
15141312111098
R31LOSBLKALN
R-0hR/W1C-0h
76543210
INVSYNHROSAFSDSG3FRERROSWOEDSDATEDSILOSEDSOSASKPTLPPHYER
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3254 PCIE_CORE_LM_I_PHY_STATUS_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-9R31R0hReserved
8LOSBLKALNR/W1C0hThis bit is set if the PHY Loses Block Alignment during data stream.
This is detected based upon an unexpected PIPE_RX_VALID input deassertion during data stream.
Write a 1 to clear this error.
7INVSYNHRR/W1C0hThis bit is set if an invalid Sync Header is detected.
00 and 11 are Invalid Sync Headers.
Write a 1 to clear this error.
.
6OSAFSDSR/W1C0hThis bit is set if an SDS is received after an SDS.
This is a framing error.
Write a 1 to clear this error.
5G3FRERRR/W1C0hThis bit is set if a framing error is detected while receiving a TLP in Gen3.
Example, if an invalid token is received in a data stream, this error is flagged.
Write a 1 to clear this error.
4OSWOEDSR/W1C0hThis bit is set if an Ordered Set Block is received without an EDS.
This is a framing error.
Write a 1 to clear this error.
3DATEDSR/W1C0hThis bit is set if a Data Block is received after an EDS.
Write a 1 to clear this error.
2ILOSEDSR/W1C0hThe Valid OS blocks after an EDS are EIOS, EIEOS and SKP.
If any other OS blocks are received after EDS, then it is a framing error and this bit is asserted.
1OSASKPR/W1C0hThis bit indicates that an Ordered Set BLock was received immediately after a SKIP OS.
This is a framing error.
Write a 1 to clear this field.
0TLPPHYERR/W1C0hThis bit indicates that a PHY Error was detected on the PIPE_RX_STATUS within a TLP.
Write a 1 to clear this field.

3.5.4.64 PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_3_REG Register (Offset = 0010023Ch) [reset = 0h]

PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_3_REG is shown in Figure 12-1656 and described in Table 12-3256.

Return to the Summary Table.

N/A

Table 12-3255 PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_3_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 023Ch
Figure 12-1656 PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_3_REG Register
3130292827262524
R2
R-0h
2322212019181716
R2
R-0h
15141312111098
R2
R-0h
76543210
R2DRCDSDESDLTEDGDPCR0
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0h
Table 12-3256 PCIE_CORE_LM_I_DEBUG_MUX_CONTROL_3_REG Register Field Descriptions
BitFieldTypeResetDescription
31-5R2R0hReserved
4DRCR/W0hUSed to disable and enable the RCB checker and by default it is enabled
3DSDESR/W0hUsed to disable and enable Surprise Down Error status logging and by default it is enabled
2DLTER/W0hUsed to disable and enable link training error logging and by default it is enabled
1DGDPCR/W0hTo disable GEN4 data parity check from LM register
0R0R0hReserved

3.5.4.65 PCIE_CORE_LM_I_PF_0_BAR_CONFIG_0_REG Register (Offset = 00100240h) [reset = 05050585h]

PCIE_CORE_LM_I_PF_0_BAR_CONFIG_0_REG is shown in Figure 12-1657 and described in Table 12-3258.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical Function 0

Table 12-3257 PCIE_CORE_LM_I_PF_0_BAR_CONFIG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0240h
Figure 12-1657 PCIE_CORE_LM_I_PF_0_BAR_CONFIG_0_REG Register
31302928272625242322212019181716
BAR3CBAR3ABAR2CBAR2A
R/W-0hR/W-5hR/W-0hR/W-5h
1514131211109876543210
BAR1CBAR1ABAR0CBAR0A
R/W-0hR/W-5hR/W-4hR/W-5h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3258 PCIE_CORE_LM_I_PF_0_BAR_CONFIG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-29BAR3CR/W0hSpecifies the configuration of BAR3.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
28-24BAR3AR/W5hSpecifies the aperture of the BAR 3 when it is configured as a
32-bit BAR.

For
32-bit BAR 3, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
23-21BAR2CR/W0hSpecifies the configuration of BAR2.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
20-16BAR2AR/W5hSpecifies the aperture of the
32-bit BAR 2 or 64bit BAR
2-3.

For
32-bit BAR 2, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
2-3, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

15-13BAR1CR/W0hSpecifies the configuration of BAR1.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8BAR1AR/W5hSpecifies the aperture of the BAR 1 when it is configured as a
32-bit BAR.

For
32-bit BAR 1, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
7-5BAR0CR/W4hSpecifies the configuration of BAR0.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0BAR0AR/W5hSpecifies the aperture of the
32-bit BAR 0 or 64bit BAR
0-1.

For
32-bit BAR 0, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
0-1, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

3.5.4.66 PCIE_CORE_LM_I_PF_0_BAR_CONFIG_1_REG Register (Offset = 00100244h) [reset = 505h]

PCIE_CORE_LM_I_PF_0_BAR_CONFIG_1_REG is shown in Figure 12-1658 and described in Table 12-3260.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical
Function.

Table 12-3259 PCIE_CORE_LM_I_PF_0_BAR_CONFIG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0244h
Figure 12-1658 PCIE_CORE_LM_I_PF_0_BAR_CONFIG_1_REG Register
3130292827262524
ERBCR24
R/W-0hR-0h
2322212019181716
R16
R-0h
15141312111098
BAR5CBAR5A
R/W-0hR/W-5h
76543210
BAR4CBAR4A
R/W-0hR/W-5h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3260 PCIE_CORE_LM_I_PF_0_BAR_CONFIG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31ERBCR/W0hSetting this bit to 1 enables the Resizable BAR Capability in the PCI Express
Configuration Space of the associated Function.
When the Resizable BAR Capability is enabled,
the apertures of the memory BARs of the corresponding Function are no longer selected by the
fields in this register, but by the setting of the registers in the Resizable BAR Capability
Structure.
30-24R24R0hReserved
23-16R16R0hReserved
15-13BAR5CR/W0hSpecifies the configuration of BAR5.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8BAR5AR/W5hSpecifies the aperture of the BAR 5 when it is configured as a
32-bit BAR.

For
32-bit BAR 5, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
7-5BAR4CR/W0hSpecifies the configuration of BAR4.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0BAR4AR/W5hSpecifies the aperture of the
32-bit BAR 4 or 64bit BAR
4-5.

For
32-bit BAR 4, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
4-5, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

3.5.4.67 PCIE_CORE_LM_I_PF_1_BAR_CONFIG_0_REG Register (Offset = 00100248h) [reset = 05050585h]

PCIE_CORE_LM_I_PF_1_BAR_CONFIG_0_REG is shown in Figure 12-1659 and described in Table 12-3262.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical Function 1

Table 12-3261 PCIE_CORE_LM_I_PF_1_BAR_CONFIG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0248h
Figure 12-1659 PCIE_CORE_LM_I_PF_1_BAR_CONFIG_0_REG Register
31302928272625242322212019181716
BAR3CBAR3ABAR2CBAR2A
R/W-0hR/W-5hR/W-0hR/W-5h
1514131211109876543210
BAR1CBAR1ABAR0CBAR0A
R/W-0hR/W-5hR/W-4hR/W-5h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3262 PCIE_CORE_LM_I_PF_1_BAR_CONFIG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-29BAR3CR/W0hSpecifies the configuration of BAR3.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
28-24BAR3AR/W5hSpecifies the aperture of the BAR 3 when it is configured as a
32-bit BAR.

For
32-bit BAR 3, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
23-21BAR2CR/W0hSpecifies the configuration of BAR2.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
20-16BAR2AR/W5hSpecifies the aperture of the
32-bit BAR 2 or 64bit BAR
2-3.

For
32-bit BAR 2, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
2-3, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

15-13BAR1CR/W0hSpecifies the configuration of BAR1.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8BAR1AR/W5hSpecifies the aperture of the BAR 1 when it is configured as a
32-bit BAR.

For
32-bit BAR 1, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
7-5BAR0CR/W4hSpecifies the configuration of BAR0.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0BAR0AR/W5hSpecifies the aperture of the
32-bit BAR 0 or 64bit BAR
0-1.

For
32-bit BAR 0, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
0-1, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

3.5.4.68 PCIE_CORE_LM_I_PF_1_BAR_CONFIG_1_REG Register (Offset = 0010024Ch) [reset = 505h]

PCIE_CORE_LM_I_PF_1_BAR_CONFIG_1_REG is shown in Figure 12-1660 and described in Table 12-3264.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical
Function.

Table 12-3263 PCIE_CORE_LM_I_PF_1_BAR_CONFIG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 024Ch
Figure 12-1660 PCIE_CORE_LM_I_PF_1_BAR_CONFIG_1_REG Register
3130292827262524
ERBCR24
R/W-0hR-0h
2322212019181716
R16
R-0h
15141312111098
BAR5CBAR5A
R/W-0hR/W-5h
76543210
BAR4CBAR4A
R/W-0hR/W-5h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3264 PCIE_CORE_LM_I_PF_1_BAR_CONFIG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31ERBCR/W0hSetting this bit to 1 enables the Resizable BAR Capability in the PCI Express
Configuration Space of the associated Function.
When the Resizable BAR Capability is enabled,
the apertures of the memory BARs of the corresponding Function are no longer selected by the
fields in this register, but by the setting of the registers in the Resizable BAR Capability
Structure.
30-24R24R0hReserved
23-16R16R0hReserved
15-13BAR5CR/W0hSpecifies the configuration of BAR5.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8BAR5AR/W5hSpecifies the aperture of the BAR 5 when it is configured as a
32-bit BAR.

For
32-bit BAR 5, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
7-5BAR4CR/W0hSpecifies the configuration of BAR4.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0BAR4AR/W5hSpecifies the aperture of the
32-bit BAR 4 or 64bit BAR
4-5.

For
32-bit BAR 4, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
4-5, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

3.5.4.69 PCIE_CORE_LM_I_PF_2_BAR_CONFIG_0_REG Register (Offset = 00100250h) [reset = 05050585h]

PCIE_CORE_LM_I_PF_2_BAR_CONFIG_0_REG is shown in Figure 12-1661 and described in Table 12-3266.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical Function 2

Table 12-3265 PCIE_CORE_LM_I_PF_2_BAR_CONFIG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0250h
Figure 12-1661 PCIE_CORE_LM_I_PF_2_BAR_CONFIG_0_REG Register
31302928272625242322212019181716
BAR3CBAR3ABAR2CBAR2A
R/W-0hR/W-5hR/W-0hR/W-5h
1514131211109876543210
BAR1CBAR1ABAR0CBAR0A
R/W-0hR/W-5hR/W-4hR/W-5h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3266 PCIE_CORE_LM_I_PF_2_BAR_CONFIG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-29BAR3CR/W0hSpecifies the configuration of BAR3.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
28-24BAR3AR/W5hSpecifies the aperture of the BAR 3 when it is configured as a
32-bit BAR.

For
32-bit BAR 3, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
23-21BAR2CR/W0hSpecifies the configuration of BAR2.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
20-16BAR2AR/W5hSpecifies the aperture of the
32-bit BAR 2 or 64bit BAR
2-3.

For
32-bit BAR 2, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
2-3, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

15-13BAR1CR/W0hSpecifies the configuration of BAR1.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8BAR1AR/W5hSpecifies the aperture of the BAR 1 when it is configured as a
32-bit BAR.

For
32-bit BAR 1, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
7-5BAR0CR/W4hSpecifies the configuration of BAR0.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0BAR0AR/W5hSpecifies the aperture of the
32-bit BAR 0 or 64bit BAR
0-1.

For
32-bit BAR 0, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
0-1, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

3.5.4.70 PCIE_CORE_LM_I_PF_2_BAR_CONFIG_1_REG Register (Offset = 00100254h) [reset = 505h]

PCIE_CORE_LM_I_PF_2_BAR_CONFIG_1_REG is shown in Figure 12-1662 and described in Table 12-3268.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical
Function.

Table 12-3267 PCIE_CORE_LM_I_PF_2_BAR_CONFIG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0254h
Figure 12-1662 PCIE_CORE_LM_I_PF_2_BAR_CONFIG_1_REG Register
3130292827262524
ERBCR24
R/W-0hR-0h
2322212019181716
R16
R-0h
15141312111098
BAR5CBAR5A
R/W-0hR/W-5h
76543210
BAR4CBAR4A
R/W-0hR/W-5h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3268 PCIE_CORE_LM_I_PF_2_BAR_CONFIG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31ERBCR/W0hSetting this bit to 1 enables the Resizable BAR Capability in the PCI Express
Configuration Space of the associated Function.
When the Resizable BAR Capability is enabled,
the apertures of the memory BARs of the corresponding Function are no longer selected by the
fields in this register, but by the setting of the registers in the Resizable BAR Capability
Structure.
30-24R24R0hReserved
23-16R16R0hReserved
15-13BAR5CR/W0hSpecifies the configuration of BAR5.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8BAR5AR/W5hSpecifies the aperture of the BAR 5 when it is configured as a
32-bit BAR.

For
32-bit BAR 5, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
7-5BAR4CR/W0hSpecifies the configuration of BAR4.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0BAR4AR/W5hSpecifies the aperture of the
32-bit BAR 4 or 64bit BAR
4-5.

For
32-bit BAR 4, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
4-5, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

3.5.4.71 PCIE_CORE_LM_I_PF_3_BAR_CONFIG_0_REG Register (Offset = 00100258h) [reset = 05050585h]

PCIE_CORE_LM_I_PF_3_BAR_CONFIG_0_REG is shown in Figure 12-1663 and described in Table 12-3270.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical Function 3

Table 12-3269 PCIE_CORE_LM_I_PF_3_BAR_CONFIG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0258h
Figure 12-1663 PCIE_CORE_LM_I_PF_3_BAR_CONFIG_0_REG Register
31302928272625242322212019181716
BAR3CBAR3ABAR2CBAR2A
R/W-0hR/W-5hR/W-0hR/W-5h
1514131211109876543210
BAR1CBAR1ABAR0CBAR0A
R/W-0hR/W-5hR/W-4hR/W-5h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3270 PCIE_CORE_LM_I_PF_3_BAR_CONFIG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-29BAR3CR/W0hSpecifies the configuration of BAR3.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
28-24BAR3AR/W5hSpecifies the aperture of the BAR 3 when it is configured as a
32-bit BAR.

For
32-bit BAR 3, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
23-21BAR2CR/W0hSpecifies the configuration of BAR2.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
20-16BAR2AR/W5hSpecifies the aperture of the
32-bit BAR 2 or 64bit BAR
2-3.

For
32-bit BAR 2, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
2-3, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

15-13BAR1CR/W0hSpecifies the configuration of BAR1.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8BAR1AR/W5hSpecifies the aperture of the BAR 1 when it is configured as a
32-bit BAR.

For
32-bit BAR 1, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
7-5BAR0CR/W4hSpecifies the configuration of BAR0.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0BAR0AR/W5hSpecifies the aperture of the
32-bit BAR 0 or 64bit BAR
0-1.

For
32-bit BAR 0, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
0-1, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

3.5.4.72 PCIE_CORE_LM_I_PF_3_BAR_CONFIG_1_REG Register (Offset = 0010025Ch) [reset = 505h]

PCIE_CORE_LM_I_PF_3_BAR_CONFIG_1_REG is shown in Figure 12-1664 and described in Table 12-3272.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical
Function.

Table 12-3271 PCIE_CORE_LM_I_PF_3_BAR_CONFIG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 025Ch
Figure 12-1664 PCIE_CORE_LM_I_PF_3_BAR_CONFIG_1_REG Register
3130292827262524
ERBCR24
R/W-0hR-0h
2322212019181716
R16
R-0h
15141312111098
BAR5CBAR5A
R/W-0hR/W-5h
76543210
BAR4CBAR4A
R/W-0hR/W-5h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3272 PCIE_CORE_LM_I_PF_3_BAR_CONFIG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31ERBCR/W0hSetting this bit to 1 enables the Resizable BAR Capability in the PCI Express
Configuration Space of the associated Function.
When the Resizable BAR Capability is enabled,
the apertures of the memory BARs of the corresponding Function are no longer selected by the
fields in this register, but by the setting of the registers in the Resizable BAR Capability
Structure.
30-24R24R0hReserved
23-16R16R0hReserved
15-13BAR5CR/W0hSpecifies the configuration of BAR5.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8BAR5AR/W5hSpecifies the aperture of the BAR 5 when it is configured as a
32-bit BAR.

For
32-bit BAR 5, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
7-5BAR4CR/W0hSpecifies the configuration of BAR4.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0BAR4AR/W5hSpecifies the aperture of the
32-bit BAR 4 or 64bit BAR
4-5.

For
32-bit BAR 4, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
4-5, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

3.5.4.73 PCIE_CORE_LM_I_PF_4_BAR_CONFIG_0_REG Register (Offset = 00100260h) [reset = 05050585h]

PCIE_CORE_LM_I_PF_4_BAR_CONFIG_0_REG is shown in Figure 12-1665 and described in Table 12-3274.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical Function 4

Table 12-3273 PCIE_CORE_LM_I_PF_4_BAR_CONFIG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0260h
Figure 12-1665 PCIE_CORE_LM_I_PF_4_BAR_CONFIG_0_REG Register
31302928272625242322212019181716
BAR3CBAR3ABAR2CBAR2A
R/W-0hR/W-5hR/W-0hR/W-5h
1514131211109876543210
BAR1CBAR1ABAR0CBAR0A
R/W-0hR/W-5hR/W-4hR/W-5h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3274 PCIE_CORE_LM_I_PF_4_BAR_CONFIG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-29BAR3CR/W0hSpecifies the configuration of BAR3.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
28-24BAR3AR/W5hSpecifies the aperture of the BAR 3 when it is configured as a
32-bit BAR.

For
32-bit BAR 3, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
23-21BAR2CR/W0hSpecifies the configuration of BAR2.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
20-16BAR2AR/W5hSpecifies the aperture of the
32-bit BAR 2 or 64bit BAR
2-3.

For
32-bit BAR 2, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
2-3, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

15-13BAR1CR/W0hSpecifies the configuration of BAR1.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8BAR1AR/W5hSpecifies the aperture of the BAR 1 when it is configured as a
32-bit BAR.

For
32-bit BAR 1, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
7-5BAR0CR/W4hSpecifies the configuration of BAR0.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0BAR0AR/W5hSpecifies the aperture of the
32-bit BAR 0 or 64bit BAR
0-1.

For
32-bit BAR 0, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
0-1, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

3.5.4.74 PCIE_CORE_LM_I_PF_4_BAR_CONFIG_1_REG Register (Offset = 00100264h) [reset = 505h]

PCIE_CORE_LM_I_PF_4_BAR_CONFIG_1_REG is shown in Figure 12-1666 and described in Table 12-3276.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical
Function.

Table 12-3275 PCIE_CORE_LM_I_PF_4_BAR_CONFIG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0264h
Figure 12-1666 PCIE_CORE_LM_I_PF_4_BAR_CONFIG_1_REG Register
3130292827262524
ERBCR24
R/W-0hR-0h
2322212019181716
R16
R-0h
15141312111098
BAR5CBAR5A
R/W-0hR/W-5h
76543210
BAR4CBAR4A
R/W-0hR/W-5h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3276 PCIE_CORE_LM_I_PF_4_BAR_CONFIG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31ERBCR/W0hSetting this bit to 1 enables the Resizable BAR Capability in the PCI Express
Configuration Space of the associated Function.
When the Resizable BAR Capability is enabled,
the apertures of the memory BARs of the corresponding Function are no longer selected by the
fields in this register, but by the setting of the registers in the Resizable BAR Capability
Structure.
30-24R24R0hReserved
23-16R16R0hReserved
15-13BAR5CR/W0hSpecifies the configuration of BAR5.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8BAR5AR/W5hSpecifies the aperture of the BAR 5 when it is configured as a
32-bit BAR.

For
32-bit BAR 5, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
7-5BAR4CR/W0hSpecifies the configuration of BAR4.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0BAR4AR/W5hSpecifies the aperture of the
32-bit BAR 4 or 64bit BAR
4-5.

For
32-bit BAR 4, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
4-5, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

3.5.4.75 PCIE_CORE_LM_I_PF_5_BAR_CONFIG_0_REG Register (Offset = 00100268h) [reset = 05050585h]

PCIE_CORE_LM_I_PF_5_BAR_CONFIG_0_REG is shown in Figure 12-1667 and described in Table 12-3278.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical Function 5

Table 12-3277 PCIE_CORE_LM_I_PF_5_BAR_CONFIG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0268h
Figure 12-1667 PCIE_CORE_LM_I_PF_5_BAR_CONFIG_0_REG Register
31302928272625242322212019181716
BAR3CBAR3ABAR2CBAR2A
R/W-0hR/W-5hR/W-0hR/W-5h
1514131211109876543210
BAR1CBAR1ABAR0CBAR0A
R/W-0hR/W-5hR/W-4hR/W-5h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3278 PCIE_CORE_LM_I_PF_5_BAR_CONFIG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-29BAR3CR/W0hSpecifies the configuration of BAR3.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
28-24BAR3AR/W5hSpecifies the aperture of the BAR 3 when it is configured as a
32-bit BAR.

For
32-bit BAR 3, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
23-21BAR2CR/W0hSpecifies the configuration of BAR2.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
20-16BAR2AR/W5hSpecifies the aperture of the
32-bit BAR 2 or 64bit BAR
2-3.

For
32-bit BAR 2, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
2-3, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

15-13BAR1CR/W0hSpecifies the configuration of BAR1.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8BAR1AR/W5hSpecifies the aperture of the BAR 1 when it is configured as a
32-bit BAR.

For
32-bit BAR 1, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
7-5BAR0CR/W4hSpecifies the configuration of BAR0.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0BAR0AR/W5hSpecifies the aperture of the
32-bit BAR 0 or 64bit BAR
0-1.

For
32-bit BAR 0, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
0-1, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

3.5.4.76 PCIE_CORE_LM_I_PF_5_BAR_CONFIG_1_REG Register (Offset = 0010026Ch) [reset = 505h]

PCIE_CORE_LM_I_PF_5_BAR_CONFIG_1_REG is shown in Figure 12-1668 and described in Table 12-3280.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical
Function.

Table 12-3279 PCIE_CORE_LM_I_PF_5_BAR_CONFIG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 026Ch
Figure 12-1668 PCIE_CORE_LM_I_PF_5_BAR_CONFIG_1_REG Register
3130292827262524
ERBCR24
R/W-0hR-0h
2322212019181716
R16
R-0h
15141312111098
BAR5CBAR5A
R/W-0hR/W-5h
76543210
BAR4CBAR4A
R/W-0hR/W-5h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3280 PCIE_CORE_LM_I_PF_5_BAR_CONFIG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31ERBCR/W0hSetting this bit to 1 enables the Resizable BAR Capability in the PCI Express
Configuration Space of the associated Function.
When the Resizable BAR Capability is enabled,
the apertures of the memory BARs of the corresponding Function are no longer selected by the
fields in this register, but by the setting of the registers in the Resizable BAR Capability
Structure.
30-24R24R0hReserved
23-16R16R0hReserved
15-13BAR5CR/W0hSpecifies the configuration of BAR5.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8BAR5AR/W5hSpecifies the aperture of the BAR 5 when it is configured as a
32-bit BAR.

For
32-bit BAR 5, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB
7-5BAR4CR/W0hSpecifies the configuration of BAR4.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0BAR4AR/W5hSpecifies the aperture of the
32-bit BAR 4 or 64bit BAR
4-5.

For
32-bit BAR 4, the valid encodings are:

00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB

For
64-bit BAR
4-5, the valid encodings are:


00000 = 128 B,
00001 = 256 B,
00010 = 512 B,
00011 = 1 KB,
00100 = 2 KB,
00101 = 4 KB,
00110 = 8 KB,
00111 = 16 KB,

01000 = 32 KB,
01001 = 64 KB,
01010 = 128 KB,
01011 = 256 KB,
01100 = 512 KB,
01101 = 1 MB,
01110 = 2 MB,

01111 = 4 MB,
10000 = 8 MB,
10001 = 16 MB,
10010 = 32 MB,
10011 = 64 MB,
10100 = 128 MB,
10101 = 256 MB,

10110 = 512 MB,
10111 = 1 GB,
11000 = 2 GB,
11001 = 4 GB,
11010 = 8 GB,
11011 = 16 GB,
11100 = 32 GB,

11101 = 64 GB,
11110 = 128 GB,
11111 = 256 GB

3.5.4.77 PCIE_CORE_LM_I_PF_0_VF_BAR_CONFIG_0_REG Register (Offset = 00100280h) [reset = 0F0F8FCFh]

PCIE_CORE_LM_I_PF_0_VF_BAR_CONFIG_0_REG is shown in Figure 12-1669 and described in Table 12-3282.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical Function 0

Table 12-3281 PCIE_CORE_LM_I_PF_0_VF_BAR_CONFIG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0280h
Figure 12-1669 PCIE_CORE_LM_I_PF_0_VF_BAR_CONFIG_0_REG Register
31302928272625242322212019181716
VFBAR3CVFBAR3AVFBAR2CVFBAR2A
R/W-0hR/W-FhR/W-0hR/W-Fh
1514131211109876543210
VFBAR1CVFBAR1AVFBAR0CVFBAR0A
R/W-4hR/W-FhR/W-6hR/W-Fh
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3282 PCIE_CORE_LM_I_PF_0_VF_BAR_CONFIG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-29VFBAR3CR/W0hSpecifies the configuration of VF BAR3.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
28-24VFBAR3AR/WFhSpecifies the aperture of the VF BAR 3 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
23-21VFBAR2CR/W0hSpecifies the configuration of VF BAR2.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
20-16VFBAR2AR/WFhSpecifies the aperture of the
32-bit VF BAR 2 or 64bit VF BAR
2-3.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes
15-13VFBAR1CR/W4hSpecifies the configuration of VF BAR1.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8VFBAR1AR/WFhSpecifies the aperture of the VF BAR 1 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
7-5VFBAR0CR/W6hSpecifies the configuration of VF BAR0.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0VFBAR0AR/WFhSpecifies the aperture of the
32-bit VF BAR 0 or 64bit VF BAR
0-1.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes

3.5.4.78 PCIE_CORE_LM_I_PF_0_VF_BAR_CONFIG_1_REG Register (Offset = 00100284h) [reset = F0Fh]

PCIE_CORE_LM_I_PF_0_VF_BAR_CONFIG_1_REG is shown in Figure 12-1670 and described in Table 12-3284.

Return to the Summary Table.

This register specifies the configuration of the VF BARs associated with the Physical
Function.

Table 12-3283 PCIE_CORE_LM_I_PF_0_VF_BAR_CONFIG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0284h
Figure 12-1670 PCIE_CORE_LM_I_PF_0_VF_BAR_CONFIG_1_REG Register
31302928272625242322212019181716
R16
R-0h
1514131211109876543210
VFBAR5CVFBAR5AVFBAR4CVFBAR4A
R/W-0hR/W-FhR/W-0hR/W-Fh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3284 PCIE_CORE_LM_I_PF_0_VF_BAR_CONFIG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R16R0hReserved
15-13VFBAR5CR/W0hSpecifies the configuration of VF BAR5.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8VFBAR5AR/WFhSpecifies the aperture of the VF BAR 5 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
7-5VFBAR4CR/W0hSpecifies the configuration of VF BAR4.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0VFBAR4AR/WFhSpecifies the aperture of the
32-bit VF BAR 4 or 64bit VF BAR
4-5.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes

3.5.4.79 PCIE_CORE_LM_I_PF_1_VF_BAR_CONFIG_0_REG Register (Offset = 00100288h) [reset = 0F0F8FCFh]

PCIE_CORE_LM_I_PF_1_VF_BAR_CONFIG_0_REG is shown in Figure 12-1671 and described in Table 12-3286.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical Function 1

Table 12-3285 PCIE_CORE_LM_I_PF_1_VF_BAR_CONFIG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0288h
Figure 12-1671 PCIE_CORE_LM_I_PF_1_VF_BAR_CONFIG_0_REG Register
31302928272625242322212019181716
VFBAR3CVFBAR3AVFBAR2CVFBAR2A
R/W-0hR/W-FhR/W-0hR/W-Fh
1514131211109876543210
VFBAR1CVFBAR1AVFBAR0CVFBAR0A
R/W-4hR/W-FhR/W-6hR/W-Fh
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3286 PCIE_CORE_LM_I_PF_1_VF_BAR_CONFIG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-29VFBAR3CR/W0hSpecifies the configuration of VF BAR3.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
28-24VFBAR3AR/WFhSpecifies the aperture of the VF BAR 3 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
23-21VFBAR2CR/W0hSpecifies the configuration of VF BAR2.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
20-16VFBAR2AR/WFhSpecifies the aperture of the
32-bit VF BAR 2 or 64bit VF BAR
2-3.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes
15-13VFBAR1CR/W4hSpecifies the configuration of VF BAR1.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8VFBAR1AR/WFhSpecifies the aperture of the VF BAR 1 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
7-5VFBAR0CR/W6hSpecifies the configuration of VF BAR0.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0VFBAR0AR/WFhSpecifies the aperture of the
32-bit VF BAR 0 or 64bit VF BAR
0-1.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes

3.5.4.80 PCIE_CORE_LM_I_PF_1_VF_BAR_CONFIG_1_REG Register (Offset = 0010028Ch) [reset = F0Fh]

PCIE_CORE_LM_I_PF_1_VF_BAR_CONFIG_1_REG is shown in Figure 12-1672 and described in Table 12-3288.

Return to the Summary Table.

This register specifies the configuration of the VF BARs associated with the Physical
Function.

Table 12-3287 PCIE_CORE_LM_I_PF_1_VF_BAR_CONFIG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 028Ch
Figure 12-1672 PCIE_CORE_LM_I_PF_1_VF_BAR_CONFIG_1_REG Register
31302928272625242322212019181716
R16
R-0h
1514131211109876543210
VFBAR5CVFBAR5AVFBAR4CVFBAR4A
R/W-0hR/W-FhR/W-0hR/W-Fh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3288 PCIE_CORE_LM_I_PF_1_VF_BAR_CONFIG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R16R0hReserved
15-13VFBAR5CR/W0hSpecifies the configuration of VF BAR5.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8VFBAR5AR/WFhSpecifies the aperture of the VF BAR 5 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
7-5VFBAR4CR/W0hSpecifies the configuration of VF BAR4.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0VFBAR4AR/WFhSpecifies the aperture of the
32-bit VF BAR 4 or 64bit VF BAR
4-5.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes

3.5.4.81 PCIE_CORE_LM_I_PF_2_VF_BAR_CONFIG_0_REG Register (Offset = 00100290h) [reset = 0F0F8FCFh]

PCIE_CORE_LM_I_PF_2_VF_BAR_CONFIG_0_REG is shown in Figure 12-1673 and described in Table 12-3290.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical Function 2

Table 12-3289 PCIE_CORE_LM_I_PF_2_VF_BAR_CONFIG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0290h
Figure 12-1673 PCIE_CORE_LM_I_PF_2_VF_BAR_CONFIG_0_REG Register
31302928272625242322212019181716
VFBAR3CVFBAR3AVFBAR2CVFBAR2A
R/W-0hR/W-FhR/W-0hR/W-Fh
1514131211109876543210
VFBAR1CVFBAR1AVFBAR0CVFBAR0A
R/W-4hR/W-FhR/W-6hR/W-Fh
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3290 PCIE_CORE_LM_I_PF_2_VF_BAR_CONFIG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-29VFBAR3CR/W0hSpecifies the configuration of VF BAR3.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
28-24VFBAR3AR/WFhSpecifies the aperture of the VF BAR 3 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
23-21VFBAR2CR/W0hSpecifies the configuration of VF BAR2.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
20-16VFBAR2AR/WFhSpecifies the aperture of the
32-bit VF BAR 2 or 64bit VF BAR
2-3.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes
15-13VFBAR1CR/W4hSpecifies the configuration of VF BAR1.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8VFBAR1AR/WFhSpecifies the aperture of the VF BAR 1 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
7-5VFBAR0CR/W6hSpecifies the configuration of VF BAR0.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0VFBAR0AR/WFhSpecifies the aperture of the
32-bit VF BAR 0 or 64bit VF BAR
0-1.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes

3.5.4.82 PCIE_CORE_LM_I_PF_2_VF_BAR_CONFIG_1_REG Register (Offset = 00100294h) [reset = F0Fh]

PCIE_CORE_LM_I_PF_2_VF_BAR_CONFIG_1_REG is shown in Figure 12-1674 and described in Table 12-3292.

Return to the Summary Table.

This register specifies the configuration of the VF BARs associated with the Physical
Function.

Table 12-3291 PCIE_CORE_LM_I_PF_2_VF_BAR_CONFIG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0294h
Figure 12-1674 PCIE_CORE_LM_I_PF_2_VF_BAR_CONFIG_1_REG Register
31302928272625242322212019181716
R16
R-0h
1514131211109876543210
VFBAR5CVFBAR5AVFBAR4CVFBAR4A
R/W-0hR/W-FhR/W-0hR/W-Fh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3292 PCIE_CORE_LM_I_PF_2_VF_BAR_CONFIG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R16R0hReserved
15-13VFBAR5CR/W0hSpecifies the configuration of VF BAR5.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8VFBAR5AR/WFhSpecifies the aperture of the VF BAR 5 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
7-5VFBAR4CR/W0hSpecifies the configuration of VF BAR4.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0VFBAR4AR/WFhSpecifies the aperture of the
32-bit VF BAR 4 or 64bit VF BAR
4-5.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes

3.5.4.83 PCIE_CORE_LM_I_PF_3_VF_BAR_CONFIG_0_REG Register (Offset = 00100298h) [reset = 0F0F8FCFh]

PCIE_CORE_LM_I_PF_3_VF_BAR_CONFIG_0_REG is shown in Figure 12-1675 and described in Table 12-3294.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical Function 3

Table 12-3293 PCIE_CORE_LM_I_PF_3_VF_BAR_CONFIG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0298h
Figure 12-1675 PCIE_CORE_LM_I_PF_3_VF_BAR_CONFIG_0_REG Register
31302928272625242322212019181716
VFBAR3CVFBAR3AVFBAR2CVFBAR2A
R/W-0hR/W-FhR/W-0hR/W-Fh
1514131211109876543210
VFBAR1CVFBAR1AVFBAR0CVFBAR0A
R/W-4hR/W-FhR/W-6hR/W-Fh
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3294 PCIE_CORE_LM_I_PF_3_VF_BAR_CONFIG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-29VFBAR3CR/W0hSpecifies the configuration of VF BAR3.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
28-24VFBAR3AR/WFhSpecifies the aperture of the VF BAR 3 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
23-21VFBAR2CR/W0hSpecifies the configuration of VF BAR2.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
20-16VFBAR2AR/WFhSpecifies the aperture of the
32-bit VF BAR 2 or 64bit VF BAR
2-3.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes
15-13VFBAR1CR/W4hSpecifies the configuration of VF BAR1.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8VFBAR1AR/WFhSpecifies the aperture of the VF BAR 1 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
7-5VFBAR0CR/W6hSpecifies the configuration of VF BAR0.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0VFBAR0AR/WFhSpecifies the aperture of the
32-bit VF BAR 0 or 64bit VF BAR
0-1.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes

3.5.4.84 PCIE_CORE_LM_I_PF_3_VF_BAR_CONFIG_1_REG Register (Offset = 0010029Ch) [reset = F0Fh]

PCIE_CORE_LM_I_PF_3_VF_BAR_CONFIG_1_REG is shown in Figure 12-1676 and described in Table 12-3296.

Return to the Summary Table.

This register specifies the configuration of the VF BARs associated with the Physical
Function.

Table 12-3295 PCIE_CORE_LM_I_PF_3_VF_BAR_CONFIG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 029Ch
Figure 12-1676 PCIE_CORE_LM_I_PF_3_VF_BAR_CONFIG_1_REG Register
31302928272625242322212019181716
R16
R-0h
1514131211109876543210
VFBAR5CVFBAR5AVFBAR4CVFBAR4A
R/W-0hR/W-FhR/W-0hR/W-Fh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3296 PCIE_CORE_LM_I_PF_3_VF_BAR_CONFIG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R16R0hReserved
15-13VFBAR5CR/W0hSpecifies the configuration of VF BAR5.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8VFBAR5AR/WFhSpecifies the aperture of the VF BAR 5 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
7-5VFBAR4CR/W0hSpecifies the configuration of VF BAR4.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0VFBAR4AR/WFhSpecifies the aperture of the
32-bit VF BAR 4 or 64bit VF BAR
4-5.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes

3.5.4.85 PCIE_CORE_LM_I_PF_4_VF_BAR_CONFIG_0_REG Register (Offset = 001002A0h) [reset = 0F0F8FCFh]

PCIE_CORE_LM_I_PF_4_VF_BAR_CONFIG_0_REG is shown in Figure 12-1677 and described in Table 12-3298.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical Function 4

Table 12-3297 PCIE_CORE_LM_I_PF_4_VF_BAR_CONFIG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 02A0h
Figure 12-1677 PCIE_CORE_LM_I_PF_4_VF_BAR_CONFIG_0_REG Register
31302928272625242322212019181716
VFBAR3CVFBAR3AVFBAR2CVFBAR2A
R/W-0hR/W-FhR/W-0hR/W-Fh
1514131211109876543210
VFBAR1CVFBAR1AVFBAR0CVFBAR0A
R/W-4hR/W-FhR/W-6hR/W-Fh
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3298 PCIE_CORE_LM_I_PF_4_VF_BAR_CONFIG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-29VFBAR3CR/W0hSpecifies the configuration of VF BAR3.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
28-24VFBAR3AR/WFhSpecifies the aperture of the VF BAR 3 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
23-21VFBAR2CR/W0hSpecifies the configuration of VF BAR2.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
20-16VFBAR2AR/WFhSpecifies the aperture of the
32-bit VF BAR 2 or 64bit VF BAR
2-3.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes
15-13VFBAR1CR/W4hSpecifies the configuration of VF BAR1.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8VFBAR1AR/WFhSpecifies the aperture of the VF BAR 1 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
7-5VFBAR0CR/W6hSpecifies the configuration of VF BAR0.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0VFBAR0AR/WFhSpecifies the aperture of the
32-bit VF BAR 0 or 64bit VF BAR
0-1.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes

3.5.4.86 PCIE_CORE_LM_I_PF_4_VF_BAR_CONFIG_1_REG Register (Offset = 001002A4h) [reset = F0Fh]

PCIE_CORE_LM_I_PF_4_VF_BAR_CONFIG_1_REG is shown in Figure 12-1678 and described in Table 12-3300.

Return to the Summary Table.

This register specifies the configuration of the VF BARs associated with the Physical
Function.

Table 12-3299 PCIE_CORE_LM_I_PF_4_VF_BAR_CONFIG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 02A4h
Figure 12-1678 PCIE_CORE_LM_I_PF_4_VF_BAR_CONFIG_1_REG Register
31302928272625242322212019181716
R16
R-0h
1514131211109876543210
VFBAR5CVFBAR5AVFBAR4CVFBAR4A
R/W-0hR/W-FhR/W-0hR/W-Fh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3300 PCIE_CORE_LM_I_PF_4_VF_BAR_CONFIG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R16R0hReserved
15-13VFBAR5CR/W0hSpecifies the configuration of VF BAR5.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8VFBAR5AR/WFhSpecifies the aperture of the VF BAR 5 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
7-5VFBAR4CR/W0hSpecifies the configuration of VF BAR4.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0VFBAR4AR/WFhSpecifies the aperture of the
32-bit VF BAR 4 or 64bit VF BAR
4-5.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes

3.5.4.87 PCIE_CORE_LM_I_PF_5_VF_BAR_CONFIG_0_REG Register (Offset = 001002A8h) [reset = 0F0F8FCFh]

PCIE_CORE_LM_I_PF_5_VF_BAR_CONFIG_0_REG is shown in Figure 12-1679 and described in Table 12-3302.

Return to the Summary Table.

This register specifies the configuration of the BARs associated with the Physical Function 5

Table 12-3301 PCIE_CORE_LM_I_PF_5_VF_BAR_CONFIG_0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 02A8h
Figure 12-1679 PCIE_CORE_LM_I_PF_5_VF_BAR_CONFIG_0_REG Register
31302928272625242322212019181716
VFBAR3CVFBAR3AVFBAR2CVFBAR2A
R/W-0hR/W-FhR/W-0hR/W-Fh
1514131211109876543210
VFBAR1CVFBAR1AVFBAR0CVFBAR0A
R/W-4hR/W-FhR/W-6hR/W-Fh
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-3302 PCIE_CORE_LM_I_PF_5_VF_BAR_CONFIG_0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-29VFBAR3CR/W0hSpecifies the configuration of VF BAR3.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
28-24VFBAR3AR/WFhSpecifies the aperture of the VF BAR 3 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
23-21VFBAR2CR/W0hSpecifies the configuration of VF BAR2.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
20-16VFBAR2AR/WFhSpecifies the aperture of the
32-bit VF BAR 2 or 64bit VF BAR
2-3.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes
15-13VFBAR1CR/W4hSpecifies the configuration of VF BAR1.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8VFBAR1AR/WFhSpecifies the aperture of the VF BAR 1 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
7-5VFBAR0CR/W6hSpecifies the configuration of VF BAR0.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0VFBAR0AR/WFhSpecifies the aperture of the
32-bit VF BAR 0 or 64bit VF BAR
0-1.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes

3.5.4.88 PCIE_CORE_LM_I_PF_5_VF_BAR_CONFIG_1_REG Register (Offset = 001002ACh) [reset = F0Fh]

PCIE_CORE_LM_I_PF_5_VF_BAR_CONFIG_1_REG is shown in Figure 12-1680 and described in Table 12-3304.

Return to the Summary Table.

This register specifies the configuration of the VF BARs associated with the Physical
Function.

Table 12-3303 PCIE_CORE_LM_I_PF_5_VF_BAR_CONFIG_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 02ACh
Figure 12-1680 PCIE_CORE_LM_I_PF_5_VF_BAR_CONFIG_1_REG Register
31302928272625242322212019181716
R16
R-0h
1514131211109876543210
VFBAR5CVFBAR5AVFBAR4CVFBAR4A
R/W-0hR/W-FhR/W-0hR/W-Fh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3304 PCIE_CORE_LM_I_PF_5_VF_BAR_CONFIG_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R16R0hReserved
15-13VFBAR5CR/W0hSpecifies the configuration of VF BAR5.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
12-8VFBAR5AR/WFhSpecifies the aperture of the VF BAR 5 when it is configured as a
32-bit BAR.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes
7-5VFBAR4CR/W0hSpecifies the configuration of VF BAR4.
The various encodings are:

000: Disabled

001-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
4-0VFBAR4AR/WFhSpecifies the aperture of the
32-bit VF BAR 4 or 64bit VF BAR
4-5.

The encodings are:
00000 = 128 Bytes,
0001 = 256 Bytes,
0010 = 512 Bytes,
0011 = 1
Kbytes,
00100 = 2 Kbytes,
00101 = 4 Kbytes,
00110 = 8 Kbytes,
00111 = 16 Kbytes,
01000 = 32
Kbytes,
01001 = 64 Kbytes,
01010 = 128 Kbytes,
01011 = 256 Kbytes,
01100 = 512 Kbytes,
01101 =
1 Mbyte,
01110 = 2 Mbytes,
01111 = 4 Mbytes,
10000 = 8 Mbytes,
10001 = 16 Mbytes,
10010 = 32
Mbytes,
10011 = 64 Mbytes,
10100 = 128 Mbytes,
10101 = 256 Mbytes,
10110 = 512 Mbytes,
10111 =
1 Gbyte,
11000 = 2 Gbytes,

11001 = 4 Gbytes,
11010 = 8 Gbytes,
11011 = 16 Gbytes,
11100 = 32
Gbytes,
11101 = 64 Gbytes,
11110 = 128 Gbytes,
11111 = 256 Gbytes

3.5.4.89 PCIE_CORE_LM_I_PF_CONFIG_REG Register (Offset = 001002C0h) [reset = 3Fh]

PCIE_CORE_LM_I_PF_CONFIG_REG is shown in Figure 12-1681 and described in Table 12-3306.

Return to the Summary Table.

This register contains the enable bits for all the Functions implemented by the Controller.
Resetting the enable bit of a Function disables the Function from responding to configuration
requests.

Table 12-3305 PCIE_CORE_LM_I_PF_CONFIG_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 02C0h
Figure 12-1681 PCIE_CORE_LM_I_PF_CONFIG_REG Register
31302928272625242322212019181716
R
R-0h
1514131211109876543210
RF5EF4EF3EF2EF1EF0E
R-0hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3306 PCIE_CORE_LM_I_PF_CONFIG_REG Register Field Descriptions
BitFieldTypeResetDescription
31-6RR0hReserved
5F5ER/W1hEnable for Function 5.
This bit can be modified from the local management bus.
4F4ER/W1hEnable for Function 4.
This bit can be modified from the local management bus.
3F3ER/W1hEnable for Function 3.
This bit can be modified from the local management bus.
2F2ER/W1hEnable for Function 2.
This bit can be modified from the local management bus.
1F1ER/W1hEnable for Function 1.
This bit can be modified from the local management bus.
0F0ER1hEnable for Function 0.
This bit is hardwired to 1.

3.5.4.90 PCIE_CORE_LM_I_RC_BAR_CONFIG_REG Register (Offset = 00100300h) [reset = 2914h]

PCIE_CORE_LM_I_RC_BAR_CONFIG_REG is shown in Figure 12-1682 and described in Table 12-3308.

Return to the Summary Table.

The root complex side of the Controller contains two memory BARs that can be used for
address-range checking of incoming requests from devices connected to it. The fields in this
register determine the configuration of these BARs.

Table 12-3307 PCIE_CORE_LM_I_RC_BAR_CONFIG_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0300h
Figure 12-1682 PCIE_CORE_LM_I_RC_BAR_CONFIG_REG Register
3130292827262524
RCBCER10
R/W-0hR-0h
2322212019181716
R10RCBARPISRCBARPIERCBARPMSRCBARPMERCBAR1C
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RCBAR1CRCBAR1ARCBAR0C
R/W-0hR/W-14hR/W-4h
76543210
RCBAR0CRCBAR0A
R/W-4hR/W-14h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3308 PCIE_CORE_LM_I_RC_BAR_CONFIG_REG Register Field Descriptions
BitFieldTypeResetDescription
31RCBCER/W0hThis bit must be set to 1 to enable BAR checking in the RC mode.
When this bit is set
to 0, the Controller will forward all incoming memory requests to the client logic without checking
their address ranges.
30-21R10R0hReserved
20RCBARPISR/W0hWidth of IO Base and Limit registers in type1 config space.
0=32 bits,
1=64bits
19RCBARPIER/W0hEnable for IO Base and Limit registers in type1 config space
18RCBARPMSR/W0hWidth of Prefetchable Memory Base and Limit registers in type1 config space.
0=32 bits,
1=64bits
17RCBARPMER/W0hEnable for Prefetchable memory base and limit registers in type1 config space
16-14RCBAR1CR/W0hSpecifies the configuration of RC BAR1.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110-
111: Reserved
13-9RCBAR1AR/W14hThis field specifies the aperture of the RC BAR 1.
The encodings are:
0000 = 4,
00001 =8B,.....
1_
1101 = 2G
8-6RCBAR0CR/W4hSpecifies the configuration of RC BAR0.
The various encodings are:

000: Disabled

001: 32bit IO BAR

010-
011: Reserved

100: 32bit memory BAR, non prefetchable

101: 32bit memory BAR, prefetchable

110: 64bit memory BAR, non prefetchable

111: 64bit memory BAR, prefetchable
5-0RCBAR0AR/W14hThis field specifies the aperture of the RC BAR 0.
The encodings are:
0000 = 4,
00001 =8B,.....
01_
1111 = 8G, ....10_
0100 = 256G.

3.5.4.91 PCIE_CORE_LM_I_GEN3_DEFAULT_PRESET_REG Register (Offset = 00100360h) [reset = 0007FF00h]

PCIE_CORE_LM_I_GEN3_DEFAULT_PRESET_REG is shown in Figure 12-1683 and described in Table 12-3310.

Return to the Summary Table.

This is register specifies the default transmitter preset and
default receiver preset hint used by Controller for lanes that have not
received EQ TS2s during Recovery.RcvrConfig LTSSM state

Table 12-3309 PCIE_CORE_LM_I_GEN3_DEFAULT_PRESET_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0360h
Figure 12-1683 PCIE_CORE_LM_I_GEN3_DEFAULT_PRESET_REG Register
31302928272625242322212019181716
R31S8GPR
R-0hR/W-7FFh
1514131211109876543210
S8GPRR7GDRXPHGDTXP
R/W-7FFhR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3310 PCIE_CORE_LM_I_GEN3_DEFAULT_PRESET_REG Register Field Descriptions
BitFieldTypeResetDescription
31-19R31R0hReserved
18-8S8GPRR/W7FFhThis register can be used to program the Presets that are supported by local
Transmitter at 8Gbps.
Default value of this register is determined by the
SUPPORTED_PRESET strap input.
Note: At 8.0 GT/s and 16.0 GT/s all preset values must be supported for Full swing signaling.
Reduced swing signaling must implement presets #4, #1, #9, #5, #6, and #3.
7R7R0hReserved
6-4GDRXPHR/W0hDefault receiver preset hint value used for a lane that did not
receive EQ TS2 in Recovery.RcvrCfg LTSSM state
3-0GDTXPR/W0hDefault transmitter preset value used for a lane that did not
receive EQ TS2 in Recovery.RcvrCfg LTSSM state

3.5.4.92 PCIE_CORE_LM_I_GEN3_GEN4_LINK_EQ_TIMEOUT_2MS_REG Register (Offset = 00100364h) [reset = C001E848h]

PCIE_CORE_LM_I_GEN3_GEN4_LINK_EQ_TIMEOUT_2MS_REG is shown in Figure 12-1684 and described in Table 12-3312.

Return to the Summary Table.

This register is used to tune the time spent for evaluation per TX Setting in Endpoint Phase 2 (RC Mode Phase 3) of GEN3, GEN4 Link Equalization.
The PCIe Spec defines a timeout of 2ms per TX setting and hence the default value for this register is set to 2ms.
This can be tweaked based on the total number of iterations done and the time required for the PHY to respond with feedback for RXEQEVAL request.
The total time taken in Endpoint Phase 2 (RC Mode Phase 3) must be less than 24 ms as defined by spec.
Guideline: (Total Number of iterations)*(link_eq_timeout_2ms_reg + max time required for PHY to respond to RXEQEVAL) less than 24ms

Table 12-3311 PCIE_CORE_LM_I_GEN3_GEN4_LINK_EQ_TIMEOUT_2MS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0364h
Figure 12-1684 PCIE_CORE_LM_I_GEN3_GEN4_LINK_EQ_TIMEOUT_2MS_REG Register
3130292827262524
RXEQABMRXEQABDR28LEQT2MS
R/W-3hR/W-0hR-0hR/W-0001E848h
2322212019181716
LEQT2MS
R/W-0001E848h
15141312111098
LEQT2MS
R/W-0001E848h
76543210
LEQT2MS
R/W-0001E848h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3312 PCIE_CORE_LM_I_GEN3_GEN4_LINK_EQ_TIMEOUT_2MS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-30RXEQABMR/W3hWhen a 24ms timeout occurs in the LTSSM Equalization Phase 2, the Controller aborts
Equalization Phase 2 and transitions to Recovery.Rcvr.Lock.

In this case, the RxEqEval output on the PIPE Interface will be de-asserted immediately [if it was asserted].

The RxEqInProgress output will stay high and waits for PhyStatus pulse.

Controller implements a timer to select an upper limit to wait for this PhyStatus pulse during an abort to de-assert RxEqInProgress.


00: Wait for a maximum of 4 PIPE_PCLK period.


01: Wait for a maximum of 8 PIPE_PCLK period.


10: Wait for a maximum of 16 PIPE_PCLK period.


11: Disabled.
Wait till PhyStatus Pulse is received.

Note: This register is used only if RxEqEval was asserted when LTSSM 24ms timeout occured in Equalization.
29RXEQABDR/W0hIn an unexpected case where the PIPE_PCLK stops due to error in equalization, this bit
can be set to de-couple RxEqInProgress from the rest of the equalization state machine.
This bit should not be set for normal usage.
28R28R0hReserved
27-0LEQT2MSR/W0001E848hTime spent for evaluation per TX Setting in Endpoint Phase 2 [RC Mode Phase 3] of Link Equalization
specified in multiples of 16ns.
eg.
the value 125000 will result in 125000*16ns = 2ms.

Simulation with reduced time mode[PCIE_SIM define] will give a samller value of 300 as power on reset value.

3.5.4.93 PCIE_CORE_LM_I_PIPE_FIFO_LATENCY_CTRL_REG Register (Offset = 00100368h) [reset = 0h]

PCIE_CORE_LM_I_PIPE_FIFO_LATENCY_CTRL_REG is shown in Figure 12-1685 and described in Table 12-3314.

Return to the Summary Table.

This is register includes bits to control pipe fifo latency

Table 12-3313 PCIE_CORE_LM_I_PIPE_FIFO_LATENCY_CTRL_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0368h
Figure 12-1685 PCIE_CORE_LM_I_PIPE_FIFO_LATENCY_CTRL_REG Register
3130292827262524
R31
R-0h
2322212019181716
R31
R-0h
15141312111098
R31
R-0h
76543210
R31DPRFLRDPTFCE
R-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3314 PCIE_CORE_LM_I_PIPE_FIFO_LATENCY_CTRL_REG Register Field Descriptions
BitFieldTypeResetDescription
31-2R31R0hReserved
1DPRFLRR/W0h
0: If FIFO empty is reached, the PIPE RX FIFO accumulates 2 entries before reading the FIFO again.

1: If FIFO empty is reached, the PIPE RX FIFO accumulates 6 entries before reading the FIFO again.
This is to prevent FIFO from reaching empty again.
Default value of this bit is 0, in order to reduce the latency through the PIPE RX FIFO.
0DPTFCER/W0hBy default, if FIFO empty is reached, the PIPE TX FIFO accumulates 2 entries before reading the FIFO again.
This is to prevent FIFO from reaching empty again.

This bit must remain at 0 to allow the PIPE TX FIFO to recover effectively from a Empty condition.

3.5.4.94 PCIE_CORE_LM_I_GEN4_DEFAULT_PRESET_REG Register (Offset = 00100374h) [reset = 0007FF00h]

PCIE_CORE_LM_I_GEN4_DEFAULT_PRESET_REG is shown in Figure 12-1686 and described in Table 12-3316.

Return to the Summary Table.

This is register specifies the default transmitter preset and
default receiver preset hint used by Controller for lanes that have not
received 16G EQ TS2s during Recovery.RcvrConfig LTSSM state

Table 12-3315 PCIE_CORE_LM_I_GEN4_DEFAULT_PRESET_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0374h
Figure 12-1686 PCIE_CORE_LM_I_GEN4_DEFAULT_PRESET_REG Register
31302928272625242322212019181716
R31S16GPR
R-0hR/W-7FFh
1514131211109876543210
S16GPRR7GDRXPHGDTXP
R/W-7FFhR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3316 PCIE_CORE_LM_I_GEN4_DEFAULT_PRESET_REG Register Field Descriptions
BitFieldTypeResetDescription
31-19R31R0hReserved
18-8S16GPRR/W7FFhThis register can be used to program the Presets that are supported by local
Transmitter at 16Gbps.
Default value of this register is determined by the
SUPPORTED_PRESET strap input.

Note: At 8.0 GT/s and 16.0 GT/s all preset values must be supported for Full swing signaling.
Reduced swing signaling must implement presets #4, #1, #9, #5, #6, and #3.
7R7R0hReserved
6-4GDRXPHR/W0hDefault Gen4 receiver preset hint value used for a lane that did not
receive 16G EQ TS2 in Recovery.RcvrCfg LTSSM state
3-0GDTXPR/W0hDefault Gen4 transmitter preset value used for a lane that did not
receive 16G EQ TS2 in Recovery.RcvrCfg LTSSM state

3.5.4.95 PCIE_CORE_LM_I_PHY_CONFIG_REG3 Register (Offset = 00100378h) [reset = 80h]

PCIE_CORE_LM_I_PHY_CONFIG_REG3 is shown in Figure 12-1687 and described in Table 12-3318.

Return to the Summary Table.

This is register specifies the PHY Specific registers for used in Gen4

Table 12-3317 PCIE_CORE_LM_I_PHY_CONFIG_REG3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0378h
Figure 12-1687 PCIE_CORE_LM_I_PHY_CONFIG_REG3 Register
313029282726252423222120191817161514131211109876543210
R24TFC4
R-0hR/W-40h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3318 PCIE_CORE_LM_I_PHY_CONFIG_REG3 Register Field Descriptions
BitFieldTypeResetDescription
31-8R24R0hReserved
7-0TFC4R/W80hFTS count transmitted by the Controller in TS1/TS2 sequences during link training.
This
value must be set based on the time needed by the receiver to acquire sync while exiting from L0S state at 16 GT/s speed.

3.5.4.96 PCIE_CORE_LM_I_GEN3_GEN4_LINK_EQ_CTRL_REG Register (Offset = 0010037Ch) [reset = 0h]

PCIE_CORE_LM_I_GEN3_GEN4_LINK_EQ_CTRL_REG is shown in Figure 12-1688 and described in Table 12-3320.

Return to the Summary Table.

This register is used to Control GEN3, GEN4 Link Equalization Procedure.

Table 12-3319 PCIE_CORE_LM_I_GEN3_GEN4_LINK_EQ_CTRL_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 037Ch
Figure 12-1688 PCIE_CORE_LM_I_GEN3_GEN4_LINK_EQ_CTRL_REG Register
3130292827262524
RES20
R-0h
2322212019181716
RES20MX16GERL
R-0hR/W-0h
15141312111098
MX8GERLRES10QG16GTQG8GT
R/W-0hR-0hR/W-0hR/W-0h
76543210
RES6EP16GREEP8GRERES3MXECC
R-0hR/W-0hR/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3320 PCIE_CORE_LM_I_GEN3_GEN4_LINK_EQ_CTRL_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20RES20R0hReserved
19-16MX16GERLR/W0hThe number of 16GT/s Equalization Requests must be finite as per PCIe specification.
This register can be used to program the maximum number of 16GT/s equalization requests automatically initiated by the Endpoint.

0000: Automatic 16GT/s Equalization Request Disabled.


0001: Automatic 16GT/s Equalization request limit is 1.

0010: Automatic 16GT/s Equalization request limit is 2.
....

1111: Automatic 16GT/s Equalization request limit is 15,
15-12MX8GERLR/W0hThe number of 8GT/s Equalization Requests must be finite as per PCIe specification.
This register can be used to program the maximum number of 8GT/s equalization requests automatically initiated by the Endpoint.

0000: Automatic 8GT/s Equalization Request Disabled.


0001: Automatic 8GT/s Equalization request limit is 1.

0010: Automatic 8GT/s Equalization request limit is 2.
....

1111: Automatic 8GT/s Equalization request limit is 15,
11-10RES10R0hReserved
9QG16GTR/W0hThis bit can be used to program the Quiesce Guarantee bit of the TS2 in
Recovery.Rcvr.Cfg state during 16GT/s Request Equalization.
8QG8GTR/W0hThis bit can be used to program the Quiesce Guarantee bit of the TS2 in
Recovery.Rcvr.Cfg state during 8GT/s Request Equalization.
7-6RES6R0hReserved
5EP16GRER/W0hWriting a 1 into this field results in the Controller to transition to Recovery.
The Request Equalization bit and Equalization Request Data Rate bit in TS2 Ordered Sets will be set to 1 in Recovery.Rcvr.Cfg to
request equalization at 16GTs.
This bit is auto-cleared by the internal logic of the Controller after the
re-training has been completed and link has reached the L0 state.

This bit is also auto-cleared when not in Gen3 or Gen4.
Device Firmware must wait for the bit to be clear before any subsequent requests.
4EP8GRER/W0hThis bit can be used by Endpoint Device FW to request for 8GT/s Equalization redo.
This bit can be set at any time after the Link is Up.
Writing a 1 into this field results in the Controller to transition to Recovery.
The Request Equalization bit in TS2 Ordered Sets will be set to 1 in Recovery.Rcvr.Cfg to
request equalization at 8GTs.
This bit is auto-cleared by the internal logic of the Controller after the
re-training has been completed and link has reached the L0 state.

This bit is also auto-cleared when not in Gen3 or Gen4.
Device Firmware must wait for the bit to be clear before any subsequent retrain requests.
3RES3R0hReserved
2-0MXECCR/W0hControls the number of consecutive RxEqEval iterations with direction change feedback of 00s before Equalization Convergence is inferred.

0 : Infer Convergence after 1 feedback of 000000

1 : Infer Convergence after 2 feedback of 000000

2 : Infer Convergence after 3 consecutive feedback of 000000
..

7 : Infer Convergence after 8 consecutive feedback of 000000.
Note: Each lane independently counts consecutive feedback of 000000.

Note: Count is reset after a non-000000 feedback on each lane.

3.5.4.97 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE0 Register (Offset = 00100380h) [reset = 000B4004h]

PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE0 is shown in Figure 12-1689 and described in Table 12-3322.

Return to the Summary Table.

This register is used to reflect the negotiated TX Preset, Coefficients at the end of GEN3 Link Equalization.

When the Controller is an Endpoint, this register reflects the Preset/Coefficients applied to the Endpoint Transmitter at the end of Gen3 Equalization Phase 3.


When the Controller is an RC, this register reflects the Preset/Coefficients applied to the RC Transmitter at the end of Gen3 Equalization Phase 2.

Table 12-3321 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0380h
Figure 12-1689 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE0 Register
3130292827262524
RES3126LEQTXCO
R-0hR-B40h
2322212019181716
LEQTXCO
R-B40h
15141312111098
LEQTXCO
R-B40h
76543210
RES75LEQTXPRVLEQTXPR
R-0hR-0hR-4h
LEGEND: R = Read Only; -n = value after reset
Table 12-3322 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RES3126R0hReserved
25-8LEQTXCORB40hTX Coefficients agreed upon for this lane.

[25:20] : Post Cursor Coefficient

[19:14] : Cursor Coefficient

[13:8] : Pre-Cusror Coefficient
7-5RES75R0hReserved
4LEQTXPRVR0hTX Preset Valid Indicator.
This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2.
3-0LEQTXPRR4hTX Preset agreed upon for this lane

3.5.4.98 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE1 Register (Offset = 00100384h) [reset = 000B4004h]

PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE1 is shown in Figure 12-1690 and described in Table 12-3324.

Return to the Summary Table.

This register is used to reflect the negotiated TX Preset, Coefficients at the end of GEN3 Link Equalization.

When the Controller is an Endpoint, this register reflects the Preset/Coefficients applied to the Endpoint Transmitter at the end of Gen3 Equalization Phase 3.


When the Controller is an RC, this register reflects the Preset/Coefficients applied to the RC Transmitter at the end of Gen3 Equalization Phase 2.

Table 12-3323 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0384h
Figure 12-1690 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE1 Register
3130292827262524
RES3126LEQTXCO
R-0hR-B40h
2322212019181716
LEQTXCO
R-B40h
15141312111098
LEQTXCO
R-B40h
76543210
RES75LEQTXPRVLEQTXPR
R-0hR-0hR-4h
LEGEND: R = Read Only; -n = value after reset
Table 12-3324 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE1 Register Field Descriptions
BitFieldTypeResetDescription
31-26RES3126R0hReserved
25-8LEQTXCORB40hTX Coefficients agreed upon for this lane.

[25:20] : Post Cursor Coefficient

[19:14] : Cursor Coefficient

[13:8] : Pre-Cusror Coefficient
7-5RES75R0hReserved
4LEQTXPRVR0hTX Preset Valid Indicator.
This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2.
3-0LEQTXPRR4hTX Preset agreed upon for this lane

3.5.4.99 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE2 Register (Offset = 00100388h) [reset = 000B4004h]

PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE2 is shown in Figure 12-1691 and described in Table 12-3326.

Return to the Summary Table.

This register is used to reflect the negotiated TX Preset, Coefficients at the end of GEN3 Link Equalization.
When the Controller is an Endpoint, this register reflects the Preset/Coefficients applied to the Endpoint Transmitter at the end of Gen3 Equalization Phase 3.
When the Controller is an RC, this register reflects the Preset/Coefficients applied to the RC Transmitter at the end of Gen3 Equalization Phase 2.

Table 12-3325 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0388h
Figure 12-1691 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE2 Register
3130292827262524
RES3126LEQTXCO
R-0hR-B40h
2322212019181716
LEQTXCO
R-B40h
15141312111098
LEQTXCO
R-B40h
76543210
RES75LEQTXPRVLEQTXPR
R-0hR-0hR-4h
Table 12-3326 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE2 Register Field Descriptions
BitFieldTypeResetDescription
31-26RES3126R0hReserved
25-8LEQTXCORB40hTX Coefficients agreed upon for this lane.

[25:20] : Post Cursor Coefficient

[19:14] : Cursor Coefficient

[13:8] : Pre-Cusror Coefficient
7-5RES75R0hReserved
4LEQTXPRVR0hTX Preset Valid Indicator.
This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2.
3-0LEQTXPRR4hTX Preset agreed upon for this lane

3.5.4.100 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE3 Register (Offset = 0010038Ch) [reset = 000B4004h]

PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE3 is shown in Figure 12-1692 and described in Table 12-3328.

Return to the Summary Table.

This register is used to reflect the negotiated TX Preset, Coefficients at the end of GEN3 Link Equalization.
When the Controller is an Endpoint, this register reflects the Preset/Coefficients applied to the Endpoint Transmitter at the end of Gen3 Equalization Phase 3.
When the Controller is an RC, this register reflects the Preset/Coefficients applied to the RC Transmitter at the end of Gen3 Equalization Phase 2.

Table 12-3327 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 038Ch
Figure 12-1692 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE3 Register
3130292827262524
RES3126LEQTXCO
R-0hR-B40h
2322212019181716
LEQTXCO
R-B40h
15141312111098
LEQTXCO
R-B40h
76543210
RES75LEQTXPRVLEQTXPR
R-0hR-0hR-4h
Table 12-3328 PCIE_CORE_LM_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE3 Register Field Descriptions
BitFieldTypeResetDescription
31-26RES3126R0hReserved
25-8LEQTXCORB40hTX Coefficients agreed upon for this lane.

[25:20] : Post Cursor Coefficient

[19:14] : Cursor Coefficient

[13:8] : Pre-Cusror Coefficient
7-5RES75R0hReserved
4LEQTXPRVR0hTX Preset Valid Indicator.
This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2.
3-0LEQTXPRR4hTX Preset agreed upon for this lane

3.5.4.101 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE0 Register (Offset = 001003C0h) [reset = 00684608h]

PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE0 is shown in Figure 12-1693 and described in Table 12-3330.

Return to the Summary Table.

This register is used to reflect the negotiated TX Preset, Coefficients at the end of GEN4 Link Equalization.

When the Controller is an Endpoint, this register reflects the Preset/Coefficients applied to the Endpoint Transmitter at the end of Gen4 Equalization Phase 3.


When the Controller is an RC, this register reflects the Preset/Coefficients applied to the RC Transmitter at the end of Gen4 Equalization Phase 2.

Table 12-3329 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 03C0h
Figure 12-1693 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE0 Register
3130292827262524
RES3126LEQTXCO
R-0hR-6846h
2322212019181716
LEQTXCO
R-6846h
15141312111098
LEQTXCO
R-6846h
76543210
RES75LEQTXPRVLEQTXPR
R-0hR-0hR-8h
LEGEND: R = Read Only; -n = value after reset
Table 12-3330 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RES3126R0hReserved
25-8LEQTXCOR6846hTX Coefficients agreed upon for this lane.

[25:20] : Post Cursor Coefficient

[19:14] : Cursor Coefficient

[13:8] : Pre-Cusror Coefficient
7-5RES75R0hReserved
4LEQTXPRVR0hTX Preset Valid Indicator.

This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2.
3-0LEQTXPRR8hTX Preset agreed upon for this lane

3.5.4.102 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE1 Register (Offset = 001003C4h) [reset = 00684608h]

PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE1 is shown in Figure 12-1694 and described in Table 12-3332.

Return to the Summary Table.

This register is used to reflect the negotiated TX Preset, Coefficients at the end of GEN4 Link Equalization.

When the Controller is an Endpoint, this register reflects the Preset/Coefficients applied to the Endpoint Transmitter at the end of Gen4 Equalization Phase 3.


When the Controller is an RC, this register reflects the Preset/Coefficients applied to the RC Transmitter at the end of Gen4 Equalization Phase 2.

Table 12-3331 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 03C4h
Figure 12-1694 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE1 Register
3130292827262524
RES3126LEQTXCO
R-0hR-6846h
2322212019181716
LEQTXCO
R-6846h
15141312111098
LEQTXCO
R-6846h
76543210
RES75LEQTXPRVLEQTXPR
R-0hR-0hR-8h
LEGEND: R = Read Only; -n = value after reset
Table 12-3332 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE1 Register Field Descriptions
BitFieldTypeResetDescription
31-26RES3126R0hReserved
25-8LEQTXCOR6846hTX Coefficients agreed upon for this lane.

[25:20] : Post Cursor Coefficient

[19:14] : Cursor Coefficient

[13:8] : Pre-Cusror Coefficient
7-5RES75R0hReserved
4LEQTXPRVR0hTX Preset Valid Indicator.

This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2.
3-0LEQTXPRR8hTX Preset agreed upon for this lane

3.5.4.103 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE2 Register (Offset = 001003C8h) [reset = 00684608h]

PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE2 is shown in Figure 12-1695 and described in Table 12-3334.

Return to the Summary Table.

This register is used to reflect the negotiated TX Preset, Coefficients at the end of GEN4 Link Equalization.
When the Controller is an Endpoint, this register reflects the Preset/Coefficients applied to the Endpoint Transmitter at the end of Gen4 Equalization Phase 3.
When the Controller is an RC, this register reflects the Preset/Coefficients applied to the RC Transmitter at the end of Gen4 Equalization Phase 2.

Table 12-3333 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 03C8h
Figure 12-1695 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE2 Register
3130292827262524
RES3126LEQTXCO
R-0hR-6846h
2322212019181716
LEQTXCO
R-6846h
15141312111098
LEQTXCO
R-6846h
76543210
RES75LEQTXPRVLEQTXPR
R-0hR-0hR-8h
Table 12-3334 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE2 Register Field Descriptions
BitFieldTypeResetDescription
31-26RES3126R0hReserved
25-8LEQTXCOR6846hTX Coefficients agreed upon for this lane.

[25:20] : Post Cursor Coefficient

[19:14] : Cursor Coefficient

[13:8] : Pre-Cusror Coefficient
7-5RES75R0hReserved
4LEQTXPRVR0hTX Preset Valid Indicator.

This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2.
3-0LEQTXPRR8hTX Preset agreed upon for this lane

3.5.4.104 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE3 Register (Offset = 001003CCh) [reset = 00684608h]

PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE3 is shown in Figure 12-1696 and described in Table 12-3336.

Return to the Summary Table.

This register is used to reflect the negotiated TX Preset, Coefficients at the end of GEN4 Link Equalization.
When the Controller is an Endpoint, this register reflects the Preset/Coefficients applied to the Endpoint Transmitter at the end of Gen4 Equalization Phase 3.
When the Controller is an RC, this register reflects the Preset/Coefficients applied to the RC Transmitter at the end of Gen4 Equalization Phase 2.

Table 12-3335 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE3 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 03CCh
Figure 12-1696 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE3 Register
3130292827262524
RES3126LEQTXCO
R-0hR-6846h
2322212019181716
LEQTXCO
R-6846h
15141312111098
LEQTXCO
R-6846h
76543210
RES75LEQTXPRVLEQTXPR
R-0hR-0hR-8h
Table 12-3336 PCIE_CORE_LM_I_GEN4_LINK_EQ_DEBUG_STATUS_REG_LANE3 Register Field Descriptions
BitFieldTypeResetDescription
31-26RES3126R0hReserved
25-8LEQTXCOR6846hTX Coefficients agreed upon for this lane.

[25:20] : Post Cursor Coefficient

[19:14] : Cursor Coefficient

[13:8] : Pre-Cusror Coefficient
7-5RES75R0hReserved
4LEQTXPRVR0hTX Preset Valid Indicator.

This bit is set when a TX Preset is received in TS1s with the use_preset bit set in Endpoint Mode Phase 3 or RC Mode Phase 2.
3-0LEQTXPRR8hTX Preset agreed upon for this lane

3.5.4.105 PCIE_CORE_LM_I_ECC_CORR_ERR_COUNT_REG_AXI Register (Offset = 00100C80h) [reset = 0h]

PCIE_CORE_LM_I_ECC_CORR_ERR_COUNT_REG_AXI is shown in Figure 12-1697 and described in Table 12-3338.

Return to the Summary Table.

This register contains the count of the number of ECC errors detected and corrected
during reads from PCIe core AXI external RAMs.

Table 12-3337 PCIE_CORE_LM_I_ECC_CORR_ERR_COUNT_REG_AXI Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0C80h
Figure 12-1697 PCIE_CORE_LM_I_ECC_CORR_ERR_COUNT_REG_AXI Register
31302928272625242322212019181716
AXI_MASTER_DIB_CERAXI_MASTER_RFIFO_CER
R/W1C-0hR/W1C-0h
1514131211109876543210
AXI_SLAVE_WFIFO_CERREORDER_CER
R/W1C-0hR/W1C-0h
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3338 PCIE_CORE_LM_I_ECC_CORR_ERR_COUNT_REG_AXI Register Field Descriptions
BitFieldTypeResetDescription
31-24AXI_MASTER_DIB_CERR/W1C0hNumber of correctable errors detected while reading from the AXI Master Read Data interleave RAM.
This is an
8-bit saturating counter that can be cleared by writing all 1s into it.
23-16AXI_MASTER_RFIFO_CERR/W1C0hNumber of correctable errors detected while reading from the AXI master read fifo RAM.
This
is an
8-bit saturating counter that can be cleared by writing all 1's into it.
15-8AXI_SLAVE_WFIFO_CERR/W1C0hNumber of correctable errors detected while reading from the AXI slave write fifo RAM.
This is an

8-bit saturating counter that can be cleared by writing all 1's into it.
7-0REORDER_CERR/W1C0hNumber of correctable errors detected while reading from the AXI slave reorder RAM.
This is an

8-bit saturating counter that can be cleared by writing all 1's into it.

3.5.4.106 PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL0 Register (Offset = 00100C88h) [reset = X]

PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL0 is shown in Figure 12-1698 and described in Table 12-3340.

Return to the Summary Table.

This register controls internal behavior of controller for low power operations.
Adjustment of this register is not required for normal operations.

Table 12-3339 PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL0 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0C88h
Figure 12-1698 PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL0 Register
3130292827262524
RESERVEDL1DLEUPL1EML1DBRI
R/W-XR/W-0hR-0hR/W-0h
2322212019181716
L1XDELAY
R/W-0h
15141312111098
L1XDELAY
R/W-0h
76543210
L1XDELAY
R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3340 PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL0 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27L1DLEUPR/W0hPending Tlps trigger a L1 exit by default.
This includes internaly generated messages and internaly blocked TLPs.
Setting this bit changes the default behavior.
This is required only for debug purpose.
26-25L1EMR0hThis field shows the last entered L1 mode.
This is useful for debug.
bit
0 - Entry mode was ASPM.
Bit
1 - Entry mode was PM.
This is reset before any new L1 entry.
24L1DBRIR/W0hBefore entering L1, controller internally blocks all TLP and Register Request interface entering
controller.
interfaces are internally unblocked while exiting L1.

This field control this behavior.
'1' in this field makes the controler to do not perform any
blocking to interfaces.
'0' makes the controller behaves normaly.
This is required only
for debug purpose.
Power shutoff feature has to be disabled while using this field.
23-0L1XDELAYR/W0hNormaly L1 substate entry process is initiated immedaitely after LTSSM enters L1.

A delay in micro-seconds can be given in this field to delay L1 substate entry process.
This timeout has
0-1us margin of error.
Power on reset value of this register can be adjusted by modifying the define
den_db_LP_DBG_CTRL_L1_SUBSTATE_ENTRY_DELAY

3.5.4.107 PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL1 Register (Offset = 00100C8Ch) [reset = X]

PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL1 is shown in Figure 12-1699 and described in Table 12-3342.

Return to the Summary Table.

This register controls internal behavior of controller for low power operations.
Adjustment of this register is not required for normal operations.

Table 12-3341 PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0C8Ch
Figure 12-1699 PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDL1ER
R-XR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3342 PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDRX
7-0L1ERR0hThis field shows the values of possible L1 or L
1-substate exit triggers.
This is useful for debug.
this is captured during L1 or L
1-substate exit process.
this field is reset during L1 entry.

0 : CLIENT_REQ_EXIT_L1 asserted


1 : Electrical Idle exit detected at link


2 : New TLP request detected


3 : Internal request to send TLP.
This includes CFG completions.
internal messages.
INTx messages


4 : Pending TX traffic available.
This could be traffic from DMA and blocked traffic due to credits at AXI.



5 : #CLKREQ assert detected


6 : CLIENT_REQ_EXIT_L1_SUBSTATE asserted

7 : Reg Access request detected

Triggers #5,6,7 are valid only with L
1-substate supported configs.

3.5.4.108 PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL2 Register (Offset = 00100C90h) [reset = X]

PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL2 is shown in Figure 12-1700 and described in Table 12-3344.

Return to the Summary Table.

This register controls internal behavior of controller for low power operations.
Adjustment of this register is not required for normal operations.

Table 12-3343 PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0C90h
Figure 12-1700 PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL2 Register
3130292827262524
L1UPACRL1CSCL1DAETL1TROWL1PSL1ERCL1EOCRESERVED
R/W-1hR/W-0hR/W-0hR-0hR/W-1hR/W-0hR/W-0hR/W-X
2322212019181716
L1TWROI
R/W-0h
15141312111098
L1TWROI
R/W-0h
76543210
L1TWROI
R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3344 PCIE_CORE_LM_LOW_POWER_DEBUG_AND_CONTROL2 Register Field Descriptions
BitFieldTypeResetDescription
31L1UPACRR/W1hSetting this field make the state machine to consider LP_CTRL_POWER_RECOVER_ACK as Client system recovery Complete ACK instead of the Controller power stable ACK.
This field is ignored if LP_CTRL_BYPASS_ENABLE unset.
If this field is set, L
1-substate machines expect that the client system finishes power up of the controller within power_on time in the L
1-substate capability register and Controller will be waiting in recovery state for ACK.
This ensure that the PHY PLL lock and client system initialization goes on in parallel.
Default value of this register can be set with the define:den_db_LP_DBG_CTRL_RECOVER_ACK_AS_CLIENT_RECOVER_ACK.
Setting this field gives the best system performance.
30L1CSCR/W0hL
1-substate removes CORE_CLK.
since the registers are implemented in core-clk, register access is not possible during L
1-substate.
If client can supply a slow clock to core[CORE_CLK] during L
1-substates, APB/mgmt access is possible in L1.x.
set this bit if client can supply slow clock to CORE_CLK when CLKREQ_IN_N is 1[de-asserted].
If this bit is set, Controller neither wake-up from L1 or generate error response for APB access during L1.x.
Controller behavior is undefined if register write is performed while slow clock is supplied to core_clk.
Recommended flow is to first exit from L
1-substate and perform register writes.
Power on reset value of this register can be adjusted by modifying the define
den_db_LP_DBG_CTRL_CLIENT_SUPPLIES_SLOW_CLK_TO_CORE_DURING_L1
29L1DAETR/W1hL1.x turns off clocks to the controller.
Default behavior is made to exit L1.x if Register
access request is present at register interface.
Setting this bit disables this feature.
If this
bit is set and CLKREQ_IN_N is 1[de-asserted], Controller responds with ERROR response
to APB requests.
Client can use CLIENT_EXIT_L1_SUBSTATE
pin to trigger L1.x exit if autonomous exit is disabled for register access.

This bit is ignored if L1 substate is disabled.
Power on reset value of this register can be adjusted by modifying the define
den_db_LP_DBG_CTRL_DISABLE_AUTONOMOUS_L1_EXIT_ON_NEW_REG_REQ
28L1TROWR0hThis is a debug status field.
'1' in this field indicates that a timeout has occured
while waiting for RX path or OUTstanding packet IDLE conditions.
This is cleared on new entry to L1.
27L1PSR/W1hThis field enabled power shutoff mechanism in L1.2 state.
This field is ignored if L1.x is not enabled.
Power on reset value of this register can be adjusted by modifying the define
den_db_LP_DBG_CTRL_POWER_SHUTOFF_ENABLE
26L1ERCR/W0hEnables waiting for RX path IDLE condition before entering L1.x.
This checks that all packets from
PCIE link has reached client side before entering L1.x.
This only a tuning register.

Not setting this regsiter will cause controller to enter L1.x to save power without checking this.
controller will resume transferring RX data once it exit from L1.x state if RX buffers were not empty.
This field is ignored if Power shutoff mechanism is enabled for L1.x and Controller will always check
RX path idle condition before turning off internal power[with cpf flow].
If timeout is enabled,
controller enters L1.x without internal power shutoff after timeout.
This bit is ignored if L1 substate is disabled.
Power on reset value of this register can be adjusted by modifying the define
den_db_LP_DBG_CTRL_WAIT_FOR_RX_BUFFER_IDLE
25L1EOCR/W0hEnable waiting for outstanding completions before entering L1.x.
Outstanding packets expected from
pcie link as well as from AXI side is checked.
FOR HAL configurations client has to assert
PREVENT_L1x_ENTRY signal to prevent L1x entry.
This only a tuning register.
Not setting this regsiter
will cause controller to enter L1.x to save power without checking this.
controller exit from L1.x as
soon as it receives expected TLps.
This field is ignored if
Power shutoff mechanism is selected for L1.x and Controller will always wait for outstanding packets
before turning off internal power[with cpf flow].
If timeout is enabled, controller enters L1.x without
internal power shutoff after timeout.
This bit is ignored if L1 substate is disabled.
Power on reset value of this register can be adjusted by modifying the define
den_db_LP_DBG_CTRL_WAIT_FOR_OUTSTANDING_CPLS
24RESERVEDR/WX
23-0L1TWROIR/W0hThis field enables a timeout mechanism while waiting for RX buffers and Outstanding Pkts before
turning off power.
Controller enters L1 substate after timeout.
A value of 0x0 disables this timeout
mechanism.
Controller do not select internal power shutoff if it enters L1.x with this timeout.
User can give timeout in micro-seconds using this register.

This field is ignored if L1 substate is disabled.

Power on reset value of this register can be adjusted by modifying the define
den_db_LP_DBG_CTRL_RX_CPL_IDLE_CHECK_TIMEOUT

3.5.4.109 PCIE_CORE_LM_TL_INTERNAL_CONTROL Register (Offset = 00100C94h) [reset = 0h]

PCIE_CORE_LM_TL_INTERNAL_CONTROL is shown in Figure 12-1701 and described in Table 12-3346.

Return to the Summary Table.

This register controls internal behavior of Transaction layer of controller.
Adjustment of this register is not required for normal operations.

Table 12-3345 PCIE_CORE_LM_TL_INTERNAL_CONTROL Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0C94h
Figure 12-1701 PCIE_CORE_LM_TL_INTERNAL_CONTROL Register
3130292827262524
RES1
R-0h
2322212019181716
RES1
R-0h
15141312111098
RES1
R-0h
76543210
RES1DOOCECFLR
R-0hR/W-1hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3346 PCIE_CORE_LM_TL_INTERNAL_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
31-2RES1R0hReserved
1DOOCR/W1hOrdering between outbound Completions and posted packets are maintainted in transaction layer.
This is achieved by blocking Completions if required.
Completions arrived after EOP of a posted packet are blocked till that posted packet is transmitted.
This Ordering check is required to conform to the PCIe ordering
rules.
This ordering check can be disabled by setting this field.
Power on reset value of this register can be adjusted by modifying the define
den_db_TL_CTRL_DISABLE_OB_ORDERING_CHECK
0ECFLRR/W0hBy default controller ignores config request if a function is under going FLR.

Setting this bit makes the controller to respond with CRS response.
Power on reset value of this register can be adjusted by modifying the define
den_db_TL_CTRL_ENABLE_CRS_UNDER_FLR

3.5.4.110 PCIE_CORE_LM_I_DTI_ATS_STATUS Register (Offset = 00100C98h) [reset = 0h]

PCIE_CORE_LM_I_DTI_ATS_STATUS is shown in Figure 12-1702 and described in Table 12-3348.

Return to the Summary Table.

This register is for reporting different error conditions/ State in DTI ATS Master

Table 12-3347 PCIE_CORE_LM_I_DTI_ATS_STATUS Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0C98h
Figure 12-1702 PCIE_CORE_LM_I_DTI_ATS_STATUS Register
3130292827262524
R10
R-0h
2322212019181716
R10ITAGCONSTATE
R-0hR-0hR-0h
15141312111098
R12
R-0h
76543210
R12ITAGTIMEOUTINVREQIGNOREDNOTAGWRONGITAG
R-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3348 PCIE_CORE_LM_I_DTI_ATS_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-22R10R0hReserved
21-17ITAGR0hItag value which timed out
16CONSTATER0hWhen set indicates the DTI Master in connected state
15-4R12R0hReserved
3ITAGTIMEOUTR/W1C0hWhen set indicates a timeout in one of the invalidation tags.
Invalidation Tag timeout duration = INVTIMERCF * 16ns * INVTIMERCC
2INVREQIGNOREDR/W1C0hWhen set indicates that the invalidation request is ignored internally by the DTI Master block
1NOTAGR/W1C0hWhen set indicates the DTI Slave returned an error for the connection request due to non availability of tags.
0WRONGITAGR/W1C0hWhen set indicates that the itag field is wrong in the invalidation completion message.

3.5.4.111 PCIE_CORE_LM_I_DTI_ATS_CTRL Register (Offset = 00100C9Ch) [reset = 27807A12h]

PCIE_CORE_LM_I_DTI_ATS_CTRL is shown in Figure 12-1703 and described in Table 12-3350.

Return to the Summary Table.

This register is for the control of DTI ATS Master

Table 12-3349 PCIE_CORE_LM_I_DTI_ATS_CTRL Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0C9Ch
Figure 12-1703 PCIE_CORE_LM_I_DTI_ATS_CTRL Register
3130292827262524
R3LDCTRLDISCONREQCONREQINVTIMERCC
R-0hR/W-1hR/W-0hR/W-0hR/W-78h
2322212019181716
INVTIMERCCINVTIMERCF
R/W-78hR/W-7A12h
15141312111098
INVTIMERCF
R/W-7A12h
76543210
INVTIMERCF
R/W-7A12h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3350 PCIE_CORE_LM_I_DTI_ATS_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-30R3R0hReserved
29LDCTRLR/W1hThis bit when programmed to 1 sends a disconnect request when link down reset happens and sends a connect request when link down indication bit is cleared.
28DISCONREQR/W0hWhen set DTI Master triggers a disconnect sequence to the DTI Slave.
This bit gets reset to 0 when the DTI master establishes a disconnection.
27CONREQR/W0hWhen set DTI Master triggers a connect sequence to the DTI Slave.
This bit gets reset to 0 when the DTI master establishes a connection.
26-20INVTIMERCCR/W78hThis is a coarse value which the individual invalidation timers check for reporting a timeout
19-0INVTIMERCFR/W7A12hThis is a master counter timeout value which triggers the invalidation tag timers to increment if an active invalidation request is present

3.5.4.112 PCIE_CORE_LM_I_SCALED_FLOW_CONTROL_MGMT_VC_SELECT_REG Register (Offset = 00100CC0h) [reset = 0h]

PCIE_CORE_LM_I_SCALED_FLOW_CONTROL_MGMT_VC_SELECT_REG is shown in Figure 12-1704 and described in Table 12-3352.

Return to the Summary Table.

Scaled Flow Control registers are implemented per VC. The VC is selected using this
register.

Table 12-3351 PCIE_CORE_LM_I_SCALED_FLOW_CONTROL_MGMT_VC_SELECT_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0CC0h
Figure 12-1704 PCIE_CORE_LM_I_SCALED_FLOW_CONTROL_MGMT_VC_SELECT_REG Register
31302928272625242322212019181716
RES3116
R-0h
1514131211109876543210
RES3116SFCVCS
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3352 PCIE_CORE_LM_I_SCALED_FLOW_CONTROL_MGMT_VC_SELECT_REG Register Field Descriptions
BitFieldTypeResetDescription
31-4RES3116R0hReserved
3-0SFCVCSR/W0hThe scaled flow management rgeister is implemented per VC.
However, to limit the
number of registers, only one VC can be accessed at a time.
This register is used to select the VC
for which Scaled Flow Control Management Register is to be accessed.

3.5.4.113 PCIE_CORE_LM_I_SCALED_FLOW_CONTROL_MGMT_REG Register (Offset = 00100CC4h) [reset = 555h]

PCIE_CORE_LM_I_SCALED_FLOW_CONTROL_MGMT_REG is shown in Figure 12-1705 and described in Table 12-3354.

Return to the Summary Table.

Scaled Flow Control management register. For multi-VC configurations, this register
accesses the VC selected in Scaled Flow Control VC Select register.

Table 12-3353 PCIE_CORE_LM_I_SCALED_FLOW_CONTROL_MGMT_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0CC4h
Figure 12-1705 PCIE_CORE_LM_I_SCALED_FLOW_CONTROL_MGMT_REG Register
31302928272625242322212019181716
RES2RCPCSRCHCSRNPPCSRNPHCSRPPCSRPHCS
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
1514131211109876543210
RES1LCPCSLCHCSLNPPCSLNPHCSLPPCSLPHCS
R-0hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3354 PCIE_CORE_LM_I_SCALED_FLOW_CONTROL_MGMT_REG Register Field Descriptions
BitFieldTypeResetDescription
31-28RES2R0hReserved
27-26RCPCSR0hThis register reflects the Completion Payload Credit Scale that is
advertised by the remote end device during DL Feature Exchange.
25-24RCHCSR0hThis register reflects the Completion Header Credit Scale that is
advertised by the remote end device during DL Feature Exchange.
23-22RNPPCSR0hThis register reflects the Non Posted Payload Credit Scale that is
advertised by the remote end device during DL Feature Exchange.
21-20RNPHCSR0hThis register reflects the Non Posted Header Credit Scale that is
advertised by the remote end device during DL Feature Exchange.
19-18RPPCSR0hThis register reflects the Posted Payload Credit Scale that is
advertised by the remote end device during DL Feature Exchange.
17-16RPHCSR0hThis register reflects the Posted Header Credit Scale that is
advertised by the remote end device during DL Feature Exchange.
15-12RES1R0hReserved
11-10LCPCSR/W1hThis register can be used to program the Completion Payload Credit Scale that will be
advertised by the Controller.
9-8LCHCSR/W1hThis register can be used to program the Completion Header Credit Scale that will be
advertised by the Controller.
7-6LNPPCSR/W1hThis register can be used to program the Non Posted Payload Credit Scale that will be
advertised by the Controller.
5-4LNPHCSR/W1hThis register can be used to program the Non Posted Header Credit Scale that will be
advertised by the Controller.
3-2LPPCSR/W1hThis register can be used to program the Posted Payload Credit Scale that will be
advertised by the Controller.
1-0LPHCSR/W1hThis register can be used to program the Posted Header Credit Scale that will be
advertised by the Controller.

3.5.4.114 PCIE_CORE_LM_I_MARGINING_PARAMETERS_1_REG Register (Offset = 00100CD0h) [reset = 05506417h]

PCIE_CORE_LM_I_MARGINING_PARAMETERS_1_REG is shown in Figure 12-1706 and described in Table 12-3356.

Return to the Summary Table.

The Lane Margining at Receiver Parameters of the PHY are advertised in this Register.

Table 12-3355 PCIE_CORE_LM_I_MARGINING_PARAMETERS_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0CD0h
Figure 12-1706 PCIE_CORE_LM_I_MARGINING_PARAMETERS_1_REG Register
3130292827262524
RESMMVO
R-0hR/W-5h
2322212019181716
MMTOMNTS
R/W-14hR/W-6h
15141312111098
MNTSMNVS
R/W-6hR/W-20h
76543210
MNVSMIESMSRMMINDLRTSMINDUDVSMVS
R/W-20hR/W-1hR/W-0hR/W-1hR/W-1hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3356 PCIE_CORE_LM_I_MARGINING_PARAMETERS_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-30RESR0hReserved
29-24MMVOR/W5hOffset from default at maximum step value as percentage of one volt.
A 0 value may be reported if the vendor chooses not to report the offset.
23-18MMTOR/W14hOffset from default at maximum step value as percentage of a nominal UI at 16.0 GT/s
A 0 value may be reported if the vendor chooses not to report the offset.
17-12MNTSR/W6hNumber of time steps from default [to either left or right], range must be at least +/-0.2 UI.
Timing offset must increase monotonically.
The number of steps in both positive [toward the end of the unit interval]
and negative [toward the beginning of the unit interval] must be identical.
11-5MNVSR/W20hNumber of voltage steps from default [either up or down], minimum range +/-50 mV as measured by 16.0 GT/s reference equalizer
Voltage offset must increase monotonically.
The number of steps in both positive and negative direction from the default sample location must be identical
This value is undefined if M VoltageSupported is 0b.
4MIESR/W1h1b Margining will not produce errors [change in the error rate] in data stream [error sampler is independent]
0b Margining may produce errors in the data stream
3MSRMR/W0h1b - Sampling Rates M SamplingRateVoltage, M SamplingRateTiming are supported
0b - Sample Count is supported
2MINDLRTSR/W1h1b - Independent Left/Right Timing Margining is supported
0b - Independent Left/Right Timing Margining is not supported
1MINDUDVSR/W1h1b - Independent Up Down Voltage Margining is supported
0b - Independent Up Down Voltage Margining is not supported
0MVSR/W1h1b - Voltage Margining is supported
0b - Voltage Margining is not supported

3.5.4.115 PCIE_CORE_LM_I_MARGINING_PARAMETERS_2_REG Register (Offset = 00100CD4h) [reset = 0h]

PCIE_CORE_LM_I_MARGINING_PARAMETERS_2_REG is shown in Figure 12-1707 and described in Table 12-3358.

Return to the Summary Table.

The Lane Margining at Receiver Parameters of the PHY are advertised in this Register.

Table 12-3357 PCIE_CORE_LM_I_MARGINING_PARAMETERS_2_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0CD4h
Figure 12-1707 PCIE_CORE_LM_I_MARGINING_PARAMETERS_2_REG Register
313029282726252423222120191817161514131211109876543210
RES1MMLMSRTMSRV
R-0hR/W-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3358 PCIE_CORE_LM_I_MARGINING_PARAMETERS_2_REG Register Field Descriptions
BitFieldTypeResetDescription
31-17RES1R0hReserved
16-12MMLR/W0hMaximum number of Lanes minus 1 that can be margined at the same time.

It is recommended that this value be greater than or equal to the number of Lanes in the Link minus 1.

Encoding Behavior is undefined if software attempts to margin more than MMaxLanes+1 at the same time.
Note: This value is permitted to exceed the number of Lanes in the Link minus 1.
11-6MSRTR/W0hThe ratio of bits tested to bits received during timing margining.

A value of 0 is a ratio of
1:64 [1 bit of every 64 bits received],
and a value of 63 is a ratio of
64:64 [all bits received].
5-0MSRVR/W0hThe ratio of bits tested to bits received during voltage margining.
A value of 0 is a ratio of
1:64 [1 bit of every 64 bits received],
and a value of 63 is a ratio of
64:64 [all bits received].

3.5.4.116 PCIE_CORE_LM_I_MARGINING_LOCAL_CONTROL_REG Register (Offset = 00100CD8h) [reset = 80000000h]

PCIE_CORE_LM_I_MARGINING_LOCAL_CONTROL_REG is shown in Figure 12-1708 and described in Table 12-3360.

Return to the Summary Table.

The Lane Margining at Receiver local control fields are implemented in this Register.

Table 12-3359 PCIE_CORE_LM_I_MARGINING_LOCAL_CONTROL_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0CD8h
Figure 12-1708 PCIE_CORE_LM_I_MARGINING_LOCAL_CONTROL_REG Register
3130292827262524
WAWTCRES
R/W-4hR-0h
2322212019181716
RES
R-0h
15141312111098
RES
R-0h
76543210
RESESMSUCEDMSUSCAMCNG4MSR
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3360 PCIE_CORE_LM_I_MARGINING_LOCAL_CONTROL_REG Register Field Descriptions
BitFieldTypeResetDescription
31-29WAWTCR/W4hWhen a WriteCommitted command is issued by the Controller, the PHY must respond with
a Write_Ack response.
The time for which the Controller waits before timing out is controlled by this register.

000: 10us

001: 100us

010: 1ms

011: 2ms

100: 10ms [default]

101: 20ms

110: 100ms

111: No Timeout
28-4RESR0hReserved
3ESMSUCER/W0h
0: [Default Value] When a Clear Error Log Command is received after a Step Margin Command, the Controller will process the Clear Error Log and respond with Clear Error Log Status.
The Step Margin command is still active in the PHY.
However, the Step Margin status will not be reflected in the Margin Status Register since the Margin Control Register holds Clear Error Log Command.
Host Margining SW needs to configure the Step Margin Command again in order to get the Step Margin Status.


1: When this bit is set to 1, the Controller waits for Host SW to read the Clear Error Log Status through a CfgRd.
After the Host read the Clear Error Log status, the Controller updates the latest Step Margin Status on to the Margin Status Register while the Margin Control Register holds Clear Error Log Command.
2DMSUSCR/W0hBy default, when a Step Margin command is received, the Controller will update Lane
Margin status to Margining in Progress when an Error Count update Or a Sample Count
update is received from PHY.
Set this bit to 1 to not update Lane Margin Status on a Sample Count update from PHY.
1AMCNG4R/W0hBy default, the Controller will process a Margin Command only if it is received
while in 16GT/s L0 State.
If a Margin Command is received when the link is not in Gen4-L0 state, then the
command will be ignored.
If this bit is set, then the Controller accepts and stores a margin command that is
received when not in Gen4 L0 state.
This command will be processed when the link
reaches Gen4 L0 state.
0MSRR/W0hThis bit can be used to reset the Margining internal registers and Margining state machines in the Controller.
When
asserted:
[i] The State machines will be reset to their default values.
[ii] All internal FIFOs will be cleared.
[iii] All the P2M and M2P registers will be reset.
[iv] This does not reset the Margining Configuration and Management Registers.
Margining Status register will show the last recorded status.
This bit will automatically self-clear after
32-CORE_CLK cycles.

3.5.4.117 PCIE_CORE_LM_I_MARGINING_ERROR_STATUS1_REG Register (Offset = 00100CDCh) [reset = 0h]

PCIE_CORE_LM_I_MARGINING_ERROR_STATUS1_REG is shown in Figure 12-1709 and described in Table 12-3362.

Return to the Summary Table.

The Lane Margining at Receiver SW Error Status fields are implemented in this Register.

Table 12-3361 PCIE_CORE_LM_I_MARGINING_ERROR_STATUS1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0CDCh
Figure 12-1709 PCIE_CORE_LM_I_MARGINING_ERROR_STATUS1_REG Register
31302928272625242322212019181716
RESISWMCLN
R-0hR-0h
1514131211109876543210
ISWMC
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3362 PCIE_CORE_LM_I_MARGINING_ERROR_STATUS1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-20RESR0hReserved
19-16ISWMCLNR0hThis field reports the Lane Number for which the Invalid command was received.

0000: Lane 0.

0001: Lane 1.
and so on.
This register is valid only when Bit-4, Invalid SW Margining Command Received, of the I_LOCAL_ERROR_STATUS_2_REGISTER is set. Bit-4 of the I_LOCAL_ERROR_STATUS_2_REGISTER has to be cleared by local firmware before another error can be logged in this field.
15-0ISWMCR0hWhen the Controller receives an Invalid Margining Command from SW in its configuration register,
the
16-bit command is logged in this register for debug.
Only the first Error is logged in this register.
This register is valid only when Bit-4, Invalid SW Margining Command Received, of the I_LOCAL_ERROR_STATUS_2_REGISTER is set. Bit-4 of the I_LOCAL_ERROR_STATUS_2_REGISTER has to be cleared by local firmware before another error can be logged in this field.

3.5.4.118 PCIE_CORE_LM_I_MARGINING_ERROR_STATUS2_REG Register (Offset = 00100CE0h) [reset = 0h]

PCIE_CORE_LM_I_MARGINING_ERROR_STATUS2_REG is shown in Figure 12-1710 and described in Table 12-3364.

Return to the Summary Table.

The Lane Margining at Receiver PHY Error Status fields are implemented in this Register.

Table 12-3363 PCIE_CORE_LM_I_MARGINING_ERROR_STATUS2_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0CE0h
Figure 12-1710 PCIE_CORE_LM_I_MARGINING_ERROR_STATUS2_REG Register
31302928272625242322212019181716
RES22UPRLNWAWTLN
R-0hR-0hR-0h
1514131211109876543210
WAWTLNRES12IPHYMCLNIPHYMC
R-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3364 PCIE_CORE_LM_I_MARGINING_ERROR_STATUS2_REG Register Field Descriptions
BitFieldTypeResetDescription
31-22RES22R0hReserved
21-18UPRLNR0hThis field reports the Lane Number for which the Controller received an unexpected
PHY Response for Lane Margining.
Unexpected PHY Response is detected by Controller if PHY writes to the Margin Status or
the Margin NAK bits of RX Margin Status 0 Register when no change in Start Margin or
Margin Offset issued by Controller or after the Write Ack Wait Timeout.

0000: Lane 0.

0001: Lane 1.
and so on.
This field is valid only when Bit-7, Unexpected PHY Response Received, of the I_LOCAL_ERROR_STATUS_2_REGISTER is set. Bit-7 of the I_LOCAL_ERROR_STATUS_2_REGISTER has to be cleared by local firmware before another error can be logged in this field.
17-14WAWTLNR0hThis field reports the Lane Number for which the Controller detected a 10ms timeout.

0000: Lane 0.

0001: Lane 1.
and so on.
This field is valid only when Bit-6, Write Ack Wait Timeout Error, of the I_LOCAL_ERROR_STATUS_2_REGISTER is set. Bit-6 of the I_LOCAL_ERROR_STATUS_2_REGISTER has to be cleared by local firmware before another error can be logged in this field.
13-12RES12R0hReserved
11-8IPHYMCLNR0hThis field reports the Lane Number for which the Invalid command was received.

0000: Lane 0.

0001: Lane 1.
and so on.
This field is valid only when Bit-5, Invalid PHY Margining Command Received, of the I_LOCAL_ERROR_STATUS_2_REGISTER is set. Bit-5 of the I_LOCAL_ERROR_STATUS_2_REGISTER has to be cleared by local firmware before another error can be logged in this field.
7-0IPHYMCR0hWhen the Controller receives an Invalid Margining Command from PHY over PIPE Interface,
the
8-bit PIPE command is logged in this register for debug.
Only the first Error is logged in this register.
This field is valid only when Bit-5, Invalid PHY Margining Command Received, of the I_LOCAL_ERROR_STATUS_2_REGISTER is set. Bit-5 of the I_LOCAL_ERROR_STATUS_2_REGISTER has to be cleared by local firmware before another error can be logged in this field.

3.5.4.119 PCIE_CORE_LM_I_LOCAL_ERROR_STATUS_2_REGISTER Register (Offset = 00100D00h) [reset = 0h]

PCIE_CORE_LM_I_LOCAL_ERROR_STATUS_2_REGISTER is shown in Figure 12-1711 and described in Table 12-3366.

Return to the Summary Table.

This is an extension of the Local Error and Status Register.
This register contains the status of the various events, errors and abnormal conditions in the
Controller. Any of the status bits can be reset by writing a 1 into the bit position.
Unless masked by the setting of the Local Interrupt Mask 2 Register,
the occurrence of any of these conditions causes the Controller to activate the LOCAL_INTERRUPT
output.

Table 12-3365 PCIE_CORE_LM_I_LOCAL_ERROR_STATUS_2_REGISTER Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0D00h
Figure 12-1711 PCIE_CORE_LM_I_LOCAL_ERROR_STATUS_2_REGISTER Register
3130292827262524
R31
R-0h
2322212019181716
R31
R-0h
15141312111098
R31LEQRQINR13_11R10PTMCNTAINVNFTSTOS
R-0hR/W1C-0hR-0hR-0hR/W1C-0hR/W1C-0h
76543210
UPRRWAWTEIPHYMCRISWMCRMSIXMSKSETSTMSIXMSKCLSTMSIMSKSETSTMSIMSKCLST
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3366 PCIE_CORE_LM_I_LOCAL_ERROR_STATUS_2_REGISTER Register Field Descriptions
BitFieldTypeResetDescription
31-15R31R0hReserved
14LEQRQINR/W1C0hEP Mode: Indicates that the Controller hardware detected a problem with equalization
and automatically requested for equalization redo at the end of the equalization.
Controller checks for problems in Recovery.Rcvr.Lock state by comparing the Tx
Coefficients agreed at end of Eq Phase2 with the Tx Coefficients received in TS1s
in Recovery.Rcvr.Lock state at the end of equalization.
Any mismatch is detected and
the Request Equalization bit is set in Recovery.Rcvg.Cfg.
This bit is set for both 8GT/s and 16GT/s equalization requests.
[i] The Link Eq Request 8GT/s bit-5 in Link Status 2 Register will be set for 8GT/s Eq Request.
[ii] The Link Eq Request 16.0 GT/s, bit-4 in 16.0 GT/s Status Register will be set for 16GT/s Eq Request.

RC Mode: Indicates that the Controller received Equalization Request from downstream component.
This bit is set for both 8GT/s and 16GT/s equalization requests.
[i] The Link Eq Request 8GT/s bit-5 in Link Status 2 Register will be set for 8GT/s Eq Request.
[ii] The Link Eq Request 16.0 GT/s, bit-4 in 16.0 GT/s Status Register will be set for 16GT/s Eq Request.
13-11R13_11R0hReserved
10R10R0hReserved
9PTMCNTAINVR/W1C0hThis status bit indicates that the Controller automatically invalidated PTM Context
because of PCIe Link exit from L0 State.
8NFTSTOSR/W1C0hThis status bit indicates that a NFTS Timeout occured.
This could occur if the PHY failed to achieve lock on the receive data before the NFTS Timeout during Rx_L0s.FTS state.
Local Firmware should consider increasing the advertized NFTS values if this event occurs.
7UPRRR/W1C0hThis bit indicates that the Controller received an unexpected
PHY Response for Lane Margining.
The lane on which this error was detected is captured in bits 21:18 of the margining_error_status2_reg register.
Unexpected PHY Response is detected by Controller if PHY writes to the Margin Status or
the Margin NAK bits of the MAC RX Margin Status 0 Register when no change in Start Margin or
Margin Offset issued by Controller or after the Write Ack Wait Timeout.
This bit is set upon receiving the first error. Local firmware must clear this bit by writing a 1 to this bit before another error can be logged in the margining_error_status2_reg register.
6WAWTER/W1C0hThis bit indicates that the Controller detected a 10ms timeout while waiting for
Write Ack Lane Margining response from a PHY.
The lane on which this timeout was detected is
captured in bits
17:14 of the margining_error_status2_reg register.
This bit is set upon receiving the first error. Local firmware must clear this bit by writing a 1 to this bit before another error can be logged in the margining_error_status2_reg register.
5IPHYMCRR/W1C0hThis bit validates the
8-bit command stored in bits
[7:0] and the Lane Number
stored in bits
[11:8] of the margining_error_status1_reg register.
This bit is set upon receiving the first Error.
Local firmware must clear this bit by writing a 1 to this bit before another error can
be logged in the margining_error_status1_reg register.
4ISWMCRR/W1C0hThis bit validates the
16-bit command stored in bits
[15:0] and the Lane Number
stored in bits
[19:16] of the margining_error_status1_reg register.
This bit is set upon receiving the first Error.
Local firmware must clear this bit by writing a 1 to this bit before another error can
be logged in the margining_error_status1_reg register.
3MSIXMSKSETSTR/W1C0hThis status bit indicates that the MSIX Function Mask of any function, PF or VF, was programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .

Note that this is a Read Only Status bit.

The MSIX Function Mask Clear status per-function is captured in the msix_function_mask_set_status_register.
Firmware has to clear the per-function bits in msix_function_mask_set_status_register in order to clear this status bit and to deassert LOCAL_INTERRUPT.

2MSIXMSKCLSTR/W1C0hThis status bit indicates that the MSIX Function Mask of any function, PF or VF, was programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .

Note that this is a Read Only Status bit.

The MSIX Function Mask Clear status per-function is captured in the msix_function_mask_cleared_status_register.
Firmware has to clear the per-function bits in msix_function_mask_cleared_status_register in order to clear this status bit and to deassert LOCAL_INTERRUPT.

1MSIMSKSETSTR/W1C0hThis status bit indicates that One or More bits of MSI Mask of any function, PF or VF, was programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .

Note that this is a Read Only Status bit.

The MSI Mask Clear status per-function is captured in the msi_mask_set_status_register.
Firmware has to clear the per-function bits in msi_mask_set_status_register in order to clear this status bit and to deassert LOCAL_INTERRUPT.

0MSIMSKCLSTR/W1C0hThis status bit indicates that One or More bits of MSI Mask of any function, PF or VF, was programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .

Note that this is a Read Only Status bit.

The MSI Mask Clear status per-function is captured in the msi_mask_cleared_status_register.
Firmware has to clear the per-function bits in msi_mask_cleared_status_register in order to clear this status bit and to deassert LOCAL_INTERRUPT.

3.5.4.120 PCIE_CORE_LM_I_LOCAL_INTRPT_MASK_2_REG Register (Offset = 00100D04h) [reset = 4200h]

PCIE_CORE_LM_I_LOCAL_INTRPT_MASK_2_REG is shown in Figure 12-1712 and described in Table 12-3368.

Return to the Summary Table.

This is an extension of the Local Interrupt Mask Register.
This register contains a mask bit for each interrupting condition in local_error_status_2_register.
Setting the bit to 1 prevents the corresponding condition in the Local Error Status 2 Register
from activating the LOCAL_INTERRUPT output.

Table 12-3367 PCIE_CORE_LM_I_LOCAL_INTRPT_MASK_2_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0D04h
Figure 12-1712 PCIE_CORE_LM_I_LOCAL_INTRPT_MASK_2_REG Register
3130292827262524
R31
R-0h
2322212019181716
R31
R-0h
15141312111098
R31LEQRQINMR13_11R10PCAIMNFTSTOM
R-0hR/W-1hR-0hR-0hR/W-1hR/W-0h
76543210
UPREMWAWTEMIPHYMEMISWMEMMSIXMSKSETMSIXMSKCLMSIMSKSETMSIMSKCL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3368 PCIE_CORE_LM_I_LOCAL_INTRPT_MASK_2_REG Register Field Descriptions
BitFieldTypeResetDescription
31-15R31R0hReserved
14LEQRQINMR/W1hMask for Link Equalization Request Interrupt.
13-11R13_11R0hReserved
10R10R0hReserved
9PCAIMR/W1hMask for PTM Context Auto Invalidated event.
8NFTSTOMR/W0hMask for NFTS Timeout.
7UPREMR/W0hUnexpected PHY Response is detected by Controller if PHY writes to the Margin Status or
the Margin NAK bits of RX Margin Status 0 Register when no change in Start Margin or
Margin Offset issued by Controller or after the Write Ack Wait Timeout
This bit can be used to Mask asserting the LOCAL_INTERRUPT output upon this error.

1: Error is masked.

0: Error is not masked.
6WAWTEMR/W0hWhen a WriteCommitted command is issued by the Controller, the PHY must respond with
a Write_Ack within 10ms on the PIPE Message Bus Interface.
However, if the Write_Ack is not received within 10ms, the Controller reports
Timeout and stops waiting for the write_ack.
This bit can be used to Mask asserting the LOCAL_INTERRUPT output upon this 10ms timeout.

1: Error is masked.

0: Error is not masked.
5IPHYMEMR/W0hWhen the Controller receives a Margining Command from PHY over the PIPE Interface, it
checks if the command is valid.
The error status is logged in local_error_status_2_register.
This bit can be used to Mask asserting the LOCAL_INTERRUPT output when the Invalid
PHY Margining Error Status is set.

1: Error is masked.

0: Error is not masked.
4ISWMEMR/W0hWhen the Controller receives a Margining Command from SW in its configuration register, it
checks if the command is valid.
The error status is logged in local_error_status_2_register.
This bit can be used to Mask asserting the LOCAL_INTERRUPT output when the Invalid
SW Margining Error Status is set.

1: Error is masked.

0: Error is not masked.
.
3MSIXMSKSETR/W0hMask for MSIX Function Mask Cleared Status.
2MSIXMSKCLR/W0hMask for MSIX Function Mask Set Status.
1MSIMSKSETR/W0hMask for MSI Mask Set Status.
0MSIMSKCLR/W0hMask for MSI Mask Cleared Status.

3.5.4.121 PCIE_CORE_LM_MSI_MASK_CLEARED_STATUS_1 Register (Offset = 00100D10h) [reset = 0h]

PCIE_CORE_LM_MSI_MASK_CLEARED_STATUS_1 is shown in Figure 12-1713 and described in Table 12-3370.

Return to the Summary Table.

This status register has one bit per function. Each function has a 32-bit MSI Mask.
If any bit in the function's MSI Mask register is configured from 1 to 0,
then the corresponding function's status bit in this register is set.
Local Firmware needs to clear this register by writing a 1.

Table 12-3369 PCIE_CORE_LM_MSI_MASK_CLEARED_STATUS_1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0D10h
Figure 12-1713 PCIE_CORE_LM_MSI_MASK_CLEARED_STATUS_1 Register
3130292827262524
R31
R-0h
2322212019181716
R31VF15MSIMSKCLSTVF14MSIMSKCLSTVF13MSIMSKCLSTVF12MSIMSKCLSTVF11MSIMSKCLSTVF10MSIMSKCLST
R-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
15141312111098
VF9MSIMSKCLSTVF8MSIMSKCLSTVF7MSIMSKCLSTVF6MSIMSKCLSTVF5MSIMSKCLSTVF4MSIMSKCLSTVF3MSIMSKCLSTVF2MSIMSKCLST
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
VF1MSIMSKCLSTVF0MSIMSKCLSTPF5MSIMSKCLSTPF4MSIMSKCLSTPF3MSIMSKCLSTPF2MSIMSKCLSTPF1MSIMSKCLSTPF0MSIMSKCLST
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3370 PCIE_CORE_LM_MSI_MASK_CLEARED_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
31-22R31R0hReserved
21VF15MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF15 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
20VF14MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF14 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
19VF13MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF13 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
18VF12MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF12 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
17VF11MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF11 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
16VF10MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF10 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
15VF9MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF9 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
14VF8MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF8 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
13VF7MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF7 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
12VF6MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF6 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
11VF5MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF5 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
10VF4MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF4 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
9VF3MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF3 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
8VF2MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF2 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
7VF1MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF1 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
6VF0MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF0 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
5PF5MSIMSKCLSTR/W1C0hEach PF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in PF5 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
4PF4MSIMSKCLSTR/W1C0hEach PF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in PF4 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
3PF3MSIMSKCLSTR/W1C0hEach PF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in PF3 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
2PF2MSIMSKCLSTR/W1C0hEach PF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in PF2 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
1PF1MSIMSKCLSTR/W1C0hEach PF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in PF1 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
0PF0MSIMSKCLSTR/W1C0hEach PF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in PF0 MSI Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.

3.5.4.122 PCIE_CORE_LM_MSI_MASK_SET_STATUS_1 Register (Offset = 00100D14h) [reset = 0h]

PCIE_CORE_LM_MSI_MASK_SET_STATUS_1 is shown in Figure 12-1714 and described in Table 12-3372.

Return to the Summary Table.

This status register has one bit per function. Each function has a 32-bit MSI Mask.
If any bit in the function's MSI Mask register is configured from 0 to 1,
then the corresponding function's status bit in this register is set.
Local Firmware needs to clear this register by writing a 1.

Table 12-3371 PCIE_CORE_LM_MSI_MASK_SET_STATUS_1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0D14h
Figure 12-1714 PCIE_CORE_LM_MSI_MASK_SET_STATUS_1 Register
3130292827262524
R31
R-0h
2322212019181716
R31VF15MSIMSKCLSTVF14MSIMSKCLSTVF13MSIMSKCLSTVF12MSIMSKCLSTVF11MSIMSKCLSTVF10MSIMSKCLST
R-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
15141312111098
VF9MSIMSKCLSTVF8MSIMSKCLSTVF7MSIMSKCLSTVF6MSIMSKCLSTVF5MSIMSKCLSTVF4MSIMSKCLSTVF3MSIMSKCLSTVF2MSIMSKCLST
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
VF1MSIMSKCLSTVF0MSIMSKCLSTPF5MSIMSKCLSTPF4MSIMSKCLSTPF3MSIMSKCLSTPF2MSIMSKCLSTPF1MSIMSKCLSTPF0MSIMSKCLST
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3372 PCIE_CORE_LM_MSI_MASK_SET_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
31-22R31R0hReserved
21VF15MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF15 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
20VF14MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF14 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
19VF13MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF13 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
18VF12MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF12 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
17VF11MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF11 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
16VF10MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF10 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
15VF9MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF9 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
14VF8MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF8 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
13VF7MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF7 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
12VF6MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF6 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
11VF5MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF5 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
10VF4MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF4 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
9VF3MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF3 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
8VF2MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF2 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
7VF1MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF1 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
6VF0MSIMSKCLSTR/W1C0hEach VF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in VF0 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
5PF5MSIMSKCLSTR/W1C0hEach PF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in PF5 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
4PF4MSIMSKCLSTR/W1C0hEach PF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in PF4 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
3PF3MSIMSKCLSTR/W1C0hEach PF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in PF3 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
2PF2MSIMSKCLSTR/W1C0hEach PF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in PF2 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
1PF1MSIMSKCLSTR/W1C0hEach PF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in PF1 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
0PF0MSIMSKCLSTR/W1C0hEach PF has a
32-bit MSI Mask.

This status bit is set when any of the
32-bits in PF0 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSI Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.

3.5.4.123 PCIE_CORE_LM_MSIX_FUNCTION_MASK_CLEARED_STATUS_1 Register (Offset = 00100D18h) [reset = 0h]

PCIE_CORE_LM_MSIX_FUNCTION_MASK_CLEARED_STATUS_1 is shown in Figure 12-1715 and described in Table 12-3374.

Return to the Summary Table.

This status register has one bit per function. Each function has a 1-bit MSIX Function Mask.
If the function's MSIX Function Mask register is configured from 1 to 0,
then the corresponding function's status bit in this register is set.
Local Firmware needs to clear this register by writing a 1.

Table 12-3373 PCIE_CORE_LM_MSIX_FUNCTION_MASK_CLEARED_STATUS_1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0D18h
Figure 12-1715 PCIE_CORE_LM_MSIX_FUNCTION_MASK_CLEARED_STATUS_1 Register
3130292827262524
R31
R-0h
2322212019181716
R31VF15MSIXMSKCLSTVF14MSIXMSKCLSTVF13MSIXMSKCLSTVF12MSIXMSKCLSTVF11MSIXMSKCLSTVF10MSIXMSKCLST
R-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
15141312111098
VF9MSIXMSKCLSTVF8MSIXMSKCLSTVF7MSIXMSKCLSTVF6MSIXMSKCLSTVF5MSIXMSKCLSTVF4MSIXMSKCLSTVF3MSIXMSKCLSTVF2MSIXMSKCLST
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
VF1MSIXMSKCLSTVF0MSIXMSKCLSTPF5MSIXMSKCLSTPF4MSIXMSKCLSTPF3MSIXMSKCLSTPF2MSIXMSKCLSTPF1MSIXMSKCLSTPF0MSIXMSKCLST
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3374 PCIE_CORE_LM_MSIX_FUNCTION_MASK_CLEARED_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
31-22R31R0hReserved
21VF15MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF15 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
20VF14MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF14 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
19VF13MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF13 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
18VF12MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF12 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
17VF11MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF11 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
16VF10MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF10 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
15VF9MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF9 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
14VF8MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF8 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
13VF7MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF7 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
12VF6MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF6 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
11VF5MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF5 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
10VF4MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF4 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
9VF3MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF3 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
8VF2MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF2 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
7VF1MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF1 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
6VF0MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF0 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
5PF5MSIXMSKCLSTR/W1C0hEach PF has a
1-bit MSIX Function Mask.

This status bit is set when the PF5 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
4PF4MSIXMSKCLSTR/W1C0hEach PF has a
1-bit MSIX Function Mask.

This status bit is set when the PF4 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
3PF3MSIXMSKCLSTR/W1C0hEach PF has a
1-bit MSIX Function Mask.

This status bit is set when the PF3 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
2PF2MSIXMSKCLSTR/W1C0hEach PF has a
1-bit MSIX Function Mask.

This status bit is set when the PF2 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
1PF1MSIXMSKCLSTR/W1C0hEach PF has a
1-bit MSIX Function Mask.

This status bit is set when the PF1 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
0PF0MSIXMSKCLSTR/W1C0hEach PF has a
1-bit MSIX Function Mask.

This status bit is set when the PF0 MSIX Function Mask is programmed or configured from 1 to 0 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.

3.5.4.124 PCIE_CORE_LM_MSIX_FUNCTION_MASK_SET_STATUS_1 Register (Offset = 00100D1Ch) [reset = 0h]

PCIE_CORE_LM_MSIX_FUNCTION_MASK_SET_STATUS_1 is shown in Figure 12-1716 and described in Table 12-3376.

Return to the Summary Table.

This status register has one bit per function. Each function has a 1-bit MSIX Function Mask.
If the function's MSIX Function Mask register is configured from 0 to 1,
then the corresponding function's status bit in this register is set.
Local Firmware needs to clear this register by writing a 1.

Table 12-3375 PCIE_CORE_LM_MSIX_FUNCTION_MASK_SET_STATUS_1 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0D1Ch
Figure 12-1716 PCIE_CORE_LM_MSIX_FUNCTION_MASK_SET_STATUS_1 Register
3130292827262524
R31
R-0h
2322212019181716
R31VF15MSIXMSKCLSTVF14MSIXMSKCLSTVF13MSIXMSKCLSTVF12MSIXMSKCLSTVF11MSIXMSKCLSTVF10MSIXMSKCLST
R-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
15141312111098
VF9MSIXMSKCLSTVF8MSIXMSKCLSTVF7MSIXMSKCLSTVF6MSIXMSKCLSTVF5MSIXMSKCLSTVF4MSIXMSKCLSTVF3MSIXMSKCLSTVF2MSIXMSKCLST
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
VF1MSIXMSKCLSTVF0MSIXMSKCLSTPF5MSIXMSKCLSTPF4MSIXMSKCLSTPF3MSIXMSKCLSTPF2MSIXMSKCLSTPF1MSIXMSKCLSTPF0MSIXMSKCLST
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3376 PCIE_CORE_LM_MSIX_FUNCTION_MASK_SET_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
31-22R31R0hReserved
21VF15MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF15 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
20VF14MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF14 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
19VF13MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF13 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
18VF12MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF12 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
17VF11MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF11 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
16VF10MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF10 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
15VF9MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF9 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
14VF8MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF8 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
13VF7MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF7 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
12VF6MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF6 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
11VF5MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF5 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
10VF4MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF4 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
9VF3MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF3 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
8VF2MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF2 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
7VF1MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF1 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
6VF0MSIXMSKCLSTR/W1C0hEach VF has a
1-bit MSIX Function Mask.

This status bit is set when the VF0 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
5PF5MSIXMSKCLSTR/W1C0hEach PF has a
1-bit MSIX Function Mask.

This status bit is set when the PF5 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
4PF4MSIXMSKCLSTR/W1C0hEach PF has a
1-bit MSIX Function Mask.

This status bit is set when the PF4 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
3PF3MSIXMSKCLSTR/W1C0hEach PF has a
1-bit MSIX Function Mask.

This status bit is set when the PF3 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
2PF2MSIXMSKCLSTR/W1C0hEach PF has a
1-bit MSIX Function Mask.

This status bit is set when the PF2 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
1PF1MSIXMSKCLSTR/W1C0hEach PF has a
1-bit MSIX Function Mask.

This status bit is set when the PF1 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
0PF0MSIXMSKCLSTR/W1C0hEach PF has a
1-bit MSIX Function Mask.

This status bit is set when the PF0 MSIX Function Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW.
This bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg.
When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg .
Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.

3.5.4.125 PCIE_CORE_LM_I_LD_CTRL Register (Offset = 00100DA0h) [reset = 015F5E10h]

PCIE_CORE_LM_I_LD_CTRL is shown in Figure 12-1717 and described in Table 12-3378.

Return to the Summary Table.

This register is for the control of Link Down Indication Auto Reset behavior

Table 12-3377 PCIE_CORE_LM_I_LD_CTRL Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DA0h
Figure 12-1717 PCIE_CORE_LM_I_LD_CTRL Register
3130292827262524
R7AUTO_EN
R-0hR/W-1h
2322212019181716
LDTIMER
R/W-005F5E10h
15141312111098
LDTIMER
R/W-005F5E10h
76543210
LDTIMER
R/W-005F5E10h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3378 PCIE_CORE_LM_I_LD_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-25R7R0hReserved
24AUTO_ENR/W1hThis bit when set indicates that the link down indication auto reset is enabled
23-0LDTIMERR/W005F5E10hThis is a counter timeout value which triggers the internal logic to reset the link down indication bit in the AXI Configuration registers

3.5.4.126 PCIE_CORE_LM_RX_ELEC_IDLE_FILTER_CONTROL Register (Offset = 00100DA4h) [reset = 04200000h]

PCIE_CORE_LM_RX_ELEC_IDLE_FILTER_CONTROL is shown in Figure 12-1718 and described in Table 12-3380.

Return to the Summary Table.

This register controls the behavior of glitch filter on the pipe rx Electrical Idle
signal from the PHY/PCS. Adjustment of this register is not required for normal operations.

Table 12-3379 PCIE_CORE_LM_RX_ELEC_IDLE_FILTER_CONTROL Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DA4h
Figure 12-1718 PCIE_CORE_LM_RX_ELEC_IDLE_FILTER_CONTROL Register
31302928272625242322212019181716
GFLCPGFLCC
R/W-4hR/W-20h
1514131211109876543210
RSVGFLDGFLD
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3380 PCIE_CORE_LM_RX_ELEC_IDLE_FILTER_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
31-24GFLCPR/W4hThis controls the glitch filter on PM Clock domain.
This counter indicates the number of PM Clocks the glitch will be filtered out.
The
total delay of the glitch filter is calculated as [PM Clock Period * Number of PM Clocks] this
delay should be same or close enough for both Core Clock[GFLCC] and PM Clock[GFLCP]
23-16GFLCCR/W20hThis controls the glitch filter on CORE Clock domain.
This counter indicates the number of CORE Clocks the glitch will be filtered out.
The
total delay of the glitch filter is calculated as [CORE Clock Period * Number of CORE Clocks] this
delay should be same or close enough for both CORE Clock[GFLCC] and PM Clock[GFLCP]
15-4RSVGFLDR0hReserved
3-0GFLDR/W0hBy default controller enables glitch filter on all lanes.
Setting this bit to one makes the controller to disable the glitch filter on that
corresponding lanes in which the bit is set.
When all bits are set to one the Glitch filter is completely bypassed,
When any bit is zero glitch filter is enabled, and de-glitching is done only on the lanes that are set to zero

3.5.4.127 PCIE_CORE_LM_I_PTM_LOCAL_CONTROL_REG Register (Offset = 00100DA8h) [reset = 1110h]

PCIE_CORE_LM_I_PTM_LOCAL_CONTROL_REG is shown in Figure 12-1719 and described in Table 12-3382.

Return to the Summary Table.

The register bits to Control PTM operation are implemented in this Register.

Table 12-3381 PCIE_CORE_LM_I_PTM_LOCAL_CONTROL_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DA8h
Figure 12-1719 PCIE_CORE_LM_I_PTM_LOCAL_CONTROL_REG Register
3130292827262524
RES29DAINVCNTINVPTMCNTRES18
R-0hR/W-0hW-0hR-0h
2322212019181716
RES18PTMRSENPTMRSM
R-0hR/W-0hR/W-0h
15141312111098
PTMRINTPTMRFRVL
R/W-1hR/W-1h
76543210
PTMRFRSCRES2PTMRQENPTMRQM
R/W-1hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3382 PCIE_CORE_LM_I_PTM_LOCAL_CONTROL_REG Register Field Descriptions
BitFieldTypeResetDescription
31-29RES29R0hReserved
28DAINVCNTR/W0hBy default, the Controller automatically invalidates PTM Context when the LTSSM
exits L0 state.
Client may disable this by writing a 1 to this register.
27INVPTMCNTW0hClient Firmware may write a 1 to this bit in order to reset the PTM Context.
This is a write-only bit.
Controller internally clears this bit.
Read from this bit returns 0.
EP Mode:
Resets the PTM Request State Machine.
PTM Context is Cleared.

RP Mode:
Resets the PTM Response State Machine.
PTM Context is Cleared.
26-18RES18R0hReserved
17PTMRSENR/W0h
EP Mode:
Reserved

RP Mode:
This bit enables Controller [RP] to respond to the received PTM Requests.
PTM Response/PTM ResponseD is determined by the PTM Response Mode bit.


1 : Controller automatically responds with Response/ResponseD messages.


0 : Controller does not respond for PTM Requests.
[PTM Feature is Bypassed.]

16PTMRSMR/W0h
EP Mode:
Reserved.

RP Mode:
This bit is used to control the number of PTM dialogs used during each PTM Master Time Request.

1 : Two Dialog Mode -
Each PTM Context will have Response followed by ResponseD.
Example:
Dialog
0:
Request -> Response.
Dialog
1:
Request -> ResponseD
Dialog
2:
Request -> Response
Dialog
3:
Request -> ResponseD


0 : Continuous Dialog Mode - Each PTM Context will have Only ResponseD.
Example:
Dialog
0:
Request -> Response.
Dialog
1:
Request -> ResponseD
Dialog
2:
Request -> ResponseD
Dialog
3:
Request -> ResponseD

15-12PTMRINTR/W1h
EP Mode:
In Single,Periodic Request Mode, this field is used to control the time interval [in us] between PTM Requests within a PTM Context.

This represents the time the Requester State Machine waits in the WAIT_1US_STATE.

0001 - 1

0010 - 2

0011 - 3

0100 - 4

0101 - 5

0110 - 6

0111 - 7

1000 - 8

1001 - 9
..

1111 - 15
This value is in [us].

RP Mode:
Reserved.

11-8PTMRFRVLR/W1h
EP Mode:
In Periodic Request Mode, this field is used to control the time interval [value] between successive PTM Context Refresh.
This represents the time the Requester State Machine waits in the VALID_PTM_CONTEXT_STATE.

0001 - 1

0010 - 2

0011 - 3

0100 - 4

0101 - 5

0110 - 6

0111 - 7

1000 - 8

1001 - 9

1010 - 1111 Reserved
This value is multiplied with the scale to determine the PTM Request Time Interval.

RP Mode:
Reserved.

7-4PTMRFRSCR/W1h
EP Mode:
In Periodic Request Mode, this field is used to control the time interval [scale] between successive PTM Context Refresh.
This represents the time the Requester State Machine waits in the VALID_PTM_CONTEXT_STATE.

0000 - 1 us

0001 - 10 us

0010 - 100 us

0011 - 1 ms

0100 - 10 ms

0101 - 100 ms

0110 - 1 s

0111 - 10 s

1000 - 100 s

1001 -
1111 - Reserved

RP Mode:
Reserved.
3-2RES2R0hReserved
1PTMRQENR/W0h
EP Mode:
This enables Endpoint to request for PTM Master Time.

1 : PTM Requests are Enabled.
In Single Request Mode, this bit is used to trigger PTM dialog to obtain PTM Master time exactly once.
This bit is auto-cleared after the PTM Master time is obtained.

In Periodic Request Mode, this bit enables periodic requests for PTM Master Time.
This bit remains set till it is cleared by the EP local firmware.


0 : PTM Requests are Disabled.
[PTM Feature is Bypassed.]
User may disable PTM requests in the Controller and, if required, generate requests from Client Master Interface.

RP Mode:
Reserved.
0PTMRQMR/W0hEP Mode:
This bit controls the pattern of PTM Requests issued by the Endpoint.

0: Single Request Mode.

1: Periodic Request Mode.

In Single Request Mode, Endpoint initiates one or two PTM Dialogs till the PTM Master Time is obtained.

In Periodic Request Mode, Endpoint initiates PTM Dialogs and obtains PTM Master at periodic intervals.
The period is programmable.

RP Mode:
Reserved.

3.5.4.128 PCIE_CORE_LM_I_PTM_LOCAL_STATUS_REG Register (Offset = 00100DACh) [reset = 0h]

PCIE_CORE_LM_I_PTM_LOCAL_STATUS_REG is shown in Figure 12-1720 and described in Table 12-3384.

Return to the Summary Table.

The status of PTM Dialog is reflected in this Register.

Table 12-3383 PCIE_CORE_LM_I_PTM_LOCAL_STATUS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DACh
Figure 12-1720 PCIE_CORE_LM_I_PTM_LOCAL_STATUS_REG Register
31302928272625242322212019181716
RES3
R-0h
1514131211109876543210
RES3PTMCNST
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3384 PCIE_CORE_LM_I_PTM_LOCAL_STATUS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-4RES3R0hReserved
3-0PTMCNSTR0h
Reflects the current status of the PTM Context.

In EP Mode:

0000 - Invalid PTM Context

0001 - Dialog 1 PTM Request Sent

0011 - Dialog 1 PTM Response Received

0111 - Dialog 2 PTM Request Sent

1111 - Dialog 2 PTM ResponseD Received and PTM Context Valid

In RP Mode:

0000 - Invalid PTM Context

0001 - Dialog 1 PTM Request Received

0011 - Dialog 1 PTM Response Sent

0111 - Dialog 2 PTM Request Received

1111 - Dialog 2 PTM ResponseD Sent and PTM Context Valid

3.5.4.129 PCIE_CORE_LM_I_PTM_LATENCY_PARAMETERS_INDEX_REG Register (Offset = 00100DB0h) [reset = 0h]

PCIE_CORE_LM_I_PTM_LATENCY_PARAMETERS_INDEX_REG is shown in Figure 12-1721 and described in Table 12-3386.

Return to the Summary Table.

The latency parameters of the PHY may be different at different speeds of operation.
Hence, the Controller implements multiple instances of the PTM Latency Parameters Register, one instance for each speed of operation.
This register is used to select the speed prior to programming the speed-specific delay parameter registers.

Table 12-3385 PCIE_CORE_LM_I_PTM_LATENCY_PARAMETERS_INDEX_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DB0h
Figure 12-1721 PCIE_CORE_LM_I_PTM_LATENCY_PARAMETERS_INDEX_REG Register
31302928272625242322212019181716
RES4
R-0h
1514131211109876543210
RES4PTMLATIN
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3386 PCIE_CORE_LM_I_PTM_LATENCY_PARAMETERS_INDEX_REG Register Field Descriptions
BitFieldTypeResetDescription
31-4RES4R0hReserved
3-0PTMLATINR/W0h
This is used by FW to select the speed for which the Latency parameters are to be programmed.

FW is required to set this to each of the supported speeds and program the corresponding latency parameters in the PTM Latency Parameters Register.

0000 - Gen1 Speed Select

0001 - Gen2 Speed Select

0010 - Gen3 Speed Select

0011 - Gen4 Speed Select
Others - Reserved

3.5.4.130 PCIE_CORE_LM_I_PTM_LATENCY_PARAMETERS_REG Register (Offset = 00100DB4h) [reset = 0h]

PCIE_CORE_LM_I_PTM_LATENCY_PARAMETERS_REG is shown in Figure 12-1722 and described in Table 12-3388.

Return to the Summary Table.

This register is used to define the PHY specific delay parameters.
This register also implements control bits to fine-tune timestamps that are captured by the Controller.
Internally, one instance of this register is implemented for each of the speeds supported by the Controller and is indexed by the PTM Latency Parameters Index Register.

Table 12-3387 PCIE_CORE_LM_I_PTM_LATENCY_PARAMETERS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DB4h
Figure 12-1722 PCIE_CORE_LM_I_PTM_LATENCY_PARAMETERS_REG Register
31302928272625242322212019181716
RXDLTUNTXDLTUNRES20PTMRXLAT
R/W-0hR/W-0hR-0hR/W-0h
1514131211109876543210
PTMRXLATPTMTXLAT
R/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3388 PCIE_CORE_LM_I_PTM_LATENCY_PARAMETERS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-28RXDLTUNR/W0h
In EP Mode:
This field can be used to add a fixed offset to the captured timestamps t4 and t4_tick.

In RP Mode:
This field can be used to add a fixed offset to the captured timestamps t2 and t2_tick.

Encoding:

0000: + 0 ns

0001: + 1ns

0010: + 2ns
....

1111: + 15ns

Separate value can be programmed for each supported speed of operation.
The speed of operation must first be programmed in the PTM Latency Parameters Index Register and then the corresponding value be programmed into this register.

27-24TXDLTUNR/W0h
In EP Mode:
This field can be used to add a fixed offset to the captured timestamps t1 and t1_tick.

In RP Mode:
This field can be used to add a fixed offset to the captured timestamps t3 and t3_tick.

Encoding:

0000: + 0 ns

0001: + 1ns

0010: + 2ns
....

1111: + 15ns

Separate value can be programmed for each supported speed of operation.
The speed of operation must first be programmed in the PTM Latency Parameters Index Register and then the corresponding value be programmed into this register.

23-20RES20R0hReserved
19-10PTMRXLATR/W0hThis field should be programmed with the parameter Receive Latency in [ns] from the PHY Datasheet.
Separate value can be programmed for each supported speed of operation.
The speed of operation must first be programmed in the PTM Latency Parameters Index Register and then the corresponding latency be programmed into this register.
9-0PTMTXLATR/W0hThis field should be programmed with the parameter Transmit Latency in [ns] from the PHY Datasheet.
Separate value can be programmed for each supported speed of operation.
The speed of operation must first be programmed in the PTM Latency Parameters Index Register and then the corresponding latency be programmed into this register.

3.5.4.131 PCIE_CORE_LM_I_PTM_CONTEXT_1_REG Register (Offset = 00100DB8h) [reset = 0h]

PCIE_CORE_LM_I_PTM_CONTEXT_1_REG is shown in Figure 12-1723 and described in Table 12-3390.

Return to the Summary Table.

PTM Context 1 Register.

Table 12-3389 PCIE_CORE_LM_I_PTM_CONTEXT_1_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DB8h
Figure 12-1723 PCIE_CORE_LM_I_PTM_CONTEXT_1_REG Register
313029282726252423222120191817161514131211109876543210
PTMT1T2
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3390 PCIE_CORE_LM_I_PTM_CONTEXT_1_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0PTMT1T2R0h
EP Mode : Represents the lower 32-bits of timestamp t1 in [ns] as recorded by Endpoint.

RP Mode : Represents the lower 32-bits of timestamp t2 in [ns] as recorded by RP.

3.5.4.132 PCIE_CORE_LM_I_PTM_CONTEXT_2_REG Register (Offset = 00100DBCh) [reset = 0h]

PCIE_CORE_LM_I_PTM_CONTEXT_2_REG is shown in Figure 12-1724 and described in Table 12-3392.

Return to the Summary Table.

PTM Context 2 Register.

Table 12-3391 PCIE_CORE_LM_I_PTM_CONTEXT_2_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DBCh
Figure 12-1724 PCIE_CORE_LM_I_PTM_CONTEXT_2_REG Register
313029282726252423222120191817161514131211109876543210
PTMT1T2U
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3392 PCIE_CORE_LM_I_PTM_CONTEXT_2_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0PTMT1T2UR0h
EP Mode : Represents the upper 32-bits of timestamp t1 in [ns] as recorded by Endpoint.

RP Mode : Represents the upper 32-bits of timestamp t2 in [ns] as recorded by RP.

3.5.4.133 PCIE_CORE_LM_I_PTM_CONTEXT_3_REG Register (Offset = 00100DC0h) [reset = 0h]

PCIE_CORE_LM_I_PTM_CONTEXT_3_REG is shown in Figure 12-1725 and described in Table 12-3394.

Return to the Summary Table.

PTM Context 3 Register.

Table 12-3393 PCIE_CORE_LM_I_PTM_CONTEXT_3_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DC0h
Figure 12-1725 PCIE_CORE_LM_I_PTM_CONTEXT_3_REG Register
313029282726252423222120191817161514131211109876543210
PTMT4T3
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3394 PCIE_CORE_LM_I_PTM_CONTEXT_3_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0PTMT4T3R0h
EP Mode : Represents the lower 32-bits of timestamp t4 in [ns] as recorded by Endpoint.

RP Mode : Represents the lower 32-bits of timestamp t3 in [ns] as recorded by RP.

3.5.4.134 PCIE_CORE_LM_I_PTM_CONTEXT_4_REG Register (Offset = 00100DC4h) [reset = 0h]

PCIE_CORE_LM_I_PTM_CONTEXT_4_REG is shown in Figure 12-1726 and described in Table 12-3396.

Return to the Summary Table.

PTM Context 4 Register.

Table 12-3395 PCIE_CORE_LM_I_PTM_CONTEXT_4_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DC4h
Figure 12-1726 PCIE_CORE_LM_I_PTM_CONTEXT_4_REG Register
313029282726252423222120191817161514131211109876543210
PTMT4T3U
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3396 PCIE_CORE_LM_I_PTM_CONTEXT_4_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0PTMT4T3UR0h
EP Mode : Represents the upper 32-bits of timestamp t4 in [ns] as recorded by Endpoint.

RP Mode : Represents the upper 32-bits of timestamp t3 in [ns] as recorded by RP.

3.5.4.135 PCIE_CORE_LM_I_PTM_CONTEXT_5_REG Register (Offset = 00100DC8h) [reset = 0h]

PCIE_CORE_LM_I_PTM_CONTEXT_5_REG is shown in Figure 12-1727 and described in Table 12-3398.

Return to the Summary Table.

PTM Context 5 Register.

Table 12-3397 PCIE_CORE_LM_I_PTM_CONTEXT_5_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DC8h
Figure 12-1727 PCIE_CORE_LM_I_PTM_CONTEXT_5_REG Register
313029282726252423222120191817161514131211109876543210
PTMT1KT2K
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3398 PCIE_CORE_LM_I_PTM_CONTEXT_5_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0PTMT1KT2KR0h
EP Mode : Represents the lower 32-bits of timestamp t1_tick in [ns] as recorded by Endpoint.

RP Mode : Represents the lower 32-bits of timestamp t2_tick in [ns] as recorded by RP.

3.5.4.136 PCIE_CORE_LM_I_PTM_CONTEXT_6_REG Register (Offset = 00100DCCh) [reset = 0h]

PCIE_CORE_LM_I_PTM_CONTEXT_6_REG is shown in Figure 12-1728 and described in Table 12-3400.

Return to the Summary Table.

PTM Context 6 Register.

Table 12-3399 PCIE_CORE_LM_I_PTM_CONTEXT_6_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DCCh
Figure 12-1728 PCIE_CORE_LM_I_PTM_CONTEXT_6_REG Register
313029282726252423222120191817161514131211109876543210
PTMT1KT2KU
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3400 PCIE_CORE_LM_I_PTM_CONTEXT_6_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0PTMT1KT2KUR0h
EP Mode : Represents the upper 32-bits of timestamp t1_tick in [ns] as recorded by Endpoint.

RP Mode : Represents the upper 32-bits of timestamp t2_tick in [ns] as recorded by RP.

3.5.4.137 PCIE_CORE_LM_I_PTM_CONTEXT_7_REG Register (Offset = 00100DD0h) [reset = 0h]

PCIE_CORE_LM_I_PTM_CONTEXT_7_REG is shown in Figure 12-1729 and described in Table 12-3402.

Return to the Summary Table.

PTM Context 7 Register.

Table 12-3401 PCIE_CORE_LM_I_PTM_CONTEXT_7_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DD0h
Figure 12-1729 PCIE_CORE_LM_I_PTM_CONTEXT_7_REG Register
313029282726252423222120191817161514131211109876543210
PTMT4KT3K
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3402 PCIE_CORE_LM_I_PTM_CONTEXT_7_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0PTMT4KT3KR0h
EP Mode : Represents the lower 32-bits of timestamp t4_tick in [ns] as recorded by Endpoint.

RP Mode : Represents the lower 32-bits of timestamp t3_tick in [ns] as recorded by RP.

3.5.4.138 PCIE_CORE_LM_I_PTM_CONTEXT_8_REG Register (Offset = 00100DD4h) [reset = 0h]

PCIE_CORE_LM_I_PTM_CONTEXT_8_REG is shown in Figure 12-1730 and described in Table 12-3404.

Return to the Summary Table.

PTM Context 8 Register.

Table 12-3403 PCIE_CORE_LM_I_PTM_CONTEXT_8_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DD4h
Figure 12-1730 PCIE_CORE_LM_I_PTM_CONTEXT_8_REG Register
313029282726252423222120191817161514131211109876543210
PTMT4KT3KU
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3404 PCIE_CORE_LM_I_PTM_CONTEXT_8_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0PTMT4KT3KUR0h
EP Mode : Represents the upper 32-bits of timestamp t4_tick in [ns] as recorded by Endpoint.

RP Mode : Represents the upper 32-bits of timestamp t3_tick in [ns] as recorded by RP.

3.5.4.139 PCIE_CORE_LM_I_PTM_CONTEXT_9_REG Register (Offset = 00100DD8h) [reset = 0h]

PCIE_CORE_LM_I_PTM_CONTEXT_9_REG is shown in Figure 12-1731 and described in Table 12-3406.

Return to the Summary Table.

PTM Context 9 Register.

Table 12-3405 PCIE_CORE_LM_I_PTM_CONTEXT_9_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DD8h
Figure 12-1731 PCIE_CORE_LM_I_PTM_CONTEXT_9_REG Register
313029282726252423222120191817161514131211109876543210
PTMT3MT2
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3406 PCIE_CORE_LM_I_PTM_CONTEXT_9_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0PTMT3MT2R0h
Propagation Delay.

EP Mode : Represents the Propagation Delay [t3 - t2] in [ns] as received in ResponseD Message by Endpoint.

RP Mode - Reserved.

3.5.4.140 PCIE_CORE_LM_I_PTM_CONTEXT_10_REG Register (Offset = 00100DDCh) [reset = 0h]

PCIE_CORE_LM_I_PTM_CONTEXT_10_REG is shown in Figure 12-1732 and described in Table 12-3408.

Return to the Summary Table.

PTM Context 10 Register.

Table 12-3407 PCIE_CORE_LM_I_PTM_CONTEXT_10_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DDCh
Figure 12-1732 PCIE_CORE_LM_I_PTM_CONTEXT_10_REG Register
313029282726252423222120191817161514131211109876543210
PTMMSTT1T
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3408 PCIE_CORE_LM_I_PTM_CONTEXT_10_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0PTMMSTT1TR0h
EP Mode - Represents the lower 32-bits of PTM Master Time at timestamp t1_tick in [ns] as computed by Endpoint.

RP Mode - Reserved.

3.5.4.141 PCIE_CORE_LM_I_PTM_CONTEXT_11_REG Register (Offset = 00100DE0h) [reset = 0h]

PCIE_CORE_LM_I_PTM_CONTEXT_11_REG is shown in Figure 12-1733 and described in Table 12-3410.

Return to the Summary Table.

PTM Context 11 Register.

Table 12-3409 PCIE_CORE_LM_I_PTM_CONTEXT_11_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DE0h
Figure 12-1733 PCIE_CORE_LM_I_PTM_CONTEXT_11_REG Register
313029282726252423222120191817161514131211109876543210
PTMMSTT1TU
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3410 PCIE_CORE_LM_I_PTM_CONTEXT_11_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0PTMMSTT1TUR0h
EP Mode - Represents the upper 32-bits of PTM Master Time at timestamp t1_tick in [ns] as computed by Endpoint.

RP Mode - Reserved.

3.5.4.142 PCIE_CORE_LM_I_ASF_INTRPT_STATUS Register (Offset = 00100DECh) [reset = 0h]

PCIE_CORE_LM_I_ASF_INTRPT_STATUS is shown in Figure 12-1734 and described in Table 12-3412.

Return to the Summary Table.

This register indicates the source of ASF interrupts. The corresponding bit in the mask
register must be clear for a bit to be set. If any bit is set in this register the asf_fatal or
asf_nonfatal signal will be asserted. Writing to either raw or masked status registers, clear both
registers. For test purposes, trigger signal interrupt event by writing to the ASF interrupt status
test register.

Table 12-3411 PCIE_CORE_LM_I_ASF_INTRPT_STATUS Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DECh
Figure 12-1734 PCIE_CORE_LM_I_ASF_INTRPT_STATUS Register
3130292827262524
R31
R-0h
2322212019181716
R31
R-0h
15141312111098
R31
R-0h
76543210
R31INTEGRERPROTERTRANSTOERCSRERDAPERSRUCORERSRCORER
R-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3412 PCIE_CORE_LM_I_ASF_INTRPT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-7R31R0hReserved
6INTEGRERR/W1C0hIntegrity error interrupt
5PROTERR/W1C0hProtocol error interrupt
4TRANSTOERR/W1C0hTransaction timeouts interrupt
3CSRERR/W1C0hConfiguration and status registers error interrupt
2DAPERR/W1C0hData and address paths error interrupt
1SRUCORERR/W1C0hSRAM Uncorrectable error interrupt
0SRCORERR/W1C0hSRAM Correctable error interrupt

3.5.4.143 PCIE_CORE_LM_I_ASF_INTRPT_RAW_STATUS Register (Offset = 00100DF0h) [reset = 0h]

PCIE_CORE_LM_I_ASF_INTRPT_RAW_STATUS is shown in Figure 12-1735 and described in Table 12-3414.

Return to the Summary Table.

A bit set in this raw register indicates a source of ASF fault in the corresponding feature.
Writing to either raw or masked status registers, clear both registers. For test purposes, trigger
signal interrupt event by writing to the ASF interrrupt status test register.

Table 12-3413 PCIE_CORE_LM_I_ASF_INTRPT_RAW_STATUS Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DF0h
Figure 12-1735 PCIE_CORE_LM_I_ASF_INTRPT_RAW_STATUS Register
3130292827262524
R31
R-0h
2322212019181716
R31
R-0h
15141312111098
R31
R-0h
76543210
R31INTEGRERPROTERTRANSTOERCSRERDAPERSRUCORERSRCORER
R-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3414 PCIE_CORE_LM_I_ASF_INTRPT_RAW_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-7R31R0hReserved
6INTEGRERR/W1C0hIntegrity error interrupt
5PROTERR/W1C0hProtocol error interrupt
4TRANSTOERR/W1C0hTransaction timeouts interrupt
3CSRERR/W1C0hConfiguration and status registers error interrupt
2DAPERR/W1C0hData and address paths error interrupt
1SRUCORERR/W1C0hSRAM Uncorrectable error interrupt
0SRCORERR/W1C0hSRAM Correctable error interrupt

3.5.4.144 PCIE_CORE_LM_I_ASF_INTRPT_MASK_REG Register (Offset = 00100DF4h) [reset = 3Fh]

PCIE_CORE_LM_I_ASF_INTRPT_MASK_REG is shown in Figure 12-1736 and described in Table 12-3416.

Return to the Summary Table.

This Register indicates which interrupt bits in the ASF interrupt status register are masked.
Setting the individual bit to zero would enable the corresponding interrupt. This register does not affect
the raw interrupt status register

Table 12-3415 PCIE_CORE_LM_I_ASF_INTRPT_MASK_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DF4h
Figure 12-1736 PCIE_CORE_LM_I_ASF_INTRPT_MASK_REG Register
3130292827262524
R31
R-0h
2322212019181716
R31
R-0h
15141312111098
R31
R-0h
76543210
R31INTEGRERMPROTERMTRANTOEMCSRERMDAPERMSRUCORERMSRCORERM
R-0hR/W-0hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3416 PCIE_CORE_LM_I_ASF_INTRPT_MASK_REG Register Field Descriptions
BitFieldTypeResetDescription
31-7R31R0hReserved
6INTEGRERMR/W0hMask bit for Integrity error interrupt
5PROTERMR/W1hMask bit for Protocol error interrupt
4TRANTOEMR/W1hMask bit for Transaction timeouts interrupt
3CSRERMR/W1hMask bit for Configuration and status registers error interrupt
2DAPERMR/W1hMask bit for Data and address paths error interrupt
1SRUCORERMR/W1hMask bit for SRAM Uncorrectable error interrupt
0SRCORERMR/W1hMask bit for SRAM Correctable error interrupt

3.5.4.145 PCIE_CORE_LM_I_ASF_INTRPT_TEST Register (Offset = 00100DF8h) [reset = 0h]

PCIE_CORE_LM_I_ASF_INTRPT_TEST is shown in Figure 12-1737 and described in Table 12-3418.

Return to the Summary Table.

Writing one to individual bits will trigger corresponding interrupt event. The raw
interrupt status will be set and the masked interrupt status will be set if the
corresponding bit in the interrupt mask register is not set.

Table 12-3417 PCIE_CORE_LM_I_ASF_INTRPT_TEST Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DF8h
Figure 12-1737 PCIE_CORE_LM_I_ASF_INTRPT_TEST Register
3130292827262524
R31
R-0h
2322212019181716
R31
R-0h
15141312111098
R31
R-0h
76543210
R31INTEGRERTPROTERTTRANTOETCSRERTDAPERTSRUCORERTSRCORERT
R-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3418 PCIE_CORE_LM_I_ASF_INTRPT_TEST Register Field Descriptions
BitFieldTypeResetDescription
31-7R31R0hReserved
6INTEGRERTW0hTest bit for Integrity error interrupt
5PROTERTW0hTest bit for Protocol error interrupt
4TRANTOETW0hTest bit for Transaction timeouts interrupt
3CSRERTW0hTest bit for Configuration and status registers error interrupt
2DAPERTW0hTest bit for Data and address paths error interrupt
1SRUCORERTW0hTest bit for SRAM Uncorrectable error interrupt
0SRCORERTW0hTest bit for SRAM Correctable error interrupt

3.5.4.146 PCIE_CORE_LM_I_ASF_INTRPT_FATAL_NONFATAL_SEL Register (Offset = 00100DFCh) [reset = 3Fh]

PCIE_CORE_LM_I_ASF_INTRPT_FATAL_NONFATAL_SEL is shown in Figure 12-1738 and described in Table 12-3420.

Return to the Summary Table.

This register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is
triggered. For each select bit, if it is set to one then a fatal interrupt (asf_int_fatal) will
be triggered. Otherwise the non-fatal interrupt (asf_int_nonfatal) will be triggered. For either
a Fatal or Non Fatal Interrupt to be triggered , the corresponding mask bit of the error needs
to be zero.

Table 12-3419 PCIE_CORE_LM_I_ASF_INTRPT_FATAL_NONFATAL_SEL Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0DFCh
Figure 12-1738 PCIE_CORE_LM_I_ASF_INTRPT_FATAL_NONFATAL_SEL Register
3130292827262524
R31
R-0h
2322212019181716
R31
R-0h
15141312111098
R31
R-0h
76543210
R31INTEGRERSPROTERSTRANTOESCSRERSDAPERSSRUCORERSSRCORERS
R-0hR/W-0hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3420 PCIE_CORE_LM_I_ASF_INTRPT_FATAL_NONFATAL_SEL Register Field Descriptions
BitFieldTypeResetDescription
31-7R31R0hReserved
6INTEGRERSR/W0hEnable Integrity error as Fatal
5PROTERSR/W1hEnable protocol interrupt as fatal
4TRANTOESR/W1hEnable transaction timeouts interrupt as fatal
3CSRERSR/W1hEnable configuration and status registers interrupt as fatal
2DAPERSR/W1hEnable data and address paths interrupt as fatal
1SRUCORERSR/W1hEnable SRAM Uncorrectable interrupt as fatal
0SRCORERSR/W1hEnable SRAM correctable interrupt as fatal

3.5.4.147 PCIE_CORE_LM_I_ASF_SRAM_CORR_FAULT_STATUS Register (Offset = 00100E00h) [reset = 0h]

PCIE_CORE_LM_I_ASF_SRAM_CORR_FAULT_STATUS is shown in Figure 12-1739 and described in Table 12-3422.

Return to the Summary Table.

These fields are updated whenever asf_sram_corr_fault input is active

Table 12-3421 PCIE_CORE_LM_I_ASF_SRAM_CORR_FAULT_STATUS Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E00h
Figure 12-1739 PCIE_CORE_LM_I_ASF_SRAM_CORR_FAULT_STATUS Register
313029282726252423222120191817161514131211109876543210
SRCORFISRCORFADR
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3422 PCIE_CORE_LM_I_ASF_SRAM_CORR_FAULT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-24SRCORFIR0hThis ENCODING indicates which SRAM Instance has a Correctable Fault.
0x7: HP_AXI Interleave Buffer
0x6: HP_AXI Master FIFO Buffer
0x5: HP_AXI Slave FIFO Buffer
0x4: HP_AXI Slave Read Re-order Buffer
0x3: HP_Completion Buffer
0x2 - 0x1: Reserved
0x0: HP_PNP buffer
23-0SRCORFADRR0hThis indicates the address where the Correctable fault was observed.

3.5.4.148 PCIE_CORE_LM_I_ASF_SRAM_UNCORR_FAULT_STATUS Register (Offset = 00100E04h) [reset = 0h]

PCIE_CORE_LM_I_ASF_SRAM_UNCORR_FAULT_STATUS is shown in Figure 12-1740 and described in Table 12-3424.

Return to the Summary Table.

These fields are updated whenever asf_sram_uncorr_fault input is active

Table 12-3423 PCIE_CORE_LM_I_ASF_SRAM_UNCORR_FAULT_STATUS Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E04h
Figure 12-1740 PCIE_CORE_LM_I_ASF_SRAM_UNCORR_FAULT_STATUS Register
313029282726252423222120191817161514131211109876543210
SRUCORFISRUCRFADR
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-3424 PCIE_CORE_LM_I_ASF_SRAM_UNCORR_FAULT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-24SRUCORFIR0hThis ENCODING indicates which SRAM Instance has a Uncorrectable Fault.

The Encoding of the SRAM is shown in Table 26
23-0SRUCRFADRR0hThis indicates the address where the Uncorrectable fault was observed.

3.5.4.149 PCIE_CORE_LM_I_ASF_SRAM_FAULT_STATSTICS Register (Offset = 00100E08h) [reset = 0h]

PCIE_CORE_LM_I_ASF_SRAM_FAULT_STATSTICS is shown in Figure 12-1741 and described in Table 12-3426.

Return to the Summary Table.

Note that this register clears when software writes to any field

Table 12-3425 PCIE_CORE_LM_I_ASF_SRAM_FAULT_STATSTICS Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E08h
Figure 12-1741 PCIE_CORE_LM_I_ASF_SRAM_FAULT_STATSTICS Register
313029282726252423222120191817161514131211109876543210
SRUCORFSSRCORFS
R/W1C-0hR/W1C-0h
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3426 PCIE_CORE_LM_I_ASF_SRAM_FAULT_STATSTICS Register Field Descriptions
BitFieldTypeResetDescription
31-16SRUCORFSR/W1C0hCounts the number of SRAM Uncorrectable errors seen.
15-0SRCORFSR/W1C0hCounts the number of SRAM Correctable errors seen.

3.5.4.150 PCIE_CORE_LM_I_ASF_TRANS_TO_CTRL Register (Offset = 00100E0Ch) [reset = 0h]

PCIE_CORE_LM_I_ASF_TRANS_TO_CTRL is shown in Figure 12-1742 and described in Table 12-3428.

Return to the Summary Table.

Register to program Transaction timeout in monitor and enable it

Table 12-3427 PCIE_CORE_LM_I_ASF_TRANS_TO_CTRL Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E0Ch
Figure 12-1742 PCIE_CORE_LM_I_ASF_TRANS_TO_CTRL Register
3130292827262524
TRTOENR1
R/W-0hR-0h
2322212019181716
R1
R-0h
15141312111098
TRTOCTRL
R/W-0h
76543210
TRTOCTRL
R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3428 PCIE_CORE_LM_I_ASF_TRANS_TO_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31TRTOENR/W0hEnable transaction timeout monitoring.
30-16R1R0hReserved
15-0TRTOCTRLR/W0hTimer value to use for transaction timeout monitor.This is counted
in resolution of 1 ms.

3.5.4.151 PCIE_CORE_LM_I_ASF_TRANS_TO_FAULT_MASK Register (Offset = 00100E10h) [reset = 0h]

PCIE_CORE_LM_I_ASF_TRANS_TO_FAULT_MASK is shown in Figure 12-1743 and described in Table 12-3430.

Return to the Summary Table.

Disables the Timeout Completion Reporting

Table 12-3429 PCIE_CORE_LM_I_ASF_TRANS_TO_FAULT_MASK Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E10h
Figure 12-1743 PCIE_CORE_LM_I_ASF_TRANS_TO_FAULT_MASK Register
3130292827262524
R31
R-0h
2322212019181716
R31
R-0h
15141312111098
R5DTIDTOMDTIUTOMAPBTOMLMITOM
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
AXSLTOMAXMSTOMHLTGTOMHLMSTOMLRESPDTOMLCFLWSTOMLTPLCFTOMPCOMTOM
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3430 PCIE_CORE_LM_I_ASF_TRANS_TO_FAULT_MASK Register Field Descriptions
BitFieldTypeResetDescription
31-16R31R0hReserved
15-12R5R0hRESERVED
11DTIDTOMR/W0hWhen written to 1 Disables DTI DN I/F timeout Reporting Error status reporting
10DTIUTOMR/W0hWhen written to 1 Disables DTI UP I/F timeout Reporting Error status reporting
9APBTOMR/W0hWhen written to 1 Disables APB I/F timeout Error status reporting
8LMITOMR/W0hWhen written to 1 Disables Local Management I/F timeout Error status reporting
7AXSLTOMR/W0hWhen written to 1 Disables AXI Slave I/F timeout Error status reporting
6AXMSTOMR/W0hWhen written to 1 Disables AXI Target I/F timeout Error status reporting
5HLTGTOMR/W0hWhen written to 1 Disables HAL Target I/F timeout Error status reporting
4HLMSTOMR/W0hWhen written to 1 Disables HAL Master I/F timeout Error status reporting
3LRESPDTOMR/W0hWhen written to 1 Disables LTSSM Recovery Speed Timeout Error status reporting
2LCFLWSTOMR/W0hWhen written to 1 Disables LTSSM Cfg Link Width Start Timeout Error status reporting
1LTPLCFTOMR/W0hWhen written to 1 Disables LTSSM Polling Configuration Timeout Error status reporting
0PCOMTOMR/W0hWhen written to 1 Disables PCIe Completion Timeout Error status reporting

3.5.4.152 PCIE_CORE_LM_I_ASF_TRANS_TO_FAULT_STATUS Register (Offset = 00100E14h) [reset = 0h]

PCIE_CORE_LM_I_ASF_TRANS_TO_FAULT_STATUS is shown in Figure 12-1744 and described in Table 12-3432.

Return to the Summary Table.

If a fault occurs the relevant status bit will be set to 1. Each bit can
be cleared by software writing 1 to each bit

Table 12-3431 PCIE_CORE_LM_I_ASF_TRANS_TO_FAULT_STATUS Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E14h
Figure 12-1744 PCIE_CORE_LM_I_ASF_TRANS_TO_FAULT_STATUS Register
3130292827262524
R31
R-0h
2322212019181716
R31
R-0h
15141312111098
R5DTIDTODTIUTOAPBTOMLMITO
R-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
AXSLTOAXMSTOHLTGTOHLMSTOLRESPDTOLCFLWSTOLTPLCFTOPCOMTO
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3432 PCIE_CORE_LM_I_ASF_TRANS_TO_FAULT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-16R31R0hReserved
15-12R5R0hRESERVED
11DTIDTOR/W1C0hDTI DN I/F Timeout detected waiting for a response from User
10DTIUTOR/W1C0hDTI UP I/F Timeout detected waiting for a response from User
9APBTOMR/W1C0hAPB I/F Timeout detected waiting for a response from User
8LMITOR/W1C0hLocal Management I/F Timeout detected waiting for a response from User
7AXSLTOR/W1C0hAXI Slave I/F Timeout detected waiting for a response
6AXMSTOR/W1C0hAXI Master I/F Timeout detected waiting for a response
5HLTGTOR/W1C0hHAL Target I/F Timeout detected waiting for a response
4HLMSTOR/W1C0hHAL Master I/F Timeout detected waiting for a response
3LRESPDTOR/W1C0hThis Indicates if the states of the LTSSM timed out .
48 ms timeout in Rec.Speed-> Detect
2LCFLWSTOR/W1C0hThis Indicates if the states of the LTSSM timed out .
24 ms Timeout observed in
Cfg.Link.Width.Start -> Detect
1LTPLCFTOR/W1C0hThis Indicates if the states of the LTSSM timed out .
48 ms Timeout observed
for Polling.Cfg-> Detect
0PCOMTOR/W1C0hThis indicates if a Non Posted requested did NOT receive any competition from
remote device with in the completion time specified

3.5.4.153 PCIE_CORE_LM_I_ASF_PROTOCOL_FAULT_MASK Register (Offset = 00100E18h) [reset = 0h]

PCIE_CORE_LM_I_ASF_PROTOCOL_FAULT_MASK is shown in Figure 12-1745 and described in Table 12-3434.

Return to the Summary Table.

This control register controls if a particular protocol error is disabled
from being used in the generation of the ASF Protocol Error.

Table 12-3433 PCIE_CORE_LM_I_ASF_PROTOCOL_FAULT_MASK Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E18h
Figure 12-1745 PCIE_CORE_LM_I_ASF_PROTOCOL_FAULT_MASK Register
3130292827262524
R2
R-0h
2322212019181716
R2
R-0h
15141312111098
AXISLDECMRPLTOMRPLROLMBADDLPMBADTLPMPHRCVERMUSPREQMECRCERRM
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
MALTLPEMRCVROVFLMUNCPLRCMCMPLABTMCPLTOMFCPROERMPOTLRCVMDLPROTM
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3434 PCIE_CORE_LM_I_ASF_PROTOCOL_FAULT_MASK Register Field Descriptions
BitFieldTypeResetDescription
31-16R2R0hRESERVED
15AXISLDECMR/W0hWhen set to 1 disables the AXI Slave/Decode Error status reporting
14RPLTOMR/W0hWhen set to 1 disables the Replay Timer Timeout status reporting
13RPLROLMR/W0hWhen set to 1 disables the Replay Number Rollover Detected status reporting
12BADDLPMR/W0hWhen set to 1 disables the Bad DLLP Detected status reporting
11BADTLPMR/W0hWhen set to 1 disables the Bad TLP Detected status reporting
10PHRCVERMR/W0hWhen set to 1 disables the PHY Receiver Error Detected status reporting
9USPREQMR/W0hWhen set to 1 disables the Unsupported Request Error status reporting
8ECRCERRMR/W0hWhen set to 1 disables the ECRC Error Detected status reporting
7MALTLPEMR/W0hWhen set to 1 disables the Malformed Error status reporting
6RCVROVFLMR/W0hWhen set to 1 disables the Receiver Overflow Error status reporting
5UNCPLRCMR/W0hWhen set to 1 disables the Unexpcted Completion status reporting
4CMPLABTMR/W0hWhen set to 1 disables the Completer Abort Error status reporting
3CPLTOMR/W0hWhen set to 1 disables the Completion Timeout status reporting
2FCPROERMR/W0hWhen set to 1 disables the Flow Control Protocol Error status reporting
1POTLRCVMR/W0hWhen set to 1 disables the Poisoned TLP received status reporting
0DLPROTMR/W0hWhen set to 1 disables the Data Link Layer Protocol Error status reporting

3.5.4.154 PCIE_CORE_LM_I_ASF_PROTOCOL_FAULT_STATUS_REG Register (Offset = 00100E1Ch) [reset = 0h]

PCIE_CORE_LM_I_ASF_PROTOCOL_FAULT_STATUS_REG is shown in Figure 12-1746 and described in Table 12-3436.

Return to the Summary Table.

This status register holds the different protocol errors observed by the IP.
This error is logged into this register if the corresponding bit in the ASF Protocol
Fault Mask Register is not masked.

Table 12-3435 PCIE_CORE_LM_I_ASF_PROTOCOL_FAULT_STATUS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E1Ch
Figure 12-1746 PCIE_CORE_LM_I_ASF_PROTOCOL_FAULT_STATUS_REG Register
3130292827262524
R2
R-0h
2322212019181716
R2
R-0h
15141312111098
AXISLVDECRPLTOMRPLROLBADDLPBADTLPMPHRCVERUSPREQECRCERR
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
MALTLPERRCVROVFLUNCMLRCVCMPLABTCPLTOFCPROERPOTLRCVDLPROT
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-3436 PCIE_CORE_LM_I_ASF_PROTOCOL_FAULT_STATUS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16R2R0hRESERVED
15AXISLVDECR/W1C0hThis bit is set when the AXI interface sends SLVERR or DECERR to the user
14RPLTOMR/W1C0hThis bit is set when the replay timer in the Data Link Layer of the Controller times out.
13RPLROLR/W1C0hThis bit is set when the replay count rolls over after three re transmissions of a
TLP at the Data Link Layer of the Controller.
12BADDLPR/W1C0hThis bit is set when an LCRC error is detected in a received DLLP
11BADTLPMR/W1C0hThis bit is set when an error is detected in a received TLP by the Data Link Layer of the Controller.
10PHRCVERR/W1C0hThis bit is set when an error is detected in the receive side of the Physical Layer of the Controller
9USPREQR/W1C0hThis bit is set when the Controller has received a request from the link that it does not support.
8ECRCERRR/W1C0hThis bit is set when the Controller has detected an ECRC error in a received TLP
7MALTLPERR/W1C0hThis bit is set when the Controller receives a malformed TLP from the link.
6RCVROVFLR/W1C0hThis bit is set when the Controller receives a TLP in violation of the receive credit currently available.
5UNCMLRCVR/W1C0hThis bit is set when the Controller has received an unexpected Completion packet from the link
4CMPLABTR/W1C0hThis bit is set when the Controller has returned the Completer Abort [CA] status to a
request received from the link.
3CPLTOR/W1C0hThis bit is set when the completion timer associated with an outstanding request times out.
2FCPROERR/W1C0hThis bit is set when certain violations of the flow control protocol are detected by the Controller.
1POTLRCVR/W1C0hThis bit is set when the Controller receives a poisoned TLP from the link.
0DLPROTR/W1C0hThis bit is set when the Controller receives an Ack or Nak DLLP whose sequence
number does not correspond to that of an unacknowledged TLP or that of the last acknowledged TLP

3.5.4.155 PCIE_CORE_LM_DUAL_TL_CTRL Register (Offset = 00100E20h) [reset = X]

PCIE_CORE_LM_DUAL_TL_CTRL is shown in Figure 12-1747 and described in Table 12-3438.

Return to the Summary Table.

This register controls Dual TL funtionality.

Table 12-3437 PCIE_CORE_LM_DUAL_TL_CTRL Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E20h
Figure 12-1747 PCIE_CORE_LM_DUAL_TL_CTRL Register
3130292827262524
RESERVED
R/W-X
2322212019181716
DTLHDRT
R/W-2h
15141312111098
DTLAW
R/W-8h
76543210
DTL_RSVDDTLTSGPLP
R-0hR/W-4hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-3438 PCIE_CORE_LM_DUAL_TL_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-16DTLHDRTR/W2hDefines the number of translation tokens that are reserved for the HP TL when selecting between inbound DTI requests.
LP DTI requests will be stalled when the number of available tokens is equal to or smaller than this value.
15-8DTLAWR/W8hDefines the number of back to back high priority TLPs output before the arbiter gives highest priority to the low priority TL for 1 TLP.
A value of '0' gives continuous highest priority to the high priority TL.
The initial value of arbiter weight can be set with the define: den_db_DUAL_TL_CTRL_TX_ARB_WEIGHT
7-4DTL_RSVDR0hRESERVED
3-1DTLTSR/W4hThis field set the ratio in which TAGs are shared among HP and LP TL.
Following value pairs describes how the value of this field creates the sharing pattern.
[0- 0% to HP TL],
[1-6.25% to HP TL],
[2-12.5%],
[3-25%],
[4-50%],
[5-75%],
[6-87.5%],
[7-93.75.5%].
The initial value of TAG share can be set with the define:den_db_DUAL_TL_CTRL_TAG_SHARE
0GPLPR/W0hBy default high priority TL errors are given priority.
If both low priority TL and high priority TL errors happen at the same time, headers from the high priority TL are captured for debug.
use this bit to change the default priority.

3.5.4.156 PCIE_CORE_LM_I_ASF_MAGIC_NUM_CTRLLER_VER_REG Register (Offset = 00100E40h) [reset = 00010BDAh]

PCIE_CORE_LM_I_ASF_MAGIC_NUM_CTRLLER_VER_REG is shown in Figure 12-1748 and described in Table 12-3440.

Return to the Summary Table.

This register contains two read only 16 bit hardcoded values used by the software.

Table 12-3439 PCIE_CORE_LM_I_ASF_MAGIC_NUM_CTRLLER_VER_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E40h
Figure 12-1748 PCIE_CORE_LM_I_ASF_MAGIC_NUM_CTRLLER_VER_REG Register
313029282726252423222120191817161514131211109876543210
CNTVERMGCNM
R-1hR-BDAh
LEGEND: R = Read Only; -n = value after reset
Table 12-3440 PCIE_CORE_LM_I_ASF_MAGIC_NUM_CTRLLER_VER_REG Register Field Descriptions
BitFieldTypeResetDescription
31-16CNTVERR1hThis 16bit value is used to determine the revision number of the controller by the software
15-0MGCNMRBDAhThis 16bit value is used for verification of base address by the software

3.5.4.157 PCIE_CORE_LM_I_EQ_DEBUG_MON_CONTROL_REG Register (Offset = 00100E4Ch) [reset = 460h]

PCIE_CORE_LM_I_EQ_DEBUG_MON_CONTROL shown in Figure 12-1749 and described in Table 12-3442.

Return to the Summary Table.

The register bits to Control EQ debug Monitor operation are implemented in this Register.

Table 12-3441 PCIE_CORE_LM_I_EQ_DEBUG_MON_CONTROL_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E4Ch
Figure 12-1749 PCIE_CORE_LM_I_EQ_DEBUG_MON_CONTROL_REG Register
3130292827262524
R1
R-0h
2322212019181716
R1
R-0h
15141312111098
R1CAPTBEHCAPTSPDSEL
R-0hR-1hR/W-0h
76543210
CAPTSPDSELCAPTPHSELCAPTLNSELCLRCAPT
R/W-0hR/W-3hR/W-0hR/W-0h
Table 12-3442 PCIE_CORE_LM_I_EQ_DEBUG_MON_CONTROL_REG Register Field Descriptions
BitFieldTypeResetDescription
31-11R1R0hReserved
10CAPTBEHR1hIf this is set , the first 64 equalization info events are captured else the last 64 events are
captured
9-7CAPTSPDSELR/W0hSelects the Link Speed at which capture is to be done

000 : Any speed,

001 : Gen 3,

010 : Gen 4,

100 : Gen 5
6-5CAPTPHSELR/W3hSelects the Equalization Phase when capture is to be done

01 : Phase 2,

10 : Phase 3,

11 : Phase 2 and 3
4-1CAPTLNSELR/W0hSelects the Lane whose Equalization Debug information is to be captured.Please
note,this signifies the physical lane number.
0CLRCAPTR/W0hSetting this bit clears all captured information in the EQ Debug Status Registers.
If it is unset then capture is allowed in status registers.

3.5.4.158 PCIE_CORE_LM_I_EQ_DEBUG_MON_STATUS0_REG Register (Offset = 00100E50h) [reset = 0h]

PCIE_CORE_LM_I_EQ_DEBUG_MON_STATUS0_REG is shown in Figure 12-1750 and described in Table 12-3444.

Return to the Summary Table.

Both the Local and Remote EQ FS and LF values are captured in this Register.

Table 12-3443 PCIE_CORE_LM_I_EQ_DEBUG_MON_STATUS0_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E50h
Figure 12-1750 PCIE_CORE_LM_I_EQ_DEBUG_MON_STATUS0_REG Register
313029282726252423222120191817161514131211109876543210
R1REMLFREMFSLCLLFLCLFS
R-0hR-0hR-0hR-0hR-0h
Table 12-3444 PCIE_CORE_LM_I_EQ_DEBUG_MON_STATUS0_REG Register Field Descriptions
BitFieldTypeResetDescription
31-24R1R0hReserved
23-18REMLFR0hRemote PHY's LF Value Of the Lane and Speed Selected.
17-12REMFSR0hRemote PHY's FS Value Of the Lane and Speed Selected.
11-6LCLLFR0hLocal PHY's LF Value Of the Lane and Speed Selected.
5-0LCLFSR0hLocal PHY's FS Value Of the Lane and Speed Selected.

3.5.4.159 PCIE_CORE_LM_I_EQ_DEBUG_MON_STATUS_REG Register (Offset = 00100E54h) [reset = 0h]

PCIE_CORE_LM_I_EQ_DEBUG_MON_STATUS_REG is shown in Figure 12-1751 and described in Table 12-3446.

Return to the Summary Table.

All the Dynamic Equalization information is captured in this Register.This is
implemented using a synchronous FIFO which stores all the captured events as sepereate 32 bit entries.The define den_db_EQ_DEBUG_FIFO_NUM_ENTRIES in defines.h controls the number of entries of the FIFO.Every read increments the read pointer and the client must store the data read. The FIFO can be cleared using the Clear all Capture bit in the EQ Debug Monitor Control Register.

Table 12-3445 PCIE_CORE_LM_I_EQ_DEBUG_MON_STATUS_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E54h
Figure 12-1751 PCIE_CORE_LM_I_EQ_DEBUG_MON_STATUS_REG Register
3130292827262524
EQPHASEDIRFED
R-0hR-0h
2322212019181716
COEFFREJEQPREVDEQPREEQCOEFF
R-0hR-0hR-0hR-0h
15141312111098
EQCOEFF
R-0h
76543210
EQCOEFF
R-0h
Table 12-3446 PCIE_CORE_LM_I_EQ_DEBUG_MON_STATUS_REG Register Field Descriptions
BitFieldTypeResetDescription
31-30EQPHASER0hEqualization Phase during Capture

00 : Phase 0,

01 : Phase 1,

10 : Phase 2,

11 : Phase 3
29-24DIRFEDR0hEP Ph2/RC Ph
3: Stores Direction Change Feedback or Preset feedback Transmitted to Remote Device.
Bit-22, EQPREVD, indicates if this is a Preset feedback or Direction Change Feedback.
EP Ph3/RC Ph
2: Reserved
23COEFFREJR0hPhase
0: Set to '1' if an unsupported preset is received in Phase0.
Phase
1: Set to '0' since no reject in phase1.
EP Ph2/RC Ph
3: Indicates Reject by the Remote end device.
This bit indicates that the
current Coefficient or Preset was rejected by the remote end device.
EP Ph3/RC Ph
2: Indicates that Controller Rejected the received settings to Remote Device in the TX TS1/TS2.
This Reject indicates the current Coefficients or Preset received from Remote Device are rejected
22EQPREVDR0h
1: Preset Valid, Indicates
[21:18] is valid.
Phase
0: Set to '1' to indicate that the intial Local Preset is Valid.
Phase
1: Set to '1' to indicate that the advertised Remote Preset is Valid.
EP Ph2/RC Ph
3: Set to 1 if controller provide preset feedback and to 0 for coefficient feedback.
EP Ph3/RC Ph
2: Reflects the use preset bit received from the remote end.
21-18EQPRER0hPhase
0: Stores Initial Local TX Preset received in Phase0.
Phase
1: Stores Initial Remote Preset advertised in Phase1.
EP Ph2/RC Phase
3: Stores Current Preset of the Remote Device.
EP Ph3/RC Phase
2: Stores Preset Received from Remote Device.
17-0EQCOEFFR0hPhase
0: Stores Initial Local TX Coefficients mapped from Initial Preset.
Phase
1: Stores Initial Remote Coefficients advertised in Phase1.
[Cp, LF, FS] ,
EP Ph2/RC Phase
3: Stores Current Coefficients of the Remote Device.
EP Ph3/RC Phase
2: Stores Coefficients Received from Remote Device.

3.5.4.160 PCIE_CORE_LM_I_AXI_FEATURE_REG Register (Offset = 00100E5Ch) [reset = 2h]

PCIE_CORE_LM_I_AXI_FEATURE_REG Register is shown in Figure 12-1752 and described in Table 12-3448.

Return to the Summary Table.

This register is for the control of AXI Features

Table 12-3447 PCIE_CORE_LM_I_AXI_FEATURE_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E5Ch
Figure 12-1752 PCIE_CORE_LM_I_AXI_FEATURE_REG Register Register
3130292827262524
R30
R-0h
2322212019181716
R30
R-0h
15141312111098
R30
R-0h
76543210
R30SLVERRCTRLR0
R-0hR/W-1hR-0h
Table 12-3448 PCIE_CORE_LM_I_AXI_FEATURE_REG Register Field Descriptions
BitFieldTypeResetDescription
31-2R30R0hReserved
1SLVERRCTRLR/W1hThis bit if set to 1, AXI Slave masks the SLVERR response to be given in case of UR or CRS completion for configuration requests.
If this bit is set to 0,UR and CRS completions from the link causes SLVERR at AXI.
0R0R0hReserved

3.5.4.161 PCIE_CORE_LM_I_LINK_EQ_CONTROL_2_REG Register (Offset = 00100E60h) [reset = 0h]

PCIE_CORE_LM_I_LINK_EQ_CONTROL_2_REG is shown in Figure 12-1753 and described in Table 12-3450.

Return to the Summary Table.

This register implements fields to control and override Link Equalization.

Table 12-3449 PCIE_CORE_LM_I_LINK_EQ_CONTROL_2_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E60h
Figure 12-1753 PCIE_CORE_LM_I_LINK_EQ_CONTROL_2_REG Register
3130292827262524
R2
R-0h
2322212019181716
R2G4OVRRPRG4OVRREN
R-0hR/W-0hR/W-0h
15141312111098
G4RMTXPRG4PRRMENG4EQTSENG3OVRRPR
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
G3OVRRPRG3OVRRENG3RMTXPRG3PRRMEN
R/W-0hR/W-0hR/W-0hR/W-0h
Table 12-3450 PCIE_CORE_LM_I_LINK_EQ_CONTROL_2_REG Register Field Descriptions
BitFieldTypeResetDescription
31-21R2R0hReserved
20-17G4OVRRPRR/W0hThis is a debug register field.
Can be used in both EP and RP Mode.
When enabled using bit-16, this Tx Preset will be applied to the local Transmitter throughout Gen4 regardless of Gen4 Equalization.
16G4OVRRENR/W0hThis is a debug bit.
Can be used in both EP and RP Mode.
If enabled, the Controller locally applies the Gen4 Local Override Tx Preset to the Local Transmitter throughout Gen4.
The Controller performs the Override Preset to Coefficient mapping and then drives on PIPE_TX_DEEMPHASIS signal on the PIPE Interface.
15-12G4RMTXPRR/W0hUsed only in EP Mode.
If enabled, this Tx Preset will be transmitted in 8G EQ TS2s during Gen3 to Gen4 Speed Change negotiation.
Also, If enabled, this Tx Preset will be transmitted in TS1s in the first iteration of Gen4 Equalization Phase2.

Note: If the Remote end device advertised the same preset at start of Equalization Phase2, then this Preset will be skipped.
11G4PRRMENR/W0hUsed only in EP Mode.
This bit enables the Controller, to feedback a Tx Preset for the Remote end Transmitter in the first iteration of Link Equalization Phase2 at Gen4 speed.
The Gen4 Tx Preset that is used for feedback is programmable in bits
[15:12] of this register.
10G4EQTSENR/W0hUsed only in EP Mode.
During Gen3 to Gen4 Speed Change negotiation, this bit enables the Controller in EP Mode to transmit 8G EQ TS2 in Recovery.Rcvr.Cfg state instead of standard TS2 as defined in PCIe specification.

The Tx Preset that will be used in the 8GT EQ TS2 is programmable in bits
[15:12] of this register.
9-6G3OVRRPRR/W0hThis is a debug register field.
Can be used in both EP and RP Mode.
When enabled using bit-5, this Tx Preset will be applied to the local Transmitter throughout Gen3 regardless of Gen3 Equalization.
5G3OVRRENR/W0hThis is a debug bit.
Can be used in both EP and RP Mode.
If enabled, the Controller locally applies the Gen3 Local Override Tx Preset to the Local Transmitter throughout Gen3.
The Controller performs the Override Preset to Coefficient mapping and then drives on PIPE_TX_DEEMPHASIS signal on the PIPE Interface.
4-1G3RMTXPRR/W0hUsed only in EP Mode.
When enabled using bit-0, this Tx Preset will be transmitted in TS1s for the Remote end Transmitter in the first iteration of Gen3 Equalization Phase2.
Reserved for RP Mode.
0G3PRRMENR/W0hUsed only in EP Mode.

This bit enables the Controller, to feedback a Tx Preset for the Remote end Transmitter in the first iteration of Link Equalization Phase2 at Gen3 speed.
The Gen3 Tx Preset that is used for feedback is programmable in bits
[4:1] of this register.
Reserved for RP Mode.

3.5.4.162 PCIE_CORE_LM_I_CORE_FEATURE_REG Register (Offset = 00100E64h) [reset = 0h]

PCIE_CORE_LM_I_CORE_FEATURE_REG is shown in Figure 12-1754 and described in Table 12-3452.

Return to the Summary Table.

This register is for the control of Core Features

Table 12-3451 PCIE_CORE_LM_I_CORE_FEATURE_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E64h
Figure 12-1754 PCIE_CORE_LM_I_CORE_FEATURE_REG Register
3130292827262524
R30
R-0h
2322212019181716
R30
R-0h
15141312111098
R30
R-0h
76543210
R30R2APBCTRLR0
R-0hR-0hR/W-0hR-0h
Table 12-3452 PCIE_CORE_LM_I_CORE_FEATURE_REG Register Field Descriptions
BitFieldTypeResetDescription
31-3R30R0hReserved
2R2R0hReserved
1APBCTRLR/W0hWhen set the Core will return SLVERR on the APB bus for Read or Writes to
Configuration or Local Management registers
0R0R0hReserved

3.5.4.163 PCIE_CORE_LM_I_DTI_ATS_CTRL_2 Register (Offset = 00100E68h) [reset = 0h]

PCIE_CORE_LM_I_DTI_ATS_CTRL_2 is shown in Figure 12-1755 and described in Table 12-3454.

Return to the Summary Table.

This register is for the control of DTI ATS Master

Table 12-3453 PCIE_CORE_LM_I_DTI_ATS_CTRL_2 Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E68h
Figure 12-1755 PCIE_CORE_LM_I_DTI_ATS_CTRL_2 Register
313029282726252423222120191817161514131211109876543210
TIDSTRMID
R/W-0hR/W-0h
Table 12-3454 PCIE_CORE_LM_I_DTI_ATS_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
31-16TIDR/W0hThis 16 bit value is used to drive the 16 bit TID_DTI_DN pin of the DTI Master
15-0STRMIDR/W0hThis 16 bit value is used to filter [upper 16 bits of the SID is matched with this value] the DTI_ATS_INV_REQ and DTI_ATS_PAGE_RESP messages sent[broadcast] from the SMMU in case of multiple DTI Masters.
This value used for the upper 16 bits of the SID in DTI_ATS_TRANS_REQ and DTI_ATS_PAGE_REQ

3.5.4.164 PCIE_CORE_LM_I_RX_INVERT_POLARITY_REG Register (Offset = 00100E88h) [reset = 0h]

PCIE_CORE_LM_I_RX_INVERT_POLARITY_REG is shown in Figure 12-1756 and described in Table 12-3456.

Return to the Summary Table.

This register shows the polarity inversion status of each lane

Table 12-3455 PCIE_CORE_LM_I_RX_INVERT_POLARITY_REG Instances
InstancePhysical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE0D90 0E88h
Figure 12-1756 PCIE_CORE_LM_I_RX_INVERT_POLARITY_REG Register
313029282726252423222120191817161514131211109876543210
R30RIPR
R-0hR-0h
Table 12-3456 PCIE_CORE_LM_I_RX_INVERT_POLARITY_REG Register Field Descriptions
BitFieldTypeResetDescription
31-4R30R0hReserved
3-0RIPRR0hShows the polarity inversion status of each lane