SLUUB65B May 2015 – December 2022
Some pin configurations and algorithm settings are configured via the Pack Configuration B data flash register, as indicated in Table 5-2. This register is programmed and read via the methods described in Section 17.2.1, Accessing the Data Flash. The register is located at subclass = 64, offset = 2.
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
ChgDoDEoC | SE_TDD | SimCtrl | SE_ISD | RSVD | LFPRelax | DoDWT | FConvEn |
1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
0x87 |
ChgDoDEoC = | Enables DoD at EoC recalculation during charging only. True when set. Default setting is recommended. |
SE_TDD = | Enables Tab Disconnect Detection. True when set. (See Section 6.6.2, Tab Disconnect Detection.) |
SimCtrl = | Dynamic Simulation of Voltage Consistency: |
0 = | Dynamic Simulation Step Enabled |
1 = | Voltage Consistency Enabled |
SE_ISD = | Enables Internal Short Detection. True when set. |
RSVD = | Bit 3 is reserved. Must be 0. |
LFPRelax = | Enables LiFePO4 long RELAXATION mode. True when set. |
DoDWT = | Enables DoD weighting feature of gauging algorithm. This feature can improve accuracy during relaxation in a flat portion of the voltage profile, especially when using LiFePO4 chemistry. True when set. |
FConvEn = | Enables fast convergence algorithm. Default setting is recommended. (See Section 7.7, Fast Resistance Scaling.) |