ZHCSJN2 May   2019 DS90UH941AS-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      应用 图
  4. 修订历史记录
  5. 说明 (续)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Electrical Characteristics
    7. 7.7 Recommended Timing for External Clock Reference
    8. 7.8 Recommended Timing for Serial Control Bus
    9. 7.9 Timing Diagrams
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  DSI Receiver
        1. 8.3.1.1 DSI Operating Modes
          1. 8.3.1.1.1 High-Speed Mode
          2. 8.3.1.1.2 Global Operation Timing Parameters
        2. 8.3.1.2 THS-SKIP Programming
        3. 8.3.1.3 DSI Errors and Status
          1. 8.3.1.3.1 DSI / DPHY Error Detection and Reporting
          2. 8.3.1.3.2 DSI Protocol Error Detection
          3. 8.3.1.3.3 DSI Error Reporting
          4. 8.3.1.3.4 DSI Error Counter
          5. 8.3.1.3.5 DSI to FPD-Link III Buffer Error
        4. 8.3.1.4 Supported DSI Video Formats
      2. 8.3.2  High-Speed Forward Channel Data Transfer
      3. 8.3.3  Back Channel Data Transfer
      4. 8.3.4  FPD-Link III Port Register Access
      5. 8.3.5  Video Control Signals
      6. 8.3.6  Power Down Pin (PDB)
      7. 8.3.7  Serial Link Fault Detect
      8. 8.3.8  Interrupt Support
        1. 8.3.8.1 Interrupt Pin (INTB)
        2. 8.3.8.2 Remote Interrupt Pin (REM_INTB)
      9. 8.3.9  GPIO Support
        1. 8.3.9.1 GPIO[3:0] Configuration
        2. 8.3.9.2 Back Channel Configuration
        3. 8.3.9.3 GPIO_REG[8:5] Configuration
      10. 8.3.10 SPI Communication
        1. 8.3.10.1 SPI Mode Configuration
        2. 8.3.10.2 Forward Channel SPI Operation
        3. 8.3.10.3 Reverse Channel SPI Operation
      11. 8.3.11 Audio Modes
        1. 8.3.11.1 I2S Audio Interface
          1. 8.3.11.1.1 I2S Transport Modes
          2. 8.3.11.1.2 I2S Repeater
          3. 8.3.11.1.3 Audio During Splitter and Replicate Modes
        2. 8.3.11.2 TDM Audio Interface
      12. 8.3.12 HDCP
        1. 8.3.12.1 HDCP I2S Audio Encryption
      13. 8.3.13 Built-In Self Test (BIST)
        1. 8.3.13.1 BIST Configuration and Status
        2. 8.3.13.2 Forward Channel and Back Channel Error Checking
      14. 8.3.14 Internal Pattern Generation
        1. 8.3.14.1 Pattern Options
        2. 8.3.14.2 Color Modes
        3. 8.3.14.3 Video Timing Modes
        4. 8.3.14.4 External Timing
        5. 8.3.14.5 Pattern Inversion
        6. 8.3.14.6 Auto-Scrolling
        7. 8.3.14.7 Additional Features
      15. 8.3.15 EMI Reduction Features
        1. 8.3.15.1 Input SSC Tolerance
    4. 8.4 Device Functional Modes
      1. 8.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])
      2. 8.4.2 Clock Modes
        1. 8.4.2.1 DSI Clock Modes
        2. 8.4.2.2 Pixel Clock Modes
          1. 8.4.2.2.1 DSI Reference Clock Mode
          2. 8.4.2.2.2 External Reference Clock Mode
          3. 8.4.2.2.3 Internal Reference Clock
          4. 8.4.2.2.4 External Reference Clock for Independent 2:2 Mode
      3. 8.4.3 Dual-DSI Input Mode
        1. 8.4.3.1 Dual DSI Operation Requirements
        2. 8.4.3.2 Enabling Dual-DSI Operation
        3. 8.4.3.3 Dual-DSI Control and Status
      4. 8.4.4 3D Format Support (Single-DSI Input)
        1. 8.4.4.1 Left/Right 3D Format Support
        2. 8.4.4.2 Alternate Line 3D Format Support
        3. 8.4.4.3 Alternate Pixel 3D Format Support
      5. 8.4.5 Independent 2:2 Mode
        1. 8.4.5.1 Configuration of Independent 2:2 Mode
        2. 8.4.5.2 Example Code for Configuring Independent 2:2 Mode
      6. 8.4.6 FPD-Link III Modes of Operation
        1. 8.4.6.1 Single-Link Mode
        2. 8.4.6.2 Dual-Link Mode
        3. 8.4.6.3 Replicate Mode
        4. 8.4.6.4 Splitter Mode
          1. 8.4.6.4.1 DSI Symmetric Splitting
            1. 8.4.6.4.1.1 Symmetric Splitting – Left/Right
            2. 8.4.6.4.1.2 Symmetric Splitting – Alternate Pixel Splitting
            3. 8.4.6.4.1.3 Symmetric Splitting – Alternate Line Splitting
          2. 8.4.6.4.2 DSI Asymmetric Splitting
            1. 8.4.6.4.2.1 Asymmetric Splitting With Cropping
            2. 8.4.6.4.2.2 Asymmetric Splitting With DSI VC-IDs
          3. 8.4.6.4.3 Configuration of Splitter Operation
    5. 8.5 Programming
      1. 8.5.1 Serial Control Bus
      2. 8.5.2 Multi-Master Arbitration Support
      3. 8.5.3 I2C Restrictions on Multi-Master Operation
      4. 8.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 8.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 8.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
    6. 8.6 Register Maps
      1. 8.6.1 Main Registers
        1. 8.6.1.1   I2C_DEVICE_ID Register (Address = 0h) [reset = Strap]
          1. Table 15. I2C_DEVICE_ID Register Field Descriptions
        2. 8.6.1.2   RESET_CTL Register (Address = 1h) [reset = Strap]
          1. Table 16. RESET_CTL Register Field Descriptions
        3. 8.6.1.3   DEVICE_CFG Register (Address = 2h) [reset = 0h]
          1. Table 17. DEVICE_CFG Register Field Descriptions
        4. 8.6.1.4   GENERAL_CFG Register (Address = 3h) [reset = 92h]
          1. Table 18. GENERAL_CFG Register Field Descriptions
        5. 8.6.1.5   GENERAL_CFG2 Register (Address = 4h) [reset = 0h]
          1. Table 19. GENERAL_CFG2 Register Field Descriptions
        6. 8.6.1.6   I2C_MASTER_CFG Register (Address = 5h) [reset = 0h]
          1. Table 20. I2C_MASTER_CFG Register Field Descriptions
        7. 8.6.1.7   DES_ID_DES_ID_1 Register (Address = 6h) [reset = 0h]
          1. Table 21. DES_ID_DES_ID_1 Register Field Descriptions
        8. 8.6.1.8   SlaveID_0 Register (Address = 7h) [reset = 0h]
          1. Table 22. SlaveID_0 Register Field Descriptions
        9. 8.6.1.9   SlaveAlias_0 Register (Address = 8h) [reset = 0h]
          1. Table 23. SlaveAlias_0 Register Field Descriptions
        10. 8.6.1.10  SDA_SETUP Register (Address = 9h) [reset = 1h]
          1. Table 24. SDA_SETUP Register Field Descriptions
        11. 8.6.1.11  CRC_ERROR0 Register (Address = Ah) [reset = 0h]
          1. Table 25. CRC_ERROR0 Register Field Descriptions
        12. 8.6.1.12  CRC_ERROR1 Register (Address = Bh) [reset = 0h]
          1. Table 26. CRC_ERROR1 Register Field Descriptions
        13. 8.6.1.13  GENERAL_STS Register (Address = Ch) [reset = 0h]
          1. Table 27. GENERAL_STS Register Field Descriptions
        14. 8.6.1.14  GPIO_0_Config Register (Address = Dh) [reset = 20h]
          1. Table 28. GPIO_0_Config Register Field Descriptions
        15. 8.6.1.15  GPIO_1_and_GPIO_2_Config Register (Address = Eh) [reset = 0h]
          1. Table 29. GPIO_1_and_GPIO_2_Config Register Field Descriptions
        16. 8.6.1.16  GPIO_3_Config Register (Address = Fh) [reset = 0h]
          1. Table 30. GPIO_3_Config Register Field Descriptions
        17. 8.6.1.17  GPIO_5_and_GPIO_6_Config Register (Address = 10h) [reset = 0h]
          1. Table 31. GPIO_5_and_GPIO_6_Config Register Field Descriptions
        18. 8.6.1.18  GPIO_7_and_GPIO_8_Config Register (Address = 11h) [reset = 0h]
          1. Table 32. GPIO_7_and_GPIO_8_Config Register Field Descriptions
        19. 8.6.1.19  DATAPATH_CTL Register (Address = 12h) [reset = 0h]
          1. Table 33. DATAPATH_CTL Register Field Descriptions
        20. 8.6.1.20  TX_MODE_STS Register (Address = 13h) [reset = Strap]
          1. Table 34. TX_MODE_STS Register Field Descriptions
        21. 8.6.1.21  TX_BIST_CTL Register (Address = 14h) [reset = 0h]
          1. Table 35. TX_BIST_CTL Register Field Descriptions
        22. 8.6.1.22  BCC_WDOG_CTL Register (Address = 16h) [reset = FEh]
          1. Table 36. BCC_WDOG_CTL Register Field Descriptions
        23. 8.6.1.23  I2C_CONTROL Register (Address = 17h) [reset = 1Eh]
          1. Table 37. I2C_CONTROL Register Field Descriptions
        24. 8.6.1.24  SCL_HIGH_TIME Register (Address = 18h) [reset = 7Fh]
          1. Table 38. SCL_HIGH_TIME Register Field Descriptions
        25. 8.6.1.25  SCL_LOW_TIME Register (Address = 19h) [reset = 7Fh]
          1. Table 39. SCL_LOW_TIME Register Field Descriptions
        26. 8.6.1.26  DATAPATH_CTL2 Register (Address = 1Ah) [reset = 1h]
          1. Table 40. DATAPATH_CTL2 Register Field Descriptions
        27. 8.6.1.27  BIST_BC_ERRORS Register (Address = 1Bh) [reset = 0h]
          1. Table 41. BIST_BC_ERRORS Register Field Descriptions
        28. 8.6.1.28  GPIO_PIN_STS1 Register (Address = 1Ch) [reset = 0h]
          1. Table 42. GPIO_PIN_STS1 Register Field Descriptions
        29. 8.6.1.29  GPIO_PIN_STS2 Register (Address = 1Dh) [reset = 0h]
          1. Table 43. GPIO_PIN_STS2 Register Field Descriptions
        30. 8.6.1.30  TX_PORT_SEL Register (Address = 1Eh) [reset = 1h]
          1. Table 44. TX_PORT_SEL Register Field Descriptions
        31. 8.6.1.31  FREQ_COUNTER Register (Address = 1Fh) [reset = 0h]
          1. Table 45. FREQ_COUNTER Register Field Descriptions
        32. 8.6.1.32  DES_CAP1 Register (Address = 20h) [reset = 0h]
          1. Table 46. DES_CAP1 Register Field Descriptions
        33. 8.6.1.33  DES_CAP2 Register (Address = 21h) [reset = 0h]
          1. Table 47. DES_CAP2 Register Field Descriptions
        34. 8.6.1.34  LINK_DET_CTL Register (Address = 26h) [reset = 0h]
          1. Table 48. LINK_DET_CTL Register Field Descriptions
        35. 8.6.1.35  MAILBOX_2E Register (Address = 2Eh) [reset = A5h]
          1. Table 49. MAILBOX_2E Register Field Descriptions
        36. 8.6.1.36  MAILBOX_2F Register (Address = 2Fh) [reset = 5Ah]
          1. Table 50. MAILBOX_2F Register Field Descriptions
        37. 8.6.1.37  REM_INTB_CTRL Register (Address = 30h) [reset = 0h]
          1. Table 51. REM_INTB_CTRL Register Field Descriptions
        38. 8.6.1.38  IMG_LINE_SIZE0 Register (Address = 32h) [reset = 0h]
          1. Table 52. IMG_LINE_SIZE0 Register Field Descriptions
        39. 8.6.1.39  IMG_LINE_SIZE1 Register (Address = 33h) [reset = 5h]
          1. Table 53. IMG_LINE_SIZE1 Register Field Descriptions
        40. 8.6.1.40  IMG_DELAY0_IMG_DELAY0_P1 Register (Address = 34h) [reset = Ch]
          1. Table 54. IMG_DELAY0_IMG_DELAY0_P1 Register Field Descriptions
        41. 8.6.1.41  IMG_DELAY1_IMG_DELAY_P1 Register (Address = 35h) [reset = 0h]
          1. Table 55. IMG_DELAY1_IMG_DELAY_P1 Register Field Descriptions
        42. 8.6.1.42  CROP_START_X0_CROP_START_X0_P1 Register (Address = 36h) [reset = 0h]
          1. Table 56. CROP_START_X0_CROP_START_X0_P1 Register Field Descriptions
        43. 8.6.1.43  CROP_START_X1_CROP_START_X1_P1 Register (Address = 37h) [reset = 0h]
          1. Table 57. CROP_START_X1_CROP_START_X1_P1 Register Field Descriptions
        44. 8.6.1.44  CROP_STOP_X0_CROP_STOP_X0_P1 Register (Address = 38h) [reset = 0h]
          1. Table 58. CROP_STOP_X0_CROP_STOP_X0_P1 Register Field Descriptions
        45. 8.6.1.45  CROP_STOP_X1_CROP_STOP_X1_P1 Register (Address = 39h) [reset = 0h]
          1. Table 59. CROP_STOP_X1_CROP_STOP_X1_P1 Register Field Descriptions
        46. 8.6.1.46  CROP_START_Y0_CROP_START_Y0_P1 Register (Address = 3Ah) [reset = 0h]
          1. Table 60. CROP_START_Y0_CROP_START_Y0_P1 Register Field Descriptions
        47. 8.6.1.47  CROP_START_Y1_CROP_START_Y1_P1 Register (Address = 3Bh) [reset = 0h]
          1. Table 61. CROP_START_Y1_CROP_START_Y1_P1 Register Field Descriptions
        48. 8.6.1.48  CROP_STOP_Y0_CROP_STOP_Y0_P1 Register (Address = 3Ch) [reset = 0h]
          1. Table 62. CROP_STOP_Y0_CROP_STOP_Y0_P1 Register Field Descriptions
        49. 8.6.1.49  CROP_STOP_Y1_CROP_STOP_Y1_P1 Register (Address = 3Dh) [reset = 0h]
          1. Table 63. CROP_STOP_Y1_CROP_STOP_Y1_P1 Register Field Descriptions
        50. 8.6.1.50  SPLIT_CLK_CTL0_SPLIT_CLK_CTL0_P1 Register (Address = 3Eh) [reset = 81h]
          1. Table 64. SPLIT_CLK_CTL0_SPLIT_CLK_CTL0_P1 Register Field Descriptions
        51. 8.6.1.51  SPLIT_CLK_CTL1_SPLIT_CLK_CTL1_P1 Register (Address = 3Fh) [reset = 2h]
          1. Table 65. SPLIT_CLK_CTL1_SPLIT_CLK_CTL1_P1 Register Field Descriptions
        52. 8.6.1.52  IND_ACC_CTL Register (Address = 40h) [reset = 0h]
          1. Table 66. IND_ACC_CTL Register Field Descriptions
        53. 8.6.1.53  IND_ACC_ADDR Register (Address = 41h) [reset = 0h]
          1. Table 67. IND_ACC_ADDR Register Field Descriptions
        54. 8.6.1.54  IND_ACC_DATA Register (Address = 42h) [reset = 0h]
          1. Table 68. IND_ACC_DATA Register Field Descriptions
        55. 8.6.1.55  BRIDGE_CTL Register (Address = 4Fh) [reset = Strap]
          1. Table 69. BRIDGE_CTL Register Field Descriptions
        56. 8.6.1.56  BRIDGE_STS Register (Address = 50h) [reset = 2h]
          1. Table 70. BRIDGE_STS Register Field Descriptions
        57. 8.6.1.57  BRIDGE_CFG Register (Address = 54h) [reset = 2h]
          1. Table 71. BRIDGE_CFG Register Field Descriptions
        58. 8.6.1.58  AUDIO_CFG Register (Address = 55h) [reset = Strap]
          1. Table 72. AUDIO_CFG Register Field Descriptions
        59. 8.6.1.59  BRIDGE_CFG2 Register (Address = 56h) [reset = Strap]
          1. Table 73. BRIDGE_CFG2 Register Field Descriptions
        60. 8.6.1.60  TDM_CONFIG Register (Address = 57h) [reset = Ah]
          1. Table 74. TDM_CONFIG Register Field Descriptions
        61. 8.6.1.61  VIDEO_3D_STS Register (Address = 58h) [reset = 0h]
          1. Table 75. VIDEO_3D_STS Register Field Descriptions
        62. 8.6.1.62  DUAL_DSI_CTL_STS Register (Address = 59h) [reset = 0h]
          1. Table 76. DUAL_DSI_CTL_STS Register Field Descriptions
        63. 8.6.1.63  DUAL_STS_DUAL_STS_P1 Register (Address = 5Ah) [reset = 0h]
          1. Table 77. DUAL_STS_DUAL_STS_P1 Register Field Descriptions
        64. 8.6.1.64  DUAL_CTL1 Register (Address = 5Bh) [reset = Strap]
          1. Table 78. DUAL_CTL1 Register Field Descriptions
        65. 8.6.1.65  DUAL_CTL2 Register (Address = 5Ch) [reset = 7h]
          1. Table 79. DUAL_CTL2 Register Field Descriptions
        66. 8.6.1.66  FREQ_LOW Register (Address = 5Dh) [reset = 6h]
          1. Table 80. FREQ_LOW Register Field Descriptions
        67. 8.6.1.67  FREQ_HIGH Register (Address = 5Eh) [reset = 2Ch]
          1. Table 81. FREQ_HIGH Register Field Descriptions
        68. 8.6.1.68  DSI_FREQ_DSI_FREQ_P1 Register (Address = 5Fh) [reset = 0h]
          1. Table 82. DSI_FREQ_DSI_FREQ_P1 Register Field Descriptions
        69. 8.6.1.69  SPI_TIMING1 Register (Address = 60h) [reset = 22h]
          1. Table 83. SPI_TIMING1 Register Field Descriptions
        70. 8.6.1.70  SPI_TIMING2 Register (Address = 61h) [reset = 2h]
          1. Table 84. SPI_TIMING2 Register Field Descriptions
        71. 8.6.1.71  SPI_CONFIG Register (Address = 62h) [reset = 0h]
          1. Table 85. SPI_CONFIG Register Field Descriptions
        72. 8.6.1.72  VCID_SPLIT_CTL Register (Address = 63h) [reset = 0h]
          1. Table 86. VCID_SPLIT_CTL Register Field Descriptions
        73. 8.6.1.73  PGCTL_PGCTL_P1 Register (Address = 64h) [reset = 10h]
          1. Table 87. PGCTL_PGCTL_P1 Register Field Descriptions
        74. 8.6.1.74  PGCFG_PGCFG_P1 Register (Address = 65h) [reset = 0h]
          1. Table 88. PGCFG_PGCFG_P1 Register Field Descriptions
        75. 8.6.1.75  PGIA_PGIA_P1 Register (Address = 66h) [reset = 0h]
          1. Table 89. PGIA_PGIA_P1 Register Field Descriptions
        76. 8.6.1.76  PGID_PGID_P1 Register (Address = 67h) [reset = 0h]
          1. Table 90. PGID_PGID_P1 Register Field Descriptions
        77. 8.6.1.77  IMG_HSYNC_CTL0_IMG_HSYNC_CTL0_P1 Register (Address = 6Ah) [reset = 0h]
          1. Table 91. IMG_HSYNC_CTL0_IMG_HSYNC_CTL0_P1 Register Field Descriptions
        78. 8.6.1.78  IMG_HSYNC_CTL1_IMG_HSYNC_CTL1_P1 Register (Address = 6Bh) [reset = 0h]
          1. Table 92. IMG_HSYNC_CTL1_IMG_HSYNC_CTL1_P1 Register Field Descriptions
        79. 8.6.1.79  IMG_HSYNC_CTL2_IMG_HSYNC_CTL2_P1 Register (Address = 6Ch) [reset = 0h]
          1. Table 93. IMG_HSYNC_CTL2_IMG_HSYNC_CTL2_P1 Register Field Descriptions
        80. 8.6.1.80  BCC_STATUS Register (Address = 6Dh) [reset = 0h]
          1. Table 94. BCC_STATUS Register Field Descriptions
        81. 8.6.1.81  BCC_CONFIG Register (Address = 6Eh) [reset = 20h]
          1. Table 95. BCC_CONFIG Register Field Descriptions
        82. 8.6.1.82  FC_BCC_TEST Register (Address = 6Fh) [reset = 0h]
          1. Table 96. FC_BCC_TEST Register Field Descriptions
        83. 8.6.1.83  SlaveID_1 Register (Address = 70h) [reset = 0h]
          1. Table 97. SlaveID_1 Register Field Descriptions
        84. 8.6.1.84  SlaveID_2 Register (Address = 71h) [reset = 0h]
          1. Table 98. SlaveID_2 Register Field Descriptions
        85. 8.6.1.85  SlaveID_3 Register (Address = 72h) [reset = 0h]
          1. Table 99. SlaveID_3 Register Field Descriptions
        86. 8.6.1.86  SlaveID_4 Register (Address = 73h) [reset = 0h]
          1. Table 100. SlaveID_4 Register Field Descriptions
        87. 8.6.1.87  SlaveID_5 Register (Address = 74h) [reset = 0h]
          1. Table 101. SlaveID_5 Register Field Descriptions
        88. 8.6.1.88  SlaveID_6 Register (Address = 75h) [reset = 0h]
          1. Table 102. SlaveID_6 Register Field Descriptions
        89. 8.6.1.89  SlaveID_7 Register (Address = 76h) [reset = 0h]
          1. Table 103. SlaveID_7 Register Field Descriptions
        90. 8.6.1.90  SlaveAlias_1 Register (Address = 77h) [reset = 0h]
          1. Table 104. SlaveAlias_1 Register Field Descriptions
        91. 8.6.1.91  SlaveAlias_2 Register (Address = 78h) [reset = 0h]
          1. Table 105. SlaveAlias_2 Register Field Descriptions
        92. 8.6.1.92  SlaveAlias_3 Register (Address = 79h) [reset = 0h]
          1. Table 106. SlaveAlias_3 Register Field Descriptions
        93. 8.6.1.93  SlaveAlias_4 Register (Address = 7Ah) [reset = 0h]
          1. Table 107. SlaveAlias_4 Register Field Descriptions
        94. 8.6.1.94  SlaveAlias_5 Register (Address = 7Bh) [reset = 0h]
          1. Table 108. SlaveAlias_5 Register Field Descriptions
        95. 8.6.1.95  SlaveAlias_6 Register (Address = 7Ch) [reset = 0h]
          1. Table 109. SlaveAlias_6 Register Field Descriptions
        96. 8.6.1.96  SlaveAlias_7 Register (Address = 7Dh) [reset = 0h]
          1. Table 110. SlaveAlias_7 Register Field Descriptions
        97. 8.6.1.97  RX_BKSV0 Register (Address = 80h) [reset = 0h]
          1. Table 111. RX_BKSV0 Register Field Descriptions
        98. 8.6.1.98  RX_BKSV1 Register (Address = 81h) [reset = 0h]
          1. Table 112. RX_BKSV1 Register Field Descriptions
        99. 8.6.1.99  RX_BKSV2 Register (Address = 82h) [reset = 0h]
          1. Table 113. RX_BKSV2 Register Field Descriptions
        100. 8.6.1.100 RX_BKSV3 Register (Address = 83h) [reset = 0h]
          1. Table 114. RX_BKSV3 Register Field Descriptions
        101. 8.6.1.101 RX_BKSV4 Register (Address = 84h) [reset = 0h]
          1. Table 115. RX_BKSV4 Register Field Descriptions
        102. 8.6.1.102 TX_KSV0 Register (Address = 90h) [reset = 0h]
          1. Table 116. TX_KSV0 Register Field Descriptions
        103. 8.6.1.103 TX_KSV1 Register (Address = 91h) [reset = 0h]
          1. Table 117. TX_KSV1 Register Field Descriptions
        104. 8.6.1.104 TX_KSV2 Register (Address = 92h) [reset = 0h]
          1. Table 118. TX_KSV2 Register Field Descriptions
        105. 8.6.1.105 TX_KSV3 Register (Address = 93h) [reset = 0h]
          1. Table 119. TX_KSV3 Register Field Descriptions
        106. 8.6.1.106 TX_KSV4 Register (Address = 94h) [reset = 0h]
          1. Table 120. TX_KSV4 Register Field Descriptions
        107. 8.6.1.107 RX_BCAPS Register (Address = A0h) [reset = 13h]
          1. Table 121. RX_BCAPS Register Field Descriptions
        108. 8.6.1.108 RX_BSTATUS0 Register (Address = A1h) [reset = 0h]
          1. Table 122. RX_BSTATUS0 Register Field Descriptions
        109. 8.6.1.109 RX_BSTATUS1 Register (Address = A2h) [reset = 0h]
          1. Table 123. RX_BSTATUS1 Register Field Descriptions
        110. 8.6.1.110 HDCP_DBG Register (Address = C0h) [reset = 0h]
          1. Table 124. HDCP_DBG Register Field Descriptions
        111. 8.6.1.111 HDCP_CFG Register (Address = C2h) [reset = 82h]
          1. Table 125. HDCP_CFG Register Field Descriptions
        112. 8.6.1.112 HDCP_CTL Register (Address = C3h) [reset = 0h]
          1. Table 126. HDCP_CTL Register Field Descriptions
        113. 8.6.1.113 HDCP_STS Register (Address = C4h) [reset = 0h]
          1. Table 127. HDCP_STS Register Field Descriptions
        114. 8.6.1.114 HDCP_ICR Register (Address = C6h) [reset = 0h]
          1. Table 128. HDCP_ICR Register Field Descriptions
        115. 8.6.1.115 HDCP_ISR Register (Address = C7h) [reset = 0h]
          1. Table 129. HDCP_ISR Register Field Descriptions
        116. 8.6.1.116 NVM_CTL Register (Address = C8h) [reset = 0h]
          1. Table 130. NVM_CTL Register Field Descriptions
        117. 8.6.1.117 HDCP_CFG2 Register (Address = CDh) [reset = 40h]
          1. Table 131. HDCP_CFG2 Register Field Descriptions
        118. 8.6.1.118 BLUE_SCREEN Register (Address = CEh) [reset = FFh]
          1. Table 132. BLUE_SCREEN Register Field Descriptions
        119. 8.6.1.119 HDCP_DBG_ALIAS Register (Address = E0h) [reset = X]
          1. Table 133. HDCP_DBG_ALIAS Register Field Descriptions
        120. 8.6.1.120 HDCP_CFG_ALIAS Register (Address = E2h) [reset = X]
          1. Table 134. HDCP_CFG_ALIAS Register Field Descriptions
        121. 8.6.1.121 HDCP_CTL_ALIAS Register (Address = E3h) [reset = X]
          1. Table 135. HDCP_CTL_ALIAS Register Field Descriptions
        122. 8.6.1.122 HDCP_STS_ALIAS Register (Address = E4h) [reset = X]
          1. Table 136. HDCP_STS_ALIAS Register Field Descriptions
        123. 8.6.1.123 HDCP_ICR_ALIAS Register (Address = E6h) [reset = X]
          1. Table 137. HDCP_ICR_ALIAS Register Field Descriptions
        124. 8.6.1.124 HDCP_ISR_ALIAS Register (Address = E7h) [reset = X]
          1. Table 138. HDCP_ISR_ALIAS Register Field Descriptions
        125. 8.6.1.125 HDCP_TX_ID0 Register (Address = F0h) [reset = 5Fh]
          1. Table 139. HDCP_TX_ID0 Register Field Descriptions
        126. 8.6.1.126 HDCP_TX_ID1 Register (Address = F1h) [reset = 55h]
          1. Table 140. HDCP_TX_ID1 Register Field Descriptions
        127. 8.6.1.127 HDCP_TX_ID2 Register (Address = F2h) [reset = 48h]
          1. Table 141. HDCP_TX_ID2 Register Field Descriptions
        128. 8.6.1.128 HDCP_TX_ID3 Register (Address = F3h) [reset = 39h]
          1. Table 142. HDCP_TX_ID3 Register Field Descriptions
        129. 8.6.1.129 HDCP_TX_ID4 Register (Address = F4h) [reset = 34h]
          1. Table 143. HDCP_TX_ID4 Register Field Descriptions
        130. 8.6.1.130 HDCP_TX_ID5 Register (Address = F5h) [reset = 31h]
          1. Table 144. HDCP_TX_ID5 Register Field Descriptions
      2. 8.6.2 DSI Port 0 and Port 1 Indirect Registers
        1. 8.6.2.1  DSI_ERR_COUNT Register (Offset = 0h) [reset = 0h]
          1. Table 147. DSI_ERR_COUNT Register Field Descriptions
        2. 8.6.2.2  DPHY_TINIT_TIMING Register (Offset = 1h) [reset = 0h]
          1. Table 148. DPHY_TINIT_TIMING Register Field Descriptions
        3. 8.6.2.3  DPHY_TERM_TIMING Register (Offset = 2h) [reset = 0h]
          1. Table 149. DPHY_TERM_TIMING Register Field Descriptions
        4. 8.6.2.4  DPHY_CLK_SETTLE_TIMING Register (Offset = 3h) [reset = 1Dh]
          1. Table 150. DPHY_CLK_SETTLE_TIMING Register Field Descriptions
        5. 8.6.2.5  DPHY_HS_SETTLE_TIMING Register (Offset = 4h) [reset = 14h]
          1. Table 151. DPHY_HS_SETTLE_TIMING Register Field Descriptions
        6. 8.6.2.6  DPHY_SKIP_TIMING Register (Offset = 5h) [reset = 3Ah]
          1. Table 152. DPHY_SKIP_TIMING Register Field Descriptions
        7. 8.6.2.7  DPHY_LP_POLARITY Register (Offset = 6h) [reset = 0h]
          1. Table 153. DPHY_LP_POLARITY Register Field Descriptions
        8. 8.6.2.8  DPHY_BYPASS Register (Offset = 7h) [reset = 0h]
          1. Table 154. DPHY_BYPASS Register Field Descriptions
        9. 8.6.2.9  HSRX_TO_CNT Register (Offset = 8h) [reset = 0h]
          1. Table 155. HSRX_TO_CNT Register Field Descriptions
        10. 8.6.2.10 DPHY_STATUS Register (Offset = Fh) [reset = 0h]
          1. Table 156. DPHY_STATUS Register Field Descriptions
        11. 8.6.2.11 DPHY_DLANE0_ERR Register (Offset = 10h) [reset = 0h]
          1. Table 157. DPHY_DLANE0_ERR Register Field Descriptions
        12. 8.6.2.12 DPHY_DLANE1_ERR Register (Offset = 11h) [reset = 0h]
          1. Table 158. DPHY_DLANE1_ERR Register Field Descriptions
        13. 8.6.2.13 DPHY_DLANE2_ERR Register (Offset = 12h) [reset = 0h]
          1. Table 159. DPHY_DLANE2_ERR Register Field Descriptions
        14. 8.6.2.14 DPHY_DLANE3_ERR Register (Offset = 13h) [reset = 0h]
          1. Table 160. DPHY_DLANE3_ERR Register Field Descriptions
        15. 8.6.2.15 DPHY_ERR_CLK_LANE Register (Offset = 14h) [reset = 0h]
          1. Table 161. DPHY_ERR_CLK_LANE Register Field Descriptions
        16. 8.6.2.16 DPHY_SYNC_STS Register (Offset = 15h) [reset = 0h]
          1. Table 162. DPHY_SYNC_STS Register Field Descriptions
        17. 8.6.2.17 DSI_CONFIG_0 Register (Offset = 20h) [reset = 7Fh]
          1. Table 163. DSI_CONFIG_0 Register Field Descriptions
        18. 8.6.2.18 DSI_CONFIG_1 Register (Offset = 21h) [reset = 0h]
          1. Table 164. DSI_CONFIG_1 Register Field Descriptions
        19. 8.6.2.19 DSI_ERR_CFG_0 Register (Offset = 22h) [reset = FFh]
          1. Table 165. DSI_ERR_CFG_0 Register Field Descriptions
        20. 8.6.2.20 DSI_ERR_CFG_1 Register (Offset = 23h) [reset = 7Fh]
          1. Table 166. DSI_ERR_CFG_1 Register Field Descriptions
        21. 8.6.2.21 DSI_STATUS Register (Offset = 28h) [reset = 0h]
          1. Table 167. DSI_STATUS Register Field Descriptions
        22. 8.6.2.22 DSI_VC_DTYPE Register (Offset = 2Ah) [reset = 0h]
          1. Table 168. DSI_VC_DTYPE Register Field Descriptions
        23. 8.6.2.23 DSI_ERR_RPT_0 Register (Offset = 2Bh) [reset = 0h]
          1. Table 169. DSI_ERR_RPT_0 Register Field Descriptions
        24. 8.6.2.24 DSI_ERR_RPT_1 Register (Offset = 2Ch) [reset = 0h]
          1. Table 170. DSI_ERR_RPT_1 Register Field Descriptions
        25. 8.6.2.25 DSI_ERR_RPT_2 Register (Offset = 2Dh) [reset = 0h]
          1. Table 171. DSI_ERR_RPT_2 Register Field Descriptions
        26. 8.6.2.26 DSI_HSW_CFG_HI Register (Offset = 30h) [reset = 0h]
          1. Table 172. DSI_HSW_CFG_HI Register Field Descriptions
        27. 8.6.2.27 DSI_HSW_CFG_LO Register (Offset = 31h) [reset = 20h]
          1. Table 173. DSI_HSW_CFG_LO Register Field Descriptions
        28. 8.6.2.28 DSI_VSW_CFG_HI Register (Offset = 32h) [reset = 0h]
          1. Table 174. DSI_VSW_CFG_HI Register Field Descriptions
        29. 8.6.2.29 DSI_VSW_CFG_LO Register (Offset = 33h) [reset = 4h]
          1. Table 175. DSI_VSW_CFG_LO Register Field Descriptions
        30. 8.6.2.30 DSI_SYNC_DLY_CFG_HI Register (Offset = 34h) [reset = 0h]
          1. Table 176. DSI_SYNC_DLY_CFG_HI Register Field Descriptions
        31. 8.6.2.31 DSI_SYNC_DLY_CFG_LO Register (Offset = 35h) [reset = 20h]
          1. Table 177. DSI_SYNC_DLY_CFG_LO Register Field Descriptions
        32. 8.6.2.32 DSI_EN_HSRX Register (Offset = 36h) [reset = 0h]
          1. Table 178. DSI_EN_HSRX Register Field Descriptions
        33. 8.6.2.33 DSI_EN_LPRX Register (Offset = 37h) [reset = 0h]
          1. Table 179. DSI_EN_LPRX Register Field Descriptions
        34. 8.6.2.34 DSI_EN_RXTERM Register (Offset = 38h) [reset = 0h]
          1. Table 180. DSI_EN_RXTERM Register Field Descriptions
        35. 8.6.2.35 DSI_PCLK_DIV_M Register (Offset = 3Ah) [reset = X]
          1. Table 181. DSI_PCLK_DIV_M Register Field Descriptions
        36. 8.6.2.36 DSI_PCLK_DIV_N Register (Offset = 3Bh) [reset = X]
          1. Table 182. DSI_PCLK_DIV_N Register Field Descriptions
      3. 8.6.3 Port 0 and Port 1 Pattern Generator Indirect Registers
        1. 8.6.3.1  PGRS Register (Offset = 0h) [reset = 0h]
          1. Table 185. PGRS Register Field Descriptions
        2. 8.6.3.2  PGGS Register (Offset = 1h) [reset = 0h]
          1. Table 186. PGGS Register Field Descriptions
        3. 8.6.3.3  PGBS Register (Offset = 2h) [reset = 0h]
          1. Table 187. PGBS Register Field Descriptions
        4. 8.6.3.4  PGCDC1 Register (Offset = 3h) [reset = 8h]
          1. Table 188. PGCDC1 Register Field Descriptions
        5. 8.6.3.5  PGTFS1 Register (Offset = 4h) [reset = 48h]
          1. Table 189. PGTFS1 Register Field Descriptions
        6. 8.6.3.6  PGTFS2 Register (Offset = 5h) [reset = 53h]
          1. Table 190. PGTFS2 Register Field Descriptions
        7. 8.6.3.7  PCTFS3 Register (Offset = 6h) [reset = 1Eh]
          1. Table 191. PCTFS3 Register Field Descriptions
        8. 8.6.3.8  PGAFS1 Register (Offset = 7h) [reset = 20h]
          1. Table 192. PGAFS1 Register Field Descriptions
        9. 8.6.3.9  PGAFS2 Register (Offset = 8h) [reset = 3h]
          1. Table 193. PGAFS2 Register Field Descriptions
        10. 8.6.3.10 PGAFS3 Register (Offset = 9h) [reset = 1Eh]
          1. Table 194. PGAFS3 Register Field Descriptions
        11. 8.6.3.11 PGHSW Register (Offset = Ah) [reset = Ah]
          1. Table 195. PGHSW Register Field Descriptions
        12. 8.6.3.12 PGVSW Register (Offset = Bh) [reset = 2h]
          1. Table 196. PGVSW Register Field Descriptions
        13. 8.6.3.13 PGHBP Register (Offset = Ch) [reset = Ah]
          1. Table 197. PGHBP Register Field Descriptions
        14. 8.6.3.14 PGVBP Register (Offset = Dh) [reset = 2h]
          1. Table 198. PGVBP Register Field Descriptions
        15. 8.6.3.15 PBSC Register (Offset = Eh) [reset = 3h]
          1. Table 199. PBSC Register Field Descriptions
        16. 8.6.3.16 PGFT Register (Offset = Fh) [reset = 1Eh]
          1. Table 200. PGFT Register Field Descriptions
        17. 8.6.3.17 PGTSC Register (Offset = 10h) [reset = Ch]
          1. Table 201. PGTSC Register Field Descriptions
        18. 8.6.3.18 PGTSO1 Register (Offset = 11h) [reset = 21h]
          1. Table 202. PGTSO1 Register Field Descriptions
        19. 8.6.3.19 PGTSO2 Register (Offset = 12h) [reset = 43h]
          1. Table 203. PGTSO2 Register Field Descriptions
        20. 8.6.3.20 PGTSO3 Register (Offset = 13h) [reset = 65h]
          1. Table 204. PGTSO3 Register Field Descriptions
        21. 8.6.3.21 PGTSO4 Register (Offset = 14h) [reset = 87h]
          1. Table 205. PGTSO4 Register Field Descriptions
        22. 8.6.3.22 PGTSO5 Register (Offset = 15h) [reset = A9h]
          1. Table 206. PGTSO5 Register Field Descriptions
        23. 8.6.3.23 PGTSO6 Register (Offset = 16h) [reset = CBh]
          1. Table 207. PGTSO6 Register Field Descriptions
        24. 8.6.3.24 PGTSO7 Register (Offset = 17h) [reset = EDh]
          1. Table 208. PGTSO7 Register Field Descriptions
        25. 8.6.3.25 PGTSO8 Register (Offset = 18h) [reset = Fh]
          1. Table 209. PGTSO8 Register Field Descriptions
        26. 8.6.3.26 PGBE Register (Offset = 19h) [reset = 0h]
          1. Table 210. PGBE Register Field Descriptions
        27. 8.6.3.27 PGCDC2 Register (Offset = 1Ah) [reset = 1h]
          1. Table 211. PGCDC2 Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 High-Speed Interconnect Guidelines
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VDD Power Supply
    2. 10.2 Power-Up and Initialization
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground
      2. 11.1.2 Routing FPD-Link III Signal Traces
      3. 11.1.3 Routing DSI Signal Traces
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

特性

  • 符合面向汽车应用的 AEC-Q100 标准 的下列特性:
    • 器件温度 2 级:环境工作温度范围为 −40℃ 至 +105℃
  • 针对具有 24 位色深的 30Hz、3K (2880x1620)、QXGA (2048x1536)、2K (2880x1080)、WUXGA (1920x1200) 或 1080p60 (1920x1080) 分辨率,支持高达 210MHz 的像素时钟频率
  • MIPI D-PHY/显示串行接口 (DSI) 接收器可提供用于连接到视频处理器或 FPGA 的高带宽接口
    • 双 DSI 输入端口,每个端口具有多达 4 个数据通道
    • 每个通道的速率高达 1.5Gbps
    • 具有对称和非对称解包功能的超级帧
    • ECC 和 CRC 生成
    • 虚拟通道功能
  • 单路和双路 FPD-Link III 输出
    • 单链路:高达 105MHz 的像素时钟
    • 双链路:高达 210MHz 的像素时钟
  • 对称和非对称视频分离
  • 支持片上密钥存储的集成 HDCP v1.4 密码引擎