ZHCSTD3B June   2022  – October 2023 BQ756506-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 说明（续）
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
        1. 8.3.1.1 AVAO_REF and AVDD_REF
        2. 8.3.1.2 LDOIN
        3. 8.3.1.3 AVDD
        4. 8.3.1.4 DVDD
        5. 8.3.1.5 CVDD and NEG5V
        6. 8.3.1.6 TSREF
      2. 8.3.2 Measurement System
        1. 8.3.2.1 Main ADC
          1. 8.3.2.1.1 Cell Voltage Measurements
            1. 8.3.2.1.1.1 Analog Front End
            2. 8.3.2.1.1.2 VC Channel Measurements
            3. 8.3.2.1.1.3 Post-ADC Digital LPF
            4. 8.3.2.1.1.4 SRP and SRN Measurements
          2. 8.3.2.1.2 Temperature Measurements
            1. 8.3.2.1.2.1 DieTemp1 Measurement
            2. 8.3.2.1.2.2 GPIOs and TSREF Measurements
          3. 8.3.2.1.3 Main ADC Operation Control
            1. 8.3.2.1.3.1 Operation Modes and Status
        2. 8.3.2.2 AUX ADC
          1. 8.3.2.2.1 AUX Cell Voltage Measurements
            1. 8.3.2.2.1.1 AUX Analog Front End
            2. 8.3.2.2.1.2 CB and Current Sense Channel Measurements
          2. 8.3.2.2.2 AUX Temperature Measurements
            1. 8.3.2.2.2.1 DieTemp2 Measurement
            2. 8.3.2.2.2.2 AUX GPIO Measurements
          3. 8.3.2.2.3 MISC Measurements
          4. 8.3.2.2.4 AUX ADC Operation Control
        3. 8.3.2.3 Synchronization Between MAIN and AUX ADC Measurements
        4. 8.3.2.4 CS ADC
      3. 8.3.3 Cell Balancing
        1. 8.3.3.1 Set Up Cell Balancing
          1. 8.3.3.1.1 Step 1: Determine Balancing Channels
          2. 8.3.3.1.2 Step 2: Select Balancing Control Methods
          3. 8.3.3.1.3 Step 3a: Balancing Thermal Management
          4. 8.3.3.1.4 Step 3b: Option to Stop On Cell Voltage Threshold
          5. 8.3.3.1.5 Step 3c: Option to Stop at Fault
        2. 8.3.3.2 Cell Balancing in SLEEP Mode
        3. 8.3.3.3 Pause and Stop Cell Balancing
          1. 8.3.3.3.1 Cell Balancing Pause
          2. 8.3.3.3.2 Cell Balancing Stop
          3. 8.3.3.3.3 Remaining CB Time
      4. 8.3.4 Integrated Hardware Protectors
        1. 8.3.4.1 OVUV Protectors
          1. 8.3.4.1.1 OVUV Operation Modes
          2. 8.3.4.1.2 OVUV Control and Status
            1. 8.3.4.1.2.1 OVUV Control
            2. 8.3.4.1.2.2 OVUV Status
        2. 8.3.4.2 OTUT Protector
          1. 8.3.4.2.1 OTUT Operation Modes
          2. 8.3.4.2.2 OTUT Control and Status
            1. 8.3.4.2.2.1 OTUT Control
            2. 8.3.4.2.2.2 OTUT Status
      5. 8.3.5 GPIO Configuration
      6. 8.3.6 Communication, OTP, Diagnostic Control
        1. 8.3.6.1 Communication
          1. 8.3.6.1.1 Serial Interface
            1. 8.3.6.1.1.1 UART Physical Layer
              1. 8.3.6.1.1.1.1 UART Transmitter
              2. 8.3.6.1.1.1.2 UART Receiver
              3. 8.3.6.1.1.1.3 COMM CLEAR
            2. 8.3.6.1.1.2 Command and Response Protocol
              1. 8.3.6.1.1.2.1 Transaction Frame Structure
                1. 8.3.6.1.1.2.1.1 Frame Initialization Byte
                2. 8.3.6.1.1.2.1.2 Device Address Byte
                3. 8.3.6.1.1.2.1.3 Register Address Bytes
                4. 8.3.6.1.1.2.1.4 Data Bytes
                5. 8.3.6.1.1.2.1.5 CRC Bytes
                6. 8.3.6.1.1.2.1.6 Calculating Frame CRC Value
                7. 8.3.6.1.1.2.1.7 Verifying Frame CRC
              2. 8.3.6.1.1.2.2 Transaction Frame Examples
                1. 8.3.6.1.1.2.2.1 Single Device Read/Write
          2. 8.3.6.1.2 Communication Timeout
            1. 8.3.6.1.2.1 Short Communication Timeout
            2. 8.3.6.1.2.2 Long Communication Timeout
          3. 8.3.6.1.3 SPI Controller
          4. 8.3.6.1.4 SPI Loopback
        2. 8.3.6.2 Fault Handling
          1. 8.3.6.2.1 Fault Status Hierarchy
            1. 8.3.6.2.1.1 Debug Registers
          2. 8.3.6.2.2 Fault Masking and Reset
            1. 8.3.6.2.2.1 Fault Masking
            2. 8.3.6.2.2.2 Fault Reset
          3. 8.3.6.2.3 Fault Signaling
        3. 8.3.6.3 Nonvolatile Memory
          1. 8.3.6.3.1 OTP Page Status
          2. 8.3.6.3.2 OTP Programming
        4. 8.3.6.4 Diagnostic Control/Status
          1. 8.3.6.4.1 Power Supplies Check
            1. 8.3.6.4.1.1 Power Supply Diagnostic Check
            2. 8.3.6.4.1.2 Power Supply BIST
          2. 8.3.6.4.2 Thermal Shutdown and Warning Check
            1. 8.3.6.4.2.1 Thermal Shutdown
            2. 8.3.6.4.2.2 Thermal Warning
          3. 8.3.6.4.3 Oscillators Watchdog
          4. 8.3.6.4.4 OTP Error Check
            1. 8.3.6.4.4.1 OTP CRC Test and Faults
            2. 8.3.6.4.4.2 OTP Margin Read
            3. 8.3.6.4.4.3 Error Check and Correct (ECC) OTP
          5. 8.3.6.4.5 Integrated Hardware Protector Check
            1. 8.3.6.4.5.1 Parity Check
            2. 8.3.6.4.5.2 OVUV and OTUT DAC Check
            3. 8.3.6.4.5.3 OVUV Protector BIST
            4. 8.3.6.4.5.4 OTUT Protector BIST
          6. 8.3.6.4.6 Diagnostic Through ADC Comparison
            1. 8.3.6.4.6.1 Cell Voltage Measurement Check
            2. 8.3.6.4.6.2 Temperature Measurement Check
            3. 8.3.6.4.6.3 Cell Balancing FETs Check
            4. 8.3.6.4.6.4 VC and CB Open Wire Check
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 SHUTDOWN Mode
          1. 8.4.1.1.1 Exit SHUTDOWN Mode
          2. 8.4.1.1.2 Enter SHUTDOWN Mode
        2. 8.4.1.2 SLEEP Mode
          1. 8.4.1.2.1 Exit SLEEP Mode
          2. 8.4.1.2.2 Enter SLEEP Mode
        3. 8.4.1.3 ACTIVE Mode
          1. 8.4.1.3.1 Exit ACTIVE Mode
          2. 8.4.1.3.2 Enter ACTIVE Mode From SHUTDOWN Mode
          3. 8.4.1.3.3 Enter ACTIVE Mode From SLEEP Mode
      2. 8.4.2 Device Reset
      3. 8.4.3 Ping
        1. 8.4.3.1 Ping
    5. 8.5 Register Maps
      1. 8.5.1 OTP Shadow Register Summary
      2. 8.5.2 Read/Write Register Summary
      3. 8.5.3 Read-Only Register Summary
      4. 8.5.4 Register Field Descriptions
        1. 8.5.4.1  Device Addressing Setup
          1. 8.5.4.1.1 DIR0_ADDR_OTP
          2. 8.5.4.1.2 DIR1_ADDR_OTP
          3. 8.5.4.1.3 CUST_MISC1 through CUST_MISC8
          4. 8.5.4.1.4 DIR0_ADDR
          5. 8.5.4.1.5 DIR1_ADDR
        2. 8.5.4.2  Device ID and Scratch Pad
          1. 8.5.4.2.1 PARTID
          2. 8.5.4.2.2 DEV_REVID
          3. 8.5.4.2.3 DIE_ID1 through DIE_ID9
        3. 8.5.4.3  General Configuration and Control
          1. 8.5.4.3.1  DEV_CONF
          2. 8.5.4.3.2  ACTIVE_CELL
          3. 8.5.4.3.3  PWR_TRANSIT_CONF
          4. 8.5.4.3.4  COMM_TIMEOUT_CONF
          5. 8.5.4.3.5  TX_HOLD_OFF
          6. 8.5.4.3.6  COMM_CTRL
          7. 8.5.4.3.7  CONTROL1
          8. 8.5.4.3.8  CONTROL2
          9. 8.5.4.3.9  CUST_CRC_HI
          10. 8.5.4.3.10 CUST_CRC_LO
          11. 8.5.4.3.11 CUST_CRC_RSLT_HI
          12. 8.5.4.3.12 CUST_CRC_RSLT_LO
        4. 8.5.4.4  Operation Status
          1. 8.5.4.4.1 DIAG_STAT
          2. 8.5.4.4.2 ADC_STAT1
          3. 8.5.4.4.3 ADC_STAT2
          4. 8.5.4.4.4 GPIO_STAT
          5. 8.5.4.4.5 BAL_STAT
          6. 8.5.4.4.6 DEV_STAT
        5. 8.5.4.5  ADC Configuration and Control
          1. 8.5.4.5.1  ADC_CONF1
          2. 8.5.4.5.2  ADC_CONF2
          3. 8.5.4.5.3  MAIN_ADC_CAL1
          4. 8.5.4.5.4  MAIN_ADC_CAL2
          5. 8.5.4.5.5  AUX_ADC_CAL1
          6. 8.5.4.5.6  AUX_ADC_CAL2
          7. 8.5.4.5.7  CS_ADC_CAL1
          8. 8.5.4.5.8  CS_ADC_CAL2
          9. 8.5.4.5.9  ADC_CTRL1
          10. 8.5.4.5.10 ADC_CTRL2
          11. 8.5.4.5.11 ADC_CTRL3
        6. 8.5.4.6  ADC Measurement Results
          1. 8.5.4.6.1  VCELL6_HI/LO
          2. 8.5.4.6.2  VCELL5_HI/LO
          3. 8.5.4.6.3  VCELL4_HI/LO
          4. 8.5.4.6.4  VCELL3_HI/LO
          5. 8.5.4.6.5  VCELL2_HI/LO
          6. 8.5.4.6.6  VCELL1_HI/LO
          7. 8.5.4.6.7  MAIN_CURRENT_HI/LO
          8. 8.5.4.6.8  CURRENT_HI/MID/LO
          9. 8.5.4.6.9  TSREF_HI/LO
          10. 8.5.4.6.10 GPIO1_HI/LO
          11. 8.5.4.6.11 GPIO2_HI/LO
          12. 8.5.4.6.12 GPIO3_HI/LO
          13. 8.5.4.6.13 GPIO4_HI/LO
          14. 8.5.4.6.14 GPIO5_HI/LO
          15. 8.5.4.6.15 GPIO6_HI/LO
          16. 8.5.4.6.16 GPIO7_HI/LO
          17. 8.5.4.6.17 GPIO8_HI/LO
          18. 8.5.4.6.18 DIETEMP1_HI/LO
          19. 8.5.4.6.19 DIETEMP2_HI/LO
          20. 8.5.4.6.20 AUX_CELL_HI/LO
          21. 8.5.4.6.21 AUX_GPIO_HI/LO
          22. 8.5.4.6.22 AUX_BAT_HI/LO
          23. 8.5.4.6.23 AUX_REFL_HI/LO
          24. 8.5.4.6.24 AUX_VBG2_HI/LO
          25. 8.5.4.6.25 AUX_AVAO_REF_HI/LO
          26. 8.5.4.6.26 AUX_AVDD_REF_HI/LO
          27. 8.5.4.6.27 AUX_OV_DAC_HI/LO
          28. 8.5.4.6.28 AUX_UV_DAC_HI/LO
          29. 8.5.4.6.29 AUX_OT_OTCB_DAC_HI/LO
          30. 8.5.4.6.30 AUX_UT_DAC_HI/LO
          31. 8.5.4.6.31 AUX_VCBDONE_DAC_HI/LO
          32. 8.5.4.6.32 AUX_VCM_HI/LO
          33. 8.5.4.6.33 REFOVDAC_HI/LO
          34. 8.5.4.6.34 DIAG_MAIN_HI/LO
          35. 8.5.4.6.35 DIAG_AUX_HI/LO
        7. 8.5.4.7  Balancing Configuration, Control and Status
          1. 8.5.4.7.1 CB_CELL6_CTRL through CB_CELL1_CTRL
          2. 8.5.4.7.2 VCB_DONE_THRESH
          3. 8.5.4.7.3 OTCB_THRESH
          4. 8.5.4.7.4 BAL_CTRL1
          5. 8.5.4.7.5 BAL_CTRL2
          6. 8.5.4.7.6 BAL_CTRL3
          7. 8.5.4.7.7 CB_COMPLETE2
          8. 8.5.4.7.8 BAL_TIME
        8. 8.5.4.8  Protector Configuration and Control
          1. 8.5.4.8.1 OV_THRESH
          2. 8.5.4.8.2 UV_THRESH
          3. 8.5.4.8.3 UV_DISABLE2
          4. 8.5.4.8.4 OTUT_THRESH
          5. 8.5.4.8.5 OVUV_CTRL
          6. 8.5.4.8.6 OTUT_CTRL
        9. 8.5.4.9  GPIO Configuration
          1. 8.5.4.9.1 GPIO_CONF1
          2. 8.5.4.9.2 GPIO_CONF2
          3. 8.5.4.9.3 GPIO_CONF3
          4. 8.5.4.9.4 GPIO_CONF4
        10. 8.5.4.10 SPI Controller
          1. 8.5.4.10.1 SPI_CONF
          2. 8.5.4.10.2 SPI_EXE
          3. 8.5.4.10.3 SPI_TX3, SPI_TX2, and SPI_TX1
          4. 8.5.4.10.4 SPI_RX3, SPI_RX2, and SPI_RX1
        11. 8.5.4.11 Diagnostic Control
          1. 8.5.4.11.1 DIAG_OTP_CTRL
          2. 8.5.4.11.2 DIAG_COMM_CTRL
          3. 8.5.4.11.3 DIAG_PWR_CTRL
          4. 8.5.4.11.4 DIAG_CBFET_CTRL2
          5. 8.5.4.11.5 DIAG_COMP_CTRL1
          6. 8.5.4.11.6 DIAG_COMP_CTRL2
          7. 8.5.4.11.7 DIAG_COMP_CTRL3
          8. 8.5.4.11.8 DIAG_COMP_CTRL4
          9. 8.5.4.11.9 DIAG_PROT_CTRL
        12. 8.5.4.12 Fault Configuration and Reset
          1. 8.5.4.12.1 FAULT_MSK1
          2. 8.5.4.12.2 FAULT_MSK2
          3. 8.5.4.12.3 FAULT_RST1
          4. 8.5.4.12.4 FAULT_RST2
        13. 8.5.4.13 Fault Status
          1. 8.5.4.13.1  FAULT_SUMMARY
          2. 8.5.4.13.2  FAULT_COMM1
          3. 8.5.4.13.3  FAULT_OTP
          4. 8.5.4.13.4  FAULT_SYS
          5. 8.5.4.13.5  FAULT_PROT1
          6. 8.5.4.13.6  FAULT_PROT2
          7. 8.5.4.13.7  FAULT_OV2
          8. 8.5.4.13.8  FAULT_UV2
          9. 8.5.4.13.9  FAULT_OT
          10. 8.5.4.13.10 FAULT_UT
          11. 8.5.4.13.11 FAULT_COMP_GPIO
          12. 8.5.4.13.12 FAULT_COMP_VCCB2
          13. 8.5.4.13.13 FAULT_COMP_VCOW2
          14. 8.5.4.13.14 FAULT_COMP_CBOW2
          15. 8.5.4.13.15 FAULT_COMP_CBFET2
          16. 8.5.4.13.16 FAULT_COMP_MISC
          17. 8.5.4.13.17 FAULT_PWR1
          18. 8.5.4.13.18 FAULT_PWR2
          19. 8.5.4.13.19 FAULT_PWR3
        14. 8.5.4.14 Debug Control and Status
          1. 8.5.4.14.1 DEBUG_UART_RC
          2. 8.5.4.14.2 DEBUG_UART_RR_TR
          3. 8.5.4.14.3 DEBUG_UART_DISCARD
          4. 8.5.4.14.4 DEBUG_UART_VALID_HI/LO
          5. 8.5.4.14.5 DEBUG_OTP_SEC_BLK
          6. 8.5.4.14.6 DEBUG_OTP_DED_BLK
        15. 8.5.4.15 OTP Programming Control and Status
          1. 8.5.4.15.1 OTP_PROG_UNLOCK1A through OTP_PROG_UNLOCK1D
          2. 8.5.4.15.2 OTP_PROG_UNLOCK2A through OTP_PROG_UNLOCK2D
          3. 8.5.4.15.3 OTP_PROG_CTRL
          4. 8.5.4.15.4 OTP_ECC_TEST
          5. 8.5.4.15.5 OTP_ECC_DATAIN1 through OTP_ECC_DATAIN9
          6. 8.5.4.15.6 OTP_ECC_DATAOUT1 through OTP_ECC_DATAOUT9
          7. 8.5.4.15.7 OTP_PROG_STAT
          8. 8.5.4.15.8 OTP_CUST1_STAT
          9. 8.5.4.15.9 OTP_CUST2_STAT
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Circuits
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Cell Sensing and Balancing Inputs
          2. 9.2.1.2.2 Synchronize Voltage and Current Measurements
          3. 9.2.1.2.3 BAT and External NPN
          4. 9.2.1.2.4 Power Supplies, Reference Input
          5. 9.2.1.2.5 GPIO For Thermistor Inputs
          6. 9.2.1.2.6 Internal Balancing Current
          7. 9.2.1.2.7 UART, NFAULT
          8. 9.2.1.2.8 Current Sense Input
        3. 9.2.1.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground Planes
      2. 11.1.2 Bypass Capacitors for Power Supplies and Reference
      3. 11.1.3 Cell Voltage Sensing
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方产品免责声明
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
8.3.6.4.4.3 Error Check and Correct (ECC) OTP

ECC:

Register values for selected registers (0x0000 to 0x002F) are permanently stored in OTP. All registers also exist as volatile storage locations at the same addresses, referred to as shadow registers. The volatile registers are for reading, writing, and device control. For a list of registers included in the OTP, see Section 8.5.1.

During wakeup, the device first loads all shadow registers with hardware default values listed in Section 8.5.1. Then the device loads the registers conditionally with OTP contents from the results of the Error Check and Correct (ECC) evaluation of the OTP. The OTP is loaded to shadow registers in 64-bit blocks; each block has its own Error Check and Correct (ECC) value stored. The ECC detects a single-bit (Single-Error-Correction) or double-bit (Double-Error-Detection) changes in OTP stored data. The ECC is calculated for each block, individually.

Single-bit errors are corrected, double-bit errors are only detected, not corrected. A block with good ECC is loaded. A block with a single-bit error is corrected, and the FAULT_OTP[SEC_DET] bit is set to flag the corrected error event. Additionally, the DEBUG_OTP_SEC_BLK register is updated with the location of the error corrected block. This enables the host to keep track of potentially damaged memory. The block is loaded to shadow registers after the single-bit error correction. Because the evaluation is on a block-by-block basis, it is possible for multiple blocks to have a single-correctable error and still be loaded correctly. Multiple-bit errors can exist with full correction, as long as they are limited to a single error per block.

A block with a bad ECC comparison (two-bit errors in one block) is not loaded and the FAULT_OTP[DED_DET] bit is set to flag the failed bit-error event. Additionally, the DEBUG_OTP_DED_BLK register is updated with the block where the double error occurred. The hardware default value remains in the register. This allows some blocks to be loaded correctly (no fail or single-bit corrected value) and some blocks not to load. When the FAULT_OTP[SEC_DET] or FAULT_OTP[DED_DET] bit is set and the condition is not cleared by a device reset, the device is corrupted and must not be used.

The ECC engine uses the industry standard 72,64 SEC DEC ECC implementation. The OTP is protected by a (72, 64) Hamming code, providing single error correction, double error detection (SECDED). For each 64 bits of data stored in OTP, an additional 8 bits of parity information are stored. The parity bits are designated p0, p1, p2, p4, p8, p16, p32, and p64. Bit p0 covers the entire encoded 72-bit ECC block. The remaining seven parity bits are assigned according to the following rule:

  • Parity bit p1 covers odd bit positions, that is, bit positions which have the least significant bit of the bit position equal to 1 (1, 3, 5, and so on), including the p1 bit itself (bit 1).
  • Parity bit p2 covers bit positions which have the second least significant bit of the bit position equal to 1 (2, 3, 6, 7, 10, 11, and so on), including the p2 bit itself (bit 2).
  • The pattern continues for p4, p8, p16, p32, and p64. Table 8-22 specifies the complete encoding.

Table 8-22 (72, 64) Parity Encoding
Bit Position 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
Encoded Bitsd63d62d61d60d59d58d57p64d56d55d54d53d52d51d50d49d48d47
Parity Bit Coveragep0xxxxxxxxxxxxxxxxxx
p1xxxxxxxxx
p2xxxxxxxxxx
p4xxxxxxxxxx
p8xxxxxxxx
p16xxxxxxxxxx
p32xxxxxxxxxx
p64xxxxxxxx
Bit Position 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36
Encoded Bitsd46d45d44d43d42d41d40d39d38d37d36d35d34d33d32d31d30d29
Parity Bit Coveragep0xxxxxxxxxxxxxxxxxx
p1xxxxxxxxx
p2xxxxxxxx
p4xxxxxxxxxx
p8xxxxxxxx
p16xxxxxx
p32xxxxxxxxxxxxxxxxxx
p64
Bit Position 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
Encoded Bitsd28d27d26p32d25d24d23d22d21d20d19d18d17d16d15d14d13d12
Parity Bit Coveragep0xxxxxxxxxxxxxxxxxx
p1xxxxxxxxx
p2xxxxxxxxxx
p4xxxxxxxx
p8xxxxxxxx
p16xxxxxxxxxxxxxx
p32xxxx
p64
Bit Position 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Encoded Bitsd11p16d10d9d8d7d6d5d4p8d36d2d1p4d0p2p1p0
Parity Bit Coveragep0xxxxxxxxxxxxxxxxxx
p1xxxxxxxxx
p2xxxxxxxx
p4xxxxxxxx
p8xxxxxxxx
p16xx
p32
p64
Table 8-23 Encoder and Decoder Data IN and OUT Positioning
ENCODER
DATA IN Encoded Bits DATA OUT Bit Positions
OTP_ECC_DATAIN 1d0 to d7OTP_ECC_DATAOUT 10 to 7
OTP_ECC_DATAIN 2d8 to d15OTP_ECC_ DATAOUT 28 to 15
OTP_ECC_DATAIN 3d16 to d23OTP_ECC_ DATAOUT 316 to 23
OTP_ECC_DATAIN 4d24 to d31OTP_ECC_ DATAOUT 424 to 31
OTP_ECC_DATAIN 5d32 to d39OTP_ECC_ DATAOUT 532 to 39
OTP_ECC_DATAIN 6d40 to d47OTP_ECC_ DATAOUT 640 to 47
OTP_ECC_DATAIN 7d48 to d55OTP_ECC_ DATAOUT 748 to 55
OTP_ECC_DATAIN 8d56 to d63OTP_ECC_ DATAOUT 856 to 63
OTP_ECC_ DATAOUT 964 to 71
DECODER
DATA IN Bit Positions DATA IN Encoded Bits
OTP_ECC_DATAIN 10 to 7OTP_ECC_DATAOUT 1d0 to d7
OTP_ECC_DATAIN 28 to 15OTP_ECC_ DATAOUT 2d8 to d15
OTP_ECC_DATAIN 316 to 23OTP_ECC_ DATAOUT 3d16 to d23
OTP_ECC_DATAIN 424 to 31OTP_ECC_ DATAOUT 4d24 to d31
OTP_ECC_DATAIN 532 to 39OTP_ECC_ DATAOUT 5d32 to d39
OTP_ECC_DATAIN 640 to 47OTP_ECC_ DATAOUT 6d40 to d47
OTP_ECC_DATAIN 748 to 55OTP_ECC_ DATAOUT 7d48 to d55
OTP_ECC_DATAIN 856 to 63OTP_ECC_ DATAOUT 8d56 to d63
OTP_ECC_DATAIN 964 to 71

ECC Diagnostic Test: The device provides a diagnostic tool to test the ECC function. There are two modes that are available to run the diagnostic. The first, auto mode (OTP_ECC_TEST[MANUAL_AUTO] = 0), uses internal data to run the tests. In auto mode, the OTP_ECC_TEST[DED_SEC] bit selects the type of test that is to be performed and the OTP_ECC_TEST[ENC_DEC] bit determines if the encoder or decoder function is to be tested. The result of the ECC test is provided in the OTP_ECC_DATAOUT* registers within 1μs delay. The test steps and expected results from each test are shown below.

Automatic Decoding steps:

  1. Set ECC Test to automatic OTP_ECC_TEST[MANUAL_AUTO] = 0
  2. Set decoder setting OTP_ECC_TEST[ENC_DEC] = 0
  3. Set decoder to single or double encoding setting with OTP_ECC_TEST[DED_SEC] (1 for DED or 0 for SEC)
  4. Clear all SEC/DED faults by FAULT_RST2[RST_OTP_DATA] = 1
  5. Enable ECC test OTP_ECC_TEST[ENABLE] = 1
  6. Read FAULT_OTP[SEC_DET] flag for SEC or FAULT_OTP[DED_DET] flag for DED
  7. Block read OTP_ECC_DATAOUT1 to OTP_ECC_DATAOUT8 to verify the decoder test results as in Table 8-24
  8. Disable ECC test OTP_ECC_TEST[ENABLE] = 0

Automatic Encoding steps:

  1. Set ECC TEST to automatic OTP_ECC_TEST[MANUAL_AUTO] = 0
  2. Set the encoder setting using OTP_ECC_TEST[ENC_DEC] = 1
  3. Enable the ECC test with OTP_ECC_TEST[ENABLE] = 1
  4. Block read OTP_ECC_DATAOUT1 to OTP_ECC_DATAOUT9 to verify the encoder test results as in Table 8-24
  5. Disable ECC test OTP_ECC_TEST[ENABLE] = 0

Table 8-24 Decoder and Encoder Test Verification
[DED_SEC][ENC_DEC][SEC_DET][DED_DET]OTP_DATAOUT*
0 (SEC test)0 (Decoder test)100x18C3 FF8A 68A9 8069
0 (SEC test)1 (Encoder test)N/AN/A0xCD 3968 C140 2EA5 ED6D
1 (DED test)0 (Decoder test)010x0000 0000 0000 0000
1 (DED test)1 (Encoder test)N/AN/A0xCD 3968 C140 2EA5 ED6D