ZHCSTD3B June   2022  – October 2023 BQ756506-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 说明（续）
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
        1. 8.3.1.1 AVAO_REF and AVDD_REF
        2. 8.3.1.2 LDOIN
        3. 8.3.1.3 AVDD
        4. 8.3.1.4 DVDD
        5. 8.3.1.5 CVDD and NEG5V
        6. 8.3.1.6 TSREF
      2. 8.3.2 Measurement System
        1. 8.3.2.1 Main ADC
          1. 8.3.2.1.1 Cell Voltage Measurements
            1. 8.3.2.1.1.1 Analog Front End
            2. 8.3.2.1.1.2 VC Channel Measurements
            3. 8.3.2.1.1.3 Post-ADC Digital LPF
            4. 8.3.2.1.1.4 SRP and SRN Measurements
          2. 8.3.2.1.2 Temperature Measurements
            1. 8.3.2.1.2.1 DieTemp1 Measurement
            2. 8.3.2.1.2.2 GPIOs and TSREF Measurements
          3. 8.3.2.1.3 Main ADC Operation Control
            1. 8.3.2.1.3.1 Operation Modes and Status
        2. 8.3.2.2 AUX ADC
          1. 8.3.2.2.1 AUX Cell Voltage Measurements
            1. 8.3.2.2.1.1 AUX Analog Front End
            2. 8.3.2.2.1.2 CB and Current Sense Channel Measurements
          2. 8.3.2.2.2 AUX Temperature Measurements
            1. 8.3.2.2.2.1 DieTemp2 Measurement
            2. 8.3.2.2.2.2 AUX GPIO Measurements
          3. 8.3.2.2.3 MISC Measurements
          4. 8.3.2.2.4 AUX ADC Operation Control
        3. 8.3.2.3 Synchronization Between MAIN and AUX ADC Measurements
        4. 8.3.2.4 CS ADC
      3. 8.3.3 Cell Balancing
        1. 8.3.3.1 Set Up Cell Balancing
          1. 8.3.3.1.1 Step 1: Determine Balancing Channels
          2. 8.3.3.1.2 Step 2: Select Balancing Control Methods
          3. 8.3.3.1.3 Step 3a: Balancing Thermal Management
          4. 8.3.3.1.4 Step 3b: Option to Stop On Cell Voltage Threshold
          5. 8.3.3.1.5 Step 3c: Option to Stop at Fault
        2. 8.3.3.2 Cell Balancing in SLEEP Mode
        3. 8.3.3.3 Pause and Stop Cell Balancing
          1. 8.3.3.3.1 Cell Balancing Pause
          2. 8.3.3.3.2 Cell Balancing Stop
          3. 8.3.3.3.3 Remaining CB Time
      4. 8.3.4 Integrated Hardware Protectors
        1. 8.3.4.1 OVUV Protectors
          1. 8.3.4.1.1 OVUV Operation Modes
          2. 8.3.4.1.2 OVUV Control and Status
            1. 8.3.4.1.2.1 OVUV Control
            2. 8.3.4.1.2.2 OVUV Status
        2. 8.3.4.2 OTUT Protector
          1. 8.3.4.2.1 OTUT Operation Modes
          2. 8.3.4.2.2 OTUT Control and Status
            1. 8.3.4.2.2.1 OTUT Control
            2. 8.3.4.2.2.2 OTUT Status
      5. 8.3.5 GPIO Configuration
      6. 8.3.6 Communication, OTP, Diagnostic Control
        1. 8.3.6.1 Communication
          1. 8.3.6.1.1 Serial Interface
            1. 8.3.6.1.1.1 UART Physical Layer
              1. 8.3.6.1.1.1.1 UART Transmitter
              2. 8.3.6.1.1.1.2 UART Receiver
              3. 8.3.6.1.1.1.3 COMM CLEAR
            2. 8.3.6.1.1.2 Command and Response Protocol
              1. 8.3.6.1.1.2.1 Transaction Frame Structure
                1. 8.3.6.1.1.2.1.1 Frame Initialization Byte
                2. 8.3.6.1.1.2.1.2 Device Address Byte
                3. 8.3.6.1.1.2.1.3 Register Address Bytes
                4. 8.3.6.1.1.2.1.4 Data Bytes
                5. 8.3.6.1.1.2.1.5 CRC Bytes
                6. 8.3.6.1.1.2.1.6 Calculating Frame CRC Value
                7. 8.3.6.1.1.2.1.7 Verifying Frame CRC
              2. 8.3.6.1.1.2.2 Transaction Frame Examples
                1. 8.3.6.1.1.2.2.1 Single Device Read/Write
          2. 8.3.6.1.2 Communication Timeout
            1. 8.3.6.1.2.1 Short Communication Timeout
            2. 8.3.6.1.2.2 Long Communication Timeout
          3. 8.3.6.1.3 SPI Controller
          4. 8.3.6.1.4 SPI Loopback
        2. 8.3.6.2 Fault Handling
          1. 8.3.6.2.1 Fault Status Hierarchy
            1. 8.3.6.2.1.1 Debug Registers
          2. 8.3.6.2.2 Fault Masking and Reset
            1. 8.3.6.2.2.1 Fault Masking
            2. 8.3.6.2.2.2 Fault Reset
          3. 8.3.6.2.3 Fault Signaling
        3. 8.3.6.3 Nonvolatile Memory
          1. 8.3.6.3.1 OTP Page Status
          2. 8.3.6.3.2 OTP Programming
        4. 8.3.6.4 Diagnostic Control/Status
          1. 8.3.6.4.1 Power Supplies Check
            1. 8.3.6.4.1.1 Power Supply Diagnostic Check
            2. 8.3.6.4.1.2 Power Supply BIST
          2. 8.3.6.4.2 Thermal Shutdown and Warning Check
            1. 8.3.6.4.2.1 Thermal Shutdown
            2. 8.3.6.4.2.2 Thermal Warning
          3. 8.3.6.4.3 Oscillators Watchdog
          4. 8.3.6.4.4 OTP Error Check
            1. 8.3.6.4.4.1 OTP CRC Test and Faults
            2. 8.3.6.4.4.2 OTP Margin Read
            3. 8.3.6.4.4.3 Error Check and Correct (ECC) OTP
          5. 8.3.6.4.5 Integrated Hardware Protector Check
            1. 8.3.6.4.5.1 Parity Check
            2. 8.3.6.4.5.2 OVUV and OTUT DAC Check
            3. 8.3.6.4.5.3 OVUV Protector BIST
            4. 8.3.6.4.5.4 OTUT Protector BIST
          6. 8.3.6.4.6 Diagnostic Through ADC Comparison
            1. 8.3.6.4.6.1 Cell Voltage Measurement Check
            2. 8.3.6.4.6.2 Temperature Measurement Check
            3. 8.3.6.4.6.3 Cell Balancing FETs Check
            4. 8.3.6.4.6.4 VC and CB Open Wire Check
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 SHUTDOWN Mode
          1. 8.4.1.1.1 Exit SHUTDOWN Mode
          2. 8.4.1.1.2 Enter SHUTDOWN Mode
        2. 8.4.1.2 SLEEP Mode
          1. 8.4.1.2.1 Exit SLEEP Mode
          2. 8.4.1.2.2 Enter SLEEP Mode
        3. 8.4.1.3 ACTIVE Mode
          1. 8.4.1.3.1 Exit ACTIVE Mode
          2. 8.4.1.3.2 Enter ACTIVE Mode From SHUTDOWN Mode
          3. 8.4.1.3.3 Enter ACTIVE Mode From SLEEP Mode
      2. 8.4.2 Device Reset
      3. 8.4.3 Ping
        1. 8.4.3.1 Ping
    5. 8.5 Register Maps
      1. 8.5.1 OTP Shadow Register Summary
      2. 8.5.2 Read/Write Register Summary
      3. 8.5.3 Read-Only Register Summary
      4. 8.5.4 Register Field Descriptions
        1. 8.5.4.1  Device Addressing Setup
          1. 8.5.4.1.1 DIR0_ADDR_OTP
          2. 8.5.4.1.2 DIR1_ADDR_OTP
          3. 8.5.4.1.3 CUST_MISC1 through CUST_MISC8
          4. 8.5.4.1.4 DIR0_ADDR
          5. 8.5.4.1.5 DIR1_ADDR
        2. 8.5.4.2  Device ID and Scratch Pad
          1. 8.5.4.2.1 PARTID
          2. 8.5.4.2.2 DEV_REVID
          3. 8.5.4.2.3 DIE_ID1 through DIE_ID9
        3. 8.5.4.3  General Configuration and Control
          1. 8.5.4.3.1  DEV_CONF
          2. 8.5.4.3.2  ACTIVE_CELL
          3. 8.5.4.3.3  PWR_TRANSIT_CONF
          4. 8.5.4.3.4  COMM_TIMEOUT_CONF
          5. 8.5.4.3.5  TX_HOLD_OFF
          6. 8.5.4.3.6  COMM_CTRL
          7. 8.5.4.3.7  CONTROL1
          8. 8.5.4.3.8  CONTROL2
          9. 8.5.4.3.9  CUST_CRC_HI
          10. 8.5.4.3.10 CUST_CRC_LO
          11. 8.5.4.3.11 CUST_CRC_RSLT_HI
          12. 8.5.4.3.12 CUST_CRC_RSLT_LO
        4. 8.5.4.4  Operation Status
          1. 8.5.4.4.1 DIAG_STAT
          2. 8.5.4.4.2 ADC_STAT1
          3. 8.5.4.4.3 ADC_STAT2
          4. 8.5.4.4.4 GPIO_STAT
          5. 8.5.4.4.5 BAL_STAT
          6. 8.5.4.4.6 DEV_STAT
        5. 8.5.4.5  ADC Configuration and Control
          1. 8.5.4.5.1  ADC_CONF1
          2. 8.5.4.5.2  ADC_CONF2
          3. 8.5.4.5.3  MAIN_ADC_CAL1
          4. 8.5.4.5.4  MAIN_ADC_CAL2
          5. 8.5.4.5.5  AUX_ADC_CAL1
          6. 8.5.4.5.6  AUX_ADC_CAL2
          7. 8.5.4.5.7  CS_ADC_CAL1
          8. 8.5.4.5.8  CS_ADC_CAL2
          9. 8.5.4.5.9  ADC_CTRL1
          10. 8.5.4.5.10 ADC_CTRL2
          11. 8.5.4.5.11 ADC_CTRL3
        6. 8.5.4.6  ADC Measurement Results
          1. 8.5.4.6.1  VCELL6_HI/LO
          2. 8.5.4.6.2  VCELL5_HI/LO
          3. 8.5.4.6.3  VCELL4_HI/LO
          4. 8.5.4.6.4  VCELL3_HI/LO
          5. 8.5.4.6.5  VCELL2_HI/LO
          6. 8.5.4.6.6  VCELL1_HI/LO
          7. 8.5.4.6.7  MAIN_CURRENT_HI/LO
          8. 8.5.4.6.8  CURRENT_HI/MID/LO
          9. 8.5.4.6.9  TSREF_HI/LO
          10. 8.5.4.6.10 GPIO1_HI/LO
          11. 8.5.4.6.11 GPIO2_HI/LO
          12. 8.5.4.6.12 GPIO3_HI/LO
          13. 8.5.4.6.13 GPIO4_HI/LO
          14. 8.5.4.6.14 GPIO5_HI/LO
          15. 8.5.4.6.15 GPIO6_HI/LO
          16. 8.5.4.6.16 GPIO7_HI/LO
          17. 8.5.4.6.17 GPIO8_HI/LO
          18. 8.5.4.6.18 DIETEMP1_HI/LO
          19. 8.5.4.6.19 DIETEMP2_HI/LO
          20. 8.5.4.6.20 AUX_CELL_HI/LO
          21. 8.5.4.6.21 AUX_GPIO_HI/LO
          22. 8.5.4.6.22 AUX_BAT_HI/LO
          23. 8.5.4.6.23 AUX_REFL_HI/LO
          24. 8.5.4.6.24 AUX_VBG2_HI/LO
          25. 8.5.4.6.25 AUX_AVAO_REF_HI/LO
          26. 8.5.4.6.26 AUX_AVDD_REF_HI/LO
          27. 8.5.4.6.27 AUX_OV_DAC_HI/LO
          28. 8.5.4.6.28 AUX_UV_DAC_HI/LO
          29. 8.5.4.6.29 AUX_OT_OTCB_DAC_HI/LO
          30. 8.5.4.6.30 AUX_UT_DAC_HI/LO
          31. 8.5.4.6.31 AUX_VCBDONE_DAC_HI/LO
          32. 8.5.4.6.32 AUX_VCM_HI/LO
          33. 8.5.4.6.33 REFOVDAC_HI/LO
          34. 8.5.4.6.34 DIAG_MAIN_HI/LO
          35. 8.5.4.6.35 DIAG_AUX_HI/LO
        7. 8.5.4.7  Balancing Configuration, Control and Status
          1. 8.5.4.7.1 CB_CELL6_CTRL through CB_CELL1_CTRL
          2. 8.5.4.7.2 VCB_DONE_THRESH
          3. 8.5.4.7.3 OTCB_THRESH
          4. 8.5.4.7.4 BAL_CTRL1
          5. 8.5.4.7.5 BAL_CTRL2
          6. 8.5.4.7.6 BAL_CTRL3
          7. 8.5.4.7.7 CB_COMPLETE2
          8. 8.5.4.7.8 BAL_TIME
        8. 8.5.4.8  Protector Configuration and Control
          1. 8.5.4.8.1 OV_THRESH
          2. 8.5.4.8.2 UV_THRESH
          3. 8.5.4.8.3 UV_DISABLE2
          4. 8.5.4.8.4 OTUT_THRESH
          5. 8.5.4.8.5 OVUV_CTRL
          6. 8.5.4.8.6 OTUT_CTRL
        9. 8.5.4.9  GPIO Configuration
          1. 8.5.4.9.1 GPIO_CONF1
          2. 8.5.4.9.2 GPIO_CONF2
          3. 8.5.4.9.3 GPIO_CONF3
          4. 8.5.4.9.4 GPIO_CONF4
        10. 8.5.4.10 SPI Controller
          1. 8.5.4.10.1 SPI_CONF
          2. 8.5.4.10.2 SPI_EXE
          3. 8.5.4.10.3 SPI_TX3, SPI_TX2, and SPI_TX1
          4. 8.5.4.10.4 SPI_RX3, SPI_RX2, and SPI_RX1
        11. 8.5.4.11 Diagnostic Control
          1. 8.5.4.11.1 DIAG_OTP_CTRL
          2. 8.5.4.11.2 DIAG_COMM_CTRL
          3. 8.5.4.11.3 DIAG_PWR_CTRL
          4. 8.5.4.11.4 DIAG_CBFET_CTRL2
          5. 8.5.4.11.5 DIAG_COMP_CTRL1
          6. 8.5.4.11.6 DIAG_COMP_CTRL2
          7. 8.5.4.11.7 DIAG_COMP_CTRL3
          8. 8.5.4.11.8 DIAG_COMP_CTRL4
          9. 8.5.4.11.9 DIAG_PROT_CTRL
        12. 8.5.4.12 Fault Configuration and Reset
          1. 8.5.4.12.1 FAULT_MSK1
          2. 8.5.4.12.2 FAULT_MSK2
          3. 8.5.4.12.3 FAULT_RST1
          4. 8.5.4.12.4 FAULT_RST2
        13. 8.5.4.13 Fault Status
          1. 8.5.4.13.1  FAULT_SUMMARY
          2. 8.5.4.13.2  FAULT_COMM1
          3. 8.5.4.13.3  FAULT_OTP
          4. 8.5.4.13.4  FAULT_SYS
          5. 8.5.4.13.5  FAULT_PROT1
          6. 8.5.4.13.6  FAULT_PROT2
          7. 8.5.4.13.7  FAULT_OV2
          8. 8.5.4.13.8  FAULT_UV2
          9. 8.5.4.13.9  FAULT_OT
          10. 8.5.4.13.10 FAULT_UT
          11. 8.5.4.13.11 FAULT_COMP_GPIO
          12. 8.5.4.13.12 FAULT_COMP_VCCB2
          13. 8.5.4.13.13 FAULT_COMP_VCOW2
          14. 8.5.4.13.14 FAULT_COMP_CBOW2
          15. 8.5.4.13.15 FAULT_COMP_CBFET2
          16. 8.5.4.13.16 FAULT_COMP_MISC
          17. 8.5.4.13.17 FAULT_PWR1
          18. 8.5.4.13.18 FAULT_PWR2
          19. 8.5.4.13.19 FAULT_PWR3
        14. 8.5.4.14 Debug Control and Status
          1. 8.5.4.14.1 DEBUG_UART_RC
          2. 8.5.4.14.2 DEBUG_UART_RR_TR
          3. 8.5.4.14.3 DEBUG_UART_DISCARD
          4. 8.5.4.14.4 DEBUG_UART_VALID_HI/LO
          5. 8.5.4.14.5 DEBUG_OTP_SEC_BLK
          6. 8.5.4.14.6 DEBUG_OTP_DED_BLK
        15. 8.5.4.15 OTP Programming Control and Status
          1. 8.5.4.15.1 OTP_PROG_UNLOCK1A through OTP_PROG_UNLOCK1D
          2. 8.5.4.15.2 OTP_PROG_UNLOCK2A through OTP_PROG_UNLOCK2D
          3. 8.5.4.15.3 OTP_PROG_CTRL
          4. 8.5.4.15.4 OTP_ECC_TEST
          5. 8.5.4.15.5 OTP_ECC_DATAIN1 through OTP_ECC_DATAIN9
          6. 8.5.4.15.6 OTP_ECC_DATAOUT1 through OTP_ECC_DATAOUT9
          7. 8.5.4.15.7 OTP_PROG_STAT
          8. 8.5.4.15.8 OTP_CUST1_STAT
          9. 8.5.4.15.9 OTP_CUST2_STAT
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Circuits
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Cell Sensing and Balancing Inputs
          2. 9.2.1.2.2 Synchronize Voltage and Current Measurements
          3. 9.2.1.2.3 BAT and External NPN
          4. 9.2.1.2.4 Power Supplies, Reference Input
          5. 9.2.1.2.5 GPIO For Thermistor Inputs
          6. 9.2.1.2.6 Internal Balancing Current
          7. 9.2.1.2.7 UART, NFAULT
          8. 9.2.1.2.8 Current Sense Input
        3. 9.2.1.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground Planes
      2. 11.1.2 Bypass Capacitors for Power Supplies and Reference
      3. 11.1.3 Cell Voltage Sensing
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方产品免责声明
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

8.5.3 Read-Only Register Summary

Register NameAddr HexRW TypeReset ValueData
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
PARTID500R0x00REV[7:0]
DEV_REVIDE00R0x00DEV_REVID[7:0]
DIE_ID1 through DIE_ID9501R0x00ID[7:0]
502R0x00ID[7:0]
503R0x00ID[7:0]
504R0x00ID[7:0]
505R0x00ID[7:0]
506R0x00ID[7:0]
507R0x00ID[7:0]
508R0x00ID[7:0]
509R0x00ID[7:0]
CUST_CRC_RSLT_HI50CR0x31CRC[7:0]
CUST_CRC_RSLT_LO50DR0xF3CRC[7:0]
OTP_ECC_DATAOUT1 through OTP_ECC_DATAOUT9510R0x00DATA[7:0]
511R0x00DATA[7:0]
512R0x00DATA[7:0]
513R0x00DATA[7:0]
514R0x00DATA[7:0]
515R0x00DATA[7:0]
516R0x00DATA[7:0]
517R0x00DATA[7:0]
518R0x00DATA[7:0]
OTP_PROG_STAT519R0x00UNLOCKOTERRUVERROVERRSUVERRSOVERRPROG ERRDONE
OTP_CUST1_STAT51AR0x00LOADEDLOAD WRNLOAD ERRFMTERRPROGOKUVOKOVOKTRY
OTP_CUST2_STAT51BR0x00LOADEDLOAD WRNLOAD ERRFMTERRPROGOKUVOKOVOKTRY
SPI_RX3, SPI_RX2, and SPI_RX1520R0x00DATA[7:0]
521R0x00DATA[7:0]
522R0x00DATA[7:0]
DIAG_STAT526R0x00RSVDDRDY_ OTUTDRDY_ OVUVDRDY_ BIST_ OTUTDRDY_ BIST_ OVUVDRDY_ BIST_ PWR
ADC_STAT1527R0x00RSVDDRDY_ CS_ADCDRDY_ AUX_ GPIODRDY_ AUX_ CELLDRDY_ AUX_ MISCDRDY_ MAIN_ ADC
ADC_STAT2528R0x00RSVDDRDY_ LPFDRDY_ GPIODRDY_ VCOWDRDY_ CBOWDRDY_ CBFETDRDY_ VCCB
GPIO_STAT52AR0x00GPIO8GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1
BAL_STAT52BR0x00INVALID_ CBCONFOT_ PAUSE_ DETCB_ INPAUSEMB_RUNCB_RUNABORT FLTMB_ DONECB_ DONE
DEV_STAT52CR0x00RSVDFACT_ CRC_ DONECUST_ CRC_ DONEOTUT_ RUNOVUV_ RUNCS_RUNAUX_ RUNMAIN_ RUN
FAULT _SUMMARY52DR0x00FAULT_ PROTFAULT_ COMP_ ADCFAULT_ OTPFAULT_ COMMFAULT_ OTUTFAULT_ OVUVFAULT_ SYSFAULT_ PWR
FAULT_COMM1530R0x00RSVDUART_TRUART_ RRUART_ RCCOMM CLR_ DETSTOP_ DET
FAULT_OTP535R0x00RSVDDED_ DETSEC_DETCUST_ CRCFACT_ CRCCUSTLD ERRFACTLD ERRGBLOV ERR
FAULT_SYS536R0x00LFORSVDGPIODRSTCTLCTSTSHUTTWARN
FAULT_PROT153AR0x00RSVDTPARITY _FAILVPARITY _FAIL
FAULT_PROT253BR0x00RSVDBIST_ ABORTTPATH _FAILVPATH _FAILUTCOMP _FAILOTCOMP _FAILOVCOMP _FAILUVCOMP _FAIL
RSVD53CR0x00RSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVD
FAULT_OV253DR0x00RSVDRSVDOV6_DETOV5_DETOV4_DETOV3_DETOV2_DETOV1_DET
RSVD53ER0x00RSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVD
FAULT_UV253FR0x00RSVDRSVDUV6_DETUV5_DETUV4_DETUV3_DETUV2_DETUV1_DET
FAULT_OT540R0x00OT8_DETOT7_DETOT6_DETOT5_DETOT4_DETOT3_DETOT2_DETOT1_DET
FAULT_UT541R0x00UT8_DETUT7_DETUT6_DETUT5_DETUT4_DETUT3_DETUT2_DETUT1_DET
FAULT_COMP_GPIO543R0x00GPIO8_ FAILGPIO7_ FAILGPIO6_ FAILGPIO5_ FAILGPIO4_ FAILGPIO3_ FAILGPIO2_ FAILGPIO1_ FAIL
RVSD545R0x00RSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVD
FAULT_COMP_VCCB2546R0x00RSVDRSVDCELL6_ FAILCELL5_ FAILCELL4_ FAILCELL3_ FAILCELL2_ FAILCELL1_ FAIL
RSVD548R0x00RSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVD
FAULT_COMP_VCOW2549R0x00RSVDRSVDVCOW6 _FAILVCOW5 _FAILVCOW4 _FAILVCOW3 _FAILVCOW2 _FAILVCOW1 _FAIL
RSVD54BR0x00RSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVD
FAULT_COMP_VBOW254CR0x00RSVDRSVDCBOW6 _FAILCBOW5 _FAILCBOW4 _FAILCBOW3 _FAILCBOW2 _FAILCBOW1 _FAIL
RSVD54ER0x00RSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVD
FAULT_COMP_CBFET254FR0x00RSVDRSVDCBFET6 _FAILCBFET5 _FAILCBFET4 _FAILCBFET3 _FAILCBFET2 _FAILCBFET1 _FAIL
FAULT_COMP_MISC550R0x00RSVDCOMP_ ADC_ ABORTLPF_FAIL
FAULT_PWR1552R0x00CVSS_ OPENDVSS_ OPENREFHM_ OPENCVDD_ UVCVDD_ OVDVDD_ OVAVDD_ OSCAVDD_ OV
FAULT_PWR2553R0x00RSVDPWRBIST _FAILRSVDREFH_ OSCNEG5V_ UVTSREF_ OSCTSREF_ UVTSREF_ OV
FAULT_PWR3554RRSVDRSVDRSVDRSVDAVDDUV _DRST
RSVD556R0x00RSVDRSVDRSVDRSVDRSVDRSVDRSVDRSVD
CB_COMPLETE2557R0x00RSVDRSVDCELL6 _DONECELL5 _DONECELL4 _DONECELL3 _DONECELL2 _DONECELL1 _DONE
BAL_TIME558R0x00TIME_UNITTIME[6:0]
RSVD568R0x80RSVD
569R0x00RSVD
RSVD56AR0x80RSVD
56BR0x00RSVD
RSVD56CR0x80RSVD
56DR0x00RSVD
RSVD56ER0x80RSVD
56FR0x00RSVD
RSVD570R0x80RSVD
571R0x00RSVD
RSVD572R0x80RSVD
573R0x00RSVD
RSVD574R0x80RSVD
575R0x00RSVD
RSVD576R0x80RSVD
577R0x00RSVD
RSVD578R0x80RSVD
579R0x00RSVD
RSVD57AR0x80RSVD
57BR0x00RSVD
VCELL6_HI/LO57CR0x80RESULT[7:0]
57DR0x00RESULT[7:0]
VCELL5_HI/LO57ER0x80RESULT[7:0]
57FR0x00RESULT[7:0]
VCELL4_HI/LO580R0x80RESULT[7:0]
581R0x00RESULT[7:0]
VCELL3_HI/LO582R0x80RESULT[7:0]
583R0x00RESULT[7:0]
VCELL2_HI/LO584R0x80RESULT[7:0]
585R0x00RESULT[7:0]
VCELL1_HI/LO586R0x80RESULT[7:0]
587R0x00RESULT[7:0]
MAIN_CURRENT_HI/LO588R0x80RESULT[7:0]
589R0x00RESULT[7:0]
TSREF_HI/LO58CR0x80RESULT[7:0]
58DR0x00RESULT[7:0]
GPIO1_HI/LO58ER0x80RESULT[7:0]
58FR0x00RESULT[7:0]
GPIO2_HI/LO590R0x80RESULT[7:0]
591R0x00RESULT[7:0]
GPIO3_HI/LO592R0x80RESULT[7:0]
593R0x00RESULT[7:0]
GPIO4_HI/LO594R0x80RESULT[7:0]
595R0x00RESULT[7:0]
GPIO5_HI/LO596R0x80RESULT[7:0]
597R0x00RESULT[7:0]
GPIO6_HI/LO598R0x80RESULT[7:0]
599R0x00RESULT[7:0]
GPIO7_HI/LO59AR0x80RESULT[7:0]
59BR0x00RESULT[7:0]
GPIO8_HI/LO59CR0x80RESULT[7:0]
59DR0x00RESULT[7:0]
DIETEMP1_HI/LO5AER0x80RESULT[7:0]
5AFR0x00RESULT[7:0]
DIETEMP2_HI/LO5B0R0x80RESULT[7:0]
5B1R0x00RESULT[7:0]
AUX_CELL_HI/LO5B2R0x80RESULT[7:0]
5B3R0x00RESULT[7:0]
AUX_GPIO_HI/LO5B4R0x80RESULT[7:0]
5B5R0x00RESULT[7:0]
AUX_BAT_HI/LO5B6R0x80RESULT[7:0]
5B7R0x00RESULT[7:0]
AUX_REFL_HI/LO5B8R0x80RESULT[7:0]
5B9R0x00RESULT[7:0]
AUX_VBG2_HI/LO5BAR0x80RESULT[7:0]
5BBR0x00RESULT[7:0]
AUX_AVAO_REF_HI/LO5BER0x80RESULT[7:0]
5BFR0x00RESULT[7:0]
AUX_AVDD_REF_HI/LO5C0R0x80RESULT[7:0]
5C1R0x00RESULT[7:0]
AUX_OV_DAC_HI/LO5C2R0x80RESULT[7:0]
5C3R0x00RESULT[7:0]
AUX_UV_DAC_HI/LO5C4R0x80RESULT[7:0]
5C5R0x00RESULT[7:0]
AUX_OT_OTCB_DAC_HI/LO5C6R0x80RESULT[7:0]
5C7R0x00RESULT[7:0]
AUX_UT_DAC_HI/LO5C8R0x80RESULT[7:0]
5C9R0x00RESULT[7:0]
AUX_VCBDONE_DAC_HI/LO5CAR0x80RESULT[7:0]
5CBR0x00RESULT[7:0]
AUX_VCM_HI/LO5CCR0x80RESULT[7:0]
5CDR0x00RESULT[7:0]
REFOVDAC_HI/LO5D0R0x00RESULT[7:0]
5D1R0x00RESULT[7:0]
DIAG_MAIN_HI/LO5D2R0x00RESULT[7:0]
5D3R0x00RESULT[7:0]
DIAG_AUX_HI/LO5D4R0x00RESULT[7:0]
5D5R0x00RESULT[7:0]
CURRENT_HI/MID/LO5D6R0x80RESULT[7:0]
5D7R0x00RESULT[7:0]
5D8R0x00RESULT[7:0]
REG_INT_RSVD780R0x33INTERNAL USE. IGNORE VALUE FROM THIS ADDRESS
DEBUG_UART_RC781R0x00RSVDRC_IERRRC_ TXDISRC_SOFRC_ BYTE_ ERRRC_ UNEXPRC_CRC
DEBUG_UART_RR_TR782R0x00RSVDTR_SOFTR_WAITRR_SOFRR_ BYTE_ ERRRR_CRC
DEBUG_UART_DISCARD789R0x00COUNT[7:0]
DEBUG_UART_VALID_HI/LO78CR0x00COUNT[7:0]
78DR0x00COUNT[7:0]
DEBUG_OTP_SEC_BLK7A0R0x00BLOCK[7:0]
DEBUG_OTP_DED_BLK7A1R0x00BLOCK[7:0]