SWRU626 December   2025 CC3501E , CC3551E

 

  1.   1
  2. 1 Read This First
    1. 1.1 About This Manual
    2. 1.2 Register, Field, and Bit Calls
    3.     Trademarks
  3. 2 Architecture Overview
    1. 2.1  Target Applications
    2. 2.2  Introduction
    3. 2.3  Internal System Diagram
    4. 2.4  Arm Cortex M33
      1. 2.4.1 Processor Core
      2. 2.4.2 SysTick Timer
      3. 2.4.3 Nested Vectored Interrupt Controller
      4. 2.4.4 System Control Block (SCB)
      5. 2.4.5 TI AI instruction extensions
    5. 2.5  Power Management
      1. 2.5.1 VDD_MAIN
      2. 2.5.2 VDD_IO
      3. 2.5.3 VDDSF
      4. 2.5.4 VDD_PA
    6. 2.6  Debug Subsystem (DEBUGSS)
    7. 2.7  Memory Subsystem (MEMSS)
      1. 2.7.1 External Memory Interface
    8. 2.8  Hardware Security Module
    9. 2.9  General Purpose Timers (GPT)
    10. 2.10 Real Time Clock (RTC)
    11. 2.11 Direct Memory Access
    12. 2.12 GPIOs
    13. 2.13 Communication Peripherals
      1. 2.13.1 UART
      2. 2.13.2 I2C
      3. 2.13.3 SPI
      4. 2.13.4 I2S
      5. 2.13.5 SDMMC
      6. 2.13.6 SDIO
      7. 2.13.7 CAN
      8. 2.13.8 ADC
  4. 3  Arm Cortex-M33 Processor
    1. 3.1 Arm Cortex-M33 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 M33 instantiation parameters
    4. 3.4 Arm Cortex-M33 System Peripheral Details
      1. 3.4.1 Floating Point Unit (FPU)
      2. 3.4.2 Memory Protection Unit (MPU)
      3. 3.4.3 Digital Signal Processing (DSP)
      4. 3.4.4 Security Attribution Unit (SAU)
      5. 3.4.5 System Timer
      6. 3.4.6 Nested Vectored Interrupt Controller
      7. 3.4.7 System Control Block
      8. 3.4.8 System Control Space
    5. 3.5 CPU Sub-System Peripheral Details
      1. 3.5.1 Trace Port Interface Unit (TPIU)
      2. 3.5.2 DAP Bridge and Debug Authentication
      3. 3.5.3 Implementation Defined Attribution Unit (IDAU)
    6. 3.6 Programming Model
      1. 3.6.1 Modes of operation and execution
        1. 3.6.1.1 Security states
        2. 3.6.1.2 Operating modes
        3. 3.6.1.3 Operating states
        4. 3.6.1.4 Privileged access and unprivileged user access
      2. 3.6.2 Instruction set summary
      3. 3.6.3 Memory model
        1. 3.6.3.1 Private Peripheral Bus
        2. 3.6.3.2 Unaligned accesses
      4. 3.6.4 Processor core registers summary
      5. 3.6.5 Exceptions
        1. 3.6.5.1 Exception handling and prioritization
    7. 3.7 TrustZone-M
      1. 3.7.1 Overview
      2. 3.7.2 M33 Configuration
      3. 3.7.3 Description of elements
        1. 3.7.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 3.7.3.1.1 Expected use
    8. 3.8 CC35xx Host MCU Registers
      1. 3.8.1 HOSTMCU_AON Registers
      2. 3.8.2 HOST_MCU Registers
      3. 3.8.3 HOST_MCU_SEC Registers
    9. 3.9 Arm® Cortex®-M33 Registers
      1. 3.9.1  CPU_ROM_TABLE Registers
      2. 3.9.2  TPIU Registers
      3. 3.9.3  DCB Registers
      4. 3.9.4  DIB Registers
      5. 3.9.5  DWT Registers
      6. 3.9.6  FPB Registers
      7. 3.9.7  FPE Registers
      8. 3.9.8  ICB Registers
      9. 3.9.9  ITM Registers
      10. 3.9.10 MPU Registers
      11. 3.9.11 NVIC Registers
      12. 3.9.12 SAU Registers
      13. 3.9.13 SCB Registers
      14. 3.9.14 SYSTIMER Registers
      15. 3.9.15 SYSTICK Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation to HardFault
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Manager
      1. 5.4.1 Introduction
      2. 5.4.2 Interrupts List
      3. 5.4.3 Wakeup Sources
      4. 5.4.4 Shared Peripherals MUX Selector
        1. 5.4.4.1 ADC HW Event Selector Mux
        2. 5.4.4.2 I2S HW Event Selector Mux
        3. 5.4.4.3 PDM HW Event Selector Mux
      5. 5.4.5 Timers MUX Selector Mux
        1. 5.4.5.1 SysTimer0 HW Event Selector Mux
        2. 5.4.5.2 SysTimer1 HW Event Selector Mux
        3. 5.4.5.3 RTC HW Event Selector Mux
      6. 5.4.6 GPTIMERs MUX Selector Mux
        1. 5.4.6.1 GPTIMER0 HW Event Selector Mux
        2. 5.4.6.2 GPTIMER1 HW Event Selector Mux
    5. 5.5 SOC_IC Registers
    6. 5.6 SOC_AON Registers
    7. 5.7 SOC_AAON Registers
  7. 6 Debug Subsystem (DEBUGSS)
    1. 6.1 Introduction
    2. 6.2 Block Diagram
    3. 6.3 Overview
    4. 6.4 Physical Interface
    5. 6.5 Debug Access Ports
    6. 6.6 Debug Features
      1. 6.6.1 Processor Debug
      2. 6.6.2 Breakpoint Unit (BPU)
      3. 6.6.3 Peripheral Debug
    7. 6.7 Behavior in Low Power Modes
    8. 6.8 Debug Access Control
    9. 6.9 SOC_DEBUGSS Registers
  8. 7 Power, Reset, Clock Management
    1. 7.1 Power Management
      1. 7.1.1 Power Supply System
        1. 7.1.1.1 VDD_MAIN
        2. 7.1.1.2 VIO
        3. 7.1.1.3 VDDSF
        4. 7.1.1.4 VPA
      2. 7.1.2 Power States
      3. 7.1.3 Power Domains
      4. 7.1.4 Brownout (BOR)
      5. 7.1.5 Boot Sequence
    2. 7.2 Reset
      1. 7.2.1 Reset Cause
      2. 7.2.2 Watchdog Timer (WDT)
    3. 7.3 Clocks
      1. 7.3.1 Fast Clock
      2. 7.3.2 Slow Clock
        1. 7.3.2.1 Slow Clock Overview
        2. 7.3.2.2 Slow Clock Tree
        3. 7.3.2.3 Slow Clock Boot Process
    4. 7.4 PRCM_AON Registers
    5. 7.5 PRCM_SCRATCHPAD Registers
  9. 8 Memory Subsystem (MEMSS)
    1. 8.1  Introduction
    2. 8.2  SRAM
    3. 8.3  D-Cache
    4. 8.4  Flash
    5. 8.5  PSRAM
    6. 8.6  XiP Memory Access
      1. 8.6.1 OTFDE
      2. 8.6.2 xSPI
      3. 8.6.3 Topology
      4. 8.6.4 µDMA
      5. 8.6.5 Arbiter
    7. 8.7  ICACHE Registers
    8. 8.8  DCACHE Registers
    9. 8.9  OSPI Registers
    10. 8.10 HOST_XIP Registers
  10. 9 Hardware Security Module (HSM)
    1. 9.1 Introduction
    2. 9.2 Overview
    3. 9.3 Mailbox and Register Access Firewall
    4. 9.4 DMA Firewall
    5. 9.5 HSM Key Storage
    6. 9.6 HSM Registers
    7. 9.7 HSM_NON_SEC Registers
    8. 9.8 HSM_SEC Registers
  11. 10Device Boot and Bootloader
    1. 10.1 CC35xx Boot Concept
    2. 10.2 Features
    3. 10.3 Vendor Images Format and Processing
      1. 10.3.1 External Flash Arrangement
      2. 10.3.2 Vendor Images Format
    4. 10.4 Boot Flows
      1. 10.4.1 Application Execution Boot Flow
      2. 10.4.2 Activation Flow
      3. 10.4.3 Initial Programming Flow
      4. 10.4.4 Reprogramming Flow
      5. 10.4.5 Wireless Connectivity Testing Tool Flow
    5. 10.5 Chain of Trust
  12. 11Direct Memory Access (DMA)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Channels Assignment
      2. 11.3.2 Transfer Types
      3. 11.3.3 Addressing Modes
      4. 11.3.4 Transfer Modes
      5. 11.3.5 DMA Aligner Support
      6. 11.3.6 Initiating DMA Transfers
      7. 11.3.7 Stopping DMA Transfers
      8. 11.3.8 Channel Priorities
      9. 11.3.9 DMA Interrupts
    4. 11.4 HOST_DMA Registers
  13. 12One Time Programming (OTP)
  14. 13General Purpose Timers (GPT)
    1. 13.1 Overview
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1  Prescaler
      2. 13.3.2  Counter
      3. 13.3.3  Target
      4. 13.3.4  Channel Input Logic
      5. 13.3.5  Channel Output Logic
      6. 13.3.6  Channel Actions
        1. 13.3.6.1 Period and Pulse Width Measurement
        2. 13.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 13.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 13.3.7  Channel Capture Configuration
      8. 13.3.8  Channel Filters
        1. 13.3.8.1 Setting up the Channel Filters
      9. 13.3.9  Synchronize Multiple GPTimers
      10. 13.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 13.4 Timer Modes
      1. 13.4.1 Quadrature Decoder
      2. 13.4.2 DMA
      3. 13.4.3 IR Generation
      4. 13.4.4 Fault and Park
      5. 13.4.5 Dead-Band
      6. 13.4.6 Dead-Band, Fault and Park
      7. 13.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 13.5 GPTIMER Registers
  15. 14System Timer (SysTimer)
    1. 14.1 Overview
    2. 14.2 Block Diagram
    3. 14.3 Functional Description
      1. 14.3.1 Common Channel Features
        1. 14.3.1.1 Compare Mode
        2. 14.3.1.2 Capture Mode
        3. 14.3.1.3 Additional Channel Arming Methods
      2. 14.3.2 Interrupts and Events
    4. 14.4 SYSRESOURCES Registers
    5. 14.5 SYSTIM Registers
  16. 15Real-Time Clock (RTC)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Interrupts and Events
      1. 15.3.1 Input Event
      2. 15.3.2 Output Event
      3. 15.3.3 Arming and Disarming Channels
    4. 15.4 CAPTURE and COMPARE Configurations
      1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
    5. 15.5 RTC Registers
  17. 16General Purpose Input/Output (GPIOs)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 I/O Mapping and Configuration
      1. 16.3.1 Basic I/O Mapping
      2. 16.3.2 Pin Mapping
    4. 16.4 Edge Detection
    5. 16.5 GPIO
    6. 16.6 I/O Pins
    7. 16.7 Unused Pins
    8. 16.8 IOMUX Registers
  18. 17Universal Asynchronous Receivers/Transmitters (UART)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 UART Functional Description
      1. 17.3.1 Transmit and Receive Logic
      2. 17.3.2 Baud Rate Generation
      3. 17.3.3 FIFO Operation
        1. 17.3.3.1 FIFO Remapping
      4. 17.3.4 Data Transmission
      5. 17.3.5 Flow Control
      6. 17.3.6 IrDA Encoding and Decoding
      7. 17.3.7 Interrupts
      8. 17.3.8 Loopback Operation
    4. 17.4 UART-LIN Specification
      1. 17.4.1 Break transmission in UART mode
      2. 17.4.2 Break reception in UART mode
      3. 17.4.3 Break/Synch transmission in LIN mode
      4. 17.4.4 Break/Synch reception in LIN mode
      5. 17.4.5 Dormant mode operation
      6. 17.4.6 Event signal generation
      7. 17.4.7 Event signal detection when device is in active/idle modes
      8. 17.4.8 Event signal detection when device is in sleep mode
    5. 17.5 Interface to Host DMA
    6. 17.6 Initialization and Configuration
    7. 17.7 UART Registers
  19. 18Serial Peripheral Interface (SPI)
    1. 18.1 Overview
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Signal Description
    3. 18.3 Functional Description
      1. 18.3.1  Clock Control
      2. 18.3.2  FIFO Operation
        1. 18.3.2.1 Transmit FIFO
        2. 18.3.2.2 Repeated Transmit Operation
        3. 18.3.2.3 Receive FIFO
        4. 18.3.2.4 FIFO Flush
      3. 18.3.3  Interrupts
      4. 18.3.4  Data Format
      5. 18.3.5  Delayed Data Sampling
      6. 18.3.6  Chip Select Control
      7. 18.3.7  Command Data Control
      8. 18.3.8  Protocol Descriptions
        1. 18.3.8.1 Motorola SPI Frame Format
        2. 18.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 18.3.8.3 MICROWIRE Frame Format
      9. 18.3.9  CRC Configuration
      10. 18.3.10 Auto CRC Functionality
      11. 18.3.11 SPI Status
      12. 18.3.12 Debug Halt
    4. 18.4 Host DMA Operation
    5. 18.5 Initialization and Configuration
    6. 18.6 SPI Registers
  20. 19Inter-Integrated Circuit (I2C) Interface
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Clock Control
        1. 19.3.1.1 Internal Clock
        2. 19.3.1.2 External Clock
      2. 19.3.2 General Architecture
        1. 19.3.2.1  Start and Stop Conditions
        2. 19.3.2.2  Data Format with 7-Bit Address
        3. 19.3.2.3  Data Format with 10-Bit Addressing
          1. 19.3.2.3.1 Additional 10-Bit Scenarios
        4. 19.3.2.4  Acknowledge
        5. 19.3.2.5  Repeated Start
        6. 19.3.2.6  Clock Stretching
        7. 19.3.2.7  Arbitration
        8. 19.3.2.8  Multi-Controller mode
        9. 19.3.2.9  Glitch Suppression
        10. 19.3.2.10 FIFO Operation
        11. 19.3.2.11 Burst Mode Operation
        12. 19.3.2.12 DMA Operation
        13. 19.3.2.13 Flush Stale Tx Data in Target Mode
          1. 19.3.2.13.1 Recommended Sequence
        14. 19.3.2.14 SMBUS 3.0 Support
          1. 19.3.2.14.1 Quick Command
          2. 19.3.2.14.2 Acknowledge Control
          3. 19.3.2.14.3 Alert Response protocol
          4. 19.3.2.14.4 Address Resolution Protocol
          5. 19.3.2.14.5 Enhanced Acknowledge Control
    4. 19.4 Initialization and Configuration
    5. 19.5 Interrupts
    6. 19.6 I2C Registers
  21. 20Secure Digital Multimedia Card (SDMMC)
    1. 20.1 Introduction
      1. 20.1.1 SDMMC Features
      2. 20.1.2 Integration
    2. 20.2 Functional Description
      1. 20.2.1  SDMMC Functional Modes
        1. 20.2.1.1 SDMMC Connected to an SD Card
        2. 20.2.1.2 Protocol and Data Format
          1. 20.2.1.2.1 Protocol
          2. 20.2.1.2.2 Data Format
      2. 20.2.2  SD Card Feedback
      3. 20.2.3  Resets
        1. 20.2.3.1 Hardware Reset
        2. 20.2.3.2 Software Reset
      4. 20.2.4  Interrupt Requests
        1. 20.2.4.1 Interrupt-Driven Operation
        2. 20.2.4.2 Polling
      5. 20.2.5  DMA Modes
        1. 20.2.5.1 DMA Peripheral Mode Operations
          1. 20.2.5.1.1 DMA Receive Mode
          2. 20.2.5.1.2 DMA Transmit Mode
      6. 20.2.6  Buffer Management
        1. 20.2.6.1 Data Buffer
          1. 20.2.6.1.1 Memory Size and Block Length
          2. 20.2.6.1.2 Data Buffer Status
      7. 20.2.7  Transfer Process
        1. 20.2.7.1 Different Types of Commands
        2. 20.2.7.2 Different Types of Responses
      8. 20.2.8  Transfer or Command Status and Error Reporting
        1. 20.2.8.1 Busy Timeout for R1b, R5b Response Type
        2. 20.2.8.2 Busy Timeout After Write CRC Status
        3. 20.2.8.3 Write CRC Status Timeout
        4. 20.2.8.4 Read Data Timeout
      9. 20.2.9  Auto Command 12 Timings
        1. 20.2.9.1 Auto Command 12 Timings During Write Transfer
        2. 20.2.9.2 Auto Command 12 Timings During Read Transfer
      10. 20.2.10 Transfer Stop
      11. 20.2.11 Output Signals Generation
        1. 20.2.11.1 Generation on Falling Edge of SDMMC Clock
        2. 20.2.11.2 Generation on Rising Edge of SDMMC Clock
      12. 20.2.12 Test Registers
      13. 20.2.13 SDMMC Hardware Status Features
    3. 20.3 Low-Level Programming Models
      1. 20.3.1 SDMMC Initialization Flow
        1. 20.3.1.1 Enable OCP and CLKADPI Clocks
        2. 20.3.1.2 SD Soft Reset Flow
        3. 20.3.1.3 Set SD Default Capabilities
        4. 20.3.1.4 SDMMC Host and Bus Configuration
      2. 20.3.2 Operational Modes Configuration
        1. 20.3.2.1 Basic Operations for SDMMC
        2. 20.3.2.2 Card Detection, Identification, and Selection
    4. 20.4 SDMMC Registers
  22. 21Secure Digital Input/Output (SDIO)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 SDIO Interface Description
      2. 21.3.2 Protocol and Data Format
      3. 21.3.3 I/O Read/Write Command
        1. 21.3.3.1 IO_WR_DIRECT Command (CMD52)
        2. 21.3.3.2 IO_WR_EXTENDED Command (CMD53)
      4. 21.3.4 Reset
      5. 21.3.5 FIFO Operation
        1. 21.3.5.1 Rx FIFO (For Host Write)
        2. 21.3.5.2 Tx FIFO (For Host Read)
      6. 21.3.6 Interrupt Request
        1. 21.3.6.1 External Host IRQ
        2. 21.3.6.2 M33 IRQ
      7. 21.3.7 Transaction Details
        1. 21.3.7.1 Host write to SDIO IP (Rx FIFO)
          1. 21.3.7.1.1 Host write to SDIO IP (Rx FIFO) – Long SW latency case
          2. 21.3.7.1.2 Host write to SDIO IP (Rx FIFO) – CRC Error Case
        2. 21.3.7.2 Host reads from SDIO (TX buffer)
    4. 21.4 SDIO_CORE Registers
    5. 21.5 SDIO_CARD_FN1 Registers
  23. 22Inter-Integrated Circuit Sound (I2S)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  Signal Descriptions
    4. 22.4  Functional Description
      1. 22.4.1 Pin Configuration
      2. 22.4.2 Serial Format Configuration
        1. 22.4.2.1 Register Configuration
      3. 22.4.3 Left-Justified (LJF)
        1. 22.4.3.1 Register Configuration
      4. 22.4.4 Right-Justified (RJF)
        1. 22.4.4.1 Register Configuration
      5. 22.4.5 DSP
        1. 22.4.5.1 Register Configuration
      6. 22.4.6 Clock Configuration
    5. 22.5  Memory Interface
      1. 22.5.1 Sample Word Length
      2. 22.5.2 Padding Mechanism
      3. 22.5.3 Channel Mapping
      4. 22.5.4 Sample Storage in Memory
      5. 22.5.5 DMA Operation
        1. 22.5.5.1 Start-Up
        2. 22.5.5.2 Operation
        3. 22.5.5.3 Shutdown
    6. 22.6  Samplestamp Generator
      1. 22.6.1 Samplestamp Counters
      2. 22.6.2 Start-Up Triggers
      3. 22.6.3 Samplestamp Capture
      4. 22.6.4 Achieving constant audio latency
    7. 22.7  Error Detection
    8. 22.8  Usage
      1. 22.8.1 Start-Up Sequence
      2. 22.8.2 Shutdown Sequence
    9. 22.9  I2S Configuration Guideline
    10. 22.10 I2S Registers
  24. 23Pulse Density Modulation (PDM)
    1. 23.1  Introduction
    2. 23.2  Block Diagram
    3. 23.3  Input Selection
      1. 23.3.1 PDM Data Mode
      2. 23.3.2 Manchester Input Mode
    4. 23.4  CIC Filter
      1. 23.4.1 Filter Design
      2. 23.4.2 Digital Filter Output
      3. 23.4.3 Offset Binary Mode
      4. 23.4.4 Twos-Complement Mode
    5. 23.5  FIFO Organization in Different Modes
      1. 23.5.1 Single Mono Microphone Configuration
        1. 23.5.1.1 24-bit Sample Size
          1. 23.5.1.1.1 32-bit Data Read
        2. 23.5.1.2 16-bit Sample Size
          1. 23.5.1.2.1 32-bit Data Read
          2. 23.5.1.2.2 16-bit Data Read
        3. 23.5.1.3 8-bit Sample Size
          1. 23.5.1.3.1 32-bit Data Read
          2. 23.5.1.3.2 16-bit Data Read
          3. 23.5.1.3.3 8-bit Data Read
      2. 23.5.2 Stereo or Dual Mono Microphone Configuration
        1. 23.5.2.1 24-bit Sample Size
          1. 23.5.2.1.1 32-bit Data Read
        2. 23.5.2.2 16-bit Sample Size
          1. 23.5.2.2.1 32-bit Data Read
          2. 23.5.2.2.2 16-bit Data Read
        3. 23.5.2.3 8-bit Sample Size
          1. 23.5.2.3.1 32-bit Data Read
          2. 23.5.2.3.2 16-bit Data Read
          3. 23.5.2.3.3 8-bit Data Read
      3. 23.5.3 FIFO Threshold Setting
      4. 23.5.4 Reset FIFO
    6. 23.6  Automatic Gain Control (AGC)
      1. 23.6.1 Operation in 2's Complement Format
      2. 23.6.2 Operation in Offset Binary Format
    7. 23.7  Interrupts
    8. 23.8  Clock Select and Control
    9. 23.9  DMA Operation
    10. 23.10 Samplestamp Generator
      1. 23.10.1 Samplestamp Counters
      2. 23.10.2 Start-Up Triggers
      3. 23.10.3 Samplestamp Capture
      4. 23.10.4 Achieving Constant Audio Latency
    11. 23.11 Debug‑Mode Flag Behavior
    12. 23.12 Software Guidelines
    13. 23.13 PDM Registers
  25. 24Analog to Digital Converter (ADC)
    1. 24.1 Overview
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1  ADC Core
      2. 24.3.2  Voltage Reference Options
      3. 24.3.3  Internal Channels
      4. 24.3.4  Resolution Modes
      5. 24.3.5  ADC Clocking
      6. 24.3.6  Power Down Behavior
      7. 24.3.7  Sampling Trigger Sources and Sampling Modes
        1. 24.3.7.1 AUTO Sampling Mode
        2. 24.3.7.2 MANUAL Sampling Mode
      8. 24.3.8  Sampling Period
      9. 24.3.9  Conversion Modes
      10. 24.3.10 ADC Data Format
      11. 24.3.11 Status Register
      12. 24.3.12 ADC Events
        1. 24.3.12.1 Generic Event Publishers (INT_EVENT0 & INT_EVENT1)
        2. 24.3.12.2 DMA Trigger Event Publisher (INT_EVENT2)
        3. 24.3.12.3 Generic Event Subscriber
      13. 24.3.13 Advanced Features
        1. 24.3.13.1 Window Comparator
        2. 24.3.13.2 DMA & FIFO Operation
          1. 24.3.13.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
          2. 24.3.13.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
          3. 24.3.13.2.3 DMA/CPU Operation Summary Matrix
        3. 24.3.13.3 Ad-hoc Single Conversion
    4. 24.4 ADC Registers
  26. 25Controller Area Network (CAN)
    1. 25.1 Introduction
    2. 25.2 Functions
    3. 25.3 DCAN Subsystem
    4. 25.4 DCAN Functional Description
      1. 25.4.1 Operating Modes
        1. 25.4.1.1 Software Initialization
        2. 25.4.1.2 Normal Operation
        3. 25.4.1.3 Restricted Operation Mode
        4. 25.4.1.4 Bus Monitoring Mode
        5. 25.4.1.5 Disabled Automatic Retransmission
          1. 25.4.1.5.1 Frame Transmission in DAR Mode
        6. 25.4.1.6 Power Down (Sleep Mode)
          1. 25.4.1.6.1 DCAN clock stop and wake operations
          2. 25.4.1.6.2 DCAN debug suspend operation
        7. 25.4.1.7 Test Modes
          1. 25.4.1.7.1 External Loop Back Mode
          2. 25.4.1.7.2 Internal Loop Back Mode
      2. 25.4.2 Timestamp Generation
        1. 25.4.2.1 Block Diagram
      3. 25.4.3 Timeout Counter
      4. 25.4.4 Rx Handling
        1. 25.4.4.1 Acceptance Filtering
          1. 25.4.4.1.1 Range Filter
          2. 25.4.4.1.2 Filter for specific IDs
          3. 25.4.4.1.3 Classic Bit Mask Filter
          4. 25.4.4.1.4 Standard Message ID Filtering
          5. 25.4.4.1.5 Extended Message ID Filtering
        2. 25.4.4.2 Rx FIFOs
          1. 25.4.4.2.1 Rx FIFO Blocking Mode
          2. 25.4.4.2.2 Rx FIFO Overwrite Mode
        3. 25.4.4.3 Dedicated Rx Buffers
          1. 25.4.4.3.1 Rx Buffer Handling
        4. 25.4.4.4 Debug on CAN Support
          1. 25.4.4.4.1 Filtering for Debug Messages
          2. 25.4.4.4.2 Debug Message Handling
      5. 25.4.5 Tx Handling
        1. 25.4.5.1 Transmit Pause
        2. 25.4.5.2 Dedicated Tx Buffers
        3. 25.4.5.3 Tx FIFO
        4. 25.4.5.4 Tx Queue
        5. 25.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 25.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 25.4.5.7 Transmit Cancellation
        8. 25.4.5.8 Tx Event Handling
      6. 25.4.6 FIFO Acknowledge Handling
      7. 25.4.7 DCAN Message RAM
        1. 25.4.7.1 Message RAM Configuration
        2. 25.4.7.2 Rx Buffer and FIFO Element
        3. 25.4.7.3 Tx Buffer Element
        4. 25.4.7.4 Tx Event FIFO Element
        5. 25.4.7.5 Standard Message ID Filter Element
        6. 25.4.7.6 Extended Message ID Filter Element
      8. 25.4.8 Interrupt Requests
    5. 25.5 DCAN Wrapper
    6. 25.6 DCAN Clock Enable
    7. 25.7 DCAN Registers
  27. 26Revision History

8.9 OSPI Registers

Table 8-34 lists the memory-mapped registers for the OSPI registers. All register offset addresses not listed in Table 8-34 should be considered as reserved locations and the register contents should not be modified.

Table 8-34 OSPI Registers
OffsetAcronymRegister NameSection
0hCONFIGConfiguration RegisterSection 8.9.1
4hDEV_INSTR_RD_CONFIGRead Instruction ConfigurationSection 8.9.2
8hDEV_INSTR_WR_CONFIGDevice Write Instruction Configuration RegisterSection 8.9.3
ChDEV_DELAYDevice Delay ControlSection 8.9.4
10hRD_DATA_CAPTUREData CaptureSection 8.9.5
14hDEV_SIZE_CONFIGMemory Size ConfigurationSection 8.9.6
18hSRAM_PARTITION_CFGMemory Partition ControlSection 8.9.7
1ChIND_AHB_ADDR_TRIGGERIndirect Address TriggerSection 8.9.8
20hDMA_PERIPH_CONFIGPeripheral ConfigurationSection 8.9.9
24hREMAP_ADDRAddress RemappingSection 8.9.10
28hMODE_BIT_CONFIGMode ConfigurationSection 8.9.11
2ChSRAM_FILLMemory Fill StatusSection 8.9.12
30hTX_THRESHTransmit ThresholdSection 8.9.13
34hRX_THRESHReceive ThresholdSection 8.9.14
38hWRITE_COMPLETION_CTRLWrite Polling ControlSection 8.9.15
3ChNO_OF_POLLS_BEF_EXPPolling Expiration RegisterSection 8.9.16
40hIRQ_STATUSInterrupt StatusSection 8.9.17
44hIRQ_MASKInterrupt Enable ControlSection 8.9.18
50hLOWER_WR_PROTWrite ProtectionSection 8.9.19
54hUPPER_WR_PROTWrite Protection ControlSection 8.9.20
58hWR_PROT_CTRLWrite Protection ControlSection 8.9.21
60hINDIRECT_READ_XFER_CTRLTransfer ControlSection 8.9.22
64hINDIRECT_READ_XFER_WATERMARKIndirect Read Transfer Watermark RegisterSection 8.9.23
68hINDIRECT_READ_XFER_STARTIndirect Read Transfer Start Address RegisterSection 8.9.24
6ChINDIRECT_READ_XFER_NUM_BYTESTransfer SizeSection 8.9.25
70hINDIRECT_WRITE_XFER_CTRLTransfer ControlSection 8.9.26
74hINDIRECT_WRITE_XFER_WATERMARKTransfer WatermarkSection 8.9.27
78hINDIRECT_WRITE_XFER_STARTTransfer Start AddressSection 8.9.28
7ChINDIRECT_WRITE_XFER_NUM_BYTESTransfer Byte CountSection 8.9.29
80hINDIRECT_TRIGGER_ADDR_RANGEAddress Range ControlSection 8.9.30
8ChFLASH_COMMAND_CTRL_MEMCommand ControlSection 8.9.31
90hFLASH_CMD_CTRLCommand ControlSection 8.9.32
94hFLASH_CMD_ADDRCommand AddressSection 8.9.33
A0hFLASH_RD_DATA_LOWERFlash Read DataSection 8.9.34
A4hFLASH_RD_DATA_UPPERFlash Command Read Data Register (Upper)Section 8.9.35
A8hFLASH_WR_DATA_LOWERLower Write DataSection 8.9.36
AChFLASH_WR_DATA_UPPERFlash Command Write Data Register (Upper)Section 8.9.37
B0hPOLLING_FLASH_STATUSPolling Flash Status RegisterSection 8.9.38
B4hPHY_CONFIGURATIONPHY ConfigurationSection 8.9.39
B8hPHY_MASTER_CONTROLPHY DLL controller Control RegisterSection 8.9.40
BChDLL_OBSERVABLE_LOWERClock Observable ValuesSection 8.9.41
C0hDLL_OBSERVABLE_UPPERUpper Observable ValuesSection 8.9.42
E0hOPCODE_EXT_LOWERLower Extension ControlSection 8.9.43
E4hOPCODE_EXT_UPPERExtended Instruction UpperSection 8.9.44
FChMODULE_IDModule IdentifierSection 8.9.45

Complex bit access types are encoded to fit into small table cells. Table 8-35 shows the codes that are used for access types in this section.

Table 8-35 OSPI Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

8.9.1 CONFIG Register (Offset = 0h) [Reset = 82080081h]

CONFIG is shown in Table 8-36.

Return to the Summary Table.

Octal-SPI Configuration Register

Table 8-36 CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31IDLER1hSerial interface and low level SPI pipeline is IDLE: This is a STATUS read-only bit. Note this is a retimed signal, so there will be some inherent delay on the generation of this status signal.
  • 0h = Disable
  • 1h = Enable
30DUAL_BYTE_OPCODE_ENR/W0hDual-byte Opcode Mode enable bit This bit is to be set in case the target Flash Device supports dual byte opcode (i.e. Macronix MX25). It is applicable for Octal I/O Mode or Protocol only so should be set back to low if the device is configured to work in another SPI Mode. If enabled, the supplementing bytes are taken from Opcode Extension Register (Lower) and from Opcode Extension Register (Upper).
  • 0h = Disable
  • 1h = Enable
29CRC_ENABLER/W0hCRC enable bit This bit is to be set in case the target Flash Device supports CRC (Macronix MX25). It is applicable for Octal DDR Protocol only so should be set back to low if the device is configured to work in another SPI Mode.
  • 0h = Disable
  • 1h = Enable
28-26RESERVEDR0h
25PIPELINE_PHYR/W1hPipeline PHY Mode enable: This bit is relevant only for configuration with PHY Module. It should be asserted to '1' between consecutive PHY pipeline reads transfers and de-asserted to '0' otherwise.
  • 0h = Disable
  • 1h = Enable
24ENABLE_DTR_PROTOCOLR/W0hEnable DTR Protocol: This bit should be set if device is configured to work in DTR protocol.
  • 0h = Disable
  • 1h = Enable
23ENABLE_AHB_DECODERR/W0hEnable AHB Decoder: Value=0 : Active peripheral is selected based on Peripheral Chip Select Lines (bits [13:10]). Value=1 Active peripheral is selected based on actual AHB address (the partition for each device is calculated with respect to bits [28:21] of Device Size Configuration Register)
  • 0h = Disable
  • 1h = Enable
22-19MSTR_BAUD_DIVR/W1hcontroller Mode Baud Rate Divisor: SPI baud rate = (controller reference clock) baud_rate_divisor. The baud rate is the clock rate divided by 2 multiplied by (Divisor + 1). Meaning, when Divisor Value is set to 0,1,2,..15 it sets the baud rate is the clock rate divided by 2, 4, 6,..32 respectively
  • 0h = Smallest value
  • Fh = Highest possible value
18ENTER_XIP_MODE_IMMR/W0hEnter XIP Mode immediately: Value=0 : If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode immediately Use this register when the external device wakes up in XIP mode (as per the contents of its non- volatile configuration register). The controller will assume the next READ instruction will be passed to the device as an XIP instruction, and therefore will not require the READ opcode to be transferred. Note: To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only after the next READ instruction is executed. Software therefore should ensure that at least one READ instruction is requested after resetting this bit in order to be sure that XIP mode is exited.
  • 0h = Disable
  • 1h = Enable
17ENTER_XIP_MODER/W0hEnter XIP Mode on next READ: Value=0 : If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : If XIP is disabled, then setting to ?1? will inform the controller that the device is ready to enter XIP on the next READ instruction. The controller will therefore send the appropriate command sequence, including mode bits to cause the device to enter XIP mode. Use this register after the controller has ensured the FLASH device has been configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only AFTER the next READ instruction is executed. Software should therefore ensure that at least one READ instruction is requested after resetting this bit before it can be sure XIP mode in the device is exited.
  • 0h = Disable
  • 1h = Enable
16ENB_AHB_ADDR_REMAPR/W0hEnable AHB Address Re-mapping: (Direct Access Mode Only) When set to 1, the incoming AHB address will be adapted and sent to the FLASH device as (address + N), where N is the value stored in the remap address register.
  • 0h = Disable
  • 1h = Enable
15ENB_DMA_IFR/W0hEnable DMA Peripheral Interface: Set to 1 to enable the DMA handshaking logic. When enabled the controller will trigger DMA transfer requests via the DMA peripheral interface. Set to 0 to disable
  • 0h = Disable
  • 1h = Enable
14WR_PROT_FLASHR/W0hWrite Protect Flash Pin: Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary.
  • 0h = Disable
  • 1h = Enable
13-10PERIPH_CS_LINESR/W0hPeripheral Chip Select Lines: Peripheral chip select lines If pdec = 0, ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 (no peripheral selected) else ss[3:0] directly drives n_ss_out[3:0]
  • 0h = Smallest value
  • Fh = Highest possible value
9PERIPH_SEL_DECR/W0hPeripheral select decode:
  • 0h = only 1 of 4 selects n_ss_out[3:0] is active 1 : allow external 4-to-16 decode (n_ss_out = ss)
  • 1h = allow external 4-to-16 decode (n_ss_out = ss)
8ENB_LEGACY_IP_MODER/W0hLegacy IP Mode Enable:
  • 0h = Use Direct Access Controller/Indirect Access Controller 1 : legacy Mode is enabled. In this mode, any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid AHB read will pop the internal RX-FIFO, retrieving data that was forwarded by the external FLASH device on the SPI lines,4,2 or 1 byte transfers are permitted and controlled via the HSIZE input.
  • 1h = legacy Mode is enabled. In this mode, any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid AHB read will pop the internal RX-FIFO, retrieving data that was forwarded by the external FLASH device on the SPI lines,4,2 or 1 byte transfers are permitted and controlled via the HSIZE input.
7ENB_DIR_ACC_CTLRR/W1hEnable Direct Access Controller:
  • 0h = disable the Direct Access Controller once current transfer of the data word (FF_W) is complete. 1 : enable the Direct Access Controller When the Direct Access Controller and Indirect Access Controller are both disabled, all AHB requested are completed with an error response.
  • 1h = enable the Direct Access Controller When the Direct Access Controller and Indirect Access Controller are both disabled, all AHB requested are completed with an error response.
6RESET_CFGR/W0hRESET pin configuration: 0 = RESET feature on DQ3 pin of the device 1 = RESET feature on dedicated pin of the device (controlling of 5th bit influences on reset_out output)
  • 0h = Disable
  • 1h = Enable
5RESET_PINR/W0hSet to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature
  • 0h = Disable
  • 1h = Enable
4HOLD_PINR/W0hSet to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature
  • 0h = Disable
  • 1h = Enable
3PHY_MODE_ENABLER/W0hPHY mode enable: When enabled, the controller is informed that PHY Module is to be used for handling SPI transfers. This bit is relevant only for configuration with PHY Module.
  • 0h = Disable
  • 1h = Enable
2SEL_CLK_PHASER/W0hSelect Clock Phase: Selects whether the clock is in an active or inactive phase outside the SPI word.
  • 0h = the SPI clock is active outside the word 1 : the SPI clock is inactive outside the word
  • 1h = the SPI clock is inactive outside the word
1SEL_CLK_POLR/W0hClock polarity outside SPI word:
  • 0h = the SPI clock is quiescent low 1 : the SPI clock is quiescent high
  • 1h = the SPI clock is quiescent high
0ENB_SPIR/W1hOctal-SPI Enable:
  • 0h = disable the Octal-SPI, once current transfer of the data word (FF_W) is complete. 1 : enable the Octal-SPI, when spi_enable = 0, all output enables are inactive and all pins are set to input mode.
  • 1h = enable the Octal-SPI, when spi_enable = 0, all output enables are inactive and all pins are set to input mode.

8.9.2 DEV_INSTR_RD_CONFIG Register (Offset = 4h) [Reset = 00000003h]

DEV_INSTR_RD_CONFIG is shown in Table 8-37.

Return to the Summary Table.

Device Read Instruction Configuration Register

Table 8-37 DEV_INSTR_RD_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28-24DUMMY_RD_CLK_CYCLESR/W0hDummy Read Clock Cycles: Number of dummy clock cycles required by device for read instruction.
  • 0h = Smallest value
  • 1Fh = Highest possible value
23-21RESERVEDR0h
20MODE_BIT_ENABLER/W0hMode Bit Enable: Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes.
  • 0h = Disable
  • 1h = Enable
19-18RESERVEDR0h
17-16DATA_XFER_TYPE_EXT_MODER/W0hData Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs and outputs. 3 : Used for Quad Input/Output instructions. For data transfers, DQ[7:0] are used as both inputs and outputs.
  • 0h = Smallest value
  • 3h = Highest possible value
15-14RESERVEDR0h
13-12ADDR_XFER_TYPE_STD_MODER/W0hAddress Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0, DQ1, DQ2 and DQ3 3 : Addresses can be shifted to the device on DQ[7:0]
  • 0h = Smallest value
  • 3h = Highest possible value
11PRED_DISR/W0hPredicted Read Disable Bit: Disable generation of predicted read when doing read accesses using Direct Mode
  • 0h = Disable
  • 1h = Enable
10DDR_ENR/W0hDDR Enable: This is to inform that opcode from rd_opcode_non_xip_fld is compliant with one of the DDR READ Commands
  • 0h = Disable
  • 1h = Enable
9-8INSTR_TYPER/W0hInstruction Type: 0 : Use Standard SPI mode (instruction always shifted into the device on DQ0 only) 1 : Use DIO-SPI mode (Instructions always sent on DQ0 and DQ1) 2 : Use QIO-SPI mode (Instructions always sent on DQ0, DQ1, DQ2 and DQ3) 3 : Use Octal-IO-SPI mode (Instructions always sent on DQ[7:0])
  • 0h = Smallest value
  • 3h = Highest possible value
7-0RD_OPCODE_NON_XIPR/W3hRead Opcode in non-XIP mode: Read Opcode to use when not in XIP mode
  • 0h = Smallest value
  • FFh = Highest possible value

8.9.3 DEV_INSTR_WR_CONFIG Register (Offset = 8h) [Reset = 00000002h]

DEV_INSTR_WR_CONFIG is shown in Table 8-38.

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Device Write Instruction Configuration Register

Table 8-38 DEV_INSTR_WR_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28-24DUMMY_WR_CLK_CYCLESR/W0hDummy Write Clock Cycles: Number of dummy clock cycles required by device for write instruction.
  • 0h = Smallest value
  • 1Fh = Highest possible value
23-18RESERVEDR0h
17-16DATA_XFER_TYPE_EXT_MODER/W0hData Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs and outputs. 3 : Used for Quad Input/Output instructions. For data transfers, DQ[7:0] are used as both inputs and outputs.
  • 0h = Smallest value
  • 3h = Highest possible value
15-14RESERVEDR0h
13-12ADDR_XFER_TYPE_STD_MODER/W0hAddress Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0, DQ1, DQ2 and DQ3 3 : Addresses can be shifted to the device on DQ[7:0]
  • 0h = Smallest value
  • 3h = Highest possible value
11-9RESERVEDR0h
8WEL_DISR/W0hWEL Disable: This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC
  • 0h = Disable
  • 1h = Enable
7-0WR_OPCODER/W2h Write Opcode
  • 0h = Smallest value
  • FFh = Highest possible value

8.9.4 DEV_DELAY Register (Offset = Ch) [Reset = 00000000h]

DEV_DELAY is shown in Table 8-39.

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Octal-SPI Device Delay Register: This register is used to introduce relative delays into the generation of the controller output signals. All timings are defined in cycles of the SPI REFERENCE CLOCK/ext_clk, defined in this table as SPI controller ref clock.

Table 8-39 DEV_DELAY Register Field Descriptions
BitFieldTypeResetDescription
31-24D_NSSR/W0hClock Delay for Chip Select Deassert: Delay in controller reference clocks for the length that the controller mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never re-asserted within an SCLK period.
  • 0h = Smallest value
  • FFh = Highest possible value
23-16D_BTWNR/W0hClock Delay for Chip Select Deactivation: Delay in controller reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different peripherals and requires the transmit FIFO to be empty.
  • 0h = Smallest value
  • FFh = Highest possible value
15-8D_AFTERR/W0hClock Delay for Last Transaction Bit: Delay in controller reference clocks between last bit of current transaction and deasserting the device chip select (n_ss_out). By default, the chip select will be deasserted on the cycle following the completion of the current transaction.
  • 0h = Smallest value
  • FFh = Highest possible value
7-0D_INITR/W0hClock Delay with n_ss_out: Delay in controller reference clocks between setting n_ss_out low and first bit transfer.
  • 0h = Smallest value
  • FFh = Highest possible value

8.9.5 RD_DATA_CAPTURE Register (Offset = 10h) [Reset = 00000001h]

RD_DATA_CAPTURE is shown in Table 8-40.

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Read Data Capture Register

Table 8-40 RD_DATA_CAPTURE Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0h
19-16DDR_READ_DELAYR/W0hDDR read delay: Delay the transmitted data by the programmed number of ref_clk cycles.This field is only relevant when DDR Read Command is executed. Otherwise can be ignored.
  • 0h = Smallest value
  • Fh = Highest possible value
15-9RESERVEDR0h
8DQS_ENABLER/W0hDQS enable bit: If enabled, signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated ref_clk..
  • 0h = Disable
  • 1h = Enable
7-6RESERVEDR0h
5SAMPLE_EDGE_SELR/W0hSample edge selection: Choose edge on which data outputs from flash memory will be sampled
  • 0h = Disable
  • 1h = Enable
4-1DELAYR/W0hRead Delay: Delay the read data capturing logic by the programmed number of ref_clk cycles
  • 0h = Smallest value
  • Fh = Highest possible value
0BYPASSR/W1hBypass the adapted loopback clock circuit
  • 0h = Disable
  • 1h = Enable

8.9.6 DEV_SIZE_CONFIG Register (Offset = 14h) [Reset = 00101002h]

DEV_SIZE_CONFIG is shown in Table 8-41.

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Device Size Configuration Register

Table 8-41 DEV_SIZE_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28-27MEM_SIZE_ON_CS3R/W0hSize of Flash Device connected to CS[3] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb.
  • 0h = Smallest value
  • 3h = Highest possible value
26-25MEM_SIZE_ON_CS2R/W0hSize of Flash Device connected to CS[2] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb.
  • 0h = Smallest value
  • 3h = Highest possible value
24-23MEM_SIZE_ON_CS1R/W0hSize of Flash Device connected to CS[1] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb.
  • 0h = Smallest value
  • 3h = Highest possible value
22-21MEM_SIZE_ON_CS0R/W0hSize of Flash Device connected to CS[0] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb.
  • 0h = Smallest value
  • 3h = Highest possible value
20-16BYTES_PER_SUBSECTORR/W10h Number of bytes per Block. This is required by the controller for performing the write protection logic. The number of bytes per block must be a power of 2 number.
  • 0h = Smallest value
  • 1Fh = Highest possible value
15-4BYTES_PER_DEVICE_PAGER/W100h Number of bytes per device page. This is required by the controller for performing FLASH writes up to and across page boundaries.
  • 0h = Smallest value
  • FFFh = Highest possible value
3-0NUM_ADDR_BYTESR/W2hNumber of address bytes. A value of 0 indicates 1 byte.
  • 0h = Smallest value
  • Fh = Highest possible value

8.9.7 SRAM_PARTITION_CFG Register (Offset = 18h) [Reset = 00000080h]

SRAM_PARTITION_CFG is shown in Table 8-42.

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SRAM Partition Configuration Register

Table 8-42 SRAM_PARTITION_CFG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0THRESHOLDR/W80hDefines the size of the indirect read partition in the SRAM, in units of SRAM locations. By default, half of the SRAM is reserved for indirect read operation, and half for indirect write. The size of this register will scale with the depth of the SRAM.

8.9.8 IND_AHB_ADDR_TRIGGER Register (Offset = 1Ch) [Reset = 00000000h]

IND_AHB_ADDR_TRIGGER is shown in Table 8-43.

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Indirect AHB Address Trigger Register

Table 8-43 IND_AHB_ADDR_TRIGGER Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR/W0h This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15, then the AHB request will be completed by fetching data from the Indirect Controllers SRAM.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.9 DMA_PERIPH_CONFIG Register (Offset = 20h) [Reset = 00000000h]

DMA_PERIPH_CONFIG is shown in Table 8-44.

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DMA Peripheral Configuration Register

Table 8-44 DMA_PERIPH_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11-8NUM_BURST_REQ_BYTESR/W0hNumber of Burst Bytes: Number of bytes in a burst type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual number of bytes used is 2**(value in this register) which will simplify implementation.
  • 0h = Smallest value
  • Fh = Highest possible value
7-4RESERVEDR0h
3-0NUM_SINGLE_REQ_BYTESR/W0hNumber of Single Bytes: Number of bytes in a single type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual number of bytes used is 2**(value in this register) which will simplify implementation.
  • 0h = Smallest value
  • Fh = Highest possible value

8.9.10 REMAP_ADDR Register (Offset = 24h) [Reset = 00000000h]

REMAP_ADDR is shown in Table 8-45.

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Remap Address Register

Table 8-45 REMAP_ADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER/W0h This register is used to remap an incoming AHB address to a different address used by the FLASH device.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.11 MODE_BIT_CONFIG Register (Offset = 28h) [Reset = 00000200h]

MODE_BIT_CONFIG is shown in Table 8-46.

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Mode Bit Configuration Register

Table 8-46 MODE_BIT_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-24RX_CRC_DATA_LOWR0hRX CRC data (lower) The first CRC byte returned after RX data chunk.
  • 0h = Smallest value
  • FFh = Highest possible value
23-16RX_CRC_DATA_UPR0hRX CRC data (upper) The second CRC byte returned after RX data chunk.
  • 0h = Smallest value
  • FFh = Highest possible value
15CRC_OUT_ENABLER/W0hCRC# output enable bit When enabled, the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly.
  • 0h = Disable
  • 1h = Enable
14-11RESERVEDR0h
10-8CHUNK_SIZER/W2hIt defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers.
  • 0h = Smallest value
  • 7h = Highest possible value
7-0MODER/W0hThese are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled.
  • 0h = Smallest value
  • FFh = Highest possible value

8.9.12 SRAM_FILL Register (Offset = 2Ch) [Reset = 00000000h]

SRAM_FILL is shown in Table 8-47.

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SRAM Fill Register

Table 8-47 SRAM_FILL Register Field Descriptions
BitFieldTypeResetDescription
31-16SRAM_FILL_INDAC_WRITER0hSRAM Fill Level (Indirect Write Partition): Identifies the current fill level of the SRAM Indirect Write partition
  • 0h = Smallest value
  • FFFFh = Highest possible value
15-0SRAM_FILL_INDAC_READR0hSRAM Fill Level (Indirect Read Partition): Identifies the current fill level of the SRAM Indirect Read partition
  • 0h = Smallest value
  • FFFFh = Highest possible value

8.9.13 TX_THRESH Register (Offset = 30h) [Reset = 00000001h]

TX_THRESH is shown in Table 8-48.

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TX Threshold Register

Table 8-48 TX_THRESH Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h
4-0LEVELR/W1hDefines the level at which the small TX FIFO not full interrupt is generated
  • 0h = Smallest value
  • 1Fh = Highest possible value

8.9.14 RX_THRESH Register (Offset = 34h) [Reset = 00000001h]

RX_THRESH is shown in Table 8-49.

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RX Threshold Register

Table 8-49 RX_THRESH Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h
4-0LEVELR/W1h Defines the level at which the small RX FIFO not empty interrupt is generated
  • 0h = Smallest value
  • 1Fh = Highest possible value

8.9.15 WRITE_COMPLETION_CTRL Register (Offset = 38h) [Reset = 00040005h]

WRITE_COMPLETION_CTRL is shown in Table 8-50.

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Write Completion Control Register: This register defines how the controller will poll the device following a write transfer

Table 8-50 WRITE_COMPLETION_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24POLL_REP_DELAYR/W0hDefines additional delay for maintain Chip Select de-asserted during auto-polling phase
  • 0h = Smallest value
  • FFh = Highest possible value
23-16POLL_COUNTR/W4hDefines the number of times the controller should expect to see a true result from the polling in successive reads of the device register.
  • 0h = Smallest value
  • FFh = Highest possible value
15ENABLE_POLLING_EXPR/W0h Set to '1' for enabling auto-polling expiration.
  • 0h = Disable
  • 1h = Enable
14DISABLE_POLLINGR/W0hThis switches off the automatic polling function
  • 0h = Disable
  • 1h = Enable
13POLLING_POLARITYR/W0hDefines the polling polarity. If '1', then the write transfer to the device will be complete if the polled bit is equal to '1'. If '0', then the write transfer to the device will be complete if the polled bit is equal to '0'.
  • 0h = Disable
  • 1h = Enable
12RESERVEDR0h
11POLLING_ADDR_ENR/W0hEnables address phase of auto-polling (Read Status) command.
  • 0h = Disable
  • 1h = Enable
10-8POLLING_BIT_INDEXR/W0hDefines the bit index that should be polled. A value of 010 means that bit 2 of the returned data will be polled for.A value of 111 means that bit 7 of the returned data will be polled for.
  • 0h = Smallest value
  • 7h = Highest possible value
7-0OPCODER/W5hDefines the opcode that should be issued by the controller when it is automatically polling for device program completion. This command is issued followed all device write operations. By default, this will poll the standard device STATUS register using opcode 0x05
  • 0h = Smallest value
  • FFh = Highest possible value

8.9.16 NO_OF_POLLS_BEF_EXP Register (Offset = 3Ch) [Reset = FFFFFFFFh]

NO_OF_POLLS_BEF_EXP is shown in Table 8-51.

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Polling Expiration Register

Table 8-51 NO_OF_POLLS_BEF_EXP Register Field Descriptions
BitFieldTypeResetDescription
31-0NO_OF_POLLS_BEF_EXPR/WFFFFFFFFhNumber of polls cycles before expiration
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.17 IRQ_STATUS Register (Offset = 40h) [Reset = 00000000h]

IRQ_STATUS is shown in Table 8-52.

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Interrupt Status Register: The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set, the interrupt output is asserted high. The fields are each cleared by writing a 1 to the field. Note that bit fields 6 thru 10 are only valid when legacy SPI mode is active.

Table 8-52 IRQ_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0h
19ECC_FAILR/W1C0hECC failure This interrupt informs the system that Flash Device reported ECC error.
  • 0h = Disable
  • 1h = Enable
18TX_CRC_CHUNK_BRKR/W1C0hTX CRC chunk was broken This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk.
  • 0h = Disable
  • 1h = Enable
17RX_CRC_DATA_VALR/W1C0hRX CRC data valid New RX CRC data was captured from Flash Device
  • 0h = Disable
  • 1h = Enable
16RX_CRC_DATA_ERRR/W1C0hRX CRC data error CRC data from Flash Device does not correspond to the one dynamically calculated by the controller.
  • 0h = Disable
  • 1h = Enable
15RESERVEDR0h
14STIG_REQ_INTR/W1C0h The controller is ready for getting another STIG request.
  • 0h = Disable
  • 1h = Enable
13POLL_EXP_INTR/W1C0h The maximum number of programmed polls cycles is expired
  • 0h = Disable
  • 1h = Enable
12INDRD_SRAM_FULLR/W1C0hIndirect Read Partition overflow: Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation
  • 0h = Disable
  • 1h = Enable
11RX_FIFO_FULLR/W1C0hSmall RX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode
  • 0h = FIFO is not full 1 : FIFO is full
  • 1h = FIFO is full
10RX_FIFO_NOT_EMPTYR/W1C0hSmall RX FIFO not empty: Current FIFO status can be ignored in non-SPI legacy mode
  • 0h = FIFO has less than RX THRESHOLD entries, 1 : FIFO has >= THRESHOLD entries
  • 1h = FIFO has >= THRESHOLD entries
9TX_FIFO_FULLR/W1C0hSmall TX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode
  • 0h = FIFO is not full, 1 : FIFO is full
  • 1h = FIFO is full
8TX_FIFO_NOT_FULLR/W1C0hSmall TX FIFO not full: Current FIFO status can be ignored in non-SPI legacy mode
  • 0h = FIFO has >= THRESHOLD entries, 1 : FIFO has less than THRESHOLD entries
  • 1h = FIFO has less than THRESHOLD entries
7RECV_OVERFLOWR/W1C0hReceive Overflow: This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX FIFO occurs coincident with a register read this flag will remain set.
  • 0h = no overflow has been detected. 1 : an overflow has occurred.
  • 1h = an overflow has occurred.
6INDIRECT_XFER_LEVEL_BREACHR/W1C0hIndirect Transfer Watermark Level Breached
  • 0h = Disable
  • 1h = Enable
5ILLEGAL_ACCESS_DETR/W1C0h Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger.
  • 0h = Disable
  • 1h = Enable
4PROT_WR_ATTEMPTR/W1C0hWrite to protected area was attempted and rejected.
  • 0h = Disable
  • 1h = Enable
3INDIRECT_TRANSFER_REJECTR/W1C0h Indirect operation was requested but could not be accepted. Two indirect operations already in storage.
  • 0h = Disable
  • 1h = Enable
2INDIRECT_OP_DONER/W1C0hIndirect Operation Complete: Controller has completed last triggered indirect operation
  • 0h = Disable
  • 1h = Enable
1UNDERFLOW_DETR/W1C0hUnderflow Detected:
  • 0h = no underflow has been detected 1 : underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with the requested write operation This bit is reset only by a system reset and cleared only when the register is read.
  • 1h = underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with the requested write operation This bit is reset only by a system reset and cleared only when the register is read.
0MODE_M_FAILR/W1C0hMode M Failure: Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in controller mode (multi-controller contention). These conditions will clear the spi_enable bit and disable the SPI. This bit is reset only by a system reset and cleared only when this register is read.
  • 0h = no mode fault has been detected 1 : a mode fault has occurred
  • 1h = a mode fault has occurred

8.9.18 IRQ_MASK Register (Offset = 44h) [Reset = 00000000h]

IRQ_MASK is shown in Table 8-53.

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Interrupt Mask: 0 : the interrupt for the corresponding interrupt status register bit is disabled. 1 : the interrupt for the corresponding interrupt status register bit is enabled.

Table 8-53 IRQ_MASK Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0h
19ECC_FAIL_MASKR/W0hECC failure Mask
  • 0h = Disable
  • 1h = Enable
18TX_CRC_CHUNK_BRK_MASKR/W0hTX CRC chunk was broken Mask
  • 0h = Disable
  • 1h = Enable
17RX_CRC_DATA_VAL_MASKR/W0hRX CRC data valid Mask
  • 0h = Disable
  • 1h = Enable
16RX_CRC_DATA_ERR_MASKR/W0hRX CRC data error Mask
  • 0h = Disable
  • 1h = Enable
15RESERVEDR0h
14STIG_REQ_MASKR/W0hSTIG request completion Mask
  • 0h = Disable
  • 1h = Enable
13POLL_EXP_INT_MASKR/W0hPolling expiration detected Mask
  • 0h = Disable
  • 1h = Enable
12INDRD_SRAM_FULL_MASKR/W0hIndirect Read Partition overflow mask
  • 0h = Disable
  • 1h = Enable
11RX_FIFO_FULL_MASKR/W0hSmall RX FIFO full Mask
  • 0h = Disable
  • 1h = Enable
10RX_FIFO_NOT_EMPTY_MASKR/W0hSmall RX FIFO not empty Mask
  • 0h = Disable
  • 1h = Enable
9TX_FIFO_FULL_MASKR/W0hSmall TX FIFO full Mask
  • 0h = Disable
  • 1h = Enable
8TX_FIFO_NOT_FULL_MASKR/W0hSmall TX FIFO not full Mask
  • 0h = Disable
  • 1h = Enable
7RECV_OVERFLOW_MASKR/W0hReceive Overflow Mask
  • 0h = Disable
  • 1h = Enable
6INDIRECT_XFER_LEVEL_BREACH_MASKR/W0hTransfer Watermark Breach Mask
  • 0h = Disable
  • 1h = Enable
5ILLEGAL_ACCESS_DET_MASKR/W0hIllegal Access Detected Mask
  • 0h = Disable
  • 1h = Enable
4PROT_WR_ATTEMPT_MASKR/W0hProtected Area Write Attempt Mask
  • 0h = Disable
  • 1h = Enable
3INDIRECT_TRANSFER_REJECT_MASKR/W0hIndirect Read Reject Mask
  • 0h = Disable
  • 1h = Enable
2INDIRECT_OP_DONE_MASKR/W0hIndirect Complete Mask
  • 0h = Disable
  • 1h = Enable
1UNDERFLOW_DET_MASKR/W0hUnderflow Detected Mask
  • 0h = Disable
  • 1h = Enable
0MODE_M_FAIL_MASKR/W0hMode M Failure Mask
  • 0h = Disable
  • 1h = Enable

8.9.19 LOWER_WR_PROT Register (Offset = 50h) [Reset = 00000000h]

LOWER_WR_PROT is shown in Table 8-54.

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Lower Write Protection Register

Table 8-54 LOWER_WR_PROT Register Field Descriptions
BitFieldTypeResetDescription
31-0SUBSECTORR/W0h The block number that defines the lower block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.20 UPPER_WR_PROT Register (Offset = 54h) [Reset = 00000000h]

UPPER_WR_PROT is shown in Table 8-55.

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Upper Write Protection Register

Table 8-55 UPPER_WR_PROT Register Field Descriptions
BitFieldTypeResetDescription
31-0SUBSECTORR/W0h The block number that defines the upper block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.21 WR_PROT_CTRL Register (Offset = 58h) [Reset = 00000000h]

WR_PROT_CTRL is shown in Table 8-56.

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Write Protection Control Register

Table 8-56 WR_PROT_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENBR/W0hWrite Protection Enable Bit: When set to 1, any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected. An AHB error response is generated and an interrupt source triggered. When set to 0, the protection region is disabled.
  • 0h = Disable
  • 1h = Enable
0INVR/W0hWrite Protection Inversion Bit: When set to 1, the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to. When set to 0, the protection region defined in the lower and upper write protection registers is the region that the system is not permitted to write to.
  • 0h = Disable
  • 1h = Enable

8.9.22 INDIRECT_READ_XFER_CTRL Register (Offset = 60h) [Reset = 00000000h]

INDIRECT_READ_XFER_CTRL is shown in Table 8-57.

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Indirect Read Transfer Control Register

Table 8-57 INDIRECT_READ_XFER_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-6NUM_IND_OPS_DONER0hThis field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed. Write a 1 to bit 5 of this register to decrement it.
  • 0h = Smallest value
  • 3h = Highest possible value
5IND_OPS_DONE_STATUSR/W1C0hIndirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it.
  • 0h = Disable
  • 1h = Enable
4RD_QUEUEDR0hTwo indirect read operations have been queued
  • 0h = Disable
  • 1h = Enable
3SRAM_FULLR/W1C0hSRAM Full: SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it.\"; indirect operation (status)
  • 0h = Disable
  • 1h = Enable
2RD_STATUSR0hIndirect Read Status: Indirect read operation in progress (status)
  • 0h = Disable
  • 1h = Enable
1CANCELW0hCancel Indirect Read: Writing a 1 to this bit will cancel all ongoing indirect read operations.
  • 0h = Disable
  • 1h = Enable
0STARTW0hStart Indirect Read: Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation.
  • 0h = Disable
  • 1h = Enable

8.9.23 INDIRECT_READ_XFER_WATERMARK Register (Offset = 64h) [Reset = 00000000h]

INDIRECT_READ_XFER_WATERMARK is shown in Table 8-58.

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Indirect Read Transfer Watermark Register

Table 8-58 INDIRECT_READ_XFER_WATERMARK Register Field Descriptions
BitFieldTypeResetDescription
31-0LEVELR/W0hWatermark Value: This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark, an interrupt is also generated. This field can be disabled by writing a value of all zeroes.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.24 INDIRECT_READ_XFER_START Register (Offset = 68h) [Reset = 00000000h]

INDIRECT_READ_XFER_START is shown in Table 8-59.

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Indirect Read Transfer Start Address Register

Table 8-59 INDIRECT_READ_XFER_START Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR/W0h This is the start address from which the indirect access will commence its READ operation.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.25 INDIRECT_READ_XFER_NUM_BYTES Register (Offset = 6Ch) [Reset = 00000000h]

INDIRECT_READ_XFER_NUM_BYTES is shown in Table 8-60.

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Indirect Read Transfer Number Bytes Register

Table 8-60 INDIRECT_READ_XFER_NUM_BYTES Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER/W0h This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.26 INDIRECT_WRITE_XFER_CTRL Register (Offset = 70h) [Reset = 00000000h]

INDIRECT_WRITE_XFER_CTRL is shown in Table 8-61.

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Indirect Write Transfer Control Register

Table 8-61 INDIRECT_WRITE_XFER_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-6NUM_IND_OPS_DONER0hThis field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed. Write a 1 to bit 5 of this register to decrement it.
  • 0h = Smallest value
  • 3h = Highest possible value
5IND_OPS_DONE_STATUSR/W1C0hIndirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it.
  • 0h = Disable
  • 1h = Enable
4WR_QUEUEDR0hTwo indirect write operations have been queued
  • 0h = Disable
  • 1h = Enable
3RESERVEDR0h
2WR_STATUSR0hIndirect Write Status: Indirect write operation in progress (status)
  • 0h = Disable
  • 1h = Enable
1CANCELW0hCancel Indirect Write: Writing a 1 to this bit will cancel all ongoing indirect write operations.
  • 0h = Disable
  • 1h = Enable
0STARTW0hStart Indirect Write: Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation.
  • 0h = Disable
  • 1h = Enable

8.9.27 INDIRECT_WRITE_XFER_WATERMARK Register (Offset = 74h) [Reset = FFFFFFFFh]

INDIRECT_WRITE_XFER_WATERMARK is shown in Table 8-62.

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Indirect Write Transfer Watermark Register

Table 8-62 INDIRECT_WRITE_XFER_WATERMARK Register Field Descriptions
BitFieldTypeResetDescription
31-0LEVELR/WFFFFFFFFhWatermark Value: This represents the maximum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level falls below the watermark, an interrupt is also generated. This field can be disabled by writing a value of all ones.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.28 INDIRECT_WRITE_XFER_START Register (Offset = 78h) [Reset = 00000000h]

INDIRECT_WRITE_XFER_START is shown in Table 8-63.

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Indirect Write Transfer Start Address Register

Table 8-63 INDIRECT_WRITE_XFER_START Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR/W0hStart of Indirect Access: This is the start address from which the indirect access will commence its READ operation.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.29 INDIRECT_WRITE_XFER_NUM_BYTES Register (Offset = 7Ch) [Reset = 00000000h]

INDIRECT_WRITE_XFER_NUM_BYTES is shown in Table 8-64.

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Indirect Write Transfer Number Bytes Register

Table 8-64 INDIRECT_WRITE_XFER_NUM_BYTES Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER/W0hIndirect Number of Bytes: This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.30 INDIRECT_TRIGGER_ADDR_RANGE Register (Offset = 80h) [Reset = 00000004h]

INDIRECT_TRIGGER_ADDR_RANGE is shown in Table 8-65.

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Indirect Trigger Address Range Register

Table 8-65 INDIRECT_TRIGGER_ADDR_RANGE Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-0IND_RANGE_WIDTHR/W4h This is the address offset of Indirect Trigger Address Register.
  • 0h = Smallest value
  • Fh = Highest possible value

8.9.31 FLASH_COMMAND_CTRL_MEM Register (Offset = 8Ch) [Reset = 00000000h]

FLASH_COMMAND_CTRL_MEM is shown in Table 8-66.

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Flash Command Control Memory Register

Table 8-66 FLASH_COMMAND_CTRL_MEM Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28-20MEM_BANK_ADDRR/W0h The address of the Memory Bank which data will be read from.
  • 0h = Smallest value
  • 1FFh = Highest possible value
19RESERVEDR0h
18-16NB_OF_STIG_READ_BYTESR/W0h It defines the number of read bytes for the extended STIG.
  • 0h = Smallest value
  • 7h = Highest possible value
15-8MEM_BANK_READ_DATAR0hLast requested data from the STIG Memory Bank.
  • 0h = Smallest value
  • FFh = Highest possible value
7-2RESERVEDR0h
1MEM_BANK_REQ_IN_PROGRESSR0hMemory Bank data request in progress.
  • 0h = Disable
  • 1h = Enable
0TRIGGER_MEM_BANK_REQW0hTrigger the Memory Bank data request.
  • 0h = Disable
  • 1h = Enable

8.9.32 FLASH_CMD_CTRL Register (Offset = 90h) [Reset = 00000000h]

FLASH_CMD_CTRL is shown in Table 8-67.

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Flash Command Control Register

Table 8-67 FLASH_CMD_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24CMD_OPCODER/W0hCommand Opcode: The command opcode field should be setup before triggering the command. For example, 0x20 maps to SubSector Erase. Writing to the execute field (bit 0) of this register launches the command. NOTE : Using this approach to issue commands to the device will make use of the instruction type of the device instruction configuration register. If this field is set to 2'b00, then the command opcode, command address, command dummy bytes and command data will all be transferred in a serial fashion. If this field is set to 2'b01, then the command opcode, command address, command dummy bytes and command data will all be transferred in parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command opcode, command address, command dummy bytes and command data will all be transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins.
  • 0h = Smallest value
  • FFh = Highest possible value
23ENB_READ_DATAR/W0hRead Data Enable: Set to 1 if the command specified in the command opcode field (bits 31:24) requires read data bytes to be received from the device.
  • 0h = Disable
  • 1h = Enable
22-20NUM_RD_DATA_BYTESR/W0hNumber of Read Data Bytes: Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes.
  • 0h = Smallest value
  • 7h = Highest possible value
19ENB_COMD_ADDRR/W0hCommand Address Enable: Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via writing a 1 to the execute field.
  • 0h = Disable
  • 1h = Enable
18ENB_MODE_BITR/W0hMode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes.
  • 0h = Disable
  • 1h = Enable
17-16NUM_ADDR_BYTESR/W0hNumber of Address Bytes: Set to the number of address bytes required (the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes
  • 0h = Smallest value
  • 3h = Highest possible value
15ENB_WRITE_DATAR/W0hWrite Data Enable: Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device.
  • 0h = Disable
  • 1h = Enable
14-12NUM_WR_DATA_BYTESR/W0hNumber of Write Data Bytes: Up to 8 Data bytes may be written using this command Set to 0 for 1 byte, 7 for 8 bytes.
  • 0h = Smallest value
  • 7h = Highest possible value
11-7NUM_DUMMY_CYCLESR/W0hNumber of Dummy cycles: Set to the number of dummy cycles required. This should be setup before triggering the command via the execute field of this register.
  • 0h = Smallest value
  • 1Fh = Highest possible value
6-3CMD_GEN_FSM_STATER0hCMD_GEN_FSM_STATE is used to define the "Polling flag": If (CMD_GEN_FSM_STATE[6:3] = 0x7 or 0x8 or 0xa or 0xb ) then "Polling_flag"=1 Usage: In order to make sure a write to external device was done and ended successfully, following condition should be met: "Command execution in progress" (FLASH_CMD_CTRL.CMD_EXEC_STATUS) = 0 AND "Polling flag" is '0'. Design NOTE: Command gen FSM polling states are: CMD_GEN_FSM_STATE == POLL_STATUS_AFTER_WRITE (0x7) CMD_GEN_FSM_STATE == POLL_STATUS_AFTER_WRITE2 (0x8) CMD_GEN_FSM_STATE == POLL_STATUS_WAIT (0xb) CMD_GEN_FSM_STATE == LET_TXFIFO_EMPTY (0xa)
  • 0h = 0x0
  • 1h = 0x1
  • 2h = 0x2
  • 3h = 0x3
  • 4h = 0x4
  • 5h = 0x5
  • 6h = 0x6
  • 7h = 0x7
  • 8h = 0x8
  • Ah = 0xa
  • Bh = 0xb
  • Ch = 0xc
2STIG_MEM_BANK_ENR/W0hSTIG Memory Bank enable bit.
  • 0h = Disable
  • 1h = Enable
1CMD_EXEC_STATUSR0hCommand execution in progress.
  • 0h = Disable
  • 1h = Enable
0CMD_EXECW0hExecute the command.
  • 0h = Disable
  • 1h = Enable

8.9.33 FLASH_CMD_ADDR Register (Offset = 94h) [Reset = 00000000h]

FLASH_CMD_ADDR is shown in Table 8-68.

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Flash Command Address Register

Table 8-68 FLASH_CMD_ADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR/W0hCommand Address: This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the address used by the command specified in the opcode field (bits 31:24) of the Flash Command Control register.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.34 FLASH_RD_DATA_LOWER Register (Offset = A0h) [Reset = 00000000h]

FLASH_RD_DATA_LOWER is shown in Table 8-69.

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Flash Command Read Data Register (Lower)

Table 8-69 FLASH_RD_DATA_LOWER Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0h This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.35 FLASH_RD_DATA_UPPER Register (Offset = A4h) [Reset = 00000000h]

FLASH_RD_DATA_UPPER is shown in Table 8-70.

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Flash Command Read Data Register (Upper)

Table 8-70 FLASH_RD_DATA_UPPER Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0h This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.36 FLASH_WR_DATA_LOWER Register (Offset = A8h) [Reset = 00000000h]

FLASH_WR_DATA_LOWER is shown in Table 8-71.

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Flash Command Write Data Register (Lower)

Table 8-71 FLASH_WR_DATA_LOWER Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hCommand Write Data Lower Byte: This is the command write data lower byte. This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the data that is to be written to the flash for any status or configuration write operation carried out by triggering the event in the Flash Command Control register.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.37 FLASH_WR_DATA_UPPER Register (Offset = ACh) [Reset = 00000000h]

FLASH_WR_DATA_UPPER is shown in Table 8-72.

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Flash Command Write Data Register (Upper)

Table 8-72 FLASH_WR_DATA_UPPER Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hCommand Write Data Upper Byte: This is the command write data upper byte. This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the data that is to be written to the flash for any status or configuration write operation carried out by triggering the event in the Flash Command Control register.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

8.9.38 POLLING_FLASH_STATUS Register (Offset = B0h) [Reset = 00000000h]

POLLING_FLASH_STATUS is shown in Table 8-73.

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Polling Flash Status Register

Table 8-73 POLLING_FLASH_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0h
20-16DEVICE_STATUS_NB_DUMMYR/W0h Number of dummy cycles for auto-polling
  • 0h = Smallest value
  • 1Fh = Highest possible value
15-9RESERVEDR0h
8DEVICE_STATUS_VALIDR0hDevice Status Valid: This should be set when value in bits from 7 to 0 is valid.
  • 0h = Disable
  • 1h = Enable
7-0DEVICE_STATUSR0h Defines actual Status Register of Device
  • 0h = Smallest value
  • FFh = Highest possible value

8.9.39 PHY_CONFIGURATION Register (Offset = B4h) [Reset = 40000000h]

PHY_CONFIGURATION is shown in Table 8-74.

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PHY Configuration Register

Table 8-74 PHY_CONFIGURATION Register Field Descriptions
BitFieldTypeResetDescription
31PHY_CONFIG_RESYNCW0h This bit is used for re-synchronisation delay lines to update them with values from TX DLL Delay and RX DLL Delay fields.
  • 0h = Disable
  • 1h = Enable
30PHY_CONFIG_RESETW1hDLL Reset bit: This bit is used for reset of Delay Lines by software.
  • 0h = Disable
  • 1h = Enable
29PHY_CONFIG_RX_DLL_BYPASSR/W0hRX DLL Bypass: This field determines id RX DLL is bypassed.
  • 0h = Disable
  • 1h = Enable
28-23RESERVEDR0h
22-16PHY_CONFIG_TX_DLL_DELAYR/W0hTX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and spi_clk.
  • 0h = Smallest value
  • 7Fh = Highest possible value
15-7RESERVEDR0h
6-0PHY_CONFIG_RX_DLL_DELAYR/W0hRX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and rx_dll_clk.
  • 0h = Smallest value
  • 7Fh = Highest possible value

8.9.40 PHY_MASTER_CONTROL Register (Offset = B8h) [Reset = 00800000h]

PHY_MASTER_CONTROL is shown in Table 8-75.

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PHY DLL controller Control Register

Table 8-75 PHY_MASTER_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24PHY_MASTER_LOCK_MODER/W0h Determines if the controller delay line locks on a full cycle or half cycle of delay.
  • 0h = Disable
  • 1h = Enable
23PHY_MASTER_BYPASS_MODER/W1h Controls the bypass mode of the controller and peripheral DLLs.
  • 0h = Disable
  • 1h = Enable
22-20PHY_MASTER_PHASE_DETECT_SELECTORR/W0h Selects the number of delay elements to be inserted between the phase detect flip-flops.
  • 0h = Smallest value
  • 7h = Highest possible value
19RESERVEDR0h
18-16PHY_MASTER_NB_INDICATIONSR/W0h Holds the number of consecutive increment or decrement indications.
  • 0h = Smallest value
  • 7h = Highest possible value
15-7RESERVEDR0h
6-0PHY_MASTER_INITIAL_DELAYR/W0h This value is the initial delay value for the DLL.
  • 0h = Smallest value
  • 7Fh = Highest possible value

8.9.41 DLL_OBSERVABLE_LOWER Register (Offset = BCh) [Reset = 00000000h]

DLL_OBSERVABLE_LOWER is shown in Table 8-76.

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DLL Observable Register Lower

Table 8-76 DLL_OBSERVABLE_LOWER Register Field Descriptions
BitFieldTypeResetDescription
31-24DLL_OBSERVABLE_LOWER_DLL_LOCK_INCR0h Holds the state of the cumulative dll_lock_inc register.
  • 0h = Smallest value
  • FFh = Highest possible value
23-16DLL_OBSERVABLE_LOWER_DLL_LOCK_DECR0h Holds the state of the cumulative dll_lock_dec register.
  • 0h = Smallest value
  • FFh = Highest possible value
15DLL_OBSERVABLE_LOWER_LOOPBACK_LOCKR0h This bit indicates that lock of loopback is done.
  • 0h = Disable
  • 1h = Enable
14-8DLL_OBSERVABLE_LOWER_LOCK_VALUER0h Reports the DLL encoder value from the controller DLL to the peripheral DLLs.
  • 0h = Smallest value
  • 7Fh = Highest possible value
7-3DLL_OBSERVABLE_LOWER_UNLOCK_COUNTERR0h Reports the number of increments or decrements required for the controller DLL to complete the locking process.
  • 0h = Smallest value
  • 1Fh = Highest possible value
2-1DLL_OBSERVABLE_LOWER_LOCK_MODER0h Defines the mode in which the DLL has achieved the lock.
  • 0h = Smallest value
  • 3h = Highest possible value
0DLL_OBSERVABLE_LOWER_DLL_LOCKR0h Indicates status of DLL.
  • 0h = Disable
  • 1h = Enable

8.9.42 DLL_OBSERVABLE_UPPER Register (Offset = C0h) [Reset = 00000000h]

DLL_OBSERVABLE_UPPER is shown in Table 8-77.

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DLL Observable Register Upper

Table 8-77 DLL_OBSERVABLE_UPPER Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0h
22-16DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUTR0h Holds the encoded value for the TX delay line for this slice.
  • 0h = Smallest value
  • 7Fh = Highest possible value
15-7RESERVEDR0h
6-0DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUTR0h Holds the encoded value for the RX delay line for this slice.
  • 0h = Smallest value
  • 7Fh = Highest possible value

8.9.43 OPCODE_EXT_LOWER Register (Offset = E0h) [Reset = 13EDFA00h]

OPCODE_EXT_LOWER is shown in Table 8-78.

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Opcode Extension Register (Lower)

Table 8-78 OPCODE_EXT_LOWER Register Field Descriptions
BitFieldTypeResetDescription
31-24EXT_READ_OPCODER/W13hSupplement byte of any Read Opcode
  • 0h = Smallest value
  • FFh = Highest possible value
23-16EXT_WRITE_OPCODER/WEDhSupplement byte of any Write Opcode
  • 0h = Smallest value
  • FFh = Highest possible value
15-8EXT_POLL_OPCODER/WFAhSupplement byte of any Polling Opcode
  • 0h = Smallest value
  • FFh = Highest possible value
7-0EXT_STIG_OPCODER/W0hSupplement byte of any STIG Opcode
  • 0h = Smallest value
  • FFh = Highest possible value

8.9.44 OPCODE_EXT_UPPER Register (Offset = E4h) [Reset = 06F90000h]

OPCODE_EXT_UPPER is shown in Table 8-79.

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Opcode Extension Register (Upper)

Table 8-79 OPCODE_EXT_UPPER Register Field Descriptions
BitFieldTypeResetDescription
31-24WEL_OPCODER/W6hFirst byte of any WEL Opcode
  • 0h = Smallest value
  • FFh = Highest possible value
23-16EXT_WEL_OPCODER/WF9hSupplement byte of any WEL Opcode
  • 0h = Smallest value
  • FFh = Highest possible value
15-0RESERVEDR0h

8.9.45 MODULE_ID Register (Offset = FCh) [Reset = 04000300h]

MODULE_ID is shown in Table 8-80.

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Module ID Register

Table 8-80 MODULE_ID Register Field Descriptions
BitFieldTypeResetDescription
31-24FIX_PATCHR4hFix/path number related to revision described by 3 LSBs of this register
  • 0h = Smallest value
  • FFh = Highest possible value
23-8MODULE_IDR3hModule/Revision ID number
  • 0h = Smallest value
  • FFFFh = Highest possible value
7-2RESERVEDR0h
1-0CONFR0hConfiguration ID number: 0 : OCTAL + PHY Configuration 1 : OCTAL Configuration 2 : QUAD + PHY Configuration 3 : QUAD Configuration
  • 0h = Smallest value
  • 3h = Highest possible value