SWRU626 User guide | 德州仪器 TI.com.cn

SWRU626 December 2025 CC3501E , CC3551E

1
1 Read This First
1. 1.1 About This Manual
2. 1.2 Register, Field, and Bit Calls
3. Trademarks
2 Architecture Overview
1. 2.1 Target Applications
2. 2.2 Introduction
3. 2.3 Internal System Diagram
4. 2.4 Arm Cortex M33
5. 2.5 Power Management
6. 2.6 Debug Subsystem (DEBUGSS)
7. 2.7 Memory Subsystem (MEMSS)
  1. 2.7.1 External Memory Interface
8. 2.8 Hardware Security Module
9. 2.9 General Purpose Timers (GPT)
10. 2.10 Real Time Clock (RTC)
11. 2.11 Direct Memory Access
12. 2.12 GPIOs
13. 2.13 Communication Peripherals
3 Arm Cortex-M33 Processor
1. 3.1 Arm Cortex-M33 Processor Introduction
2. 3.2 Block Diagram
3. 3.3 M33 instantiation parameters
4. 3.4 Arm Cortex-M33 System Peripheral Details
5. 3.5 CPU Sub-System Peripheral Details
6. 3.6 Programming Model
7. 3.7 TrustZone-M
8. 3.8 CC35xx Host MCU Registers
9. 3.9 Arm® Cortex®-M33 Registers
4 Memory Map
1. 4.1 Memory Map
5 Interrupts and Events
1. 5.1 Exception Model
2. 5.2 Fault Handling
3. 5.3 Security State Switches
4. 5.4 Event Manager
5. 5.5 SOC_IC Registers
6. 5.6 SOC_AON Registers
7. 5.7 SOC_AAON Registers
6 Debug Subsystem (DEBUGSS)
1. 6.1 Introduction
2. 6.2 Block Diagram
3. 6.3 Overview
4. 6.4 Physical Interface
5. 6.5 Debug Access Ports
6. 6.6 Debug Features
7. 6.7 Behavior in Low Power Modes
8. 6.8 Debug Access Control
9. 6.9 SOC_DEBUGSS Registers
7 Power, Reset, Clock Management
1. 7.1 Power Management
2. 7.2 Reset
  1. 7.2.1 Reset Cause
  2. 7.2.2 Watchdog Timer (WDT)
3. 7.3 Clocks
  1. 7.3.1 Fast Clock
  2. 7.3.2 Slow Clock
4. 7.4 PRCM_AON Registers
5. 7.5 PRCM_SCRATCHPAD Registers
8 Memory Subsystem (MEMSS)
1. 8.1 Introduction
2. 8.2 SRAM
3. 8.3 D-Cache
4. 8.4 Flash
5. 8.5 PSRAM
6. 8.6 XiP Memory Access
7. 8.7 ICACHE Registers
8. 8.8 DCACHE Registers
9. 8.9 OSPI Registers
10. 8.10 HOST_XIP Registers
9 Hardware Security Module (HSM)
1. 9.1 Introduction
2. 9.2 Overview
3. 9.3 Mailbox and Register Access Firewall
4. 9.4 DMA Firewall
5. 9.5 HSM Key Storage
6. 9.6 HSM Registers
7. 9.7 HSM_NON_SEC Registers
8. 9.8 HSM_SEC Registers
10Device Boot and Bootloader
1. 10.1 CC35xx Boot Concept
2. 10.2 Features
3. 10.3 Vendor Images Format and Processing
  1. 10.3.1 External Flash Arrangement
  2. 10.3.2 Vendor Images Format
4. 10.4 Boot Flows
5. 10.5 Chain of Trust
11Direct Memory Access (DMA)
1. 11.1 Overview
2. 11.2 Block Diagram
3. 11.3 Functional Description
4. 11.4 HOST_DMA Registers
12One Time Programming (OTP)
13General Purpose Timers (GPT)
1. 13.1 Overview
2. 13.2 Block Diagram
3. 13.3 Functional Description
4. 13.4 Timer Modes
5. 13.5 GPTIMER Registers
14System Timer (SysTimer)
1. 14.1 Overview
2. 14.2 Block Diagram
3. 14.3 Functional Description
  1. 14.3.1 Common Channel Features
  2. 14.3.2 Interrupts and Events
4. 14.4 SYSRESOURCES Registers
5. 14.5 SYSTIM Registers
15Real-Time Clock (RTC)
1. 15.1 Introduction
2. 15.2 Block Diagram
3. 15.3 Interrupts and Events
4. 15.4 CAPTURE and COMPARE Configurations
  1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
  2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
5. 15.5 RTC Registers
16General Purpose Input/Output (GPIOs)
1. 16.1 Introduction
2. 16.2 Block Diagram
3. 16.3 I/O Mapping and Configuration
  1. 16.3.1 Basic I/O Mapping
  2. 16.3.2 Pin Mapping
4. 16.4 Edge Detection
5. 16.5 GPIO
6. 16.6 I/O Pins
7. 16.7 Unused Pins
8. 16.8 IOMUX Registers
17Universal Asynchronous Receivers/Transmitters (UART)
1. 17.1 Introduction
2. 17.2 Block Diagram
3. 17.3 UART Functional Description
4. 17.4 UART-LIN Specification
5. 17.5 Interface to Host DMA
6. 17.6 Initialization and Configuration
7. 17.7 UART Registers
18Serial Peripheral Interface (SPI)
1. 18.1 Overview
  1. 18.1.1 Features
  2. 18.1.2 Block Diagram
2. 18.2 Signal Description
3. 18.3 Functional Description
4. 18.4 Host DMA Operation
5. 18.5 Initialization and Configuration
6. 18.6 SPI Registers
19Inter-Integrated Circuit (I2C) Interface
1. 19.1 Introduction
2. 19.2 Block Diagram
3. 19.3 Functional Description
  1. 19.3.1 Clock Control
    1. 19.3.1.1 Internal Clock
    2. 19.3.1.2 External Clock
  2. 19.3.2 General Architecture
4. 19.4 Initialization and Configuration
5. 19.5 Interrupts
6. 19.6 I2C Registers
20Secure Digital Multimedia Card (SDMMC)
1. 20.1 Introduction
  1. 20.1.1 SDMMC Features
  2. 20.1.2 Integration
2. 20.2 Functional Description
3. 20.3 Low-Level Programming Models
  1. 20.3.1 SDMMC Initialization Flow
  2. 20.3.2 Operational Modes Configuration
    1. 20.3.2.1 Basic Operations for SDMMC
    2. 20.3.2.2 Card Detection, Identification, and Selection
4. 20.4 SDMMC Registers
21Secure Digital Input/Output (SDIO)
1. 21.1 Introduction
2. 21.2 Block Diagram
3. 21.3 Functional Description
4. 21.4 SDIO_CORE Registers
5. 21.5 SDIO_CARD_FN1 Registers
22Inter-Integrated Circuit Sound (I2S)
1. 22.1 Introduction
2. 22.2 Block Diagram
3. 22.3 Signal Descriptions
4. 22.4 Functional Description
5. 22.5 Memory Interface
6. 22.6 Samplestamp Generator
7. 22.7 Error Detection
8. 22.8 Usage
  1. 22.8.1 Start-Up Sequence
  2. 22.8.2 Shutdown Sequence
9. 22.9 I2S Configuration Guideline
10. 22.10 I2S Registers
23Pulse Density Modulation (PDM)
1. 23.1 Introduction
2. 23.2 Block Diagram
3. 23.3 Input Selection
  1. 23.3.1 PDM Data Mode
  2. 23.3.2 Manchester Input Mode
4. 23.4 CIC Filter
5. 23.5 FIFO Organization in Different Modes
6. 23.6 Automatic Gain Control (AGC)
  1. 23.6.1 Operation in 2's Complement Format
  2. 23.6.2 Operation in Offset Binary Format
7. 23.7 Interrupts
8. 23.8 Clock Select and Control
9. 23.9 DMA Operation
10. 23.10 Samplestamp Generator
11. 23.11 Debug‑Mode Flag Behavior
12. 23.12 Software Guidelines
13. 23.13 PDM Registers
24Analog to Digital Converter (ADC)
1. 24.1 Overview
2. 24.2 Block Diagram
3. 24.3 Functional Description
4. 24.4 ADC Registers
25Controller Area Network (CAN)
1. 25.1 Introduction
2. 25.2 Functions
3. 25.3 DCAN Subsystem
4. 25.4 DCAN Functional Description
5. 25.5 DCAN Wrapper
6. 25.6 DCAN Clock Enable
7. 25.7 DCAN Registers
26Revision History

13.5 GPTIMER Registers

Table 13-4 lists the memory-mapped registers for the GPTIMER registers. All register offset addresses not listed in Table 13-4 should be considered as reserved locations and the register contents should not be modified.

Table 13-4 GPTIMER Registers

Offset	Acronym	Register Name	Section
0h	DESC	Description	Section 13.5.1
4h	DESCEX	Description Extended	Section 13.5.2
8h	STARTCFG	Start Configuration	Section 13.5.3
Ch	CTL	Timer Control	Section 13.5.4
10h	OUTCTL	Output Control	Section 13.5.5
14h	CNTR	Counter	Section 13.5.6
18h	PRECFG	Clock Prescaler Configuration	Section 13.5.7
1Ch	PREEVENT	Prescaler Event	Section 13.5.8
3Ch	DMA	Direct Memory Accsess	Section 13.5.9
40h	DMARW	Direct Memory Accsess	Section 13.5.10
44h	ADCTRG	Direct Memory Accsess	Section 13.5.11
48h	IOCTL	IO Control Register	Section 13.5.12
68h	IMASK	Interrupt Mask	Section 13.5.13
6Ch	RIS	Raw Interrupt Status	Section 13.5.14
70h	MIS	Masked Interrupt Status	Section 13.5.15
74h	ISET	Interrupt Set	Section 13.5.16
78h	ICLR	Interrupt Clear	Section 13.5.17
7Ch	IMSET	Interrupt Clear	Section 13.5.18
80h	IMCLR	Interrupt Clear	Section 13.5.19
84h	EMU	Interrupt Clear	Section 13.5.20
C0h	C0CFG	Channel 0 Configuration	Section 13.5.21
C4h	C1CFG	Channel 1 Configuration	Section 13.5.22
C8h	C2CFG	Channel 2 Configuration	Section 13.5.23
FCh	PTGT	Target	Section 13.5.24
100h	PC0CC	Pipeline Channel 0 Capture Compare	Section 13.5.25
104h	PC1CC	Pipeline Channel 1 Capture Compare	Section 13.5.26
108h	PC2CC	Pipeline Channel 2 Capture Compare	Section 13.5.27
13Ch	TGT	Target	Section 13.5.28
140h	C0CC	Channel Capture Compare	Section 13.5.29
144h	C1CC	Channel Capture Compare	Section 13.5.30
148h	C2CC	Channel Capture Compare	Section 13.5.31
17Ch	PTGTNC	Shadow Target	Section 13.5.32
180h	PC0CCNC	Pipeline Channel 0 Capture Compare No Clear	Section 13.5.33
184h	PC1CCNC	Pipeline Channel 1 Capture Compare No Clear	Section 13.5.34
188h	PC2CCNC	Pipeline Channel 2 Capture Compare No Clear	Section 13.5.35
1BCh	TGTNC	Shadow Target No Clear	Section 13.5.36
1C0h	C0CCNC	Channel 0 Capture Compare No Clear	Section 13.5.37
1C4h	C1CCNC	Channel 1 Capture Compare No Clear	Section 13.5.38
1C8h	C2CCNC	Channel 2 Capture Compare No Clear	Section 13.5.39
1000h	CLKCFG	Clock Enable Register	Section 13.5.40

Complex bit access types are encoded to fit into small table cells. Table 13-5 shows the codes that are used for access types in this section.

Table 13-5 GPTIMER Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

13.5.1 DESC Register (Offset = 0h) [Reset = DE491000h]

DESC is shown in Table 13-6.

Return to the Summary Table.

Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 13-6 DESC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	MODID	R	DE49h	Module identifier used to uniquely identify this IP.
15-12	STDIPOFF	R	1h	Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
11-8	INSTIDX	R	0h	IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number.
7-4	MAJREV	R	1h	Major revision of IP.
3-0	MINREV	R	0h	Minor revision of IP.

13.5.2 DESCEX Register (Offset = 4h) [Reset = 00000000h]

DESCEX is shown in Table 13-7.

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Description Extended This register describes the parameters of the LGPT.

Table 13-7 DESCEX Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19	HIR	R	1h	Has IR logic.
18	HDBF	R	1h	Has Dead-Band, Fault, and Park logic.
17-14	PREW	R	8h	Prescaler width. The prescaler can maximum be configured to 2^PREW-1.
13	HQDEC	R	1h	Has Quadrature Decoder.
12	HCIF	R	1h	Has channel input filter.
11-8	CIFS	R	8h	Channel input filter size. The prevailing state filter can maximum be configured to 2^CIFS-1.
7	HDMA	R	1h	Has uDMA output and logic.
6	HINT	R	1h	Has interrupt output and logic.
5-4	CNTRW	R	0h	Counter bit-width. The maximum counter value is equal to 2^CNTRW-1. 0h = 16-bit counter. 1h = 24-bit counter. 2h = 32-bit counter. 3h = RESERVED
3-0	NCH	R	4h	Number of channels.

13.5.3 STARTCFG Register (Offset = 8h) [Reset = 00000000h]

STARTCFG is shown in Table 13-8.

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Start Configuration This register is only for when MODE is configured to one of the SYNC modes. This register defines when this LGPT starts.

Table 13-8 STARTCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1-0	LGPT0	R/W	0h	LGPT start

13.5.4 CTL Register (Offset = Ch) [Reset = 00000000h]

CTL is shown in Table 13-9.

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Timer Control

Table 13-9 CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	C2RST	W	0h	Channel 2 reset. 0h = No effect. 1h = Reset [C2CC.], [PC2CC.], and [C2CFG.*].
9	C1RST	W	0h	Channel 1 reset. 0h = No effect. 1h = Reset [C1CC.], [PC1CC.], and [C1CFG.*].
8	C0RST	W	0h	Channel 0 reset. 0h = No effect. 1h = Reset [C0CC], PC0CC, and C0CFG.
7-6	RESERVED	R	0h	Reserved
5	INTP	R/W	0h	Interrupt Phase. This bit field controls when the TGT and ZERO interrupts are set. 0h = TGT and ZERO are set one system clock cycle after [CNTR.] = TARGET/ZERO. 1h = TGT and ZERO are set one timer clock cycle after [CNTR.] = TARGET/ZERO.
4-3	CMPDIR	R/W	0h	Compare direction. This bit field controls the direction the counter must have in order to set the [RIS.] compare interrupts. 0h = Compare [RIS.] fields are set on up count and down count. 1h = Compare [RIS.] fields are only set on up count. 2h = Compare [RIS.] fields are only set on down count. 3h = RESERVED
2-0	MODE	R/W	0h	Timer mode control The [CNTR.] restarts from 0 when MODE is written to UP_ONCE, UP_PER, UPDWN_PER, QDEC, SYNC_UP_ONCE, SYNC_UP_PER or SYNC_UPDWN_PER. When writing MODE all internally queued updates to the channels and [TGT.] is cleared. When configuring the timer, MODE should be the last thing to configure. If changing timer configuration after MODE has been set is necessary, instructions, if any, given in the configuration registers should be followed. See for example [C0CFG.]. 0h = Disable timer. Updates to counter, channels, and events stop. 1h = Count up once. The timer increments from 0 to target value, then stops and sets MODE to DIS. 2h = Count up periodically. The timer increments from 0 to target value, repeatedly. Period = (target value + 1) timer clock period 3h = Count up and down periodically. The timer counts from 0 to target value and back to 0, repeatedly. Period = (target value * 2) * timer clock period 4h = The timer functions as a quadrature decoder. IOC input 0, IOC input 1 and IOC input 2 are used respectively as PHA, PHB and IDX inputs. IDX can be turned off by setting EDGE = NONE. The timer clock frequency sets the sample rate of the QDEC logic. This frequency can be configured in [PRECFG.]. 5h = Start counting up once synchronous to another LGPT, selected within [STARTCFG.]. The timer is started by setting MODE = UP_ONCE automatically. It then functions as a normal timer in MODE = UP_ONCE, incrementing from 0 to target value, then stops and sets MODE to DIS. 6h = Start counting up periodically synchronous to another LGPT, selected within [STARTCFG.]. The timer is started by setting MODE = UP_PER automatically. It then operates as a normal timer in MODE = UP_PER, incrementing from 0 to target value, repeatedly. Period = (target value 2) * timer clock period 7h = Start counting up and down periodically synchronous to another LGPT, selected within [STARTCFG.]. The timer is started by setting MODE = UPDWN_PER automatically. It then operates as a normal timer in MODE = UPDWN_PER, counting from 0 to target value and back to 0, repeatedly. Period = (target value 2) * timer clock period

13.5.5 OUTCTL Register (Offset = 10h) [Reset = 00000000h]

OUTCTL is shown in Table 13-10.

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Output Control Set and clear individual outputs manually. Manual update of an output takes priority over automatic channel updates to the same output. It is not possible to set and clear an output at the same time, such requests will be neglected. An output can be automatically cleared, set, toggled, or pulsed by each channel, listed in decreasing order of priority. The action with highest priority happens when multiple channels want to update an output at the same time. All outputs are connected to the event fabric and the IO controller. The outputs going to the IO controller have an additional complementary output, this output is the inverted IO output. Both the IO and the IO complementary outputs are passed through an IO Controller, see [IOCTL.*].

Table 13-10 OUTCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	SETOUT2	W	0h	Set output 2. Write 1 to set output 2.
4	CLROUT2	W	0h	Clear output 2. Write 1 to clear output 2.
3	SETOUT1	W	0h	Set output 1. Write 1 to set output 1.
2	CLROUT1	W	0h	Clear output 1. Write 1 to clear output 1.
1	SETOUT0	W	0h	Set output 0. Write 1 to set output 0.
0	CLROUT0	W	0h	Clear output 0. Write 1 to clear output 0.

13.5.6 CNTR Register (Offset = 14h) [Reset = 00000000h]

CNTR is shown in Table 13-11.

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Counter The counter of this timer. After MODE is set the counter updates at the rate specified in [PRECFG.*].

Table 13-11 CNTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	Current counter value. If MODE = QDEC this can be used to set the initial counter value during QDEC.

13.5.7 PRECFG Register (Offset = 18h) [Reset = 00000000h]

PRECFG is shown in Table 13-12.

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Clock Prescaler Configuration This register is used to set the timer clock period. The prescaler is a counter which counts down from the value TICKDIV. When the prescaler counter reaches zero, [CNTR.*] is updated. The field TICKDIV effectively divides the prescaler tick source. The timer clock frequency can be calculated as TICKSRC/(TICKDIV+1).

Table 13-12 PRECFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-8	TICKDIV	R/W	0h	Tick division. TICKDIV determines the timer clock frequency for the counter, and timer output updates. The timer clock frequency is the clock selected by TICKSRC divided by (TICKDIV + 1). This inverse is the timer clock period. 0x00: Divide by 1. 0x01: Divide by 2. ... 0xFF: Divide by 256.
7-2	RESERVED	R	0h	Reserved
1-0	TICKSRC	R/W	0h	Prescaler tick source. TICKSRC determines the source which decrements the prescaler. 0h = Prescaler is updated at the system clock. 1h = Prescaler is updated at the rising edge of TICKEN. 2h = Prescaler is updated at the falling edge of TICKEN. 3h = Prescaler is updated at both edges of TICKEN.

13.5.8 PREEVENT Register (Offset = 1Ch) [Reset = 00000000h]

PREEVENT is shown in Table 13-13.

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Prescaler Event This register is used to output a logic high signal before the zero crossing of the prescaler counter. The output is routed to the IOC.

Table 13-13 PREEVENT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	VAL	R/W	0h	Sets the HIGH time of the prescaler event output. Event goes high when the prescaler counter equals [VAL]. Event goes low when prescaler counter is 0. Note: - Can be used to precharge or turn an external component on for a short time before sampling, like in QDEC. - If there is a requirement to create such events that have very short periods compared to timer clock period, use two timers. One timer acts as prescaler and event generator for another timer.

13.5.9 DMA Register (Offset = 3Ch) [Reset = 00000000h]

DMA is shown in Table 13-14.

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Direct Memory Access This register is used to enable DMA requests from the timer and set the register addresses which the DMA will access (read/write). Choose DMA request source by setting the REQ field. The setting of the corresponding interrupt in the [RIS.*] registers also sets the DMA request. Upon a DMA request defined by REQ an internal address pointer is set to Address*4. Every access to [DMARW.*] will increment the internal pointer by 4 such that the next DMA access will be to the next register. The internal pointer will stop after RWC increments. Further access will be ignored.

Table 13-14 DMA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	RWC	R/W	0h	The read/write counter. RWCNTR+1 is the number of times the DMA can access (read/write) the DMARW register. For each DMA access to DMARW an internal counter is incremented, writing to the next address field. Address + 4*RWC is the final register address which can be accessed by the DMA.
15	RESERVED	R	0h	Reserved
14-8	Address	R/W	0h	The base address which the DMA access when reading/writing DMARW. The base address is set by taking the 9 LSB of the physical address and divide by 4. For example, if you wanted the Address to point to the PTGT register you should set Address = 0x0FC/4.
7-3	RESERVED	R	0h	Reserved
2-0	REQ	R/W	0h	DMA request trigger 0h = Disabled 1h = Setting of TGT generates a DMA request. 2h = Setting of ZERO generates a DMA request. 3h = Setting of FAULT generates a DMA request. 4h = Setting of C0CC generates a DMA request. 5h = Setting of C1CC generates a DMA request. 6h = Setting of C2CC generates a DMA request. 7h = Setting of C3CC generates a DMA request.

13.5.10 DMARW Register (Offset = 40h) [Reset = 00000000h]

DMARW is shown in Table 13-15.

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Direct Memory Access This register is used by the DMA to access (read/write) register inside this LGPT module. Each access to this register will increment the internal DMA address counter. See [DMA.*] for description.

Table 13-15 DMARW Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	DMA read write value. The value that is read/written from/to the registers.

13.5.11 ADCTRG Register (Offset = 44h) [Reset = 00000000h]

ADCTRG is shown in Table 13-16.

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ADC Trigger This register is used to enable ADC trigger from the timer. Choose ADC trigger source by setting the SRC field. The setting of the corresponding interrupt in the [RIS.*] registers also sets the ADC trigger.

Table 13-16 ADCTRG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	SRC	R/W	0h	ADC request trigger 0h = Disabled 1h = Setting of TGT generates an ADC trigger. 2h = Setting of ZERO generates an ADC trigger. 3h = Setting of FAULT generates an ADC trigger. 4h = Setting of C0CC generates an ADC trigger. 5h = Setting of C1CC generates an ADC trigger. 6h = Setting of C2CC generates an ADC trigger. 7h = Setting of C3CC generates an ADC trigger.

13.5.12 IOCTL Register (Offset = 48h) [Reset = 00000000h]

IOCTL is shown in Table 13-17.

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IO Controller This register controls the IO outputs.

Table 13-17 IOCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-14	RESERVED	R	0h	Reserved
13-12	RESERVED	R	0h	Reserved
11-10	COUT2	R/W	0h	IO complementary output 2 control This bit field controls IO complementary output 2. 0h = Normal output. The IO complementary output is not changed. 1h = Driven low. The IO complementary output is driven low. 2h = Driven high. The IO complementary output is driven high. 3h = Inverted value. The IO complementary output is inverted.
9-8	OUT2	R/W	0h	IO output 2 control This bit field controls IO output 2. 0h = Normal output. The IO output is not changed. 1h = Driven low. The IO output is driven low. 2h = Driven high. The IO output is driven high. 3h = Inverted value. The IO output is inverted.
7-6	COUT1	R/W	0h	IO complementary output 1 control This bit field controls IO complementary output 1. 0h = Normal output. The IO complementary output is not changed. 1h = Driven low. The IO complementary output is driven low. 2h = Driven high. The IO complementary output is driven high. 3h = Inverted value. The IO complementary output is inverted.
5-4	OUT1	R/W	0h	IO output 1 control This bit field controls IO output 1. 0h = Normal output. The IO output is not changed. 1h = Driven low. The IO output is driven low. 2h = Driven high. The IO output is driven high. 3h = Inverted value. The IO output is inverted.
3-2	COUT0	R/W	0h	IO complementary output 0 control This bit field controls IO complementary output 0. 0h = Normal output. The IO complementary output is not changed. 1h = Driven low. The IO complementary output is driven low. 2h = Driven high. The IO complementary output is driven high. 3h = Inverted value. The IO complementary output is inverted.
1-0	OUT0	R/W	0h	IO output 0 control This bit field controls IO output 0. 0h = Normal output. The IO output is not changed. 1h = Driven low. The IO output is driven low. 2h = Driven high. The IO output is driven high. 3h = Inverted value. The IO output is inverted.

13.5.13 IMASK Register (Offset = 68h) [Reset = 00000000h]

IMASK is shown in Table 13-18.

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Interrupt mask. This register selects interrupt sources which are allowed to pass from [RIS.*] to [MIS.*] when the corresponding bit-fields are set to 1.

Table 13-18 IMASK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	C2CC	R/W	0h	Enable C2CC interrupt. 0h = Disable 1h = Enable
9	C1CC	R/W	0h	Enable C1CC interrupt. 0h = Disable 1h = Enable
8	C0CC	R/W	0h	Enable C0CC interrupt. 0h = Disable 1h = Enable
7	RESERVED	R	0h	Reserved
6	FAULT	R/W	0h	Enable FAULT interrupt. 0h = Disable 1h = Enable
5	IDX	R/W	0h	Enable IDX interrupt. 0h = Disable 1h = Enable
4	DIRCHNG	R/W	0h	Enable DIRCHNG interrupt. 0h = Disable 1h = Enable
3	CNTRCHNG	R/W	0h	Enable CNTRCHNG interrupt. 0h = Disable 1h = Enable
2	DBLTRANS	R/W	0h	Enable DBLTRANS interrupt. 0h = Disable 1h = Enable
1	ZERO	R/W	0h	Enable ZERO interrupt. 0h = Disable 1h = Enable
0	TGT	R/W	0h	Enable TGT interrupt. 0h = Disable 1h = Enable

13.5.14 RIS Register (Offset = 6Ch) [Reset = 00000000h]

RIS is shown in Table 13-19.

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Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.

Table 13-19 RIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	C2CC	R	0h	Status of the [C2CC] interrupt. The interrupt is set when [C2CC] has capture or compare event. 0h = Cleared 1h = Set
9	C1CC	R	0h	Status of the [C1CC] interrupt. The interrupt is set when [C1CC] has capture or compare event. 0h = Cleared 1h = Set
8	C0CC	R	0h	Status of the [C0CC] interrupt. The interrupt is set when [C0CC] has capture or compare event. 0h = Cleared 1h = Set
7	RESERVED	R	0h	Reserved
6	FAULT	R	0h	Status of the [FAULT] interrupt. The interrupt is set immediately on active fault input. 0h = Cleared 1h = Set
5	IDX	R	0h	Status of the [IDX] interrupt. The interrupt is set when [IDX] is active. 0h = Cleared 1h = Set
4	DIRCHNG	R	0h	Status of the [DIRCHNG] interrupt. The interrupt is set when the direction of the counter changes. 0h = Cleared 1h = Set
3	CNTRCHNG	R	0h	Status of the [CNTRCHNG] interrupt. The interrupt is set when the counter increments or decrements. 0h = Cleared 1h = Set
2	DBLTRANS	R	0h	Status of the [DBLTRANS] interrupt. The interrupt is set when a double transition has happened during QDEC mode. 0h = Cleared 1h = Set
1	ZERO	R	0h	Status of the [ZERO] interrupt. The interrupt is set when [CNTR.*] = 0. 0h = Cleared 1h = Set
0	TGT	R	0h	Status of the [TGT] interrupt. The interrupt is set when [CNTR.] = [TGT.]. 0h = Cleared 1h = Set

13.5.15 MIS Register (Offset = 70h) [Reset = 00000000h]

MIS is shown in Table 13-20.

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Masked interrupt status. This register is simply a bit-wise AND of the contents of [IMASK.*] and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.

Table 13-20 MIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	C2CC	R	0h	Masked status of the C2CC interrupt. 0h = Cleared 1h = Set
9	C1CC	R	0h	Masked status of the C1CC interrupt. 0h = Cleared 1h = Set
8	C0CC	R	0h	Masked status of the C0CC interrupt. 0h = Cleared 1h = Set
7	RESERVED	R	0h	Reserved
6	FAULT	R	0h	Masked status of the FAULT interrupt. 0h = Cleared 1h = Set
5	IDX	R	0h	Masked status of the IDX interrupt. 0h = Cleared 1h = Set
4	DIRCHNG	R	0h	Masked status of the DIRCHNG interrupt. 0h = Cleared 1h = Set
3	CNTRCHNG	R	0h	Masked status of the CNTRCHNG interrupt. 0h = Cleared 1h = Set
2	DBLTRANS	R	0h	Masked status of the DBLTRANS interrupt. 0h = Cleared 1h = Set
1	ZERO	R	0h	Masked status of the ZERO interrupt. 0h = Cleared 1h = Set
0	TGT	R	0h	Masked status of the TGT interrupt. 0h = Cleared 1h = Set

13.5.16 ISET Register (Offset = 74h) [Reset = 00000000h]

ISET is shown in Table 13-21.

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Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding [RIS.*] bit also gets set. If the corresponding [IMASK.*] bit is set, then the corresponding [MIS.*] register bit also gets set.

Table 13-21 ISET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	C2CC	W	0h	Set the C2CC interrupt. 0h = No effect 1h = Set
9	C1CC	W	0h	Set the C1CC interrupt. 0h = No effect 1h = Set
8	C0CC	W	0h	Set the C0CC interrupt. 0h = No effect 1h = Set
7	RESERVED	R	0h	Reserved
6	FAULT	W	0h	Set the FAULT interrupt. 0h = No effect 1h = Set
5	IDX	W	0h	Set the IDX interrupt. 0h = No effect 1h = Set
4	DIRCHNG	W	0h	Set the DIRCHNG interrupt. 0h = No effect 1h = Set
3	CNTRCHNG	W	0h	Set the CNTRCHNG interrupt. 0h = No effect 1h = Set
2	DBLTRANS	W	0h	Set the DBLTRANS interrupt. 0h = No effect 1h = Set
1	ZERO	W	0h	Set the ZERO interrupt. 0h = No effect 1h = Set
0	TGT	W	0h	Set the TGT interrupt. 0h = No effect 1h = Set

13.5.17 ICLR Register (Offset = 78h) [Reset = 00000000h]

ICLR is shown in Table 13-22.

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Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding [RIS.*] bit also gets cleared. If the corresponding [IMASK.*] bit is set, then the corresponding [MIS.*] register bit also gets cleared.

Table 13-22 ICLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	C2CC	W	0h	Clear the C2CC interrupt. 0h = No effect 1h = Clear
9	C1CC	W	0h	Clear the C1CC interrupt. 0h = No effect 1h = Clear
8	C0CC	W	0h	Clear the C0CC interrupt. 0h = No effect 1h = Clear
7	RESERVED	R	0h	Reserved
6	FAULT	W	0h	Clear the FAULT interrupt. 0h = No effect 1h = Clear
5	IDX	W	0h	Clear the IDX interrupt. 0h = No effect 1h = Clear
4	DIRCHNG	W	0h	Clear the DIRCHNG interrupt. 0h = No effect 1h = Clear
3	CNTRCHNG	W	0h	Clear the CNTRCHNG interrupt. 0h = No effect 1h = Clear
2	DBLTRANS	W	0h	Clear the DBLTRANS interrupt. 0h = No effect 1h = Clear
1	ZERO	W	0h	Clear the ZERO interrupt. 0h = No effect 1h = Clear
0	TGT	W	0h	Clear the TGT interrupt. 0h = No effect 1h = Clear

13.5.18 IMSET Register (Offset = 7Ch) [Reset = 00000000h]

IMSET is shown in Table 13-23.

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Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding [IMASK.*] bit.

Table 13-23 IMSET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	C2CC	W	0h	Set the C2CC mask. 0h = No effect 1h = Set
9	C1CC	W	0h	Set the C1CC mask. 0h = No effect 1h = Set
8	C0CC	W	0h	Set the C0CC mask. 0h = No effect 1h = Set
7	RESERVED	R	0h	Reserved
6	FAULT	W	0h	Set the FAULT mask. 0h = No effect 1h = Set
5	IDX	W	0h	Set the IDX mask. 0h = No effect 1h = Set
4	DIRCHNG	W	0h	Set the DIRCHNG mask. 0h = No effect 1h = Set
3	CNTRCHNG	W	0h	Set the CNTRCHNG mask. 0h = No effect 1h = Set
2	DBLTRANS	W	0h	Set the DBLTRANS mask. 0h = No effect 1h = Set
1	ZERO	W	0h	Set the ZERO mask. 0h = No effect 1h = Set
0	TGT	W	0h	Set the TGT mask. 0h = No effect 1h = Set

13.5.19 IMCLR Register (Offset = 80h) [Reset = 00000000h]

IMCLR is shown in Table 13-24.

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Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding [IMASK.*] bit.

Table 13-24 IMCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	C2CC	W	0h	Clear the C2CC mask. 0h = No effect 1h = Clear
9	C1CC	W	0h	Clear the C1CC mask. 0h = No effect 1h = Clear
8	C0CC	W	0h	Clear the C0CC mask. 0h = No effect 1h = Clear
7	RESERVED	R	0h	Reserved
6	FAULT	W	0h	Clear the FAULT mask. 0h = No effect 1h = Clear
5	IDX	W	0h	Clear the IDX mask. 0h = No effect 1h = Clear
4	DIRCHNG	W	0h	Clear the DIRCHNG mask. 0h = No effect 1h = Clear
3	CNTRCHNG	W	0h	Clear the CNTRCHNG mask. 0h = No effect 1h = Clear
2	DBLTRANS	W	0h	Clear the DBLTRANS mask. 0h = No effect 1h = Clear
1	ZERO	W	0h	Clear the ZERO mask. 0h = No effect 1h = Clear
0	TGT	W	0h	Clear the TGT mask. 0h = No effect 1h = Clear

13.5.20 EMU Register (Offset = 84h) [Reset = 00000000h]

EMU is shown in Table 13-25.

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Debug control This register can be used to freeze the timer when CPU halts when HALT is set to 1. When HALT is set to 0, or when the CPU releases debug halt, the filters and edge detection logic is flushed and the timer starts. For setting a predefined output value during a CPU debug halt, [PARK.*], if the timer has this register, should be configured additionally. If this timer does not have the [PARK.*] register a predefined output value during CPU halt is not possible.

Table 13-25 EMU Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1	CTL	R/W	0h	Halt control. Configure when the counter shall stop upon CPU halt. This bitfield only applies if HALT = 1. 0h = Immediate reaction. The counter stops immediately on debug halt. 1h = Zero condition. The counter stops when [CNTR.*] = 0.
0	HALT	R/W	0h	Halt LGPT when CPU is halted in debug. 0h = Disable. 1h = Enable.

13.5.21 C0CFG Register (Offset = C0h) [Reset = 00000000h]

C0CFG is shown in Table 13-26.

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Channel 0 Configuration This register configures channel function and enables outputs. Each channel has an edge-detection circuit. The the edge-detection circuit is: - enabled while [CCACT] selects a capture function and MODE is different from DIS. - flushed while [CCACT] selects a capture function and MODE is changed from DIS to another mode. The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. The channel input signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above. - the [CCACT] field is reconfigured while CTL.MODE is different from DIS. Primary use scenario is to select [CCACT] before starting the timer. Follow these steps to configure [CCACT] to a capture action while MODE is different from DIS: - Set [EDGE] to NONE. - Configure [CCACT]. - Wait for three system clock periods before setting [EDGE] different from NONE. These steps prevent capture events caused by expired signal values in edge-detection circuit.

Table 13-26 C0CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	OUT2	R/W	0h	Output 2 enable. When 0 < [CCACT] < 8, OUT2 becomes zero after a capture or compare event. 0h = Channel 0 does not control output 2. 1h = Channel 0 controls output 2.
9	OUT1	R/W	0h	Output 1 enable. When 0 < [CCACT] < 8, OUT1 becomes zero after a capture or compare event. 0h = Channel 0 does not control output 1. 1h = Channel 0 controls output 1.
8	OUT0	R/W	0h	Output 0 enable. When 0 < [CCACT] < 8, OUT0 becomes zero after a capture or compare event. 0h = Channel 0 does not control output 0. 1h = Channel 0 controls output 0.
7	RESERVED	R	0h	Reserved
6	INPUT	R/W	0h	Select channel input. 0h = Event fabric 1h = IO controller
5-4	EDGE	R/W	0h	Determines the edge that triggers the channel input event. This happens post filter. 0h = Input is turned off. 1h = Input event is triggered at rising edge. 2h = Input event is triggered at falling edge. 3h = Input event is triggered at both edges.
3-0	CCACT	R/W	0h	Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of [CNTR.]. The corresponding output event will be set 1 timer period after [CNTR.] = [C0CC.]. 0h = Disable channel. 1h = Set on capture, and then disable channel. Channel function sequence: - Set enabled outputs on capture event and copy VAL to VAL. - Disable channel. Primary use scenario is to select this function before starting the timer. Follow these steps to select this function while MODE is different from DIS: - Set CCACT to SET_ON_CAPT with no output enable. - Configure [INPUT] (optional). - Wait for three timer clock periods as defined in [PRECFG.] before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit. 2h = Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when VAL = 0. - Toggle enabled outputs when VAL = VAL. - Disable channel. Enabled outputs are set when VAL = 0 and VAL = 0. 3h = Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled outputs when VAL = 0. - Toggle enabled outputs when VAL = VAL. - Disable channel. Enabled outputs are cleared when VAL = 0 and VAL = 0. 4h = Clear on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when VAL = VAL. - Disable channel. 5h = Set on compare, and then disable channel. Channel function sequence: - Set enabled outputs when VAL = VAL. - Disable channel. 6h = Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled outputs when VAL = VAL. - Disable channel. 7h = Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled outputs when VAL = VAL. - Disable channel. The output is high for two timer clock periods. 8h = Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by [INPUT] relative to the signal edge given by [EDGE]. Set enabled outputs and C0CC when VAL contains signal period and VAL contains signal pulse width. Notes: - Make sure to configure [INPUT] and CCACT when MODE equals DIS, then set MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when VAL contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - To observe a timeout event the TGT interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal [TGT]. Signal property requirements: - Signal Period >= 2 * ( 1 + TICKDIV ) * timer clock period. - Signal Period <= MAX([CNTR.]) (1 + TICKDIV ) * timer clock period. - Signal low and high phase >= (1 + TICKDIV ) * timer clock period. 9h = Set on capture repeatedly. Channel function sequence: - Set enabled outputs on capture event and copy VAL to VAL. Ah = Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled outputs when VAL = 0. - Toggle enabled outputs when VAL = VAL. Set MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When VAL <= VAL: Duty cycle = 1 - ( VAL / VAL ). When VAL > VAL: Duty cycle = 0. Enabled outputs are set when VAL = 0 and VAL = 0. Bh = Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled outputs when VAL = 0. - Toggle enabled outputs when VAL = VAL. Set MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When VAL <= VAL: Duty cycle = VAL / ( VAL + 1 ). When VAL > VAL: Duty cycle = 1. Enabled outputs are cleared when VAL = 0 and VAL = 0. Ch = Clear on compare repeatedly. Channel function sequence: - Clear enabled outputs when VAL = VAL. Dh = Set on compare repeatedly. Channel function sequence: - Set enabled outputs when VAL = VAL. Eh = Toggle on compare repeatedly. Channel function sequence: - Toggle enabled outputs when VAL = VAL. Fh = Pulse on compare repeatedly. Channel function sequence: - Pulse enabled outputs when VAL = VAL. The output is high for two timer clock periods.

13.5.22 C1CFG Register (Offset = C4h) [Reset = 00000000h]

C1CFG is shown in Table 13-27.

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Channel 1 Configuration This register configures channel function and enables outputs. Each channel has an edge-detection circuit. The the edge-detection circuit is: - enabled while [CCACT] selects a capture function and MODE is different from DIS. - flushed while [CCACT] selects a capture function and MODE is changed from DIS to another mode. The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. The channel input signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above. - the [CCACT] field is reconfigured while CTL.MODE is different from DIS. Primary use scenario is to select [CCACT] before starting the timer. Follow these steps to configure [CCACT] to a capture action while MODE is different from DIS: - Set [EDGE] to NONE. - Configure [CCACT]. - Wait for three system clock periods before setting [EDGE] different from NONE. These steps prevent capture events caused by expired signal values in edge-detection circuit.

Table 13-27 C1CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	OUT2	R/W	0h	Output 2 enable. When 0 < [CCACT] < 8, OUT2 becomes zero after a capture or compare event. 0h = Channel 1 does not control output 2. 1h = Channel 1 controls output 2.
9	OUT1	R/W	0h	Output 1 enable. When 0 < [CCACT] < 8, OUT1 becomes zero after a capture or compare event. 0h = Channel 1 does not control output 1. 1h = Channel 1 controls output 1.
8	OUT0	R/W	0h	Output 0 enable. When 0 < [CCACT] < 8, OUT0 becomes zero after a capture or compare event. 0h = Channel 1 does not control output 0. 1h = Channel 1 controls output 0.
7	RESERVED	R	0h	Reserved
6	INPUT	R/W	0h	Select channel input. 0h = Event fabric 1h = IO controller
5-4	EDGE	R/W	0h	Determines the edge that triggers the channel input event. This happens post filter. 0h = Input is turned off. 1h = Input event is triggered at rising edge. 2h = Input event is triggered at falling edge. 3h = Input event is triggered at both edges.
3-0	CCACT	R/W	0h	Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of [CNTR.]. The corresponding output event will be set 1 timer period after [CNTR.] = [C1CC.]. 0h = Disable channel. 1h = Set on capture, and then disable channel. Channel function sequence: - Set enabled outputs on capture event and copy VAL to VAL. - Disable channel. Primary use scenario is to select this function before starting the timer. Follow these steps to select this function while MODE is different from DIS: - Set CCACT to SET_ON_CAPT with no output enable. - Configure [INPUT] (optional). - Wait for three timer clock periods as defined in [PRECFG.] before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit. 2h = Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when VAL = 0. - Toggle enabled outputs when VAL = VAL. - Disable channel. Enabled outputs are set when VAL = 0 and VAL = 0. 3h = Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled outputs when VAL = 0. - Toggle enabled outputs when VAL = VAL. - Disable channel. Enabled outputs are cleared when VAL = 0 and VAL = 0. 4h = Clear on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when VAL = VAL. - Disable channel. 5h = Set on compare, and then disable channel. Channel function sequence: - Set enabled outputs when VAL = VAL. - Disable channel. 6h = Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled outputs when VAL = VAL. - Disable channel. 7h = Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled outputs when VAL = VAL. - Disable channel. The output is high for two timer clock periods. 8h = Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by [INPUT] relative to the signal edge given by [EDGE]. Set enabled outputs and C1CC when VAL contains signal period and VAL contains signal pulse width. Notes: - Make sure to configure [INPUT] and CCACT when MODE equals DIS, then set MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when VAL contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - To observe a timeout event the TGT interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal [TGT]. Signal property requirements: - Signal Period >= 2 * ( 1 + TICKDIV ) * timer clock period. - Signal Period <= MAX([CNTR.]) (1 + TICKDIV ) * timer clock period. - Signal low and high phase >= (1 + TICKDIV ) * timer clock period. 9h = Set on capture repeatedly. Channel function sequence: - Set enabled outputs on capture event and copy VAL to VAL. Ah = Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled outputs when VAL = 0. - Toggle enabled outputs when VAL = VAL. Set MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When VAL <= VAL: Duty cycle = 1 - ( VAL / VAL ). When VAL > VAL: Duty cycle = 0. Enabled outputs are set when VAL = 0 and VAL = 0. Bh = Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled outputs when VAL = 0. - Toggle enabled outputs when VAL = VAL. Set MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When VAL <= VAL: Duty cycle = VAL / ( VAL + 1 ). When VAL > VAL: Duty cycle = 1. Enabled outputs are cleared when VAL = 0 and VAL = 0. Ch = Clear on compare repeatedly. Channel function sequence: - Clear enabled outputs when VAL = VAL. Dh = Set on compare repeatedly. Channel function sequence: - Set enabled outputs when VAL = VAL. Eh = Toggle on compare repeatedly. Channel function sequence: - Toggle enabled outputs when VAL = VAL. Fh = Pulse on compare repeatedly. Channel function sequence: - Pulse enabled outputs when VAL = VAL. The output is high for two timer clock periods.

13.5.23 C2CFG Register (Offset = C8h) [Reset = 00000000h]

C2CFG is shown in Table 13-28.

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Channel 2 Configuration This register configures channel function and enables outputs. Each channel has an edge-detection circuit. The the edge-detection circuit is: - enabled while [CCACT] selects a capture function and MODE is different from DIS. - flushed while [CCACT] selects a capture function and MODE is changed from DIS to another mode. The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. The channel input signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above. - the [CCACT] field is reconfigured while CTL.MODE is different from DIS. Primary use scenario is to select [CCACT] before starting the timer. Follow these steps to configure [CCACT] to a capture action while MODE is different from DIS: - Set [EDGE] to NONE. - Configure [CCACT]. - Wait for three system clock periods before setting [EDGE] different from NONE. These steps prevent capture events caused by expired signal values in edge-detection circuit.

Table 13-28 C2CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	OUT2	R/W	0h	Output 2 enable. When 0 < [CCACT] < 8, OUT2 becomes zero after a capture or compare event. 0h = Channel 2 does not control output 2. 1h = Channel 2 controls output 2.
9	OUT1	R/W	0h	Output 1 enable. When 0 < [CCACT] < 8, OUT1 becomes zero after a capture or compare event. 0h = Channel 2 does not control output 1. 1h = Channel 2 controls output 1.
8	OUT0	R/W	0h	Output 0 enable. When 0 < [CCACT] < 8, OUT0 becomes zero after a capture or compare event. 0h = Channel 2 does not control output 0. 1h = Channel 2 controls output 0.
7	RESERVED	R	0h	Reserved
6	INPUT	R/W	0h	Select channel input. 0h = Event fabric 1h = IO controller
5-4	EDGE	R/W	0h	Determines the edge that triggers the channel input event. This happens post filter. 0h = Input is turned off. 1h = Input event is triggered at rising edge. 2h = Input event is triggered at falling edge. 3h = Input event is triggered at both edges.
3-0	CCACT	R/W	0h	Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of [CNTR.]. The corresponding output event will be set 1 timer period after [CNTR.] = [C2CC.]. 0h = Disable channel. 1h = Set on capture, and then disable channel. Channel function sequence: - Set enabled outputs on capture event and copy VAL to VAL. - Disable channel. Primary use scenario is to select this function before starting the timer. Follow these steps to select this function while MODE is different from DIS: - Set CCACT to SET_ON_CAPT with no output enable. - Configure [INPUT] (optional). - Wait for three timer clock periods as defined in [PRECFG.] before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit. 2h = Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when VAL = 0. - Toggle enabled outputs when VAL = VAL. - Disable channel. Enabled outputs are set when VAL = 0 and VAL = 0. 3h = Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled outputs when VAL = 0. - Toggle enabled outputs when VAL = VAL. - Disable channel. Enabled outputs are cleared when VAL = 0 and VAL = 0. 4h = Clear on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when VAL = VAL. - Disable channel. 5h = Set on compare, and then disable channel. Channel function sequence: - Set enabled outputs when VAL = VAL. - Disable channel. 6h = Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled outputs when VAL = VAL. - Disable channel. 7h = Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled outputs when VAL = VAL. - Disable channel. The output is high for two timer clock periods. 8h = Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by [INPUT] relative to the signal edge given by [EDGE]. Set enabled outputs and C2CC when VAL contains signal period and VAL contains signal pulse width. Notes: - Make sure to configure [INPUT] and CCACT when MODE equals DIS, then set MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when VAL contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - To observe a timeout event the TGT interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal [TGT]. Signal property requirements: - Signal Period >= 2 * ( 1 + TICKDIV ) * timer clock period. - Signal Period <= MAX([CNTR.]) (1 + TICKDIV ) * timer clock period. - Signal low and high phase >= (1 + TICKDIV ) * timer clock period. 9h = Set on capture repeatedly. Channel function sequence: - Set enabled outputs on capture event and copy VAL to VAL. Ah = Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled outputs when VAL = 0. - Toggle enabled outputs when VAL = VAL. Set MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When VAL <= VAL: Duty cycle = 1 - ( VAL / VAL ). When VAL > VAL: Duty cycle = 0. Enabled outputs are set when VAL = 0 and VAL = 0. Bh = Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled outputs when VAL = 0. - Toggle enabled outputs when VAL = VAL. Set MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When VAL <= VAL: Duty cycle = VAL / ( VAL + 1 ). When VAL > VAL: Duty cycle = 1. Enabled outputs are cleared when VAL = 0 and VAL = 0. Ch = Clear on compare repeatedly. Channel function sequence: - Clear enabled outputs when VAL = VAL. Dh = Set on compare repeatedly. Channel function sequence: - Set enabled outputs when VAL = VAL. Eh = Toggle on compare repeatedly. Channel function sequence: - Toggle enabled outputs when VAL = VAL. Fh = Pulse on compare repeatedly. Channel function sequence: - Pulse enabled outputs when VAL = VAL. The output is high for two timer clock periods.

13.5.24 PTGT Register (Offset = FCh) [Reset = 00000000h]

PTGT is shown in Table 13-29.

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Pipeline Target A read or write to this register will clear the ZERO and TGT interrupt. If MODE != QDEC. Target value for next counter period. The timer will copy VAL to VAL on the upcoming [CNTR.*] zero crossing only if VAL has been written. The copy does not happen when restarting the timer. This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM. If MODE = QDEC The [CNTR.*] value is updated with VALUE on IDX if the counter is counting down. If the counter is counting up, [CNTR.*] is loaded with zero on IDX. In this mode the VALUE is not loaded into [TGT] on zero crossing.

Table 13-29 PTGT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	The pipleline target value.

13.5.25 PC0CC Register (Offset = 100h) [Reset = 00000000h]

PC0CC is shown in Table 13-30.

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Pipeline Channel 0 Capture Compare

Table 13-30 PC0CC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will clear the C0CC interrupt. Compare mode: An update of VAL will be transferred to VAL when the next VAL is zero and MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by EDGE.

13.5.26 PC1CC Register (Offset = 104h) [Reset = 00000000h]

PC1CC is shown in Table 13-31.

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Pipeline Channel 1 Capture Compare

Table 13-31 PC1CC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will clear the C1CC interrupt. Compare mode: An update of VAL will be transferred to VAL when the next VAL is zero and MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by EDGE.

13.5.27 PC2CC Register (Offset = 108h) [Reset = 00000000h]

PC2CC is shown in Table 13-32.

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Pipeline Channel 2 Capture Compare

Table 13-32 PC2CC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will clear the C2CC interrupt. Compare mode: An update of VAL will be transferred to VAL when the next VAL is zero and MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by EDGE.

13.5.28 TGT Register (Offset = 13Ch) [Reset = 00000000h]

TGT is shown in Table 13-33.

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Target User defined counter target. A read or write to this register will clear the ZERO and TGT interrupt.

Table 13-33 TGT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	User defined counter target value.

13.5.29 C0CC Register (Offset = 140h) [Reset = 00000000h]

C0CC is shown in Table 13-34.

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Channel 0 Capture Compare

Table 13-34 C0CC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will clear the C0CC interrupt. Compare mode: VAL is compared against VAL and an event is generated as specified by CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. CCACT determines if VAL is a signal period or a regular capture value.

13.5.30 C1CC Register (Offset = 144h) [Reset = 00000000h]

C1CC is shown in Table 13-35.

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Channel 1 Capture Compare

Table 13-35 C1CC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will clear the C1CC interrupt. Compare mode: VAL is compared against VAL and an event is generated as specified by CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. CCACT determines if VAL is a signal period or a regular capture value.

13.5.31 C2CC Register (Offset = 148h) [Reset = 00000000h]

C2CC is shown in Table 13-36.

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Channel 2 Capture Compare

Table 13-36 C2CC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will clear the C2CC interrupt. Compare mode: VAL is compared against VAL and an event is generated as specified by CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. CCACT determines if VAL is a signal period or a regular capture value.

13.5.32 PTGTNC Register (Offset = 17Ch) [Reset = 00000000h]

PTGTNC is shown in Table 13-37.

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Pipeline Target No Clear Use this register to read or write to [PTGT.*] without clearing the ZERO and TGT interrupt.

Table 13-37 PTGTNC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	A read or write to this register will not clear the TGT interrupt. If MODE != QDEC. Target value for next counter period. The timer copies VAL to VAL when VAL becomes 0. The copy does not happen when restarting the timer. This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM. If MODE = QDEC. The VAL is updated with VAL on IDX. VAL is not loaded into VAL when VAL becomes 0.

13.5.33 PC0CCNC Register (Offset = 180h) [Reset = 00000000h]

PC0CCNC is shown in Table 13-38.

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Pipeline Channel 0 Capture Compare No Clear

Table 13-38 PC0CCNC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will not clear the C0CC interrupt. Compare mode: An update of VAL will be transferred to VAL when the next VAL is zero and MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by EDGE.

13.5.34 PC1CCNC Register (Offset = 184h) [Reset = 00000000h]

PC1CCNC is shown in Table 13-39.

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Pipeline Channel 1 Capture Compare No Clear

Table 13-39 PC1CCNC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will not clear the C1CC interrupt. Compare mode: An update of VAL will be transferred to VAL when the next VAL is zero and MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by EDGE.

13.5.35 PC2CCNC Register (Offset = 188h) [Reset = 00000000h]

PC2CCNC is shown in Table 13-40.

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Pipeline Channel 2 Capture Compare No Clear

Table 13-40 PC2CCNC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will not clear the C2CC interrupt. Compare mode: An update of VAL will be transferred to VAL when the next VAL is zero and MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by EDGE.

13.5.36 TGTNC Register (Offset = 1BCh) [Reset = 00000000h]

TGTNC is shown in Table 13-41.

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Target No Clear Use this register to read or write to [TGT.*] without clearing the ZERO and TGT interrupt.

Table 13-41 TGTNC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	User defined counter target value.

13.5.37 C0CCNC Register (Offset = 1C0h) [Reset = 00000000h]

C0CCNC is shown in Table 13-42.

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Channel 0 Capture Compare No Clear

Table 13-42 C0CCNC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will not clear the C0CC interrupt. Compare mode: VAL is compared against VAL and an event is generated as specified by CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. CCACT determines if VAL is a signal period or a regular capture value.

13.5.38 C1CCNC Register (Offset = 1C4h) [Reset = 00000000h]

C1CCNC is shown in Table 13-43.

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Channel 1 Capture Compare No Clear

Table 13-43 C1CCNC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will not clear the C1CC interrupt. Compare mode: VAL is compared against VAL and an event is generated as specified by CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. CCACT determines if VAL is a signal period or a regular capture value.

13.5.39 C2CCNC Register (Offset = 1C8h) [Reset = 00000000h]

C2CCNC is shown in Table 13-44.

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Channel 2 Capture Compare No Clear

Table 13-44 C2CCNC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R/W	0h	Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will not clear the C2CC interrupt. Compare mode: VAL is compared against VAL and an event is generated as specified by CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. CCACT determines if VAL is a signal period or a regular capture value.

13.5.40 CLKCFG Register (Offset = 1000h) [Reset = 00000000h]

CLKCFG is shown in Table 13-45.

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Clock Enable Register

Table 13-45 CLKCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ENABLE	R/W	0h	GPTimer main clock Enable