SWRU626 December   2025 CC3501E , CC3551E

 

  1.   1
  2. 1 Read This First
    1. 1.1 About This Manual
    2. 1.2 Register, Field, and Bit Calls
    3.     Trademarks
  3. 2 Architecture Overview
    1. 2.1  Target Applications
    2. 2.2  Introduction
    3. 2.3  Internal System Diagram
    4. 2.4  Arm Cortex M33
      1. 2.4.1 Processor Core
      2. 2.4.2 SysTick Timer
      3. 2.4.3 Nested Vectored Interrupt Controller
      4. 2.4.4 System Control Block (SCB)
      5. 2.4.5 TI AI instruction extensions
    5. 2.5  Power Management
      1. 2.5.1 VDD_MAIN
      2. 2.5.2 VDD_IO
      3. 2.5.3 VDDSF
      4. 2.5.4 VDD_PA
    6. 2.6  Debug Subsystem (DEBUGSS)
    7. 2.7  Memory Subsystem (MEMSS)
      1. 2.7.1 External Memory Interface
    8. 2.8  Hardware Security Module
    9. 2.9  General Purpose Timers (GPT)
    10. 2.10 Real Time Clock (RTC)
    11. 2.11 Direct Memory Access
    12. 2.12 GPIOs
    13. 2.13 Communication Peripherals
      1. 2.13.1 UART
      2. 2.13.2 I2C
      3. 2.13.3 SPI
      4. 2.13.4 I2S
      5. 2.13.5 SDMMC
      6. 2.13.6 SDIO
      7. 2.13.7 CAN
      8. 2.13.8 ADC
  4. 3  Arm Cortex-M33 Processor
    1. 3.1 Arm Cortex-M33 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 M33 instantiation parameters
    4. 3.4 Arm Cortex-M33 System Peripheral Details
      1. 3.4.1 Floating Point Unit (FPU)
      2. 3.4.2 Memory Protection Unit (MPU)
      3. 3.4.3 Digital Signal Processing (DSP)
      4. 3.4.4 Security Attribution Unit (SAU)
      5. 3.4.5 System Timer
      6. 3.4.6 Nested Vectored Interrupt Controller
      7. 3.4.7 System Control Block
      8. 3.4.8 System Control Space
    5. 3.5 CPU Sub-System Peripheral Details
      1. 3.5.1 Trace Port Interface Unit (TPIU)
      2. 3.5.2 DAP Bridge and Debug Authentication
      3. 3.5.3 Implementation Defined Attribution Unit (IDAU)
    6. 3.6 Programming Model
      1. 3.6.1 Modes of operation and execution
        1. 3.6.1.1 Security states
        2. 3.6.1.2 Operating modes
        3. 3.6.1.3 Operating states
        4. 3.6.1.4 Privileged access and unprivileged user access
      2. 3.6.2 Instruction set summary
      3. 3.6.3 Memory model
        1. 3.6.3.1 Private Peripheral Bus
        2. 3.6.3.2 Unaligned accesses
      4. 3.6.4 Processor core registers summary
      5. 3.6.5 Exceptions
        1. 3.6.5.1 Exception handling and prioritization
    7. 3.7 TrustZone-M
      1. 3.7.1 Overview
      2. 3.7.2 M33 Configuration
      3. 3.7.3 Description of elements
        1. 3.7.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 3.7.3.1.1 Expected use
    8. 3.8 CC35xx Host MCU Registers
      1. 3.8.1 HOSTMCU_AON Registers
      2. 3.8.2 HOST_MCU Registers
      3. 3.8.3 HOST_MCU_SEC Registers
    9. 3.9 Arm® Cortex®-M33 Registers
      1. 3.9.1  CPU_ROM_TABLE Registers
      2. 3.9.2  TPIU Registers
      3. 3.9.3  DCB Registers
      4. 3.9.4  DIB Registers
      5. 3.9.5  DWT Registers
      6. 3.9.6  FPB Registers
      7. 3.9.7  FPE Registers
      8. 3.9.8  ICB Registers
      9. 3.9.9  ITM Registers
      10. 3.9.10 MPU Registers
      11. 3.9.11 NVIC Registers
      12. 3.9.12 SAU Registers
      13. 3.9.13 SCB Registers
      14. 3.9.14 SYSTIMER Registers
      15. 3.9.15 SYSTICK Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation to HardFault
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Manager
      1. 5.4.1 Introduction
      2. 5.4.2 Interrupts List
      3. 5.4.3 Wakeup Sources
      4. 5.4.4 Shared Peripherals MUX Selector
        1. 5.4.4.1 ADC HW Event Selector Mux
        2. 5.4.4.2 I2S HW Event Selector Mux
        3. 5.4.4.3 PDM HW Event Selector Mux
      5. 5.4.5 Timers MUX Selector Mux
        1. 5.4.5.1 SysTimer0 HW Event Selector Mux
        2. 5.4.5.2 SysTimer1 HW Event Selector Mux
        3. 5.4.5.3 RTC HW Event Selector Mux
      6. 5.4.6 GPTIMERs MUX Selector Mux
        1. 5.4.6.1 GPTIMER0 HW Event Selector Mux
        2. 5.4.6.2 GPTIMER1 HW Event Selector Mux
    5. 5.5 SOC_IC Registers
    6. 5.6 SOC_AON Registers
    7. 5.7 SOC_AAON Registers
  7. 6 Debug Subsystem (DEBUGSS)
    1. 6.1 Introduction
    2. 6.2 Block Diagram
    3. 6.3 Overview
    4. 6.4 Physical Interface
    5. 6.5 Debug Access Ports
    6. 6.6 Debug Features
      1. 6.6.1 Processor Debug
      2. 6.6.2 Breakpoint Unit (BPU)
      3. 6.6.3 Peripheral Debug
    7. 6.7 Behavior in Low Power Modes
    8. 6.8 Debug Access Control
    9. 6.9 SOC_DEBUGSS Registers
  8. 7 Power, Reset, Clock Management
    1. 7.1 Power Management
      1. 7.1.1 Power Supply System
        1. 7.1.1.1 VDD_MAIN
        2. 7.1.1.2 VIO
        3. 7.1.1.3 VDDSF
        4. 7.1.1.4 VPA
      2. 7.1.2 Power States
      3. 7.1.3 Power Domains
      4. 7.1.4 Brownout (BOR)
      5. 7.1.5 Boot Sequence
    2. 7.2 Reset
      1. 7.2.1 Reset Cause
      2. 7.2.2 Watchdog Timer (WDT)
    3. 7.3 Clocks
      1. 7.3.1 Fast Clock
      2. 7.3.2 Slow Clock
        1. 7.3.2.1 Slow Clock Overview
        2. 7.3.2.2 Slow Clock Tree
        3. 7.3.2.3 Slow Clock Boot Process
    4. 7.4 PRCM_AON Registers
    5. 7.5 PRCM_SCRATCHPAD Registers
  9. 8 Memory Subsystem (MEMSS)
    1. 8.1  Introduction
    2. 8.2  SRAM
    3. 8.3  D-Cache
    4. 8.4  Flash
    5. 8.5  PSRAM
    6. 8.6  XiP Memory Access
      1. 8.6.1 OTFDE
      2. 8.6.2 xSPI
      3. 8.6.3 Topology
      4. 8.6.4 µDMA
      5. 8.6.5 Arbiter
    7. 8.7  ICACHE Registers
    8. 8.8  DCACHE Registers
    9. 8.9  OSPI Registers
    10. 8.10 HOST_XIP Registers
  10. 9 Hardware Security Module (HSM)
    1. 9.1 Introduction
    2. 9.2 Overview
    3. 9.3 Mailbox and Register Access Firewall
    4. 9.4 DMA Firewall
    5. 9.5 HSM Key Storage
    6. 9.6 HSM Registers
    7. 9.7 HSM_NON_SEC Registers
    8. 9.8 HSM_SEC Registers
  11. 10Device Boot and Bootloader
    1. 10.1 CC35xx Boot Concept
    2. 10.2 Features
    3. 10.3 Vendor Images Format and Processing
      1. 10.3.1 External Flash Arrangement
      2. 10.3.2 Vendor Images Format
    4. 10.4 Boot Flows
      1. 10.4.1 Application Execution Boot Flow
      2. 10.4.2 Activation Flow
      3. 10.4.3 Initial Programming Flow
      4. 10.4.4 Reprogramming Flow
      5. 10.4.5 Wireless Connectivity Testing Tool Flow
    5. 10.5 Chain of Trust
  12. 11Direct Memory Access (DMA)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Channels Assignment
      2. 11.3.2 Transfer Types
      3. 11.3.3 Addressing Modes
      4. 11.3.4 Transfer Modes
      5. 11.3.5 DMA Aligner Support
      6. 11.3.6 Initiating DMA Transfers
      7. 11.3.7 Stopping DMA Transfers
      8. 11.3.8 Channel Priorities
      9. 11.3.9 DMA Interrupts
    4. 11.4 HOST_DMA Registers
  13. 12One Time Programming (OTP)
  14. 13General Purpose Timers (GPT)
    1. 13.1 Overview
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1  Prescaler
      2. 13.3.2  Counter
      3. 13.3.3  Target
      4. 13.3.4  Channel Input Logic
      5. 13.3.5  Channel Output Logic
      6. 13.3.6  Channel Actions
        1. 13.3.6.1 Period and Pulse Width Measurement
        2. 13.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 13.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 13.3.7  Channel Capture Configuration
      8. 13.3.8  Channel Filters
        1. 13.3.8.1 Setting up the Channel Filters
      9. 13.3.9  Synchronize Multiple GPTimers
      10. 13.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 13.4 Timer Modes
      1. 13.4.1 Quadrature Decoder
      2. 13.4.2 DMA
      3. 13.4.3 IR Generation
      4. 13.4.4 Fault and Park
      5. 13.4.5 Dead-Band
      6. 13.4.6 Dead-Band, Fault and Park
      7. 13.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 13.5 GPTIMER Registers
  15. 14System Timer (SysTimer)
    1. 14.1 Overview
    2. 14.2 Block Diagram
    3. 14.3 Functional Description
      1. 14.3.1 Common Channel Features
        1. 14.3.1.1 Compare Mode
        2. 14.3.1.2 Capture Mode
        3. 14.3.1.3 Additional Channel Arming Methods
      2. 14.3.2 Interrupts and Events
    4. 14.4 SYSRESOURCES Registers
    5. 14.5 SYSTIM Registers
  16. 15Real-Time Clock (RTC)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Interrupts and Events
      1. 15.3.1 Input Event
      2. 15.3.2 Output Event
      3. 15.3.3 Arming and Disarming Channels
    4. 15.4 CAPTURE and COMPARE Configurations
      1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
    5. 15.5 RTC Registers
  17. 16General Purpose Input/Output (GPIOs)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 I/O Mapping and Configuration
      1. 16.3.1 Basic I/O Mapping
      2. 16.3.2 Pin Mapping
    4. 16.4 Edge Detection
    5. 16.5 GPIO
    6. 16.6 I/O Pins
    7. 16.7 Unused Pins
    8. 16.8 IOMUX Registers
  18. 17Universal Asynchronous Receivers/Transmitters (UART)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 UART Functional Description
      1. 17.3.1 Transmit and Receive Logic
      2. 17.3.2 Baud Rate Generation
      3. 17.3.3 FIFO Operation
        1. 17.3.3.1 FIFO Remapping
      4. 17.3.4 Data Transmission
      5. 17.3.5 Flow Control
      6. 17.3.6 IrDA Encoding and Decoding
      7. 17.3.7 Interrupts
      8. 17.3.8 Loopback Operation
    4. 17.4 UART-LIN Specification
      1. 17.4.1 Break transmission in UART mode
      2. 17.4.2 Break reception in UART mode
      3. 17.4.3 Break/Synch transmission in LIN mode
      4. 17.4.4 Break/Synch reception in LIN mode
      5. 17.4.5 Dormant mode operation
      6. 17.4.6 Event signal generation
      7. 17.4.7 Event signal detection when device is in active/idle modes
      8. 17.4.8 Event signal detection when device is in sleep mode
    5. 17.5 Interface to Host DMA
    6. 17.6 Initialization and Configuration
    7. 17.7 UART Registers
  19. 18Serial Peripheral Interface (SPI)
    1. 18.1 Overview
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Signal Description
    3. 18.3 Functional Description
      1. 18.3.1  Clock Control
      2. 18.3.2  FIFO Operation
        1. 18.3.2.1 Transmit FIFO
        2. 18.3.2.2 Repeated Transmit Operation
        3. 18.3.2.3 Receive FIFO
        4. 18.3.2.4 FIFO Flush
      3. 18.3.3  Interrupts
      4. 18.3.4  Data Format
      5. 18.3.5  Delayed Data Sampling
      6. 18.3.6  Chip Select Control
      7. 18.3.7  Command Data Control
      8. 18.3.8  Protocol Descriptions
        1. 18.3.8.1 Motorola SPI Frame Format
        2. 18.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 18.3.8.3 MICROWIRE Frame Format
      9. 18.3.9  CRC Configuration
      10. 18.3.10 Auto CRC Functionality
      11. 18.3.11 SPI Status
      12. 18.3.12 Debug Halt
    4. 18.4 Host DMA Operation
    5. 18.5 Initialization and Configuration
    6. 18.6 SPI Registers
  20. 19Inter-Integrated Circuit (I2C) Interface
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Clock Control
        1. 19.3.1.1 Internal Clock
        2. 19.3.1.2 External Clock
      2. 19.3.2 General Architecture
        1. 19.3.2.1  Start and Stop Conditions
        2. 19.3.2.2  Data Format with 7-Bit Address
        3. 19.3.2.3  Data Format with 10-Bit Addressing
          1. 19.3.2.3.1 Additional 10-Bit Scenarios
        4. 19.3.2.4  Acknowledge
        5. 19.3.2.5  Repeated Start
        6. 19.3.2.6  Clock Stretching
        7. 19.3.2.7  Arbitration
        8. 19.3.2.8  Multi-Controller mode
        9. 19.3.2.9  Glitch Suppression
        10. 19.3.2.10 FIFO Operation
        11. 19.3.2.11 Burst Mode Operation
        12. 19.3.2.12 DMA Operation
        13. 19.3.2.13 Flush Stale Tx Data in Target Mode
          1. 19.3.2.13.1 Recommended Sequence
        14. 19.3.2.14 SMBUS 3.0 Support
          1. 19.3.2.14.1 Quick Command
          2. 19.3.2.14.2 Acknowledge Control
          3. 19.3.2.14.3 Alert Response protocol
          4. 19.3.2.14.4 Address Resolution Protocol
          5. 19.3.2.14.5 Enhanced Acknowledge Control
    4. 19.4 Initialization and Configuration
    5. 19.5 Interrupts
    6. 19.6 I2C Registers
  21. 20Secure Digital Multimedia Card (SDMMC)
    1. 20.1 Introduction
      1. 20.1.1 SDMMC Features
      2. 20.1.2 Integration
    2. 20.2 Functional Description
      1. 20.2.1  SDMMC Functional Modes
        1. 20.2.1.1 SDMMC Connected to an SD Card
        2. 20.2.1.2 Protocol and Data Format
          1. 20.2.1.2.1 Protocol
          2. 20.2.1.2.2 Data Format
      2. 20.2.2  SD Card Feedback
      3. 20.2.3  Resets
        1. 20.2.3.1 Hardware Reset
        2. 20.2.3.2 Software Reset
      4. 20.2.4  Interrupt Requests
        1. 20.2.4.1 Interrupt-Driven Operation
        2. 20.2.4.2 Polling
      5. 20.2.5  DMA Modes
        1. 20.2.5.1 DMA Peripheral Mode Operations
          1. 20.2.5.1.1 DMA Receive Mode
          2. 20.2.5.1.2 DMA Transmit Mode
      6. 20.2.6  Buffer Management
        1. 20.2.6.1 Data Buffer
          1. 20.2.6.1.1 Memory Size and Block Length
          2. 20.2.6.1.2 Data Buffer Status
      7. 20.2.7  Transfer Process
        1. 20.2.7.1 Different Types of Commands
        2. 20.2.7.2 Different Types of Responses
      8. 20.2.8  Transfer or Command Status and Error Reporting
        1. 20.2.8.1 Busy Timeout for R1b, R5b Response Type
        2. 20.2.8.2 Busy Timeout After Write CRC Status
        3. 20.2.8.3 Write CRC Status Timeout
        4. 20.2.8.4 Read Data Timeout
      9. 20.2.9  Auto Command 12 Timings
        1. 20.2.9.1 Auto Command 12 Timings During Write Transfer
        2. 20.2.9.2 Auto Command 12 Timings During Read Transfer
      10. 20.2.10 Transfer Stop
      11. 20.2.11 Output Signals Generation
        1. 20.2.11.1 Generation on Falling Edge of SDMMC Clock
        2. 20.2.11.2 Generation on Rising Edge of SDMMC Clock
      12. 20.2.12 Test Registers
      13. 20.2.13 SDMMC Hardware Status Features
    3. 20.3 Low-Level Programming Models
      1. 20.3.1 SDMMC Initialization Flow
        1. 20.3.1.1 Enable OCP and CLKADPI Clocks
        2. 20.3.1.2 SD Soft Reset Flow
        3. 20.3.1.3 Set SD Default Capabilities
        4. 20.3.1.4 SDMMC Host and Bus Configuration
      2. 20.3.2 Operational Modes Configuration
        1. 20.3.2.1 Basic Operations for SDMMC
        2. 20.3.2.2 Card Detection, Identification, and Selection
    4. 20.4 SDMMC Registers
  22. 21Secure Digital Input/Output (SDIO)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 SDIO Interface Description
      2. 21.3.2 Protocol and Data Format
      3. 21.3.3 I/O Read/Write Command
        1. 21.3.3.1 IO_WR_DIRECT Command (CMD52)
        2. 21.3.3.2 IO_WR_EXTENDED Command (CMD53)
      4. 21.3.4 Reset
      5. 21.3.5 FIFO Operation
        1. 21.3.5.1 Rx FIFO (For Host Write)
        2. 21.3.5.2 Tx FIFO (For Host Read)
      6. 21.3.6 Interrupt Request
        1. 21.3.6.1 External Host IRQ
        2. 21.3.6.2 M33 IRQ
      7. 21.3.7 Transaction Details
        1. 21.3.7.1 Host write to SDIO IP (Rx FIFO)
          1. 21.3.7.1.1 Host write to SDIO IP (Rx FIFO) – Long SW latency case
          2. 21.3.7.1.2 Host write to SDIO IP (Rx FIFO) – CRC Error Case
        2. 21.3.7.2 Host reads from SDIO (TX buffer)
    4. 21.4 SDIO_CORE Registers
    5. 21.5 SDIO_CARD_FN1 Registers
  23. 22Inter-Integrated Circuit Sound (I2S)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  Signal Descriptions
    4. 22.4  Functional Description
      1. 22.4.1 Pin Configuration
      2. 22.4.2 Serial Format Configuration
        1. 22.4.2.1 Register Configuration
      3. 22.4.3 Left-Justified (LJF)
        1. 22.4.3.1 Register Configuration
      4. 22.4.4 Right-Justified (RJF)
        1. 22.4.4.1 Register Configuration
      5. 22.4.5 DSP
        1. 22.4.5.1 Register Configuration
      6. 22.4.6 Clock Configuration
    5. 22.5  Memory Interface
      1. 22.5.1 Sample Word Length
      2. 22.5.2 Padding Mechanism
      3. 22.5.3 Channel Mapping
      4. 22.5.4 Sample Storage in Memory
      5. 22.5.5 DMA Operation
        1. 22.5.5.1 Start-Up
        2. 22.5.5.2 Operation
        3. 22.5.5.3 Shutdown
    6. 22.6  Samplestamp Generator
      1. 22.6.1 Samplestamp Counters
      2. 22.6.2 Start-Up Triggers
      3. 22.6.3 Samplestamp Capture
      4. 22.6.4 Achieving constant audio latency
    7. 22.7  Error Detection
    8. 22.8  Usage
      1. 22.8.1 Start-Up Sequence
      2. 22.8.2 Shutdown Sequence
    9. 22.9  I2S Configuration Guideline
    10. 22.10 I2S Registers
  24. 23Pulse Density Modulation (PDM)
    1. 23.1  Introduction
    2. 23.2  Block Diagram
    3. 23.3  Input Selection
      1. 23.3.1 PDM Data Mode
      2. 23.3.2 Manchester Input Mode
    4. 23.4  CIC Filter
      1. 23.4.1 Filter Design
      2. 23.4.2 Digital Filter Output
      3. 23.4.3 Offset Binary Mode
      4. 23.4.4 Twos-Complement Mode
    5. 23.5  FIFO Organization in Different Modes
      1. 23.5.1 Single Mono Microphone Configuration
        1. 23.5.1.1 24-bit Sample Size
          1. 23.5.1.1.1 32-bit Data Read
        2. 23.5.1.2 16-bit Sample Size
          1. 23.5.1.2.1 32-bit Data Read
          2. 23.5.1.2.2 16-bit Data Read
        3. 23.5.1.3 8-bit Sample Size
          1. 23.5.1.3.1 32-bit Data Read
          2. 23.5.1.3.2 16-bit Data Read
          3. 23.5.1.3.3 8-bit Data Read
      2. 23.5.2 Stereo or Dual Mono Microphone Configuration
        1. 23.5.2.1 24-bit Sample Size
          1. 23.5.2.1.1 32-bit Data Read
        2. 23.5.2.2 16-bit Sample Size
          1. 23.5.2.2.1 32-bit Data Read
          2. 23.5.2.2.2 16-bit Data Read
        3. 23.5.2.3 8-bit Sample Size
          1. 23.5.2.3.1 32-bit Data Read
          2. 23.5.2.3.2 16-bit Data Read
          3. 23.5.2.3.3 8-bit Data Read
      3. 23.5.3 FIFO Threshold Setting
      4. 23.5.4 Reset FIFO
    6. 23.6  Automatic Gain Control (AGC)
      1. 23.6.1 Operation in 2's Complement Format
      2. 23.6.2 Operation in Offset Binary Format
    7. 23.7  Interrupts
    8. 23.8  Clock Select and Control
    9. 23.9  DMA Operation
    10. 23.10 Samplestamp Generator
      1. 23.10.1 Samplestamp Counters
      2. 23.10.2 Start-Up Triggers
      3. 23.10.3 Samplestamp Capture
      4. 23.10.4 Achieving Constant Audio Latency
    11. 23.11 Debug‑Mode Flag Behavior
    12. 23.12 Software Guidelines
    13. 23.13 PDM Registers
  25. 24Analog to Digital Converter (ADC)
    1. 24.1 Overview
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1  ADC Core
      2. 24.3.2  Voltage Reference Options
      3. 24.3.3  Internal Channels
      4. 24.3.4  Resolution Modes
      5. 24.3.5  ADC Clocking
      6. 24.3.6  Power Down Behavior
      7. 24.3.7  Sampling Trigger Sources and Sampling Modes
        1. 24.3.7.1 AUTO Sampling Mode
        2. 24.3.7.2 MANUAL Sampling Mode
      8. 24.3.8  Sampling Period
      9. 24.3.9  Conversion Modes
      10. 24.3.10 ADC Data Format
      11. 24.3.11 Status Register
      12. 24.3.12 ADC Events
        1. 24.3.12.1 Generic Event Publishers (INT_EVENT0 & INT_EVENT1)
        2. 24.3.12.2 DMA Trigger Event Publisher (INT_EVENT2)
        3. 24.3.12.3 Generic Event Subscriber
      13. 24.3.13 Advanced Features
        1. 24.3.13.1 Window Comparator
        2. 24.3.13.2 DMA & FIFO Operation
          1. 24.3.13.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
          2. 24.3.13.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
          3. 24.3.13.2.3 DMA/CPU Operation Summary Matrix
        3. 24.3.13.3 Ad-hoc Single Conversion
    4. 24.4 ADC Registers
  26. 25Controller Area Network (CAN)
    1. 25.1 Introduction
    2. 25.2 Functions
    3. 25.3 DCAN Subsystem
    4. 25.4 DCAN Functional Description
      1. 25.4.1 Operating Modes
        1. 25.4.1.1 Software Initialization
        2. 25.4.1.2 Normal Operation
        3. 25.4.1.3 Restricted Operation Mode
        4. 25.4.1.4 Bus Monitoring Mode
        5. 25.4.1.5 Disabled Automatic Retransmission
          1. 25.4.1.5.1 Frame Transmission in DAR Mode
        6. 25.4.1.6 Power Down (Sleep Mode)
          1. 25.4.1.6.1 DCAN clock stop and wake operations
          2. 25.4.1.6.2 DCAN debug suspend operation
        7. 25.4.1.7 Test Modes
          1. 25.4.1.7.1 External Loop Back Mode
          2. 25.4.1.7.2 Internal Loop Back Mode
      2. 25.4.2 Timestamp Generation
        1. 25.4.2.1 Block Diagram
      3. 25.4.3 Timeout Counter
      4. 25.4.4 Rx Handling
        1. 25.4.4.1 Acceptance Filtering
          1. 25.4.4.1.1 Range Filter
          2. 25.4.4.1.2 Filter for specific IDs
          3. 25.4.4.1.3 Classic Bit Mask Filter
          4. 25.4.4.1.4 Standard Message ID Filtering
          5. 25.4.4.1.5 Extended Message ID Filtering
        2. 25.4.4.2 Rx FIFOs
          1. 25.4.4.2.1 Rx FIFO Blocking Mode
          2. 25.4.4.2.2 Rx FIFO Overwrite Mode
        3. 25.4.4.3 Dedicated Rx Buffers
          1. 25.4.4.3.1 Rx Buffer Handling
        4. 25.4.4.4 Debug on CAN Support
          1. 25.4.4.4.1 Filtering for Debug Messages
          2. 25.4.4.4.2 Debug Message Handling
      5. 25.4.5 Tx Handling
        1. 25.4.5.1 Transmit Pause
        2. 25.4.5.2 Dedicated Tx Buffers
        3. 25.4.5.3 Tx FIFO
        4. 25.4.5.4 Tx Queue
        5. 25.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 25.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 25.4.5.7 Transmit Cancellation
        8. 25.4.5.8 Tx Event Handling
      6. 25.4.6 FIFO Acknowledge Handling
      7. 25.4.7 DCAN Message RAM
        1. 25.4.7.1 Message RAM Configuration
        2. 25.4.7.2 Rx Buffer and FIFO Element
        3. 25.4.7.3 Tx Buffer Element
        4. 25.4.7.4 Tx Event FIFO Element
        5. 25.4.7.5 Standard Message ID Filter Element
        6. 25.4.7.6 Extended Message ID Filter Element
      8. 25.4.8 Interrupt Requests
    5. 25.5 DCAN Wrapper
    6. 25.6 DCAN Clock Enable
    7. 25.7 DCAN Registers
  27. 26Revision History

11.4 HOST_DMA Registers

Table 11-1 lists the memory-mapped registers for the HOST_DMA registers. All register offset addresses not listed in Table 11-1 should be considered as reserved locations and the register contents should not be modified.

Table 11-1 HOST_DMA Registers
OffsetAcronymRegister NameSection
0hCHCTL0Channel Assignment ControlSection 11.4.1
4hCHCTL1Channel Assignment MapSection 11.4.2
18hPRIOCFGPriority Channel ConfigurationSection 11.4.3
1000hCH0STAChannel StatusSection 11.4.4
1004hCH0TIPTRInput Pointer AddressSection 11.4.5
1008hCH0OPTROutput Address PointerSection 11.4.6
100ChCH0TCTLTransaction ControlSection 11.4.7
1010hCH0TCTL2Transfer Control ConfigurationSection 11.4.8
1014hCH0TSTATransaction StatusSection 11.4.9
101ChCH0JCTLChannel Job ControlSection 11.4.10
2000hCH1STAChannel StatusSection 11.4.11
2004hCH1TIPTRInput Pointer AddressSection 11.4.12
2008hCH1TOPTROutput Pointer AddressSection 11.4.13
200ChCH1TCTLTransaction ControlSection 11.4.14
2010hCH1TCTRL2Transaction ControlSection 11.4.15
2014hCH1TSTATransaction StatusSection 11.4.16
201ChCH1JCTLChannel Job ControlSection 11.4.17
3000hCH2STAChannel StatusSection 11.4.18
3004hCH2TIPTRInput Address PointerSection 11.4.19
3008hCH2TOPTROutput Address PointerSection 11.4.20
300ChCH2TCTLTransaction ControlSection 11.4.21
3010hCH2TCTL2DMA Command InterfaceSection 11.4.22
3014hCH2TSTATransaction StatusSection 11.4.23
301ChCH2JCTLChannel 2 ControlSection 11.4.24
4000hCH3STAChannel StatusSection 11.4.25
4004hCH3TIPTRInput Address PointerSection 11.4.26
4008hCH3TOPTROutput Address PointerSection 11.4.27
400ChCH3TCTLTransaction ControlSection 11.4.28
4010hCH3TCTL2Channel 3 ControlSection 11.4.29
4014hCH3TSTAChannel 3 StatusSection 11.4.30
401ChCH3JCTLChannel 3 ControlSection 11.4.31
5000hCH4STAChannel Status InformationSection 11.4.32
5004hCH4TIPTRInput Address PointerSection 11.4.33
5008hCH4TOPTROutput Address PointerSection 11.4.34
500ChCH4TCTLTransaction ControlSection 11.4.35
5010hCH4TCTL2Channel 4 Transfer ControlSection 11.4.36
5014hCH4TSTATransfer Status Channel 4Section 11.4.37
501ChCH4JCTLChannel 4 ControlSection 11.4.38
6000hCH5STAChannel StatusSection 11.4.39
6004hCH5TIPTRInput Address PointerSection 11.4.40
6008hCH5TOPTROutput Address PointerSection 11.4.41
600ChCH5TCTLChannel 5 ControlSection 11.4.42
6010hCH5TCTL2Transfer ControlSection 11.4.43
6014hCH5TSTATransaction StatusSection 11.4.44
601ChCH5JCTLChannel 5 ControlSection 11.4.45
7000hCH6STAChannel StatusSection 11.4.46
7004hCH6TIPTRInput Address PointerSection 11.4.47
7008hCH6TOPTROutput Address PointerSection 11.4.48
700ChCH6TCTLTransaction ControlSection 11.4.49
7010hCH6TCTL2Channel 6 ControlSection 11.4.50
7014hCH6TSTATransaction StatusSection 11.4.51
701ChCH6JCTLChannel 6 ControlSection 11.4.52
8000hCH7STAChannel StatusSection 11.4.53
8004hCH7TIPTRInput Address PointerSection 11.4.54
8008hCH7TOPTROutput Address PointerSection 11.4.55
800ChCH7TCTLTransaction ControlSection 11.4.56
8010hCH7TCTL2Channel 7 ControlSection 11.4.57
8014hCH7TSTAChannel 7 StatusSection 11.4.58
801ChCH7JCTLChannel 7 ControlSection 11.4.59
9000hCH8STAChannel StatusSection 11.4.60
9004hCH8TIPTRInput Address PointerSection 11.4.61
9008hCH8TOPTROutput Address PointerSection 11.4.62
900ChCH8TCTLChannel 8 ControlSection 11.4.63
9010hCH8TCTL2Channel 8 ControlSection 11.4.64
9014hCH8TSTAChannel 8 StatusSection 11.4.65
901ChCH8JCTLChannel 8 ControlSection 11.4.66
A000hCH9STAChannel StatusSection 11.4.67
A004hCH9TIPTROutput Address PointerSection 11.4.68
A008hCH9TOPTROutput Address PointerSection 11.4.69
A00ChCH9TCTLTransaction ControlSection 11.4.70
A010hCH9TCTL2Channel 9 ControlSection 11.4.71
A014hCH9TSTATransaction StatusSection 11.4.72
A01ChCH9JCTLChannel 9 ControlSection 11.4.73
B000hCH10STAChannel StatusSection 11.4.74
B004hCH10TIPTRInput Address PointerSection 11.4.75
B008hCH10TOPTROutput Address PointerSection 11.4.76
B00ChCH10TCTLChannel 10 ControlSection 11.4.77
B010hCH10TCTL2Channel 10 ControlSection 11.4.78
B014hCH10TSTATransfer StatusSection 11.4.79
B01ChCH10JCTLChannel 10 ControlSection 11.4.80
C000hCH11STAChannel Status InformationSection 11.4.81
C004hCH11TIPTRInput Address PointerSection 11.4.82
C008hCH11TOPTROutput Address PointerSection 11.4.83
C00ChCH11TCTLChannel Transaction ControlSection 11.4.84
C010hCH11TCTL2Channel 11 Transfer ControlSection 11.4.85
C014hCH11TSTAChannel Transaction StatusSection 11.4.86
C01ChCH11JCTLChannel 11 ControlSection 11.4.87
D000hCH12STAChannel StatusSection 11.4.88
D004hCH12TIPTRInput PointerSection 11.4.89
D008hCH12TOPTROutput Address PointerSection 11.4.90
D00ChCH12TCTLTransaction ControlSection 11.4.91
D010hCH12TCTL2Channel 12 TransferSection 11.4.92
D014hCH12TSTATransaction StatusSection 11.4.93
D01ChCH12JCTLJob ControlSection 11.4.94
E000hCH13STAChannel Status RegisterSection 11.4.95
E004hCH13TIPTRInput Address PointerSection 11.4.96
E008hCH13TOPTROutput Address PointerSection 11.4.97
E00ChCH13TCTLChannel Transaction ControlSection 11.4.98
E010hCH13TCTL2Channel 13 TransferSection 11.4.99
E014hCH13TSTATransfer StatusSection 11.4.100
E01ChCH13JCTLChannel 13 ControlSection 11.4.101

Complex bit access types are encoded to fit into small table cells. Table 11-2 shows the codes that are used for access types in this section.

Table 11-2 HOST_DMA Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

11.4.1 CHCTL0 Register (Offset = 0h) [Reset = 00000000h]

CHCTL0 is shown in Table 11-3.

Return to the Summary Table.

Host DMA Channel Controlled by Defined Peripheral. The value of each fields concats with [HOST_DMA:JOBCTLCHx.SRCDSTCFG] (when x is channel num) if [CHCTL0.CHx] = 4 and [JOBCTLCHx.SRCDSTCFG] = 1 (value = 0100_1 = 9) then flow control signals of channel x are connected to periph number 9 flow control signals Note: [CHCTL0.CHx] = 0xF is forbidden. This configuration should be only used for Dynamic Switch

Table 11-3 CHCTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-28CH7R/W0hChannel 7 Control. The following Enums represent the configuration values to bind the DMA channel to each peripheral:
  • 0h = UART0 peripheral
  • 1h = UART1 peripheral
  • 2h = SPI0 peripheral
  • 3h = SPI1 peripheral
  • 4h = I2C0 peripheral
  • 5h = I2C1 peripheral
  • 6h = SDMMC peripheral
  • 7h = SDIO peripheral
  • 8h = DCAN peripheral
  • 9h = ADC peripheral
  • Ah = PDM peripheral
  • Bh = HIF peripheral
  • Ch = UART2 peripheral
27-24CH6R/W0hChannel 6 Control. The following Enums represent the configuration values to bind the DMA channel to each peripheral:
  • 0h = UART0 peripheral
  • 1h = UART1 peripheral
  • 2h = SPI0 peripheral
  • 3h = SPI1 peripheral
  • 4h = I2C0 peripheral
  • 5h = I2C1 peripheral
  • 6h = SDMMC peripheral
  • 7h = SDIO peripheral
  • 8h = DCAN peripheral
  • 9h = ADC peripheral
  • Ah = PDM peripheral
  • Bh = HIF peripheral
  • Ch = UART2 peripheral
23-20CH5R/W0hChannel 5 Control. The following Enums represent the configuration values to bind the DMA channel to each peripheral:
  • 0h = UART0 peripheral
  • 1h = UART1 peripheral
  • 2h = SPI0 peripheral
  • 3h = SPI1 peripheral
  • 4h = I2C0 peripheral
  • 5h = I2C1 peripheral
  • 6h = SDMMC peripheral
  • 7h = SDIO peripheral
  • 8h = DCAN peripheral
  • 9h = ADC peripheral
  • Ah = PDM peripheral
  • Bh = HIF peripheral
  • Ch = UART2 peripheral
19-16CH4R/W0hChannel 4 Control. The following Enums represent the configuration values to bind the DMA channel to each peripheral:
  • 0h = UART0 peripheral
  • 1h = UART1 peripheral
  • 2h = SPI0 peripheral
  • 3h = SPI1 peripheral
  • 4h = I2C0 peripheral
  • 5h = I2C1 peripheral
  • 6h = SDMMC peripheral
  • 7h = SDIO peripheral
  • 8h = DCAN peripheral
  • 9h = ADC peripheral
  • Ah = PDM peripheral
  • Bh = HIF peripheral
  • Ch = UART2 peripheral
15-12CH3R/W0hChannel 3 Control. The following Enums represent the configuration values to bind the DMA channel to each peripheral:
  • 0h = UART0 peripheral
  • 1h = UART1 peripheral
  • 2h = SPI0 peripheral
  • 3h = SPI1 peripheral
  • 4h = I2C0 peripheral
  • 5h = I2C1 peripheral
  • 6h = SDMMC peripheral
  • 7h = SDIO peripheral
  • 8h = DCAN peripheral
  • 9h = ADC peripheral
  • Ah = PDM peripheral
  • Bh = HIF peripheral
  • Ch = UART2 peripheral
11-8CH2R/W0hChannel 2 Control. The following Enums represent the configuration values to bind the DMA channel to each peripheral:
  • 0h = UART0 peripheral
  • 1h = UART1 peripheral
  • 2h = SPI0 peripheral
  • 3h = SPI1 peripheral
  • 4h = I2C0 peripheral
  • 5h = I2C1 peripheral
  • 6h = SDMMC peripheral
  • 7h = SDIO peripheral
  • 8h = DCAN peripheral
  • 9h = ADC peripheral
  • Ah = PDM peripheral
  • Bh = HIF peripheral
  • Ch = UART2 peripheral
7-4CH1R/W0hChannel 1 Control. The following Enums represent the configuration values to bind the DMA channel to each peripheral:
  • 0h = UART0 peripheral
  • 1h = UART1 peripheral
  • 2h = SPI0 peripheral
  • 3h = SPI1 peripheral
  • 4h = I2C0 peripheral
  • 5h = I2C1 peripheral
  • 6h = SDMMC peripheral
  • 7h = SDIO peripheral
  • 8h = DCAN peripheral
  • 9h = ADC peripheral
  • Ah = PDM peripheral
  • Bh = HIF peripheral
  • Ch = UART2 peripheral
3-0CH0R/W0hChannel 0 Control. The following Enums represent the configuration values to bind the DMA channel to each peripheral:
  • 0h = UART0 peripheral
  • 1h = UART1 peripheral
  • 2h = SPI0 peripheral
  • 3h = SPI1 peripheral
  • 4h = I2C0 peripheral
  • 5h = I2C1 peripheral
  • 6h = SDMMC peripheral
  • 7h = SDIO peripheral
  • 8h = DCAN peripheral
  • 9h = ADC peripheral
  • Ah = PDM peripheral
  • Bh = HIF peripheral
  • Ch = UART2 peripheral

11.4.2 CHCTL1 Register (Offset = 4h) [Reset = 00000000h]

CHCTL1 is shown in Table 11-4.

Return to the Summary Table.

Host DMA Channel Controlled by Defined Peripheral. The value of each fields concats with [HOST_DMA:JOBCTLCHx.SRCDSTCFG] (when x is channel num) if [CHCTL1.CHx] = 4 and [JOBCTLCHx.SRCDSTCFG] = 1 (value = 0100_1 = 9) then flow control signals of channel x are connected to periph number 9 flow control signals Note: [CHCTL0.CHx] = 0xF is forbidden. This configuration should be only used for Dynamic Switch

Table 11-4 CHCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-20CH13R/W0hChannel 13 Control. The following Enums represent the configuration values to bind the DMA channel to each peripheral:
  • 0h = UART0 peripheral
  • 1h = UART1 peripheral
  • 2h = SPI0 peripheral
  • 3h = SPI1 peripheral
  • 4h = I2C0 peripheral
  • 5h = I2C1 peripheral
  • 6h = SDMMC peripheral
  • 7h = SDIO peripheral
  • 8h = DCAN peripheral
  • 9h = ADC peripheral
  • Ah = PDM peripheral
  • Bh = HIF peripheral
  • Ch = UART2 peripheral
19-16CH12R/W0hChannel 12 Control. The following Enums represent the configuration values to bind the DMA channel to each peripheral:
  • 0h = UART0 peripheral
  • 1h = UART1 peripheral
  • 2h = SPI0 peripheral
  • 3h = SPI1 peripheral
  • 4h = I2C0 peripheral
  • 5h = I2C1 peripheral
  • 6h = SDMMC peripheral
  • 7h = SDIO peripheral
  • 8h = DCAN peripheral
  • 9h = ADC peripheral
  • Ah = PDM peripheral
  • Bh = HIF peripheral
  • Ch = UART2 peripheral
15-12CH11R/W0hChannel 11 Control. The following Enums represent the configuration values to bind the DMA channel to each peripheral:
  • 0h = UART0 peripheral
  • 1h = UART1 peripheral
  • 2h = SPI0 peripheral
  • 3h = SPI1 peripheral
  • 4h = I2C0 peripheral
  • 5h = I2C1 peripheral
  • 6h = SDMMC peripheral
  • 7h = SDIO peripheral
  • 8h = DCAN peripheral
  • 9h = ADC peripheral
  • Ah = PDM peripheral
  • Bh = HIF peripheral
  • Ch = UART2 peripheral
11-8CH10R/W0hChannel 10 Control. The following Enums represent the configuration values to bind the DMA channel to each peripheral:
  • 0h = UART0 peripheral
  • 1h = UART1 peripheral
  • 2h = SPI0 peripheral
  • 3h = SPI1 peripheral
  • 4h = I2C0 peripheral
  • 5h = I2C1 peripheral
  • 6h = SDMMC peripheral
  • 7h = SDIO peripheral
  • 8h = DCAN peripheral
  • 9h = ADC peripheral
  • Ah = PDM peripheral
  • Bh = HIF peripheral
  • Ch = UART2 peripheral
7-4CH9R/W0hChannel 9 Control. The following Enums represent the configuration values to bind the DMA channel to each peripheral:
  • 0h = UART0 peripheral
  • 1h = UART1 peripheral
  • 2h = SPI0 peripheral
  • 3h = SPI1 peripheral
  • 4h = I2C0 peripheral
  • 5h = I2C1 peripheral
  • 6h = SDMMC peripheral
  • 7h = SDIO peripheral
  • 8h = DCAN peripheral
  • 9h = ADC peripheral
  • Ah = PDM peripheral
  • Bh = HIF peripheral
  • Ch = UART2 peripheral
3-0CH8R/W0hChannel 8 Control. The following Enums represent the configuration values to bind the DMA channel to each peripheral:
  • 0h = UART0 peripheral
  • 1h = UART1 peripheral
  • 2h = SPI0 peripheral
  • 3h = SPI1 peripheral
  • 4h = I2C0 peripheral
  • 5h = I2C1 peripheral
  • 6h = SDMMC peripheral
  • 7h = SDIO peripheral
  • 8h = DCAN peripheral
  • 9h = ADC peripheral
  • Ah = PDM peripheral
  • Bh = HIF peripheral
  • Ch = UART2 peripheral

11.4.3 PRIOCFG Register (Offset = 18h) [Reset = 1F0F0F00h]

PRIOCFG is shown in Table 11-5.

Return to the Summary Table.

Priority Channel Configuration.

Table 11-5 PRIOCFG Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-24MAXBLOCKSR/W1FhMaximum consecutive priority blocks. Maximum consecutive block transactions of 'priority channels' . After this number of consecutive blocks one of 'roubd robin' channels will win arbitration. 31 means there is no limitation on number of consecutive priority blocks
23-20RESERVEDR0hReserved
19-16CH2NDR/WFhSecond priority channel. channel with second highest prioriry
15-12RESERVEDR0hReserved
11-8CH1STR/WFhFirst priority channel. channel with highest prioriry
7-1RESERVEDR0hReserved
0PRIOENR/W0hEnable priority channel. Enable one channel to be prioritize - no round rubin would be done

11.4.4 CH0STA Register (Offset = 1000h) [Reset = 00000000h]

CH0STA is shown in Table 11-6.

Return to the Summary Table.

Channel Status FSM state and run indication.

Table 11-6 CH0STA Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16RUNR0hIndication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.
15-12RESERVEDR0hReserved
11-8FSMSTATER0hFSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST
7-3RESERVEDR0hReserved
2-0HWEVENTR0hHW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION

11.4.5 CH0TIPTR Register (Offset = 1004h) [Reset = 00000000h]

CH0TIPTR is shown in Table 11-7.

Return to the Summary Table.

Input Pointer Channel Transaction. 32 bit address pointer of channel current input.

Table 11-7 CH0TIPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0IPTRR/W0hTransaction input pointer. 32 bit address pointer of channel current input.

11.4.6 CH0OPTR Register (Offset = 1008h) [Reset = 00000000h]

CH0OPTR is shown in Table 11-8.

Return to the Summary Table.

Output Pointer Channel Transaction. 32 bit address pointer of channel current output.

Table 11-8 CH0OPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0OPTRR/W0hTransaction output pointer. 32 bit address pointer of channel current output.

11.4.7 CH0TCTL Register (Offset = 100Ch) [Reset = 00000000h]

CH0TCTL is shown in Table 11-9.

Return to the Summary Table.

Transaction control

Table 11-9 CH0TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-24ENDIANESSR/W0h0 -no endianess, 1 - byte endianess, 2 - bit endianess
23-18RESERVEDR0hReserved
17SPARER/W0hspare
16BURSTREQR/W0hUse burst request. In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.
15-14RESERVEDR0hReserved
13-0TRANSBR/W0hTransaction bytes number. Number of bytes of the transaction to move from source to destination.

11.4.8 CH0TCTL2 Register (Offset = 1010h) [Reset = 00000000h]

CH0TCTL2 is shown in Table 11-10.

Return to the Summary Table.

DMA command interface

Table 11-10 CH0TCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CMDW0h1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error. Type:Write-Clear.

11.4.9 CH0TSTA Register (Offset = 1014h) [Reset = 00000000h]

CH0TSTA is shown in Table 11-11.

Return to the Summary Table.

Transaction Status. Job completion reason - either last transaction or exception

Table 11-11 CH0TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-16REMAINBR0hRemain bytes number. Number of bytes remaining to complete the transaction.
15-8OFFSETR0hWord offset. Offset in words from block boundary. Actually number of word have been transferred in this block
7-1RESERVEDR0hReserved
0STAR0hchannel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.

11.4.10 CH0JCTL Register (Offset = 101Ch) [Reset = 00000000h]

CH0JCTL is shown in Table 11-12.

Return to the Summary Table.

Job control register

Table 11-12 CH0JCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ENCLRR/W0hEnable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)
29SRCDSTCFGR/W0h0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph
28FIFOMODDR/W0hDestination pointer fifo mode
27FIFOMODSR/W0hSource pointer fifo mode
26DMASIGBPSR/W0hTie high channel DMA req signal. This is useful for memory to memort transaction
25BLKMODEDSTR/W0hDestination pointer wrap around mode 0: no wrap around(non block mode) 1: with wrap around(block mode)
24BLKMODESRCR/W0hsource pointer wrap around mode 0: no wrap around(non block mode) 1: with wrap around(block mode)
23-22RESERVEDR0hReserved
21-16BLKSIZER/W0hsize of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.
15-2RESERVEDR0hReserved
1-0WORDSIZER/W0h00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits

11.4.11 CH1STA Register (Offset = 2000h) [Reset = 00000000h]

CH1STA is shown in Table 11-13.

Return to the Summary Table.

Channel Status FSM state and run indication.

Table 11-13 CH1STA Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16RUNR0hIndication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.
15-12RESERVEDR0hReserved
11-8FSMSTATER0hFSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST
7-3RESERVEDR0hReserved
2-0HWEVENTR0hHW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION

11.4.12 CH1TIPTR Register (Offset = 2004h) [Reset = 00000000h]

CH1TIPTR is shown in Table 11-14.

Return to the Summary Table.

32 bit address pointer of channel current input.

Table 11-14 CH1TIPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0IPTRR/W0h32 bit address pointer of channel current input.

11.4.13 CH1TOPTR Register (Offset = 2008h) [Reset = 00000000h]

CH1TOPTR is shown in Table 11-15.

Return to the Summary Table.

32 bit address pointer of channel current output.

Table 11-15 CH1TOPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0OPTRR/W0h32 bit address pointer of channel current output.

11.4.14 CH1TCTL Register (Offset = 200Ch) [Reset = 00000000h]

CH1TCTL is shown in Table 11-16.

Return to the Summary Table.

Transaction control

Table 11-16 CH1TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-24ENDIANESSR/W0h0 -no endianess, 1 - byte endianess, 2 - bit endianess
23-18RESERVEDR0hReserved
17SPARER/W0hspare
16BURSTREQR/W0hIn case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.
15-14RESERVEDR0hReserved
13-0TRANSBR/W0hNumber of bytes of the transaction to move from source to destination.

11.4.15 CH1TCTRL2 Register (Offset = 2010h) [Reset = 00000000h]

CH1TCTRL2 is shown in Table 11-17.

Return to the Summary Table.

DMA command interface

Table 11-17 CH1TCTRL2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CMDW0h1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.

11.4.16 CH1TSTA Register (Offset = 2014h) [Reset = 00000000h]

CH1TSTA is shown in Table 11-18.

Return to the Summary Table.

Job completion reason - either last transaction or exception

Table 11-18 CH1TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-16REMAINBR0hNumber of bytes remaining to complete the transaction.
15-8OFFSETR0hOffset in words from block boundary. Actually number of word have been transferred in this block
7-1RESERVEDR0hReserved
0STAR0hchannel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.

11.4.17 CH1JCTL Register (Offset = 201Ch) [Reset = 00000000h]

CH1JCTL is shown in Table 11-19.

Return to the Summary Table.

Job control register

Table 11-19 CH1JCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ENCLRR/W0hEnable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)
29SRCDSTCFGR/W0h0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph
28FIFOMODDR/W0hDestination pointer fifo mode
27FIFOMODSR/W0hSource pointer fifo mode
26DMASIGBPSR/W0hTie high channel DMA req signal. This is useful for memory to memort transaction
25BLKMODEDSTR/W0hDestination pointer wrap around mode 0: no wrap around(non block mode) 1: with wrap around(block mode)
24BLKMODESRCR/W0hsource pointer wrap around mode 0: no wrap around(non block mode) 1: with wrap around(block mode)
23-22RESERVEDR0hReserved
21-16BLKSIZER/W0hsize of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.
15-2RESERVEDR0hReserved
1-0WORDSIZER/W0h00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits

11.4.18 CH2STA Register (Offset = 3000h) [Reset = 00000000h]

CH2STA is shown in Table 11-20.

Return to the Summary Table.

Channel Status FSM state and run indication.

Table 11-20 CH2STA Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16RUNR0hIndication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.
15-12RESERVEDR0hReserved
11-8FSMSTATER0hFSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST
7-3RESERVEDR0hReserved
2-0HWEVENTR0hHW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION

11.4.19 CH2TIPTR Register (Offset = 3004h) [Reset = 00000000h]

CH2TIPTR is shown in Table 11-21.

Return to the Summary Table.

32 bit address pointer of channel current input.

Table 11-21 CH2TIPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0IPTRR/W0h32 bit address pointer of channel current input.

11.4.20 CH2TOPTR Register (Offset = 3008h) [Reset = 00000000h]

CH2TOPTR is shown in Table 11-22.

Return to the Summary Table.

32 bit address pointer of channel current output.

Table 11-22 CH2TOPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0OPTRR/W0h32 bit address pointer of channel current output.

11.4.21 CH2TCTL Register (Offset = 300Ch) [Reset = 00000000h]

CH2TCTL is shown in Table 11-23.

Return to the Summary Table.

Transaction control

Table 11-23 CH2TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-24ENDIANESSR/W0h0 -no endianess, 1 - byte endianess, 2 - bit endianess
23-18RESERVEDR0hReserved
17SPARER/W0hspare
16BURSTREQR/W0hIn case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.
15-14RESERVEDR0hReserved
13-0TRANSBR/W0hNumber of bytes of the transaction to move from source to destination.

11.4.22 CH2TCTL2 Register (Offset = 3010h) [Reset = 00000000h]

CH2TCTL2 is shown in Table 11-24.

Return to the Summary Table.

DMA command interface

Table 11-24 CH2TCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CMDW0h1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.

11.4.23 CH2TSTA Register (Offset = 3014h) [Reset = 00000000h]

CH2TSTA is shown in Table 11-25.

Return to the Summary Table.

Job completion reason - either last transaction or exception

Table 11-25 CH2TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-16REMAINBR0hNumber of bytes remaining to complete the transaction.
15-8OFFSETR0hOffset in words from block boundary. Actually number of word have been transferred in this block
7-1RESERVEDR0hReserved
0STAR0hchannel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.

11.4.24 CH2JCTL Register (Offset = 301Ch) [Reset = 00000000h]

CH2JCTL is shown in Table 11-26.

Return to the Summary Table.

Job control register

Table 11-26 CH2JCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ENCLRR/W0hEnable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)
29SRCDSTCFGR/W0h0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph
28FIFOMODDR/W0hDestination pointer fifo mode
27FIFOMODSR/W0hSource pointer fifo mode
26DMASIGBPSR/W0hTie high channel DMA req signal. This is useful for memory to memort transaction
25-22RESERVEDR0hReserved
21-16BLKSIZER/W0hsize of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.
15-2RESERVEDR0hReserved
1-0WORDSIZER/W0h00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits

11.4.25 CH3STA Register (Offset = 4000h) [Reset = 00000000h]

CH3STA is shown in Table 11-27.

Return to the Summary Table.

Channel Status FSM state and run indication.

Table 11-27 CH3STA Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16RUNR0hIndication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.
15-12RESERVEDR0hReserved
11-8FSMSTATER0hFSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST
7-3RESERVEDR0hReserved
2-0HWEVENTR0hHW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION

11.4.26 CH3TIPTR Register (Offset = 4004h) [Reset = 00000000h]

CH3TIPTR is shown in Table 11-28.

Return to the Summary Table.

32 bit address pointer of channel current input.

Table 11-28 CH3TIPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0IPTRR/W0h32 bit address pointer of channel current input.

11.4.27 CH3TOPTR Register (Offset = 4008h) [Reset = 00000000h]

CH3TOPTR is shown in Table 11-29.

Return to the Summary Table.

32 bit address pointer of channel current output.

Table 11-29 CH3TOPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0OPTRR/W0h32 bit address pointer of channel current output.

11.4.28 CH3TCTL Register (Offset = 400Ch) [Reset = 00000000h]

CH3TCTL is shown in Table 11-30.

Return to the Summary Table.

Transaction control

Table 11-30 CH3TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-24ENDIANESSR/W0h0 -no endianess, 1 - byte endianess, 2 - bit endianess
23-18RESERVEDR0hReserved
17SPARER/W0hspare
16BURSTREQR/W0hIn case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.
15-14RESERVEDR0hReserved
13-0TRANSBR/W0hNumber of bytes of the transaction to move from source to destination.

11.4.29 CH3TCTL2 Register (Offset = 4010h) [Reset = 00000000h]

CH3TCTL2 is shown in Table 11-31.

Return to the Summary Table.

DMA command interface

Table 11-31 CH3TCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CMDW0h1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.

11.4.30 CH3TSTA Register (Offset = 4014h) [Reset = 00000000h]

CH3TSTA is shown in Table 11-32.

Return to the Summary Table.

Job completion reason - either last transaction or exception

Table 11-32 CH3TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-16REMAINBR0hNumber of bytes remaining to complete the transaction.
15-8OFFSETR0hOffset in words from block boundary. Actually number of word have been transferred in this block
7-1RESERVEDR0hReserved
0STAR0hchannel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.

11.4.31 CH3JCTL Register (Offset = 401Ch) [Reset = 00000000h]

CH3JCTL is shown in Table 11-33.

Return to the Summary Table.

Job control register

Table 11-33 CH3JCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ENCLRR/W0hEnable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)
29SRCDSTCFGR/W0h0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph
28FIFOMODDR/W0hDestination pointer fifo mode
27FIFOMODSR/W0hSource pointer fifo mode
26DMASIGBPSR/W0hTie high channel DMA req signal. This is useful for memory to memort transaction
25-22RESERVEDR0hReserved
21-16BLKSIZER/W0hsize of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.
15-2RESERVEDR0hReserved
1-0WORDSIZER/W0h00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits

11.4.32 CH4STA Register (Offset = 5000h) [Reset = 00000000h]

CH4STA is shown in Table 11-34.

Return to the Summary Table.

Channel Status FSM state and run indication.

Table 11-34 CH4STA Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16RUNR0hIndication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.
15-12RESERVEDR0hReserved
11-8FSMSTATER0hFSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST
7-3RESERVEDR0hReserved
2-0HWEVENTR0hHW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION

11.4.33 CH4TIPTR Register (Offset = 5004h) [Reset = 00000000h]

CH4TIPTR is shown in Table 11-35.

Return to the Summary Table.

32 bit address pointer of channel current input.

Table 11-35 CH4TIPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0INPTRR/W0h32 bit address pointer of channel current input.

11.4.34 CH4TOPTR Register (Offset = 5008h) [Reset = 00000000h]

CH4TOPTR is shown in Table 11-36.

Return to the Summary Table.

32 bit address pointer of channel current output.

Table 11-36 CH4TOPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0OPTRR/W0h32 bit address pointer of channel current output.

11.4.35 CH4TCTL Register (Offset = 500Ch) [Reset = 00000000h]

CH4TCTL is shown in Table 11-37.

Return to the Summary Table.

Transaction control

Table 11-37 CH4TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-24ENDIANESSR/W0h0 -no endianess, 1 - byte endianess, 2 - bit endianess
23-18RESERVEDR0hReserved
17SPARER/W0hspare
16BURSTREQR/W0hIn case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.
15-14RESERVEDR0hReserved
13-0TRANSBR/W0hNumber of bytes of the transaction to move from source to destination.

11.4.36 CH4TCTL2 Register (Offset = 5010h) [Reset = 00000000h]

CH4TCTL2 is shown in Table 11-38.

Return to the Summary Table.

DMA command interface

Table 11-38 CH4TCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CMDW0h1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.

11.4.37 CH4TSTA Register (Offset = 5014h) [Reset = 00000000h]

CH4TSTA is shown in Table 11-39.

Return to the Summary Table.

Job completion reason - either last transaction or exception

Table 11-39 CH4TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-16REMAINBR0hNumber of bytes remaining to complete the transaction.
15-8OFFSETR0hOffset in words from block boundary. Actually number of word have been transferred in this block
7-1RESERVEDR0hReserved
0STAR0hchannel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.

11.4.38 CH4JCTL Register (Offset = 501Ch) [Reset = 00000000h]

CH4JCTL is shown in Table 11-40.

Return to the Summary Table.

Job control register

Table 11-40 CH4JCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ENCLRR/W0hEnable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)
29SRCDSTCFGR/W0h0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph
28FIFOMODDR/W0hDestination pointer fifo mode
27FIFOMODSR/W0hSource pointer fifo mode
26DMASIGBPSR/W0hTie high channel DMA req signal. This is useful for memory to memort transaction
25-22RESERVEDR0hReserved
21-16BLKSIZER/W0hsize of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.
15-2RESERVEDR0hReserved
1-0WORDSIZER/W0h00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits

11.4.39 CH5STA Register (Offset = 6000h) [Reset = 00000000h]

CH5STA is shown in Table 11-41.

Return to the Summary Table.

Channel Status FSM state and run indication.

Table 11-41 CH5STA Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16RUNR0hIndication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.
15-12RESERVEDR0hReserved
11-8FSMSTATER0hFSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST
7-3RESERVEDR0hReserved
2-0HWEVENTR0hHW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION

11.4.40 CH5TIPTR Register (Offset = 6004h) [Reset = 00000000h]

CH5TIPTR is shown in Table 11-42.

Return to the Summary Table.

32 bit address pointer of channel current input.

Table 11-42 CH5TIPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0IPTRR/W0h32 bit address pointer of channel current input.

11.4.41 CH5TOPTR Register (Offset = 6008h) [Reset = 00000000h]

CH5TOPTR is shown in Table 11-43.

Return to the Summary Table.

32 bit address pointer of channel current output.

Table 11-43 CH5TOPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0OPTRR/W0h32 bit address pointer of channel current output.

11.4.42 CH5TCTL Register (Offset = 600Ch) [Reset = 00000000h]

CH5TCTL is shown in Table 11-44.

Return to the Summary Table.

Transaction control

Table 11-44 CH5TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-24ENDIANESSR/W0h0 -no endianess, 1 - byte endianess, 2 - bit endianess
23-18RESERVEDR0hReserved
17SPARER/W0hspare
16BURSTREQR/W0hIn case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.
15-14RESERVEDR0hReserved
13-0TRANSBR/W0hNumber of bytes of the transaction to move from source to destination.

11.4.43 CH5TCTL2 Register (Offset = 6010h) [Reset = 00000000h]

CH5TCTL2 is shown in Table 11-45.

Return to the Summary Table.

DMA command interface

Table 11-45 CH5TCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CMDW0h1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.

11.4.44 CH5TSTA Register (Offset = 6014h) [Reset = 00000000h]

CH5TSTA is shown in Table 11-46.

Return to the Summary Table.

Job completion reason - either last transaction or exception

Table 11-46 CH5TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-16REMAINBR0hNumber of bytes remaining to complete the transaction.
15-8OFFSETR0hOffset in words from block boundary. Actually number of word have been transferred in this block
7-1RESERVEDR0hReserved
0STAR0hchannel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.

11.4.45 CH5JCTL Register (Offset = 601Ch) [Reset = 00000000h]

CH5JCTL is shown in Table 11-47.

Return to the Summary Table.

Job control register

Table 11-47 CH5JCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ENCLRR/W0hEnable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)
29SRCDSTCFGR/W0h0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph
28FIFOMODDR/W0hDestination pointer fifo mode
27FIFOMODSR/W0hSource pointer fifo mode
26DMASIGBPSR/W0hTie high channel DMA req signal. This is useful for memory to memort transaction
25-22RESERVEDR0hReserved
21-16BLKSIZER/W0hsize of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.
15-2RESERVEDR0hReserved
1-0WORDSIZER/W0h00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits

11.4.46 CH6STA Register (Offset = 7000h) [Reset = 00000000h]

CH6STA is shown in Table 11-48.

Return to the Summary Table.

Channel Status FSM state and run indication.

Table 11-48 CH6STA Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16RUNR0hIndication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.
15-12RESERVEDR0hReserved
11-8FSMSTATER0hFSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST
7-3RESERVEDR0hReserved
2-0HWEVENTR0hHW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION

11.4.47 CH6TIPTR Register (Offset = 7004h) [Reset = 00000000h]

CH6TIPTR is shown in Table 11-49.

Return to the Summary Table.

32 bit address pointer of channel current input.

Table 11-49 CH6TIPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0IPTRR/W0h32 bit address pointer of channel current input.

11.4.48 CH6TOPTR Register (Offset = 7008h) [Reset = 00000000h]

CH6TOPTR is shown in Table 11-50.

Return to the Summary Table.

32 bit address pointer of channel current output.

Table 11-50 CH6TOPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0OPTRR/W0h32 bit address pointer of channel current output.

11.4.49 CH6TCTL Register (Offset = 700Ch) [Reset = 00000000h]

CH6TCTL is shown in Table 11-51.

Return to the Summary Table.

Transaction control

Table 11-51 CH6TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-24ENDIANESSR/W0h0 -no endianess, 1 - byte endianess, 2 - bit endianess
23-18RESERVEDR0hReserved
17SPARER/W0hspare
16BURSTREQR/W0hIn case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.
15-14RESERVEDR0hReserved
13-0TRANSBR/W0hNumber of bytes of the transaction to move from source to destination.

11.4.50 CH6TCTL2 Register (Offset = 7010h) [Reset = 00000000h]

CH6TCTL2 is shown in Table 11-52.

Return to the Summary Table.

DMA command interface

Table 11-52 CH6TCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CMDW0h1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.

11.4.51 CH6TSTA Register (Offset = 7014h) [Reset = 00000000h]

CH6TSTA is shown in Table 11-53.

Return to the Summary Table.

Job completion reason - either last transaction or exception

Table 11-53 CH6TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-16REMAINBR0hNumber of bytes remaining to complete the transaction.
15-8WORDOFFSETR0hOffset in words from block boundary. Actually number of word have been transferred in this block
7-1RESERVEDR0hReserved
0STAR0hchannel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.

11.4.52 CH6JCTL Register (Offset = 701Ch) [Reset = 00000000h]

CH6JCTL is shown in Table 11-54.

Return to the Summary Table.

Job control register

Table 11-54 CH6JCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ENCLRR/W0hEnable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)
29SRCDSTCFGR/W0h0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph
28FIFOMODDR/W0hDestination pointer fifo mode
27FIFOMODSR/W0hSource pointer fifo mode
26DMASIGBPSR/W0hTie high channel DMA req signal. This is useful for memory to memort transaction
25-22RESERVEDR0hReserved
21-16BLKSIZER/W0hsize of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.
15-2RESERVEDR0hReserved
1-0WORDSIZER/W0h00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits

11.4.53 CH7STA Register (Offset = 8000h) [Reset = 00000000h]

CH7STA is shown in Table 11-55.

Return to the Summary Table.

Channel Status FSM state and run indication.

Table 11-55 CH7STA Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16RUNR0hIndication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.
15-12RESERVEDR0hReserved
11-8FSMSTATER0hFSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST
7-3RESERVEDR0hReserved
2-0HWEVENTR0hHW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION

11.4.54 CH7TIPTR Register (Offset = 8004h) [Reset = 00000000h]

CH7TIPTR is shown in Table 11-56.

Return to the Summary Table.

32 bit address pointer of channel current input.

Table 11-56 CH7TIPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0IPTRR/W0h32 bit address pointer of channel current input.

11.4.55 CH7TOPTR Register (Offset = 8008h) [Reset = 00000000h]

CH7TOPTR is shown in Table 11-57.

Return to the Summary Table.

32 bit address pointer of channel current output.

Table 11-57 CH7TOPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0OPTRR/W0h32 bit address pointer of channel current output.

11.4.56 CH7TCTL Register (Offset = 800Ch) [Reset = 00000000h]

CH7TCTL is shown in Table 11-58.

Return to the Summary Table.

Transaction control

Table 11-58 CH7TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-24ENDIANESSR/W0h0 -no endianess, 1 - byte endianess, 2 - bit endianess
23-18RESERVEDR0hReserved
17SPARER/W0hspare
16BURSTREQR/W0hIn case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.
15-14RESERVEDR0hReserved
13-0TRANSBR/W0hNumber of bytes of the transaction to move from source to destination.

11.4.57 CH7TCTL2 Register (Offset = 8010h) [Reset = 00000000h]

CH7TCTL2 is shown in Table 11-59.

Return to the Summary Table.

DMA command interface

Table 11-59 CH7TCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CMDW0h1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.

11.4.58 CH7TSTA Register (Offset = 8014h) [Reset = 00000000h]

CH7TSTA is shown in Table 11-60.

Return to the Summary Table.

Job completion reason - either last transaction or exception

Table 11-60 CH7TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-16REMAINBR0hNumber of bytes remaining to complete the transaction.
15-8OFFSETR0hOffset in words from block boundary. Actually number of word have been transferred in this block
7-1RESERVEDR0hReserved
0STAR0hchannel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.

11.4.59 CH7JCTL Register (Offset = 801Ch) [Reset = 00000000h]

CH7JCTL is shown in Table 11-61.

Return to the Summary Table.

Job control register

Table 11-61 CH7JCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ENCLRR/W0hEnable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)
29SRCDSTCFGR/W0h0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph
28FIFOMODDR/W0hDestination pointer fifo mode
27FIFOMODSR/W0hSource pointer fifo mode
26DMASIGBPSR/W0hTie high channel DMA req signal. This is useful for memory to memort transaction
25-22RESERVEDR0hReserved
21-16BLKSIZER/W0hsize of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.
15-2RESERVEDR0hReserved
1-0WORDSIZER/W0h00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits

11.4.60 CH8STA Register (Offset = 9000h) [Reset = 00000000h]

CH8STA is shown in Table 11-62.

Return to the Summary Table.

Channel Status FSM state and run indication.

Table 11-62 CH8STA Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16RUNR0hIndication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.
15-12RESERVEDR0hReserved
11-8FSMSTATER0hFSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST
7-3RESERVEDR0hReserved
2-0HWEVENTR0hHW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION

11.4.61 CH8TIPTR Register (Offset = 9004h) [Reset = 00000000h]

CH8TIPTR is shown in Table 11-63.

Return to the Summary Table.

32 bit address pointer of channel current input.

Table 11-63 CH8TIPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0IPTRR/W0h32 bit address pointer of channel current input.

11.4.62 CH8TOPTR Register (Offset = 9008h) [Reset = 00000000h]

CH8TOPTR is shown in Table 11-64.

Return to the Summary Table.

32 bit address pointer of channel current output.

Table 11-64 CH8TOPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0OPTRR/W0h32 bit address pointer of channel current output.

11.4.63 CH8TCTL Register (Offset = 900Ch) [Reset = 00000000h]

CH8TCTL is shown in Table 11-65.

Return to the Summary Table.

Transaction control

Table 11-65 CH8TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-24ENDIANESSR/W0h0 -no endianess, 1 - byte endianess, 2 - bit endianess
23-18RESERVEDR0hReserved
17SPARER/W0hspare
16BURSTREQR/W0hIn case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.
15-14RESERVEDR0hReserved
13-0TRANSBR/W0hNumber of bytes of the transaction to move from source to destination.

11.4.64 CH8TCTL2 Register (Offset = 9010h) [Reset = 00000000h]

CH8TCTL2 is shown in Table 11-66.

Return to the Summary Table.

DMA command interface

Table 11-66 CH8TCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CMDW0h1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.

11.4.65 CH8TSTA Register (Offset = 9014h) [Reset = 00000000h]

CH8TSTA is shown in Table 11-67.

Return to the Summary Table.

Job completion reason - either last transaction or exception

Table 11-67 CH8TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-16REMAINBR0hNumber of bytes remaining to complete the transaction.
15-8OFFSETR0hOffset in words from block boundary. Actually number of word have been transferred in this block
7-1RESERVEDR0hReserved
0STAR0hchannel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.

11.4.66 CH8JCTL Register (Offset = 901Ch) [Reset = 00000000h]

CH8JCTL is shown in Table 11-68.

Return to the Summary Table.

Job control register

Table 11-68 CH8JCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ENCLRR/W0hEnable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)
29SRCDSTCFGR/W0h0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph
28FIFOMODDR/W0hDestination pointer fifo mode
27FIFOMODSR/W0hSource pointer fifo mode
26DMASIGBPSR/W0hTie high channel DMA req signal. This is useful for memory to memort transaction
25-22RESERVEDR0hReserved
21-16BLKSIZER/W0hsize of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.
15-2RESERVEDR0hReserved
1-0WORDSIZER/W0h00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits

11.4.67 CH9STA Register (Offset = A000h) [Reset = 00000000h]

CH9STA is shown in Table 11-69.

Return to the Summary Table.

Channel Status FSM state and run indication.

Table 11-69 CH9STA Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16RUNR0hIndication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.
15-12RESERVEDR0hReserved
11-8FSMSTATER0hFSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST
7-3RESERVEDR0hReserved
2-0HWEVENTR0hHW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION

11.4.68 CH9TIPTR Register (Offset = A004h) [Reset = 00000000h]

CH9TIPTR is shown in Table 11-70.

Return to the Summary Table.

32 bit address pointer of channel current input.

Table 11-70 CH9TIPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0IPTRR/W0h32 bit address pointer of channel current input.

11.4.69 CH9TOPTR Register (Offset = A008h) [Reset = 00000000h]

CH9TOPTR is shown in Table 11-71.

Return to the Summary Table.

32 bit address pointer of channel current output.

Table 11-71 CH9TOPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0OPTRR/W0h32 bit address pointer of channel current output.

11.4.70 CH9TCTL Register (Offset = A00Ch) [Reset = 00000000h]

CH9TCTL is shown in Table 11-72.

Return to the Summary Table.

Transaction control

Table 11-72 CH9TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-24ENDIANESSR/W0h0 -no endianess, 1 - byte endianess, 2 - bit endianess
23-18RESERVEDR0hReserved
17SPARER/W0hspare
16BURSTREQR/W0hIn case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.
15-14RESERVEDR0hReserved
13-0TRANSBR/W0hNumber of bytes of the transaction to move from source to destination.

11.4.71 CH9TCTL2 Register (Offset = A010h) [Reset = 00000000h]

CH9TCTL2 is shown in Table 11-73.

Return to the Summary Table.

DMA command interface

Table 11-73 CH9TCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CMDW0h1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.

11.4.72 CH9TSTA Register (Offset = A014h) [Reset = 00000000h]

CH9TSTA is shown in Table 11-74.

Return to the Summary Table.

Job completion reason - either last transaction or exception

Table 11-74 CH9TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-16REMAINBR0hNumber of bytes remaining to complete the transaction.
15-8OFFSETR0hOffset in words from block boundary. Actually number of word have been transferred in this block
7-1RESERVEDR0hReserved
0STAR0hchannel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.

11.4.73 CH9JCTL Register (Offset = A01Ch) [Reset = 00000000h]

CH9JCTL is shown in Table 11-75.

Return to the Summary Table.

Job control register

Table 11-75 CH9JCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ENCLRR/W0hEnable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)
29SRCDSTCFGR/W0h0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph
28FIFOMODDR/W0hDestination pointer fifo mode
27FIFOMODSR/W0hSource pointer fifo mode
26DMASIGBPSR/W0hTie high channel DMA req signal. This is useful for memory to memort transaction
25-22RESERVEDR0hReserved
21-16BLKSIZER/W0hsize of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.
15-2RESERVEDR0hReserved
1-0WORDSIZER/W0h00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits

11.4.74 CH10STA Register (Offset = B000h) [Reset = 00000000h]

CH10STA is shown in Table 11-76.

Return to the Summary Table.

Channel Status FSM state and run indication.

Table 11-76 CH10STA Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16RUNR0hIndication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.
15-12RESERVEDR0hReserved
11-8FSMSTATER0hFSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST
7-3RESERVEDR0hReserved
2-0HWEVENTR0hHW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION

11.4.75 CH10TIPTR Register (Offset = B004h) [Reset = 00000000h]

CH10TIPTR is shown in Table 11-77.

Return to the Summary Table.

32 bit address pointer of channel current input.

Table 11-77 CH10TIPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0IPTRR/W0h32 bit address pointer of channel current input.

11.4.76 CH10TOPTR Register (Offset = B008h) [Reset = 00000000h]

CH10TOPTR is shown in Table 11-78.

Return to the Summary Table.

32 bit address pointer of channel current output.

Table 11-78 CH10TOPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0OPTRR/W0h32 bit address pointer of channel current output.

11.4.77 CH10TCTL Register (Offset = B00Ch) [Reset = 00000000h]

CH10TCTL is shown in Table 11-79.

Return to the Summary Table.

Transaction control

Table 11-79 CH10TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-24ENDIANESSR/W0h0 -no endianess, 1 - byte endianess, 2 - bit endianess
23-18RESERVEDR0hReserved
17SPARER/W0hspare
16BURSTREQR/W0hIn case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.
15-14RESERVEDR0hReserved
13-0TRANSBR/W0hNumber of bytes of the transaction to move from source to destination.

11.4.78 CH10TCTL2 Register (Offset = B010h) [Reset = 00000000h]

CH10TCTL2 is shown in Table 11-80.

Return to the Summary Table.

DMA command interface

Table 11-80 CH10TCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CMDW0h1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.

11.4.79 CH10TSTA Register (Offset = B014h) [Reset = 00000000h]

CH10TSTA is shown in Table 11-81.

Return to the Summary Table.

Job completion reason - either last transaction or exception

Table 11-81 CH10TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-16REMAINBR0hNumber of bytes remaining to complete the transaction.
15-8OFFSETR0hOffset in words from block boundary. Actually number of word have been transferred in this block
7-1RESERVEDR0hReserved
0STAR0hchannel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.

11.4.80 CH10JCTL Register (Offset = B01Ch) [Reset = 00000000h]

CH10JCTL is shown in Table 11-82.

Return to the Summary Table.

Job control register

Table 11-82 CH10JCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ENCLRR/W0hEnable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)
29SRCDSTCFGR/W0h0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph
28FIFOMODDR/W0hDestination pointer fifo mode
27FIFOMODSR/W0hSource pointer fifo mode
26DMASIGBPSR/W0hTie high channel DMA req signal. This is useful for memory to memort transaction
25-24RESERVEDR0hReserved
23-16BLKSIZER/W0hsize of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.
15-2RESERVEDR0hReserved
1-0WORDSIZER/W0h00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits

11.4.81 CH11STA Register (Offset = C000h) [Reset = 00000000h]

CH11STA is shown in Table 11-83.

Return to the Summary Table.

Channel Status FSM state and run indication.

Table 11-83 CH11STA Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16RUNR0hIndication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.
15-12RESERVEDR0hReserved
11-8FSMSTATER0hFSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST
7-3RESERVEDR0hReserved
2-0HWEVENTR0hHW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION

11.4.82 CH11TIPTR Register (Offset = C004h) [Reset = 00000000h]

CH11TIPTR is shown in Table 11-84.

Return to the Summary Table.

32 bit address pointer of channel current input.

Table 11-84 CH11TIPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0IPTRR/W0h32 bit address pointer of channel current input.

11.4.83 CH11TOPTR Register (Offset = C008h) [Reset = 00000000h]

CH11TOPTR is shown in Table 11-85.

Return to the Summary Table.

32 bit address pointer of channel current output.

Table 11-85 CH11TOPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0OPTRR/W0h32 bit address pointer of channel current output.

11.4.84 CH11TCTL Register (Offset = C00Ch) [Reset = 00000000h]

CH11TCTL is shown in Table 11-86.

Return to the Summary Table.

Transaction control

Table 11-86 CH11TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-24ENDIANESSR/W0h0 -no endianess, 1 - byte endianess, 2 - bit endianess
23-18RESERVEDR0hReserved
17SPARER/W0hspare
16BURSTREQR/W0hIn case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.
15-14RESERVEDR0hReserved
13-0TRANSBR/W0hNumber of bytes of the transaction to move from source to destination.

11.4.85 CH11TCTL2 Register (Offset = C010h) [Reset = 00000000h]

CH11TCTL2 is shown in Table 11-87.

Return to the Summary Table.

DMA command interface

Table 11-87 CH11TCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CMDW0h1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.

11.4.86 CH11TSTA Register (Offset = C014h) [Reset = 00000000h]

CH11TSTA is shown in Table 11-88.

Return to the Summary Table.

Job completion reason - either last transaction or exception

Table 11-88 CH11TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-16REMAINBR0hNumber of bytes remaining to complete the transaction.
15-8OFFSETR0hOffset in words from block boundary. Actually number of word have been transferred in this block
7-1RESERVEDR0hReserved
0STAR0hchannel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.

11.4.87 CH11JCTL Register (Offset = C01Ch) [Reset = 00000000h]

CH11JCTL is shown in Table 11-89.

Return to the Summary Table.

Job control register

Table 11-89 CH11JCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ENCLRR/W0hEnable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)
29SRCDSTCFGR/W0h0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph
28FIFOMODDR/W0hDestination pointer fifo mode
27FIFOMODSR/W0hSource pointer fifo mode
26DMASIGBPSR/W0hTie high channel DMA req signal. This is useful for memory to memort transaction
25-22RESERVEDR0hReserved
21-16BLKSIZER/W0hsize of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.
15-2RESERVEDR0hReserved
1-0WORDSIZER/W0h00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits

11.4.88 CH12STA Register (Offset = D000h) [Reset = 00000000h]

CH12STA is shown in Table 11-90.

Return to the Summary Table.

Channel Status FSM state and run indication.

Table 11-90 CH12STA Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16RUNR0hIndication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.
15-12RESERVEDR0hReserved
11-8FSMSTATER0hFSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST
7-3RESERVEDR0hReserved
2-0HWEVENTR0hHW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION

11.4.89 CH12TIPTR Register (Offset = D004h) [Reset = 00000000h]

CH12TIPTR is shown in Table 11-91.

Return to the Summary Table.

32 bit address pointer of channel current input.

Table 11-91 CH12TIPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0IPTRR/W0h32 bit address pointer of channel current input.

11.4.90 CH12TOPTR Register (Offset = D008h) [Reset = 00000000h]

CH12TOPTR is shown in Table 11-92.

Return to the Summary Table.

32 bit address pointer of channel current output.

Table 11-92 CH12TOPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0OPTRR/W0h32 bit address pointer of channel current output.

11.4.91 CH12TCTL Register (Offset = D00Ch) [Reset = 00000000h]

CH12TCTL is shown in Table 11-93.

Return to the Summary Table.

Transaction control

Table 11-93 CH12TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-24ENDIANESSR/W0h0 -no endianess, 1 - byte endianess, 2 - bit endianess
23-18RESERVEDR0hReserved
17SPARER/W0hspare
16BURSTREQR/W0hIn case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.
15-14RESERVEDR0hReserved
13-0TRANSBR/W0hNumber of bytes of the transaction to move from source to destination.

11.4.92 CH12TCTL2 Register (Offset = D010h) [Reset = 00000000h]

CH12TCTL2 is shown in Table 11-94.

Return to the Summary Table.

DMA command interface

Table 11-94 CH12TCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CMDW0h1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.

11.4.93 CH12TSTA Register (Offset = D014h) [Reset = 00000000h]

CH12TSTA is shown in Table 11-95.

Return to the Summary Table.

Job completion reason - either last transaction or exception

Table 11-95 CH12TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-16REMAINBR0hNumber of bytes remaining to complete the transaction.
15-8OFFSETR0hOffset in words from block boundary. Actually number of word have been transferred in this block
7-1RESERVEDR0hReserved
0STAR0hchannel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.

11.4.94 CH12JCTL Register (Offset = D01Ch) [Reset = 00000000h]

CH12JCTL is shown in Table 11-96.

Return to the Summary Table.

Job control register

Table 11-96 CH12JCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ENCLRR/W0hEnable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)
29SRCDSTCFGR/W0h0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph
28FIFOMODDR/W0hDestination pointer fifo mode
27FIFOMODSR/W0hSource pointer fifo mode
26DMASIGBPSR/W0hTie high channel DMA req signal. This is useful for memory to memort transaction
25-22RESERVEDR0hReserved
21-16BLKSIZER/W0hsize of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.
15-2RESERVEDR0hReserved
1-0WORDSIZER/W0h00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits

11.4.95 CH13STA Register (Offset = E000h) [Reset = 00000000h]

CH13STA is shown in Table 11-97.

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Channel Status FSM state and run indication.

Table 11-97 CH13STA Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16RUNR0hIndication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.
15-12RESERVEDR0hReserved
11-8FSMSTATER0hFSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST
7-3RESERVEDR0hReserved
2-0HWEVENTR0hHW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION

11.4.96 CH13TIPTR Register (Offset = E004h) [Reset = 00000000h]

CH13TIPTR is shown in Table 11-98.

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32 bit address pointer of channel current input.

Table 11-98 CH13TIPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0IPTRR/W0h32 bit address pointer of channel current input.

11.4.97 CH13TOPTR Register (Offset = E008h) [Reset = 00000000h]

CH13TOPTR is shown in Table 11-99.

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32 bit address pointer of channel current output.

Table 11-99 CH13TOPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0OPTRR/W0h32 bit address pointer of channel current output.

11.4.98 CH13TCTL Register (Offset = E00Ch) [Reset = 00000000h]

CH13TCTL is shown in Table 11-100.

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Transaction control

Table 11-100 CH13TCTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-24ENDIANESSR/W0h0 -no endianess, 1 - byte endianess, 2 - bit endianess
23-18RESERVEDR0hReserved
17SPARER/W0hspare
16BURSTREQR/W0hIn case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.
15-14RESERVEDR0hReserved
13-0TRANSBR/W0hNumber of bytes of the transaction to move from source to destination.

11.4.99 CH13TCTL2 Register (Offset = E010h) [Reset = 00000000h]

CH13TCTL2 is shown in Table 11-101.

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DMA command interface

Table 11-101 CH13TCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0CMDW0h1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.

11.4.100 CH13TSTA Register (Offset = E014h) [Reset = 00000000h]

CH13TSTA is shown in Table 11-102.

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Job completion reason - either last transaction or exception

Table 11-102 CH13TSTA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-16REMAINBR0hNumber of bytes remaining to complete the transaction.
15-8OFFSETR0hOffset in words from block boundary. Actually number of word have been transferred in this block
7-1RESERVEDR0hReserved
0STAR0hchannel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.

11.4.101 CH13JCTL Register (Offset = E01Ch) [Reset = 00000000h]

CH13JCTL is shown in Table 11-103.

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Job control register

Table 11-103 CH13JCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ENCLRR/W0hEnable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)
29SRCDSTCFGR/W0h0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph
28FIFOMODDR/W0hDestination pointer fifo mode
27FIFOMODSR/W0hSource pointer fifo mode
26DMASIGBPSR/W0hTie high channel DMA req signal. This is useful for memory to memort transaction
25-22RESERVEDR0hReserved
21-16BLKSIZER/W0hsize of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.
15-2RESERVEDR0hReserved
1-0WORDSIZER/W0h00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits