SWRU626 December   2025 CC3501E , CC3551E

 

  1.   1
  2. 1 Read This First
    1. 1.1 About This Manual
    2. 1.2 Register, Field, and Bit Calls
    3.     Trademarks
  3. 2 Architecture Overview
    1. 2.1  Target Applications
    2. 2.2  Introduction
    3. 2.3  Internal System Diagram
    4. 2.4  Arm Cortex M33
      1. 2.4.1 Processor Core
      2. 2.4.2 SysTick Timer
      3. 2.4.3 Nested Vectored Interrupt Controller
      4. 2.4.4 System Control Block (SCB)
      5. 2.4.5 TI AI instruction extensions
    5. 2.5  Power Management
      1. 2.5.1 VDD_MAIN
      2. 2.5.2 VDD_IO
      3. 2.5.3 VDDSF
      4. 2.5.4 VDD_PA
    6. 2.6  Debug Subsystem (DEBUGSS)
    7. 2.7  Memory Subsystem (MEMSS)
      1. 2.7.1 External Memory Interface
    8. 2.8  Hardware Security Module
    9. 2.9  General Purpose Timers (GPT)
    10. 2.10 Real Time Clock (RTC)
    11. 2.11 Direct Memory Access
    12. 2.12 GPIOs
    13. 2.13 Communication Peripherals
      1. 2.13.1 UART
      2. 2.13.2 I2C
      3. 2.13.3 SPI
      4. 2.13.4 I2S
      5. 2.13.5 SDMMC
      6. 2.13.6 SDIO
      7. 2.13.7 CAN
      8. 2.13.8 ADC
  4. 3  Arm Cortex-M33 Processor
    1. 3.1 Arm Cortex-M33 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 M33 instantiation parameters
    4. 3.4 Arm Cortex-M33 System Peripheral Details
      1. 3.4.1 Floating Point Unit (FPU)
      2. 3.4.2 Memory Protection Unit (MPU)
      3. 3.4.3 Digital Signal Processing (DSP)
      4. 3.4.4 Security Attribution Unit (SAU)
      5. 3.4.5 System Timer
      6. 3.4.6 Nested Vectored Interrupt Controller
      7. 3.4.7 System Control Block
      8. 3.4.8 System Control Space
    5. 3.5 CPU Sub-System Peripheral Details
      1. 3.5.1 Trace Port Interface Unit (TPIU)
      2. 3.5.2 DAP Bridge and Debug Authentication
      3. 3.5.3 Implementation Defined Attribution Unit (IDAU)
    6. 3.6 Programming Model
      1. 3.6.1 Modes of operation and execution
        1. 3.6.1.1 Security states
        2. 3.6.1.2 Operating modes
        3. 3.6.1.3 Operating states
        4. 3.6.1.4 Privileged access and unprivileged user access
      2. 3.6.2 Instruction set summary
      3. 3.6.3 Memory model
        1. 3.6.3.1 Private Peripheral Bus
        2. 3.6.3.2 Unaligned accesses
      4. 3.6.4 Processor core registers summary
      5. 3.6.5 Exceptions
        1. 3.6.5.1 Exception handling and prioritization
    7. 3.7 TrustZone-M
      1. 3.7.1 Overview
      2. 3.7.2 M33 Configuration
      3. 3.7.3 Description of elements
        1. 3.7.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 3.7.3.1.1 Expected use
    8. 3.8 CC35xx Host MCU Registers
      1. 3.8.1 HOSTMCU_AON Registers
      2. 3.8.2 HOST_MCU Registers
      3. 3.8.3 HOST_MCU_SEC Registers
    9. 3.9 Arm® Cortex®-M33 Registers
      1. 3.9.1  CPU_ROM_TABLE Registers
      2. 3.9.2  TPIU Registers
      3. 3.9.3  DCB Registers
      4. 3.9.4  DIB Registers
      5. 3.9.5  DWT Registers
      6. 3.9.6  FPB Registers
      7. 3.9.7  FPE Registers
      8. 3.9.8  ICB Registers
      9. 3.9.9  ITM Registers
      10. 3.9.10 MPU Registers
      11. 3.9.11 NVIC Registers
      12. 3.9.12 SAU Registers
      13. 3.9.13 SCB Registers
      14. 3.9.14 SYSTIMER Registers
      15. 3.9.15 SYSTICK Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation to HardFault
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Manager
      1. 5.4.1 Introduction
      2. 5.4.2 Interrupts List
      3. 5.4.3 Wakeup Sources
      4. 5.4.4 Shared Peripherals MUX Selector
        1. 5.4.4.1 ADC HW Event Selector Mux
        2. 5.4.4.2 I2S HW Event Selector Mux
        3. 5.4.4.3 PDM HW Event Selector Mux
      5. 5.4.5 Timers MUX Selector Mux
        1. 5.4.5.1 SysTimer0 HW Event Selector Mux
        2. 5.4.5.2 SysTimer1 HW Event Selector Mux
        3. 5.4.5.3 RTC HW Event Selector Mux
      6. 5.4.6 GPTIMERs MUX Selector Mux
        1. 5.4.6.1 GPTIMER0 HW Event Selector Mux
        2. 5.4.6.2 GPTIMER1 HW Event Selector Mux
    5. 5.5 SOC_IC Registers
    6. 5.6 SOC_AON Registers
    7. 5.7 SOC_AAON Registers
  7. 6 Debug Subsystem (DEBUGSS)
    1. 6.1 Introduction
    2. 6.2 Block Diagram
    3. 6.3 Overview
    4. 6.4 Physical Interface
    5. 6.5 Debug Access Ports
    6. 6.6 Debug Features
      1. 6.6.1 Processor Debug
      2. 6.6.2 Breakpoint Unit (BPU)
      3. 6.6.3 Peripheral Debug
    7. 6.7 Behavior in Low Power Modes
    8. 6.8 Debug Access Control
    9. 6.9 SOC_DEBUGSS Registers
  8. 7 Power, Reset, Clock Management
    1. 7.1 Power Management
      1. 7.1.1 Power Supply System
        1. 7.1.1.1 VDD_MAIN
        2. 7.1.1.2 VIO
        3. 7.1.1.3 VDDSF
        4. 7.1.1.4 VPA
      2. 7.1.2 Power States
      3. 7.1.3 Power Domains
      4. 7.1.4 Brownout (BOR)
      5. 7.1.5 Boot Sequence
    2. 7.2 Reset
      1. 7.2.1 Reset Cause
      2. 7.2.2 Watchdog Timer (WDT)
    3. 7.3 Clocks
      1. 7.3.1 Fast Clock
      2. 7.3.2 Slow Clock
        1. 7.3.2.1 Slow Clock Overview
        2. 7.3.2.2 Slow Clock Tree
        3. 7.3.2.3 Slow Clock Boot Process
    4. 7.4 PRCM_AON Registers
    5. 7.5 PRCM_SCRATCHPAD Registers
  9. 8 Memory Subsystem (MEMSS)
    1. 8.1  Introduction
    2. 8.2  SRAM
    3. 8.3  D-Cache
    4. 8.4  Flash
    5. 8.5  PSRAM
    6. 8.6  XiP Memory Access
      1. 8.6.1 OTFDE
      2. 8.6.2 xSPI
      3. 8.6.3 Topology
      4. 8.6.4 µDMA
      5. 8.6.5 Arbiter
    7. 8.7  ICACHE Registers
    8. 8.8  DCACHE Registers
    9. 8.9  OSPI Registers
    10. 8.10 HOST_XIP Registers
  10. 9 Hardware Security Module (HSM)
    1. 9.1 Introduction
    2. 9.2 Overview
    3. 9.3 Mailbox and Register Access Firewall
    4. 9.4 DMA Firewall
    5. 9.5 HSM Key Storage
    6. 9.6 HSM Registers
    7. 9.7 HSM_NON_SEC Registers
    8. 9.8 HSM_SEC Registers
  11. 10Device Boot and Bootloader
    1. 10.1 CC35xx Boot Concept
    2. 10.2 Features
    3. 10.3 Vendor Images Format and Processing
      1. 10.3.1 External Flash Arrangement
      2. 10.3.2 Vendor Images Format
    4. 10.4 Boot Flows
      1. 10.4.1 Application Execution Boot Flow
      2. 10.4.2 Activation Flow
      3. 10.4.3 Initial Programming Flow
      4. 10.4.4 Reprogramming Flow
      5. 10.4.5 Wireless Connectivity Testing Tool Flow
    5. 10.5 Chain of Trust
  12. 11Direct Memory Access (DMA)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Channels Assignment
      2. 11.3.2 Transfer Types
      3. 11.3.3 Addressing Modes
      4. 11.3.4 Transfer Modes
      5. 11.3.5 DMA Aligner Support
      6. 11.3.6 Initiating DMA Transfers
      7. 11.3.7 Stopping DMA Transfers
      8. 11.3.8 Channel Priorities
      9. 11.3.9 DMA Interrupts
    4. 11.4 HOST_DMA Registers
  13. 12One Time Programming (OTP)
  14. 13General Purpose Timers (GPT)
    1. 13.1 Overview
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1  Prescaler
      2. 13.3.2  Counter
      3. 13.3.3  Target
      4. 13.3.4  Channel Input Logic
      5. 13.3.5  Channel Output Logic
      6. 13.3.6  Channel Actions
        1. 13.3.6.1 Period and Pulse Width Measurement
        2. 13.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 13.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 13.3.7  Channel Capture Configuration
      8. 13.3.8  Channel Filters
        1. 13.3.8.1 Setting up the Channel Filters
      9. 13.3.9  Synchronize Multiple GPTimers
      10. 13.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 13.4 Timer Modes
      1. 13.4.1 Quadrature Decoder
      2. 13.4.2 DMA
      3. 13.4.3 IR Generation
      4. 13.4.4 Fault and Park
      5. 13.4.5 Dead-Band
      6. 13.4.6 Dead-Band, Fault and Park
      7. 13.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 13.5 GPTIMER Registers
  15. 14System Timer (SysTimer)
    1. 14.1 Overview
    2. 14.2 Block Diagram
    3. 14.3 Functional Description
      1. 14.3.1 Common Channel Features
        1. 14.3.1.1 Compare Mode
        2. 14.3.1.2 Capture Mode
        3. 14.3.1.3 Additional Channel Arming Methods
      2. 14.3.2 Interrupts and Events
    4. 14.4 SYSRESOURCES Registers
    5. 14.5 SYSTIM Registers
  16. 15Real-Time Clock (RTC)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Interrupts and Events
      1. 15.3.1 Input Event
      2. 15.3.2 Output Event
      3. 15.3.3 Arming and Disarming Channels
    4. 15.4 CAPTURE and COMPARE Configurations
      1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
    5. 15.5 RTC Registers
  17. 16General Purpose Input/Output (GPIOs)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 I/O Mapping and Configuration
      1. 16.3.1 Basic I/O Mapping
      2. 16.3.2 Pin Mapping
    4. 16.4 Edge Detection
    5. 16.5 GPIO
    6. 16.6 I/O Pins
    7. 16.7 Unused Pins
    8. 16.8 IOMUX Registers
  18. 17Universal Asynchronous Receivers/Transmitters (UART)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 UART Functional Description
      1. 17.3.1 Transmit and Receive Logic
      2. 17.3.2 Baud Rate Generation
      3. 17.3.3 FIFO Operation
        1. 17.3.3.1 FIFO Remapping
      4. 17.3.4 Data Transmission
      5. 17.3.5 Flow Control
      6. 17.3.6 IrDA Encoding and Decoding
      7. 17.3.7 Interrupts
      8. 17.3.8 Loopback Operation
    4. 17.4 UART-LIN Specification
      1. 17.4.1 Break transmission in UART mode
      2. 17.4.2 Break reception in UART mode
      3. 17.4.3 Break/Synch transmission in LIN mode
      4. 17.4.4 Break/Synch reception in LIN mode
      5. 17.4.5 Dormant mode operation
      6. 17.4.6 Event signal generation
      7. 17.4.7 Event signal detection when device is in active/idle modes
      8. 17.4.8 Event signal detection when device is in sleep mode
    5. 17.5 Interface to Host DMA
    6. 17.6 Initialization and Configuration
    7. 17.7 UART Registers
  19. 18Serial Peripheral Interface (SPI)
    1. 18.1 Overview
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Signal Description
    3. 18.3 Functional Description
      1. 18.3.1  Clock Control
      2. 18.3.2  FIFO Operation
        1. 18.3.2.1 Transmit FIFO
        2. 18.3.2.2 Repeated Transmit Operation
        3. 18.3.2.3 Receive FIFO
        4. 18.3.2.4 FIFO Flush
      3. 18.3.3  Interrupts
      4. 18.3.4  Data Format
      5. 18.3.5  Delayed Data Sampling
      6. 18.3.6  Chip Select Control
      7. 18.3.7  Command Data Control
      8. 18.3.8  Protocol Descriptions
        1. 18.3.8.1 Motorola SPI Frame Format
        2. 18.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 18.3.8.3 MICROWIRE Frame Format
      9. 18.3.9  CRC Configuration
      10. 18.3.10 Auto CRC Functionality
      11. 18.3.11 SPI Status
      12. 18.3.12 Debug Halt
    4. 18.4 Host DMA Operation
    5. 18.5 Initialization and Configuration
    6. 18.6 SPI Registers
  20. 19Inter-Integrated Circuit (I2C) Interface
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Clock Control
        1. 19.3.1.1 Internal Clock
        2. 19.3.1.2 External Clock
      2. 19.3.2 General Architecture
        1. 19.3.2.1  Start and Stop Conditions
        2. 19.3.2.2  Data Format with 7-Bit Address
        3. 19.3.2.3  Data Format with 10-Bit Addressing
          1. 19.3.2.3.1 Additional 10-Bit Scenarios
        4. 19.3.2.4  Acknowledge
        5. 19.3.2.5  Repeated Start
        6. 19.3.2.6  Clock Stretching
        7. 19.3.2.7  Arbitration
        8. 19.3.2.8  Multi-Controller mode
        9. 19.3.2.9  Glitch Suppression
        10. 19.3.2.10 FIFO Operation
        11. 19.3.2.11 Burst Mode Operation
        12. 19.3.2.12 DMA Operation
        13. 19.3.2.13 Flush Stale Tx Data in Target Mode
          1. 19.3.2.13.1 Recommended Sequence
        14. 19.3.2.14 SMBUS 3.0 Support
          1. 19.3.2.14.1 Quick Command
          2. 19.3.2.14.2 Acknowledge Control
          3. 19.3.2.14.3 Alert Response protocol
          4. 19.3.2.14.4 Address Resolution Protocol
          5. 19.3.2.14.5 Enhanced Acknowledge Control
    4. 19.4 Initialization and Configuration
    5. 19.5 Interrupts
    6. 19.6 I2C Registers
  21. 20Secure Digital Multimedia Card (SDMMC)
    1. 20.1 Introduction
      1. 20.1.1 SDMMC Features
      2. 20.1.2 Integration
    2. 20.2 Functional Description
      1. 20.2.1  SDMMC Functional Modes
        1. 20.2.1.1 SDMMC Connected to an SD Card
        2. 20.2.1.2 Protocol and Data Format
          1. 20.2.1.2.1 Protocol
          2. 20.2.1.2.2 Data Format
      2. 20.2.2  SD Card Feedback
      3. 20.2.3  Resets
        1. 20.2.3.1 Hardware Reset
        2. 20.2.3.2 Software Reset
      4. 20.2.4  Interrupt Requests
        1. 20.2.4.1 Interrupt-Driven Operation
        2. 20.2.4.2 Polling
      5. 20.2.5  DMA Modes
        1. 20.2.5.1 DMA Peripheral Mode Operations
          1. 20.2.5.1.1 DMA Receive Mode
          2. 20.2.5.1.2 DMA Transmit Mode
      6. 20.2.6  Buffer Management
        1. 20.2.6.1 Data Buffer
          1. 20.2.6.1.1 Memory Size and Block Length
          2. 20.2.6.1.2 Data Buffer Status
      7. 20.2.7  Transfer Process
        1. 20.2.7.1 Different Types of Commands
        2. 20.2.7.2 Different Types of Responses
      8. 20.2.8  Transfer or Command Status and Error Reporting
        1. 20.2.8.1 Busy Timeout for R1b, R5b Response Type
        2. 20.2.8.2 Busy Timeout After Write CRC Status
        3. 20.2.8.3 Write CRC Status Timeout
        4. 20.2.8.4 Read Data Timeout
      9. 20.2.9  Auto Command 12 Timings
        1. 20.2.9.1 Auto Command 12 Timings During Write Transfer
        2. 20.2.9.2 Auto Command 12 Timings During Read Transfer
      10. 20.2.10 Transfer Stop
      11. 20.2.11 Output Signals Generation
        1. 20.2.11.1 Generation on Falling Edge of SDMMC Clock
        2. 20.2.11.2 Generation on Rising Edge of SDMMC Clock
      12. 20.2.12 Test Registers
      13. 20.2.13 SDMMC Hardware Status Features
    3. 20.3 Low-Level Programming Models
      1. 20.3.1 SDMMC Initialization Flow
        1. 20.3.1.1 Enable OCP and CLKADPI Clocks
        2. 20.3.1.2 SD Soft Reset Flow
        3. 20.3.1.3 Set SD Default Capabilities
        4. 20.3.1.4 SDMMC Host and Bus Configuration
      2. 20.3.2 Operational Modes Configuration
        1. 20.3.2.1 Basic Operations for SDMMC
        2. 20.3.2.2 Card Detection, Identification, and Selection
    4. 20.4 SDMMC Registers
  22. 21Secure Digital Input/Output (SDIO)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 SDIO Interface Description
      2. 21.3.2 Protocol and Data Format
      3. 21.3.3 I/O Read/Write Command
        1. 21.3.3.1 IO_WR_DIRECT Command (CMD52)
        2. 21.3.3.2 IO_WR_EXTENDED Command (CMD53)
      4. 21.3.4 Reset
      5. 21.3.5 FIFO Operation
        1. 21.3.5.1 Rx FIFO (For Host Write)
        2. 21.3.5.2 Tx FIFO (For Host Read)
      6. 21.3.6 Interrupt Request
        1. 21.3.6.1 External Host IRQ
        2. 21.3.6.2 M33 IRQ
      7. 21.3.7 Transaction Details
        1. 21.3.7.1 Host write to SDIO IP (Rx FIFO)
          1. 21.3.7.1.1 Host write to SDIO IP (Rx FIFO) – Long SW latency case
          2. 21.3.7.1.2 Host write to SDIO IP (Rx FIFO) – CRC Error Case
        2. 21.3.7.2 Host reads from SDIO (TX buffer)
    4. 21.4 SDIO_CORE Registers
    5. 21.5 SDIO_CARD_FN1 Registers
  23. 22Inter-Integrated Circuit Sound (I2S)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  Signal Descriptions
    4. 22.4  Functional Description
      1. 22.4.1 Pin Configuration
      2. 22.4.2 Serial Format Configuration
        1. 22.4.2.1 Register Configuration
      3. 22.4.3 Left-Justified (LJF)
        1. 22.4.3.1 Register Configuration
      4. 22.4.4 Right-Justified (RJF)
        1. 22.4.4.1 Register Configuration
      5. 22.4.5 DSP
        1. 22.4.5.1 Register Configuration
      6. 22.4.6 Clock Configuration
    5. 22.5  Memory Interface
      1. 22.5.1 Sample Word Length
      2. 22.5.2 Padding Mechanism
      3. 22.5.3 Channel Mapping
      4. 22.5.4 Sample Storage in Memory
      5. 22.5.5 DMA Operation
        1. 22.5.5.1 Start-Up
        2. 22.5.5.2 Operation
        3. 22.5.5.3 Shutdown
    6. 22.6  Samplestamp Generator
      1. 22.6.1 Samplestamp Counters
      2. 22.6.2 Start-Up Triggers
      3. 22.6.3 Samplestamp Capture
      4. 22.6.4 Achieving constant audio latency
    7. 22.7  Error Detection
    8. 22.8  Usage
      1. 22.8.1 Start-Up Sequence
      2. 22.8.2 Shutdown Sequence
    9. 22.9  I2S Configuration Guideline
    10. 22.10 I2S Registers
  24. 23Pulse Density Modulation (PDM)
    1. 23.1  Introduction
    2. 23.2  Block Diagram
    3. 23.3  Input Selection
      1. 23.3.1 PDM Data Mode
      2. 23.3.2 Manchester Input Mode
    4. 23.4  CIC Filter
      1. 23.4.1 Filter Design
      2. 23.4.2 Digital Filter Output
      3. 23.4.3 Offset Binary Mode
      4. 23.4.4 Twos-Complement Mode
    5. 23.5  FIFO Organization in Different Modes
      1. 23.5.1 Single Mono Microphone Configuration
        1. 23.5.1.1 24-bit Sample Size
          1. 23.5.1.1.1 32-bit Data Read
        2. 23.5.1.2 16-bit Sample Size
          1. 23.5.1.2.1 32-bit Data Read
          2. 23.5.1.2.2 16-bit Data Read
        3. 23.5.1.3 8-bit Sample Size
          1. 23.5.1.3.1 32-bit Data Read
          2. 23.5.1.3.2 16-bit Data Read
          3. 23.5.1.3.3 8-bit Data Read
      2. 23.5.2 Stereo or Dual Mono Microphone Configuration
        1. 23.5.2.1 24-bit Sample Size
          1. 23.5.2.1.1 32-bit Data Read
        2. 23.5.2.2 16-bit Sample Size
          1. 23.5.2.2.1 32-bit Data Read
          2. 23.5.2.2.2 16-bit Data Read
        3. 23.5.2.3 8-bit Sample Size
          1. 23.5.2.3.1 32-bit Data Read
          2. 23.5.2.3.2 16-bit Data Read
          3. 23.5.2.3.3 8-bit Data Read
      3. 23.5.3 FIFO Threshold Setting
      4. 23.5.4 Reset FIFO
    6. 23.6  Automatic Gain Control (AGC)
      1. 23.6.1 Operation in 2's Complement Format
      2. 23.6.2 Operation in Offset Binary Format
    7. 23.7  Interrupts
    8. 23.8  Clock Select and Control
    9. 23.9  DMA Operation
    10. 23.10 Samplestamp Generator
      1. 23.10.1 Samplestamp Counters
      2. 23.10.2 Start-Up Triggers
      3. 23.10.3 Samplestamp Capture
      4. 23.10.4 Achieving Constant Audio Latency
    11. 23.11 Debug‑Mode Flag Behavior
    12. 23.12 Software Guidelines
    13. 23.13 PDM Registers
  25. 24Analog to Digital Converter (ADC)
    1. 24.1 Overview
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1  ADC Core
      2. 24.3.2  Voltage Reference Options
      3. 24.3.3  Internal Channels
      4. 24.3.4  Resolution Modes
      5. 24.3.5  ADC Clocking
      6. 24.3.6  Power Down Behavior
      7. 24.3.7  Sampling Trigger Sources and Sampling Modes
        1. 24.3.7.1 AUTO Sampling Mode
        2. 24.3.7.2 MANUAL Sampling Mode
      8. 24.3.8  Sampling Period
      9. 24.3.9  Conversion Modes
      10. 24.3.10 ADC Data Format
      11. 24.3.11 Status Register
      12. 24.3.12 ADC Events
        1. 24.3.12.1 Generic Event Publishers (INT_EVENT0 & INT_EVENT1)
        2. 24.3.12.2 DMA Trigger Event Publisher (INT_EVENT2)
        3. 24.3.12.3 Generic Event Subscriber
      13. 24.3.13 Advanced Features
        1. 24.3.13.1 Window Comparator
        2. 24.3.13.2 DMA & FIFO Operation
          1. 24.3.13.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
          2. 24.3.13.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
          3. 24.3.13.2.3 DMA/CPU Operation Summary Matrix
        3. 24.3.13.3 Ad-hoc Single Conversion
    4. 24.4 ADC Registers
  26. 25Controller Area Network (CAN)
    1. 25.1 Introduction
    2. 25.2 Functions
    3. 25.3 DCAN Subsystem
    4. 25.4 DCAN Functional Description
      1. 25.4.1 Operating Modes
        1. 25.4.1.1 Software Initialization
        2. 25.4.1.2 Normal Operation
        3. 25.4.1.3 Restricted Operation Mode
        4. 25.4.1.4 Bus Monitoring Mode
        5. 25.4.1.5 Disabled Automatic Retransmission
          1. 25.4.1.5.1 Frame Transmission in DAR Mode
        6. 25.4.1.6 Power Down (Sleep Mode)
          1. 25.4.1.6.1 DCAN clock stop and wake operations
          2. 25.4.1.6.2 DCAN debug suspend operation
        7. 25.4.1.7 Test Modes
          1. 25.4.1.7.1 External Loop Back Mode
          2. 25.4.1.7.2 Internal Loop Back Mode
      2. 25.4.2 Timestamp Generation
        1. 25.4.2.1 Block Diagram
      3. 25.4.3 Timeout Counter
      4. 25.4.4 Rx Handling
        1. 25.4.4.1 Acceptance Filtering
          1. 25.4.4.1.1 Range Filter
          2. 25.4.4.1.2 Filter for specific IDs
          3. 25.4.4.1.3 Classic Bit Mask Filter
          4. 25.4.4.1.4 Standard Message ID Filtering
          5. 25.4.4.1.5 Extended Message ID Filtering
        2. 25.4.4.2 Rx FIFOs
          1. 25.4.4.2.1 Rx FIFO Blocking Mode
          2. 25.4.4.2.2 Rx FIFO Overwrite Mode
        3. 25.4.4.3 Dedicated Rx Buffers
          1. 25.4.4.3.1 Rx Buffer Handling
        4. 25.4.4.4 Debug on CAN Support
          1. 25.4.4.4.1 Filtering for Debug Messages
          2. 25.4.4.4.2 Debug Message Handling
      5. 25.4.5 Tx Handling
        1. 25.4.5.1 Transmit Pause
        2. 25.4.5.2 Dedicated Tx Buffers
        3. 25.4.5.3 Tx FIFO
        4. 25.4.5.4 Tx Queue
        5. 25.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 25.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 25.4.5.7 Transmit Cancellation
        8. 25.4.5.8 Tx Event Handling
      6. 25.4.6 FIFO Acknowledge Handling
      7. 25.4.7 DCAN Message RAM
        1. 25.4.7.1 Message RAM Configuration
        2. 25.4.7.2 Rx Buffer and FIFO Element
        3. 25.4.7.3 Tx Buffer Element
        4. 25.4.7.4 Tx Event FIFO Element
        5. 25.4.7.5 Standard Message ID Filter Element
        6. 25.4.7.6 Extended Message ID Filter Element
      8. 25.4.8 Interrupt Requests
    5. 25.5 DCAN Wrapper
    6. 25.6 DCAN Clock Enable
    7. 25.7 DCAN Registers
  27. 26Revision History

3.9.13 SCB Registers

Table 3-504 lists the memory-mapped registers for the SCB registers. All register offset addresses not listed in Table 3-504 should be considered as reserved locations and the register contents should not be modified.

Table 3-504 SCB Registers
OffsetAcronymRegister NameSection
0hREVIDRProvides implementation-specific minor revision informationSection 3.9.13.1
4hCPUIDProvides identification information for the PE, including an implementer code for the device and a device ID numberSection 3.9.13.2
8hICSRControls and provides status information for NMI, PendSV, SysTick and interruptsSection 3.9.13.3
ChVTORIndicates the offset of the vector table base address from memory address 0x00000000Section 3.9.13.4
10hAIRCRThis register is used to determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point).Section 3.9.13.5
14hSCRThis register is used for power-management functions, i.e., signaling to the system when the processor can enter a low power state, controlling how the processor enters and exits low power states.Section 3.9.13.6
18hCCRSets or returns configuration and control dataSection 3.9.13.7
1ChSHPR1Sets or returns priority for system handlers 4 - 7Section 3.9.13.8
20hSHPR2Sets or returns priority for system handlers 8 - 11Section 3.9.13.9
24hSHPR3Sets or returns priority for system handlers 12 - 15Section 3.9.13.10
28hSHCSRProvides access to the active and pending status of system exceptionsSection 3.9.13.11
2ChCFSRContains the three Configurable Fault Status RegistersSection 3.9.13.12
30hHFSRShows the cause of any HardFaultsSection 3.9.13.13
34hDFSRShows which debug event occurredSection 3.9.13.14
38hMMFARShows the address of the memory location that caused an MPU faultSection 3.9.13.15
3ChBFARShows the address associated with a precise data access BusFaultSection 3.9.13.16
40hAFSRThis register is used to determine additional system fault information to software. Single-cycle high level on an auxiliary faults is latched as one. The bit can only be cleared by writing a one to the corresponding bit. Auxiliary fault inputs to the **CPU** are tied to 0.Section 3.9.13.17
44hID_PFR0Gives top-level information about the instruction set supported by the PESection 3.9.13.18
48hID_PFR1Gives information about the programmers' model and Extensions supportSection 3.9.13.19
4ChID_DFR0Provides top level information about the debug systemSection 3.9.13.20
50hID_AFR0Provides information about the IMPLEMENTATION DEFINED features of the PESection 3.9.13.21
54hID_MMFR0Provides information about the implemented memory model and memory management supportSection 3.9.13.22
58hID_MMFR1Provides information about the implemented memory model and memory management supportSection 3.9.13.23
5ChID_MMFR2Provides information about the implemented memory model and memory management supportSection 3.9.13.24
60hID_MMFR3Provides information about the implemented memory model and memory management supportSection 3.9.13.25
64hID_ISAR0Provides information about the instruction set implemented by the PESection 3.9.13.26
68hID_ISAR1Provides information about the instruction set implemented by the PESection 3.9.13.27
6ChID_ISAR2Provides information about the instruction set implemented by the PESection 3.9.13.28
70hID_ISAR3Provides information about the instruction set implemented by the PESection 3.9.13.29
74hID_ISAR4Provides information about the instruction set implemented by the PESection 3.9.13.30
78hID_ISAR5Provides information about the instruction set implemented by the PESection 3.9.13.31
7ChCLIDRIdentifies the type of caches implemented and the level of coherency and unificationSection 3.9.13.32
80hCTRThe CTR provides information about the architecture of the currently selected cacheSection 3.9.13.33
84hCCSIDRProvides information about the architecture of the caches. CCSIDR is RES0 if CLIDR is zero.Section 3.9.13.34
88hCSSELRSelects the current Cache Size ID Register, CCSIDR, by specifying the required cache level and the cacheSection 3.9.13.35
8ChCPACRSpecifies the access privileges for coprocessors and the FP ExtensionSection 3.9.13.36
90hNSACRDefines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7Section 3.9.13.37

Complex bit access types are encoded to fit into small table cells. Table 3-505 shows the codes that are used for access types in this section.

Table 3-505 SCB Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

3.9.13.1 REVIDR Register (Offset = 0h) [Reset = 00000000h]

REVIDR is shown in Table 3-506.

Return to the Summary Table.

Provides implementation-specific minor revision information

Table 3-506 REVIDR Register Field Descriptions
BitFieldTypeResetDescription
31-0IMPLEMENTAION_DEFINEDR411FD210hThe contents of this field are IMPLEMENTATION DEFINED

3.9.13.2 CPUID Register (Offset = 4h) [Reset = 00000000h]

CPUID is shown in Table 3-507.

Return to the Summary Table.

Provides identification information for the PE, including an implementer code for the device and a device ID number

Table 3-507 CPUID Register Field Descriptions
BitFieldTypeResetDescription
31-24ImplementerR41hThis field must hold an implementer code that has been assigned by ARM
23-20VariantR1hIMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product
19-16ArchitectureRFhDefines the Architecture implemented by the PE
15-4PartNoRD21hIMPLEMENTATION DEFINED primary part number for the device
3-0RevisionR0hIMPLEMENTATION DEFINED revision number for the device

3.9.13.3 ICSR Register (Offset = 8h) [Reset = 00000000h]

ICSR is shown in Table 3-508.

Return to the Summary Table.

Controls and provides status information for NMI, PendSV, SysTick and interrupts

Table 3-508 ICSR Register Field Descriptions
BitFieldTypeResetDescription
31PENDNMISETR0hIndicates whether the NMI exception is pending
30PENDNMICLRW0hAllows the NMI exception pend state to be cleared
29RES0R0hReserved, RES0
28PENDSVSETR0hIndicates whether the PendSV `FTSSS exception is pending
27PENDSVCLRW0hAllows the PendSV exception pend state to be cleared `FTSSS
26PENDSTSETR0hIndicates whether the SysTick `FTSSS exception is pending
25PENDSTCLRW0hAllows the SysTick exception pend state to be cleared `FTSSS
24STTNSR/W0hControls whether in a single SysTick implementation, the SysTick is Secure or Non-secure
23ISRPREEMPTR0hIndicates whether a pending exception will be serviced on exit from debug halt state
22ISRPENDINGR0hIndicates whether an external interrupt, generated by the NVIC, is pending
21RES0_1R0hReserved, RES0
20-12VECTPENDINGR0hThe exception number of the highest priority pending and enabled interrupt
11RETTOBASER0hIn Handler mode, indicates whether there is more than one active exception
10-9RES0_2R0hReserved, RES0
8-0VECTACTIVER0hThe exception number of the current executing exception

3.9.13.4 VTOR Register (Offset = Ch) [Reset = 00000000h]

VTOR is shown in Table 3-509.

Return to the Summary Table.

Indicates the offset of the vector table base address from memory address 0x00000000

Table 3-509 VTOR Register Field Descriptions
BitFieldTypeResetDescription
31-7TBLOFFR00823FA4hBits 31 down to 7 of the vector table base offset.
6-0RES0R10hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.9.13.5 AIRCR Register (Offset = 10h) [Reset = 00000000h]

AIRCR is shown in Table 3-510.

Return to the Summary Table.

This register is used to determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point).

Table 3-510 AIRCR Register Field Descriptions
BitFieldTypeResetDescription
31-16VECTKEYR/WFA05hRegister key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. Otherwise the write value is ignored. Read always returns 0xFA05.
15ENDIANESSR0hData endianness bit
0 Little-endian.
1 Big-endian.
14PRISR0hPrioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is
enabled.
13BFHFNMINSR/W0hBusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI
exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception
0x0 BusFault, HardFault, and NMI are Secure.
0x1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault.
12-11RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
10-8PRIGROUPR/W0hInterrupt priority grouping field. This field determines the split of group priority from
subpriority
7-4RES4R0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3SYSRESETREQSR/W0hSystem reset request Secure only. The value of this bit defines whether the SYSRESETREQ bit is functional
for Non-secure use
2SYSRESETREQW0hSystem reset request. This bit allows software or a debugger to request a system reset:
0 Do not request a system reset.
1 Request a system reset.
This bit is not banked between Security states.
1VECTCLRACTIVEW0hReserved for Debug use. This bit reads as 0. When writing to the register you must write
0 to this bit, otherwise behavior is UNPREDICTABLE.
1RESERVEDR0hReserved
0RES0R0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.9.13.6 SCR Register (Offset = 14h) [Reset = 00000000h]

SCR is shown in Table 3-511.

Return to the Summary Table.

This register is used for power-management functions, i.e., signaling to the system when the processor can enter a low power state, controlling how the processor enters and exits low power states.

Table 3-511 SCR Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4SEVONPENDR/W0hSend Event on Pending bit:
0 Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
1 Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the
processor is not waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction or an external event.
This bit is banked between Security states.
3SLEEPDEEPSR/W0hControls whether the SLEEPDEEP bit is only accessible from the Secure state:
0 The SLEEPDEEP bit accessible from both Security states.
1 The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state.
This bit in only accessible from the Secure state, and behaves as RAZ/WI when accessed from the Nonsecure
state.
This bit is not banked between Security states.
2SLEEPDEEPR/W0hControls whether the processor uses sleep or deep sleep as its low power mode.
0 Sleep.
1 Deep sleep.
This bit is not banked between Security states.
1SLEEPONEXITR/W0hIndicates sleep-on-exit when returning from Handler mode to Thread mode:
0 Do not sleep when returning to Thread mode.
1 Enter sleep, or deep sleep, on return from an ISR.
Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
This bit is banked between Security states.
0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

3.9.13.7 CCR Register (Offset = 18h) [Reset = 00000000h]

CCR is shown in Table 3-512.

Return to the Summary Table.

Sets or returns configuration and control data

Table 3-512 CCR Register Field Descriptions
BitFieldTypeResetDescription
31-19RES0R0hReserved, RES0
18BPR0hEnables program flow prediction `FTSSS
17ICR0hThis is a global enable bit for instruction caches in the selected Security state
16DCR0hEnables data caching of all data accesses to Normal memory `FTSSS
15-11RES0_1R0hReserved, RES0
10STKOFHFNMIGNR/W0hControls the effect of a stack limit violation while executing at a requested priority less than 0
9RES1R1hReserved, RES1
8BFHFNMIGNR/W0hDetermines the effect of precise BusFaults on handlers running at a requested priority less than 0
7-5RES0_2R0hReserved, RES0
4DIV_0_TRPR/W0hControls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero
3UNALIGN_TRPR/W0hControls the trapping of unaligned word or halfword accesses
2RES0_3R0hReserved, RES0
1USERSETMPENDR/W0hDetermines whether unprivileged accesses are permitted to pend interrupts via the STIR
0RES1_1R1hReserved, RES1

3.9.13.8 SHPR1 Register (Offset = 1Ch) [Reset = 00000000h]

SHPR1 is shown in Table 3-513.

Return to the Summary Table.

Sets or returns priority for system handlers 4 - 7

Table 3-513 SHPR1 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_7R/W0hPriority of system handler 7, SecureFault
23-16PRI_6R/W0hPriority of system handler 6, UsageFault
15-8PRI_5R/W0hPriority of system handler 5, BusFault
7-0PRI_4R/W0hPriority of system handler 4, MemManage

3.9.13.9 SHPR2 Register (Offset = 20h) [Reset = 00000000h]

SHPR2 is shown in Table 3-514.

Return to the Summary Table.

Sets or returns priority for system handlers 8 - 11

Table 3-514 SHPR2 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_11R/W0hPriority of system handler 11, SVCall
23-0RES0RXhReserved, RES0

3.9.13.10 SHPR3 Register (Offset = 24h) [Reset = 00000000h]

SHPR3 is shown in Table 3-515.

Return to the Summary Table.

Sets or returns priority for system handlers 12 - 15

Table 3-515 SHPR3 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_15R/W0hPriority of system handler 15, SysTick
23-16PRI_14R/W0hPriority of system handler 14, PendSV
15-0RES0_0R0hReserved, RES0

3.9.13.11 SHCSR Register (Offset = 28h) [Reset = 00000000h]

SHCSR is shown in Table 3-516.

Return to the Summary Table.

Provides access to the active and pending status of system exceptions

Table 3-516 SHCSR Register Field Descriptions
BitFieldTypeResetDescription
31-22RES0R0hReserved, RES0
21HARDFAULTPENDEDR/W0h`IAAMO the pending state of the HardFault exception `CTTSSS
20SECUREFAULTPENDEDR/W0h`IAAMO the pending state of the SecureFault exception
19SECUREFAULTENAR/W0h`DW the SecureFault exception is enabled
18USGFAULTENAR/W0h`DW the UsageFault exception is enabled `FTSSS
17BUSFAULTENAR/W0h`DW the BusFault exception is enabled
16MEMFAULTENAR/W0h`DW the MemManage exception is enabled `FTSSS
15SVCALLPENDEDR/W0h`IAAMO the pending state of the SVCall exception `FTSSS
14BUSFAULTPENDEDR/W0h`IAAMO the pending state of the BusFault exception
13MEMFAULTPENDEDR/W0h`IAAMO the pending state of the MemManage exception `FTSSS
12USGFAULTPENDEDR/W0hThe UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS
11SYSTICKACTR/W0h`IAAMO the active state of the SysTick exception `FTSSS
10PENDSVACTR/W0h`IAAMO the active state of the PendSV exception `FTSSS
9RES0_1R0hReserved, RES0
8MONITORACTR/W0h`IAAMO the active state of the DebugMonitor exception
7SVCALLACTR/W0h`IAAMO the active state of the SVCall exception `FTSSS
6RES0_2R0hReserved, RES0
5NMIACTR/W0h`IAAMO the active state of the NMI exception
4SECUREFAULTACTR/W0h`IAAMO the active state of the SecureFault exception
3USGFAULTACTR/W0h`IAAMO the active state of the UsageFault exception `FTSSS
2HARDFAULTACTR/W0hIndicates and allows limited modification of the active state of the HardFault exception `FTSSS
1BUSFAULTACTR/W0h`IAAMO the active state of the BusFault exception
0MEMFAULTACTR/W0h`IAAMO the active state of the MemManage exception `FTSSS

3.9.13.12 CFSR Register (Offset = 2Ch) [Reset = 00000000h]

CFSR is shown in Table 3-517.

Return to the Summary Table.

Contains the three Configurable Fault Status Registers

Table 3-517 CFSR Register Field Descriptions
BitFieldTypeResetDescription
31-26RES0_3R0hReserved, RES0
25DIVBYZEROR/W0hSticky flag indicating whether an integer division by zero error has occurred
24UNALIGNEDR/W0hSticky flag indicating whether an unaligned access error has occurred
23-21RES0_1_2R0hReserved, RES0
20STKOFR/W0hSticky flag indicating whether a stack overflow error has occurred
19NOCPR/W0hSticky flag indicating whether a coprocessor disabled or not present error has occurred
18INVPCR/W0hSticky flag indicating whether an integrity check error has occurred
17INVSTATER/W0hSticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred
16UNDEFINSTRR/W0hSticky flag indicating whether an undefined instruction error has occurred
15BFARVALIDR/W0hIndicates validity of the contents of the BFAR register
14RES0_2R0hReserved, RES0
13LSPERRR/W0hRecords whether a BusFault occurred during FP lazy state preservation
12STKERRR/W0hRecords whether a derived BusFault occurred during exception entry stacking
11UNSTKERRR/W0hRecords whether a derived BusFault occurred during exception return unstacking
10IMPRECISERRR/W0hRecords whether an imprecise data access error has occurred
9PRECISERRR/W0hRecords whether a precise data access error has occurred
8IBUSERRR/W0hRecords whether a BusFault on an instruction prefetch has occurred
7MMARVALIDR/W0hIndicates validity of the MMFAR register
6RES0R0hReserved, RES0
5MLSPERRR/W0hRecords whether a MemManage fault occurred during FP lazy state preservation
4MSTKERRR/W0hRecords whether a derived MemManage fault occurred during exception entry stacking
3MUNSTKERRR/W0hRecords whether a derived MemManage fault occurred during exception return unstacking
2RES0_1R0hReserved, RES0
1DACCVIOLR/W0hRecords whether a data access violation has occurred
0IACCVIOLR/W0hRecords whether an instruction related memory access violation has occurred

3.9.13.13 HFSR Register (Offset = 30h) [Reset = 00000000h]

HFSR is shown in Table 3-518.

Return to the Summary Table.

Shows the cause of any HardFaults

Table 3-518 HFSR Register Field Descriptions
BitFieldTypeResetDescription
31DEBUGEVTR/W0hIndicates when a Debug event has occurred
30FORCEDR/W0hIndicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled
29-2RES0RXhReserved, RES0
1VECTTBLR/W0hIndicates when a fault has occurred because of a vector table read error on exception processing
0RES0_1R0hReserved, RES0

3.9.13.14 DFSR Register (Offset = 34h) [Reset = 00000000h]

DFSR is shown in Table 3-519.

Return to the Summary Table.

Shows which debug event occurred

Table 3-519 DFSR Register Field Descriptions
BitFieldTypeResetDescription
31-5RES0RXhReserved, RES0
4EXTERNALR/W0hSticky flag indicating whether an External debug request debug event has occurred
3VCATCHR/W0hSticky flag indicating whether a Vector catch debug event has occurred
2DWTTRAPR/W0hSticky flag indicating whether a Watchpoint debug event has occurred
1BKPTR/W0hSticky flag indicating whether a Breakpoint debug event has occurred
0HALTEDR/W0hSticky flag indicating that a Halt request debug event or Step debug event has occurred

3.9.13.15 MMFAR Register (Offset = 38h) [Reset = 00000000h]

MMFAR is shown in Table 3-520.

Return to the Summary Table.

Shows the address of the memory location that caused an MPU fault

Table 3-520 MMFAR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/W0hThis register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN

3.9.13.16 BFAR Register (Offset = 3Ch) [Reset = 00000000h]

BFAR is shown in Table 3-521.

Return to the Summary Table.

Shows the address associated with a precise data access BusFault

Table 3-521 BFAR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/W0hThis register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN

3.9.13.17 AFSR Register (Offset = 40h) [Reset = 00000000h]

AFSR is shown in Table 3-522.

Return to the Summary Table.

This register is used to determine additional system fault information to software. Single-cycle high level on an auxiliary faults is latched as one. The bit can only be cleared by writing a one to the corresponding bit. Auxiliary fault inputs to the CPU are tied to 0.

Table 3-522 AFSR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0IMPDEFR/W0hImplementation defined. The bits map directly onto the signal assignment to the auxiliary fault inputs. Tied to 0

3.9.13.18 ID_PFR0 Register (Offset = 44h) [Reset = 00000000h]

ID_PFR0 is shown in Table 3-523.

Return to the Summary Table.

Gives top-level information about the instruction set supported by the PE

Table 3-523 ID_PFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RES0RXhReserved, RES0
7-4State1R3hT32 instruction set support
3-0State0R0hA32 instruction set support

3.9.13.19 ID_PFR1 Register (Offset = 48h) [Reset = 00000000h]

ID_PFR1 is shown in Table 3-524.

Return to the Summary Table.

Gives information about the programmers' model and Extensions support

Table 3-524 ID_PFR1 Register Field Descriptions
BitFieldTypeResetDescription
31-12RES0RXhReserved, RES0
11-8MProgModR2hIdentifies support for the M-Profile programmers' model support
7-4SecurityR1hIdentifies whether the Security Extension is implemented
3-0RES0_1R0hReserved, RES0

3.9.13.20 ID_DFR0 Register (Offset = 4Ch) [Reset = 00000000h]

ID_DFR0 is shown in Table 3-525.

Return to the Summary Table.

Provides top level information about the debug system

Table 3-525 ID_DFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-24RES0R0hReserved, RES0
23-20MProfDbgR2hIndicates the supported M-profile debug architecture
19-0RES0_1RXhReserved, RES0

3.9.13.21 ID_AFR0 Register (Offset = 50h) [Reset = 00000000h]

ID_AFR0 is shown in Table 3-526.

Return to the Summary Table.

Provides information about the IMPLEMENTATION DEFINED features of the PE

Table 3-526 ID_AFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RES0R0hReserved, RES0
15-12IMPDEF3R0hIMPLEMENTATION DEFINED meaning
11-8IMPDEF2R0hIMPLEMENTATION DEFINED meaning
7-4IMPDEF1R0hIMPLEMENTATION DEFINED meaning
3-0IMPDEF0R0hIMPLEMENTATION DEFINED meaning

3.9.13.22 ID_MMFR0 Register (Offset = 54h) [Reset = 00000000h]

ID_MMFR0 is shown in Table 3-527.

Return to the Summary Table.

Provides information about the implemented memory model and memory management support

Table 3-527 ID_MMFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-24RES0R0hReserved, RES0
23-20AuxRegR1hIndicates support for Auxiliary Control Registers
19-16TCMR0hIndicates support for tightly coupled memories (TCMs)
15-12ShareLvlR1hIndicates the number of shareability levels implemented
11-8OuterShrRFhIndicates the outermost shareability domain implemented
7-4PMSAR4hIndicates support for the protected memory system architecture (PMSA)
3-0RES0_1R0hReserved, RES0

3.9.13.23 ID_MMFR1 Register (Offset = 58h) [Reset = 00000000h]

ID_MMFR1 is shown in Table 3-528.

Return to the Summary Table.

Provides information about the implemented memory model and memory management support

Table 3-528 ID_MMFR1 Register Field Descriptions
BitFieldTypeResetDescription
31-0RES0R0hReserved, RES0

3.9.13.24 ID_MMFR2 Register (Offset = 5Ch) [Reset = 00000000h]

ID_MMFR2 is shown in Table 3-529.

Return to the Summary Table.

Provides information about the implemented memory model and memory management support

Table 3-529 ID_MMFR2 Register Field Descriptions
BitFieldTypeResetDescription
31-28RES0R0hReserved, RES0
27-24WFIStallR1hIndicates the support for Wait For Interrupt (WFI) stalling
23-0RES0_1RXhReserved, RES0

3.9.13.25 ID_MMFR3 Register (Offset = 60h) [Reset = 00000000h]

ID_MMFR3 is shown in Table 3-530.

Return to the Summary Table.

Provides information about the implemented memory model and memory management support

Table 3-530 ID_MMFR3 Register Field Descriptions
BitFieldTypeResetDescription
31-12RES0RXhReserved, RES0
11-8BPMaintR0hIndicates the supported branch predictor maintenance
7-4CMaintSWR0hIndicates the supported cache maintenance operations by set/way
3-0CMaintVAR0hIndicates the supported cache maintenance operations by address

3.9.13.26 ID_ISAR0 Register (Offset = 64h) [Reset = 00000000h]

ID_ISAR0 is shown in Table 3-531.

Return to the Summary Table.

Provides information about the instruction set implemented by the PE

Table 3-531 ID_ISAR0 Register Field Descriptions
BitFieldTypeResetDescription
31-28RES0R0hReserved, RES0
27-24DivideR1hIndicates the supported Divide instructions
23-20DebugR1hIndicates the implemented Debug instructions
19-16CoprocR4hIndicates the supported Coprocessor instructions
15-12CmpBranchR1hIndicates the supported combined Compare and Branch instructions
11-8BitFieldR1hIndicates the supported bit field instructions
7-4BitCountR1hIndicates the supported bit count instructions
3-0RES0_1R0hReserved, RES0

3.9.13.27 ID_ISAR1 Register (Offset = 68h) [Reset = 00000000h]

ID_ISAR1 is shown in Table 3-532.

Return to the Summary Table.

Provides information about the instruction set implemented by the PE

Table 3-532 ID_ISAR1 Register Field Descriptions
BitFieldTypeResetDescription
31-28RES0R0hReserved, RES0
27-24InterworkR2hIndicates the implemented Interworking instructions
23-20ImmediateR2hIndicates the implemented for data-processing instructions with long immediates
19-16IfThenR1hIndicates the implemented If-Then instructions
15-12ExtendR2hIndicates the implemented Extend instructions
11-0RES0_1R0hReserved, RES0

3.9.13.28 ID_ISAR2 Register (Offset = 6Ch) [Reset = 00000000h]

ID_ISAR2 is shown in Table 3-533.

Return to the Summary Table.

Provides information about the instruction set implemented by the PE

Table 3-533 ID_ISAR2 Register Field Descriptions
BitFieldTypeResetDescription
31-28ReversalR2hIndicates the implemented Reversal instructions
27-24RES0R0hReserved, RES0
23-20MultUR2hIndicates the implemented advanced unsigned Multiply instructions
19-16MultSR3hIndicates the implemented advanced signed Multiply instructions
15-12MultR2hIndicates the implemented additional Multiply instructions
11-8MultiAccessIntR2hIndicates the support for interruptible multi-access instructions
7-4MemHintR3hIndicates the implemented Memory Hint instructions
3-0LoadStoreR2hIndicates the implemented additional load/store instructions

3.9.13.29 ID_ISAR3 Register (Offset = 70h) [Reset = 00000000h]

ID_ISAR3 is shown in Table 3-534.

Return to the Summary Table.

Provides information about the instruction set implemented by the PE

Table 3-534 ID_ISAR3 Register Field Descriptions
BitFieldTypeResetDescription
31-28RES0R0hReserved, RES0
27-24TrueNOPR1hIndicates the implemented true NOP instructions
23-20T32CopyR1hIndicates the support for T32 non flag-setting MOV instructions
19-16TabBranchR1hIndicates the implemented Table Branch instructions
15-12SynchPrimR1hUsed in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions
11-8SVCR1hIndicates the implemented SVC instructions
7-4SIMDR3hIndicates the implemented SIMD instructions
3-0SaturateR1hIndicates the implemented saturating instructions

3.9.13.30 ID_ISAR4 Register (Offset = 74h) [Reset = 00000000h]

ID_ISAR4 is shown in Table 3-535.

Return to the Summary Table.

Provides information about the instruction set implemented by the PE

Table 3-535 ID_ISAR4 Register Field Descriptions
BitFieldTypeResetDescription
31-28RES0R0hReserved, RES0
27-24PSR_MR1hIndicates the implemented M profile instructions to modify the PSRs
23-20SyncPrim_fracR3hUsed in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions
19-16BarrierR1hIndicates the implemented Barrier instructions
15-12RES0_1R0hReserved, RES0
11-8WritebackR1hIndicates the support for writeback addressing modes
7-4WithShiftsR3hIndicates the support for writeback addressing modes
3-0UnprivR2hIndicates the implemented unprivileged instructions

3.9.13.31 ID_ISAR5 Register (Offset = 78h) [Reset = 00000000h]

ID_ISAR5 is shown in Table 3-536.

Return to the Summary Table.

Provides information about the instruction set implemented by the PE

Table 3-536 ID_ISAR5 Register Field Descriptions
BitFieldTypeResetDescription
31-0RES0R0hReserved, RES0

3.9.13.32 CLIDR Register (Offset = 7Ch) [Reset = 00000000h]

CLIDR is shown in Table 3-537.

Return to the Summary Table.

Identifies the type of caches implemented and the level of coherency and unification

Table 3-537 CLIDR Register Field Descriptions
BitFieldTypeResetDescription
31-30ICBR0hThis field indicates the boundary between inner and outer domain
  • 0h = Not disclosed in this mechanism
  • 1h = L1 cache is the highest inner level
  • 2h = L2 cache is the highest inner level
  • 3h = L3 cache is the highest inner level
29-27LoUUR0hThis field indicates the Level of Unification Uniprocessor for the cache
hierarchy
26-24LoCR0hThis field indicates the Level of Coherence for the cache hierarchy
23-21LoUISR0hEnables Non-secure access to coprocessor CP0
20-18Ctype7R0hCache type field 7. Indicates the type of cache implemented at level 7.
  • 0h = No cache
  • 1h = Instruction cache only
  • 2h = Data cache only
  • 3h = Separate instruction and data caches
  • 4h = Unified cache
17-15Ctype6R0hCache type field 6. Indicates the type of cache implemented at level 6.
  • 0h = No cache
  • 1h = Instruction cache only
  • 2h = Data cache only
  • 3h = Separate instruction and data caches
  • 4h = Unified cache
14-12Ctype5R0hCache type field 5. Indicates the type of cache implemented at level 5.
  • 0h = No cache
  • 1h = Instruction cache only
  • 2h = Data cache only
  • 3h = Separate instruction and data caches
  • 4h = Unified cache
11-9Ctype4R0hCache type field 4. Indicates the type of cache implemented at level 4.
  • 0h = No cache
  • 1h = Instruction cache only
  • 2h = Data cache only
  • 3h = Separate instruction and data caches
  • 4h = Unified cache
8-6Ctype3R0hCache type field 3. Indicates the type of cache implemented at level 3.
  • 0h = No cache
  • 1h = Instruction cache only
  • 2h = Data cache only
  • 3h = Separate instruction and data caches
  • 4h = Unified cache
5-3Ctype2R0hCache type field 2. Indicates the type of cache implemented at level 2.
  • 0h = No cache
  • 1h = Instruction cache only
  • 2h = Data cache only
  • 3h = Separate instruction and data caches
  • 4h = Unified cache
2-0Ctype1R0hCache type field 1. Indicates the type of cache implemented at level 1.
  • 0h = No cache
  • 1h = Instruction cache only
  • 2h = Data cache only
  • 3h = Separate instruction and data caches
  • 4h = Unified cache

3.9.13.33 CTR Register (Offset = 80h) [Reset = 00000000h]

CTR is shown in Table 3-538.

Return to the Summary Table.

The CTR provides information about the architecture of the currently selected cache

Table 3-538 CTR Register Field Descriptions
BitFieldTypeResetDescription
31RES1R1hReserved, RES1
30-28RES0R0hReserved, RES0
27-24CWGR0hLog2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified
23-20ERGR0hLog2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions
19-16DminLineR0hLog2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE
15-14RES1_1R3hReserved, RES1
13-4RES0_1R0hReserved, RES0
3-0IminLineR0hLog2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE

3.9.13.34 CCSIDR Register (Offset = 84h) [Reset = 00000000h]

CCSIDR is shown in Table 3-539.

Return to the Summary Table.

Provides information about the architecture of the caches. CCSIDR is RES0 if CLIDR is zero.

Table 3-539 CCSIDR Register Field Descriptions
BitFieldTypeResetDescription
31WTR1hIndicates whether the currently selected cache level supports Write-Through
  • 0h = Not supported
  • 1h = Supported
30WBR0hIndicates whether the currently selected cache level supports Write-Back
  • 0h = Not supported
  • 1h = Supported
29RAR0hIndicates whether the currently selected cache level supports read-allocation
  • 0h = Not supported
  • 1h = Supported
28WAR0hIndicates whether the currently selected cache level supports write-allocation
  • 0h = Not supported
  • 1h = Supported
27-13NumSetsR6hIndicates (Number of sets in the currently selected cache) - 1. Therefore, a value of 0
indicates that 1 is set in the cache. The number of sets does not have to be a power of 2
12-3AssociativityR0hIndicates (Associativity of cache) - 1. A value of 0 indicates an associativity of 1. The
associativity does not have to be a power of 2
2-0LineSizeR0hIndicates (Log2(Number of words per line in the currently selected cache)) - 2.

3.9.13.35 CSSELR Register (Offset = 88h) [Reset = 00000000h]

CSSELR is shown in Table 3-540.

Return to the Summary Table.

Selects the current Cache Size ID Register, CCSIDR, by specifying the required cache level and the cache
type (either instruction or data cache)

Table 3-540 CSSELR Register Field Descriptions
BitFieldTypeResetDescription
31-4Res0R08000C00hReserved,Res0
3-1LevelR0hSelects which cache level is to be identified. Permitted values are from 0b000, indicating Level
1 cache, to 0b110 indicating Level 7 cache
  • 0h = Level 1 cache
  • 1h = Level 2 cache
  • 2h = Level 3 cache
  • 3h = Level 4 cache
  • 4h = Level 5 cache
  • 5h = Level 6 cache
  • 6h = Level 7 cache
0InDR0hSelects whether the instruction or the data cache is to be identified
  • 0h = Data or unified cache
  • 1h = Instruction cache

3.9.13.36 CPACR Register (Offset = 8Ch) [Reset = 00000000h]

CPACR is shown in Table 3-541.

Return to the Summary Table.

Specifies the access privileges for coprocessors and the FP Extension

Table 3-541 CPACR Register Field Descriptions
BitFieldTypeResetDescription
31-24RES0R0hReserved, RES0
23-22CP11R/W0hThe value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN
21-20CP10R/W0hDefines the access rights for the floating-point functionality
19-16RES0_1R0hReserved, RES0
15-14CP7R/W0h Controls access privileges for coprocessor 7
13-12CP6R/W0h Controls access privileges for coprocessor 6
11-10CP5R/W0h Controls access privileges for coprocessor 5
9-8CP4R/W0h Controls access privileges for coprocessor 4
7-6CP3R/W0h Controls access privileges for coprocessor 3
5-4CP2R/W0h Controls access privileges for coprocessor 2
3-2CP1R/W0h Controls access privileges for coprocessor 1
1-0CP0R/W0h Controls access privileges for coprocessor 0

3.9.13.37 NSACR Register (Offset = 90h) [Reset = 00000000h]

NSACR is shown in Table 3-542.

Return to the Summary Table.

Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7

Table 3-542 NSACR Register Field Descriptions
BitFieldTypeResetDescription
31-12RES0RXhReserved, RES0
11CP11R/W0hEnables Non-secure access to the Floating-point Extension
10CP10R/W0hEnables Non-secure access to the Floating-point Extension
9-8RES0_1R0hReserved, RES0
7CP7R/W0hEnables Non-secure access to coprocessor CP7
6CP6R/W0hEnables Non-secure access to coprocessor CP6
5CP5R/W0hEnables Non-secure access to coprocessor CP5
4CP4R/W0hEnables Non-secure access to coprocessor CP4
3CP3R/W0hEnables Non-secure access to coprocessor CP3
2CP2R/W0hEnables Non-secure access to coprocessor CP2
1CP1R/W0hEnables Non-secure access to coprocessor CP1
0CP0R/W0hEnables Non-secure access to coprocessor CP0