SWRU626 December   2025 CC3501E , CC3551E

 

  1.   1
  2. 1 Read This First
    1. 1.1 About This Manual
    2. 1.2 Register, Field, and Bit Calls
    3.     Trademarks
  3. 2 Architecture Overview
    1. 2.1  Target Applications
    2. 2.2  Introduction
    3. 2.3  Internal System Diagram
    4. 2.4  Arm Cortex M33
      1. 2.4.1 Processor Core
      2. 2.4.2 SysTick Timer
      3. 2.4.3 Nested Vectored Interrupt Controller
      4. 2.4.4 System Control Block (SCB)
      5. 2.4.5 TI AI instruction extensions
    5. 2.5  Power Management
      1. 2.5.1 VDD_MAIN
      2. 2.5.2 VDD_IO
      3. 2.5.3 VDDSF
      4. 2.5.4 VDD_PA
    6. 2.6  Debug Subsystem (DEBUGSS)
    7. 2.7  Memory Subsystem (MEMSS)
      1. 2.7.1 External Memory Interface
    8. 2.8  Hardware Security Module
    9. 2.9  General Purpose Timers (GPT)
    10. 2.10 Real Time Clock (RTC)
    11. 2.11 Direct Memory Access
    12. 2.12 GPIOs
    13. 2.13 Communication Peripherals
      1. 2.13.1 UART
      2. 2.13.2 I2C
      3. 2.13.3 SPI
      4. 2.13.4 I2S
      5. 2.13.5 SDMMC
      6. 2.13.6 SDIO
      7. 2.13.7 CAN
      8. 2.13.8 ADC
  4. 3  Arm Cortex-M33 Processor
    1. 3.1 Arm Cortex-M33 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 M33 instantiation parameters
    4. 3.4 Arm Cortex-M33 System Peripheral Details
      1. 3.4.1 Floating Point Unit (FPU)
      2. 3.4.2 Memory Protection Unit (MPU)
      3. 3.4.3 Digital Signal Processing (DSP)
      4. 3.4.4 Security Attribution Unit (SAU)
      5. 3.4.5 System Timer
      6. 3.4.6 Nested Vectored Interrupt Controller
      7. 3.4.7 System Control Block
      8. 3.4.8 System Control Space
    5. 3.5 CPU Sub-System Peripheral Details
      1. 3.5.1 Trace Port Interface Unit (TPIU)
      2. 3.5.2 DAP Bridge and Debug Authentication
      3. 3.5.3 Implementation Defined Attribution Unit (IDAU)
    6. 3.6 Programming Model
      1. 3.6.1 Modes of operation and execution
        1. 3.6.1.1 Security states
        2. 3.6.1.2 Operating modes
        3. 3.6.1.3 Operating states
        4. 3.6.1.4 Privileged access and unprivileged user access
      2. 3.6.2 Instruction set summary
      3. 3.6.3 Memory model
        1. 3.6.3.1 Private Peripheral Bus
        2. 3.6.3.2 Unaligned accesses
      4. 3.6.4 Processor core registers summary
      5. 3.6.5 Exceptions
        1. 3.6.5.1 Exception handling and prioritization
    7. 3.7 TrustZone-M
      1. 3.7.1 Overview
      2. 3.7.2 M33 Configuration
      3. 3.7.3 Description of elements
        1. 3.7.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 3.7.3.1.1 Expected use
    8. 3.8 CC35xx Host MCU Registers
      1. 3.8.1 HOSTMCU_AON Registers
      2. 3.8.2 HOST_MCU Registers
      3. 3.8.3 HOST_MCU_SEC Registers
    9. 3.9 Arm® Cortex®-M33 Registers
      1. 3.9.1  CPU_ROM_TABLE Registers
      2. 3.9.2  TPIU Registers
      3. 3.9.3  DCB Registers
      4. 3.9.4  DIB Registers
      5. 3.9.5  DWT Registers
      6. 3.9.6  FPB Registers
      7. 3.9.7  FPE Registers
      8. 3.9.8  ICB Registers
      9. 3.9.9  ITM Registers
      10. 3.9.10 MPU Registers
      11. 3.9.11 NVIC Registers
      12. 3.9.12 SAU Registers
      13. 3.9.13 SCB Registers
      14. 3.9.14 SYSTIMER Registers
      15. 3.9.15 SYSTICK Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation to HardFault
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Manager
      1. 5.4.1 Introduction
      2. 5.4.2 Interrupts List
      3. 5.4.3 Wakeup Sources
      4. 5.4.4 Shared Peripherals MUX Selector
        1. 5.4.4.1 ADC HW Event Selector Mux
        2. 5.4.4.2 I2S HW Event Selector Mux
        3. 5.4.4.3 PDM HW Event Selector Mux
      5. 5.4.5 Timers MUX Selector Mux
        1. 5.4.5.1 SysTimer0 HW Event Selector Mux
        2. 5.4.5.2 SysTimer1 HW Event Selector Mux
        3. 5.4.5.3 RTC HW Event Selector Mux
      6. 5.4.6 GPTIMERs MUX Selector Mux
        1. 5.4.6.1 GPTIMER0 HW Event Selector Mux
        2. 5.4.6.2 GPTIMER1 HW Event Selector Mux
    5. 5.5 SOC_IC Registers
    6. 5.6 SOC_AON Registers
    7. 5.7 SOC_AAON Registers
  7. 6 Debug Subsystem (DEBUGSS)
    1. 6.1 Introduction
    2. 6.2 Block Diagram
    3. 6.3 Overview
    4. 6.4 Physical Interface
    5. 6.5 Debug Access Ports
    6. 6.6 Debug Features
      1. 6.6.1 Processor Debug
      2. 6.6.2 Breakpoint Unit (BPU)
      3. 6.6.3 Peripheral Debug
    7. 6.7 Behavior in Low Power Modes
    8. 6.8 Debug Access Control
    9. 6.9 SOC_DEBUGSS Registers
  8. 7 Power, Reset, Clock Management
    1. 7.1 Power Management
      1. 7.1.1 Power Supply System
        1. 7.1.1.1 VDD_MAIN
        2. 7.1.1.2 VIO
        3. 7.1.1.3 VDDSF
        4. 7.1.1.4 VPA
      2. 7.1.2 Power States
      3. 7.1.3 Power Domains
      4. 7.1.4 Brownout (BOR)
      5. 7.1.5 Boot Sequence
    2. 7.2 Reset
      1. 7.2.1 Reset Cause
      2. 7.2.2 Watchdog Timer (WDT)
    3. 7.3 Clocks
      1. 7.3.1 Fast Clock
      2. 7.3.2 Slow Clock
        1. 7.3.2.1 Slow Clock Overview
        2. 7.3.2.2 Slow Clock Tree
        3. 7.3.2.3 Slow Clock Boot Process
    4. 7.4 PRCM_AON Registers
    5. 7.5 PRCM_SCRATCHPAD Registers
  9. 8 Memory Subsystem (MEMSS)
    1. 8.1  Introduction
    2. 8.2  SRAM
    3. 8.3  D-Cache
    4. 8.4  Flash
    5. 8.5  PSRAM
    6. 8.6  XiP Memory Access
      1. 8.6.1 OTFDE
      2. 8.6.2 xSPI
      3. 8.6.3 Topology
      4. 8.6.4 µDMA
      5. 8.6.5 Arbiter
    7. 8.7  ICACHE Registers
    8. 8.8  DCACHE Registers
    9. 8.9  OSPI Registers
    10. 8.10 HOST_XIP Registers
  10. 9 Hardware Security Module (HSM)
    1. 9.1 Introduction
    2. 9.2 Overview
    3. 9.3 Mailbox and Register Access Firewall
    4. 9.4 DMA Firewall
    5. 9.5 HSM Key Storage
    6. 9.6 HSM Registers
    7. 9.7 HSM_NON_SEC Registers
    8. 9.8 HSM_SEC Registers
  11. 10Device Boot and Bootloader
    1. 10.1 CC35xx Boot Concept
    2. 10.2 Features
    3. 10.3 Vendor Images Format and Processing
      1. 10.3.1 External Flash Arrangement
      2. 10.3.2 Vendor Images Format
    4. 10.4 Boot Flows
      1. 10.4.1 Application Execution Boot Flow
      2. 10.4.2 Activation Flow
      3. 10.4.3 Initial Programming Flow
      4. 10.4.4 Reprogramming Flow
      5. 10.4.5 Wireless Connectivity Testing Tool Flow
    5. 10.5 Chain of Trust
  12. 11Direct Memory Access (DMA)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Channels Assignment
      2. 11.3.2 Transfer Types
      3. 11.3.3 Addressing Modes
      4. 11.3.4 Transfer Modes
      5. 11.3.5 DMA Aligner Support
      6. 11.3.6 Initiating DMA Transfers
      7. 11.3.7 Stopping DMA Transfers
      8. 11.3.8 Channel Priorities
      9. 11.3.9 DMA Interrupts
    4. 11.4 HOST_DMA Registers
  13. 12One Time Programming (OTP)
  14. 13General Purpose Timers (GPT)
    1. 13.1 Overview
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1  Prescaler
      2. 13.3.2  Counter
      3. 13.3.3  Target
      4. 13.3.4  Channel Input Logic
      5. 13.3.5  Channel Output Logic
      6. 13.3.6  Channel Actions
        1. 13.3.6.1 Period and Pulse Width Measurement
        2. 13.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 13.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 13.3.7  Channel Capture Configuration
      8. 13.3.8  Channel Filters
        1. 13.3.8.1 Setting up the Channel Filters
      9. 13.3.9  Synchronize Multiple GPTimers
      10. 13.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 13.4 Timer Modes
      1. 13.4.1 Quadrature Decoder
      2. 13.4.2 DMA
      3. 13.4.3 IR Generation
      4. 13.4.4 Fault and Park
      5. 13.4.5 Dead-Band
      6. 13.4.6 Dead-Band, Fault and Park
      7. 13.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 13.5 GPTIMER Registers
  15. 14System Timer (SysTimer)
    1. 14.1 Overview
    2. 14.2 Block Diagram
    3. 14.3 Functional Description
      1. 14.3.1 Common Channel Features
        1. 14.3.1.1 Compare Mode
        2. 14.3.1.2 Capture Mode
        3. 14.3.1.3 Additional Channel Arming Methods
      2. 14.3.2 Interrupts and Events
    4. 14.4 SYSRESOURCES Registers
    5. 14.5 SYSTIM Registers
  16. 15Real-Time Clock (RTC)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Interrupts and Events
      1. 15.3.1 Input Event
      2. 15.3.2 Output Event
      3. 15.3.3 Arming and Disarming Channels
    4. 15.4 CAPTURE and COMPARE Configurations
      1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
    5. 15.5 RTC Registers
  17. 16General Purpose Input/Output (GPIOs)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 I/O Mapping and Configuration
      1. 16.3.1 Basic I/O Mapping
      2. 16.3.2 Pin Mapping
    4. 16.4 Edge Detection
    5. 16.5 GPIO
    6. 16.6 I/O Pins
    7. 16.7 Unused Pins
    8. 16.8 IOMUX Registers
  18. 17Universal Asynchronous Receivers/Transmitters (UART)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 UART Functional Description
      1. 17.3.1 Transmit and Receive Logic
      2. 17.3.2 Baud Rate Generation
      3. 17.3.3 FIFO Operation
        1. 17.3.3.1 FIFO Remapping
      4. 17.3.4 Data Transmission
      5. 17.3.5 Flow Control
      6. 17.3.6 IrDA Encoding and Decoding
      7. 17.3.7 Interrupts
      8. 17.3.8 Loopback Operation
    4. 17.4 UART-LIN Specification
      1. 17.4.1 Break transmission in UART mode
      2. 17.4.2 Break reception in UART mode
      3. 17.4.3 Break/Synch transmission in LIN mode
      4. 17.4.4 Break/Synch reception in LIN mode
      5. 17.4.5 Dormant mode operation
      6. 17.4.6 Event signal generation
      7. 17.4.7 Event signal detection when device is in active/idle modes
      8. 17.4.8 Event signal detection when device is in sleep mode
    5. 17.5 Interface to Host DMA
    6. 17.6 Initialization and Configuration
    7. 17.7 UART Registers
  19. 18Serial Peripheral Interface (SPI)
    1. 18.1 Overview
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Signal Description
    3. 18.3 Functional Description
      1. 18.3.1  Clock Control
      2. 18.3.2  FIFO Operation
        1. 18.3.2.1 Transmit FIFO
        2. 18.3.2.2 Repeated Transmit Operation
        3. 18.3.2.3 Receive FIFO
        4. 18.3.2.4 FIFO Flush
      3. 18.3.3  Interrupts
      4. 18.3.4  Data Format
      5. 18.3.5  Delayed Data Sampling
      6. 18.3.6  Chip Select Control
      7. 18.3.7  Command Data Control
      8. 18.3.8  Protocol Descriptions
        1. 18.3.8.1 Motorola SPI Frame Format
        2. 18.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 18.3.8.3 MICROWIRE Frame Format
      9. 18.3.9  CRC Configuration
      10. 18.3.10 Auto CRC Functionality
      11. 18.3.11 SPI Status
      12. 18.3.12 Debug Halt
    4. 18.4 Host DMA Operation
    5. 18.5 Initialization and Configuration
    6. 18.6 SPI Registers
  20. 19Inter-Integrated Circuit (I2C) Interface
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Clock Control
        1. 19.3.1.1 Internal Clock
        2. 19.3.1.2 External Clock
      2. 19.3.2 General Architecture
        1. 19.3.2.1  Start and Stop Conditions
        2. 19.3.2.2  Data Format with 7-Bit Address
        3. 19.3.2.3  Data Format with 10-Bit Addressing
          1. 19.3.2.3.1 Additional 10-Bit Scenarios
        4. 19.3.2.4  Acknowledge
        5. 19.3.2.5  Repeated Start
        6. 19.3.2.6  Clock Stretching
        7. 19.3.2.7  Arbitration
        8. 19.3.2.8  Multi-Controller mode
        9. 19.3.2.9  Glitch Suppression
        10. 19.3.2.10 FIFO Operation
        11. 19.3.2.11 Burst Mode Operation
        12. 19.3.2.12 DMA Operation
        13. 19.3.2.13 Flush Stale Tx Data in Target Mode
          1. 19.3.2.13.1 Recommended Sequence
        14. 19.3.2.14 SMBUS 3.0 Support
          1. 19.3.2.14.1 Quick Command
          2. 19.3.2.14.2 Acknowledge Control
          3. 19.3.2.14.3 Alert Response protocol
          4. 19.3.2.14.4 Address Resolution Protocol
          5. 19.3.2.14.5 Enhanced Acknowledge Control
    4. 19.4 Initialization and Configuration
    5. 19.5 Interrupts
    6. 19.6 I2C Registers
  21. 20Secure Digital Multimedia Card (SDMMC)
    1. 20.1 Introduction
      1. 20.1.1 SDMMC Features
      2. 20.1.2 Integration
    2. 20.2 Functional Description
      1. 20.2.1  SDMMC Functional Modes
        1. 20.2.1.1 SDMMC Connected to an SD Card
        2. 20.2.1.2 Protocol and Data Format
          1. 20.2.1.2.1 Protocol
          2. 20.2.1.2.2 Data Format
      2. 20.2.2  SD Card Feedback
      3. 20.2.3  Resets
        1. 20.2.3.1 Hardware Reset
        2. 20.2.3.2 Software Reset
      4. 20.2.4  Interrupt Requests
        1. 20.2.4.1 Interrupt-Driven Operation
        2. 20.2.4.2 Polling
      5. 20.2.5  DMA Modes
        1. 20.2.5.1 DMA Peripheral Mode Operations
          1. 20.2.5.1.1 DMA Receive Mode
          2. 20.2.5.1.2 DMA Transmit Mode
      6. 20.2.6  Buffer Management
        1. 20.2.6.1 Data Buffer
          1. 20.2.6.1.1 Memory Size and Block Length
          2. 20.2.6.1.2 Data Buffer Status
      7. 20.2.7  Transfer Process
        1. 20.2.7.1 Different Types of Commands
        2. 20.2.7.2 Different Types of Responses
      8. 20.2.8  Transfer or Command Status and Error Reporting
        1. 20.2.8.1 Busy Timeout for R1b, R5b Response Type
        2. 20.2.8.2 Busy Timeout After Write CRC Status
        3. 20.2.8.3 Write CRC Status Timeout
        4. 20.2.8.4 Read Data Timeout
      9. 20.2.9  Auto Command 12 Timings
        1. 20.2.9.1 Auto Command 12 Timings During Write Transfer
        2. 20.2.9.2 Auto Command 12 Timings During Read Transfer
      10. 20.2.10 Transfer Stop
      11. 20.2.11 Output Signals Generation
        1. 20.2.11.1 Generation on Falling Edge of SDMMC Clock
        2. 20.2.11.2 Generation on Rising Edge of SDMMC Clock
      12. 20.2.12 Test Registers
      13. 20.2.13 SDMMC Hardware Status Features
    3. 20.3 Low-Level Programming Models
      1. 20.3.1 SDMMC Initialization Flow
        1. 20.3.1.1 Enable OCP and CLKADPI Clocks
        2. 20.3.1.2 SD Soft Reset Flow
        3. 20.3.1.3 Set SD Default Capabilities
        4. 20.3.1.4 SDMMC Host and Bus Configuration
      2. 20.3.2 Operational Modes Configuration
        1. 20.3.2.1 Basic Operations for SDMMC
        2. 20.3.2.2 Card Detection, Identification, and Selection
    4. 20.4 SDMMC Registers
  22. 21Secure Digital Input/Output (SDIO)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 SDIO Interface Description
      2. 21.3.2 Protocol and Data Format
      3. 21.3.3 I/O Read/Write Command
        1. 21.3.3.1 IO_WR_DIRECT Command (CMD52)
        2. 21.3.3.2 IO_WR_EXTENDED Command (CMD53)
      4. 21.3.4 Reset
      5. 21.3.5 FIFO Operation
        1. 21.3.5.1 Rx FIFO (For Host Write)
        2. 21.3.5.2 Tx FIFO (For Host Read)
      6. 21.3.6 Interrupt Request
        1. 21.3.6.1 External Host IRQ
        2. 21.3.6.2 M33 IRQ
      7. 21.3.7 Transaction Details
        1. 21.3.7.1 Host write to SDIO IP (Rx FIFO)
          1. 21.3.7.1.1 Host write to SDIO IP (Rx FIFO) – Long SW latency case
          2. 21.3.7.1.2 Host write to SDIO IP (Rx FIFO) – CRC Error Case
        2. 21.3.7.2 Host reads from SDIO (TX buffer)
    4. 21.4 SDIO_CORE Registers
    5. 21.5 SDIO_CARD_FN1 Registers
  23. 22Inter-Integrated Circuit Sound (I2S)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  Signal Descriptions
    4. 22.4  Functional Description
      1. 22.4.1 Pin Configuration
      2. 22.4.2 Serial Format Configuration
        1. 22.4.2.1 Register Configuration
      3. 22.4.3 Left-Justified (LJF)
        1. 22.4.3.1 Register Configuration
      4. 22.4.4 Right-Justified (RJF)
        1. 22.4.4.1 Register Configuration
      5. 22.4.5 DSP
        1. 22.4.5.1 Register Configuration
      6. 22.4.6 Clock Configuration
    5. 22.5  Memory Interface
      1. 22.5.1 Sample Word Length
      2. 22.5.2 Padding Mechanism
      3. 22.5.3 Channel Mapping
      4. 22.5.4 Sample Storage in Memory
      5. 22.5.5 DMA Operation
        1. 22.5.5.1 Start-Up
        2. 22.5.5.2 Operation
        3. 22.5.5.3 Shutdown
    6. 22.6  Samplestamp Generator
      1. 22.6.1 Samplestamp Counters
      2. 22.6.2 Start-Up Triggers
      3. 22.6.3 Samplestamp Capture
      4. 22.6.4 Achieving constant audio latency
    7. 22.7  Error Detection
    8. 22.8  Usage
      1. 22.8.1 Start-Up Sequence
      2. 22.8.2 Shutdown Sequence
    9. 22.9  I2S Configuration Guideline
    10. 22.10 I2S Registers
  24. 23Pulse Density Modulation (PDM)
    1. 23.1  Introduction
    2. 23.2  Block Diagram
    3. 23.3  Input Selection
      1. 23.3.1 PDM Data Mode
      2. 23.3.2 Manchester Input Mode
    4. 23.4  CIC Filter
      1. 23.4.1 Filter Design
      2. 23.4.2 Digital Filter Output
      3. 23.4.3 Offset Binary Mode
      4. 23.4.4 Twos-Complement Mode
    5. 23.5  FIFO Organization in Different Modes
      1. 23.5.1 Single Mono Microphone Configuration
        1. 23.5.1.1 24-bit Sample Size
          1. 23.5.1.1.1 32-bit Data Read
        2. 23.5.1.2 16-bit Sample Size
          1. 23.5.1.2.1 32-bit Data Read
          2. 23.5.1.2.2 16-bit Data Read
        3. 23.5.1.3 8-bit Sample Size
          1. 23.5.1.3.1 32-bit Data Read
          2. 23.5.1.3.2 16-bit Data Read
          3. 23.5.1.3.3 8-bit Data Read
      2. 23.5.2 Stereo or Dual Mono Microphone Configuration
        1. 23.5.2.1 24-bit Sample Size
          1. 23.5.2.1.1 32-bit Data Read
        2. 23.5.2.2 16-bit Sample Size
          1. 23.5.2.2.1 32-bit Data Read
          2. 23.5.2.2.2 16-bit Data Read
        3. 23.5.2.3 8-bit Sample Size
          1. 23.5.2.3.1 32-bit Data Read
          2. 23.5.2.3.2 16-bit Data Read
          3. 23.5.2.3.3 8-bit Data Read
      3. 23.5.3 FIFO Threshold Setting
      4. 23.5.4 Reset FIFO
    6. 23.6  Automatic Gain Control (AGC)
      1. 23.6.1 Operation in 2's Complement Format
      2. 23.6.2 Operation in Offset Binary Format
    7. 23.7  Interrupts
    8. 23.8  Clock Select and Control
    9. 23.9  DMA Operation
    10. 23.10 Samplestamp Generator
      1. 23.10.1 Samplestamp Counters
      2. 23.10.2 Start-Up Triggers
      3. 23.10.3 Samplestamp Capture
      4. 23.10.4 Achieving Constant Audio Latency
    11. 23.11 Debug‑Mode Flag Behavior
    12. 23.12 Software Guidelines
    13. 23.13 PDM Registers
  25. 24Analog to Digital Converter (ADC)
    1. 24.1 Overview
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1  ADC Core
      2. 24.3.2  Voltage Reference Options
      3. 24.3.3  Internal Channels
      4. 24.3.4  Resolution Modes
      5. 24.3.5  ADC Clocking
      6. 24.3.6  Power Down Behavior
      7. 24.3.7  Sampling Trigger Sources and Sampling Modes
        1. 24.3.7.1 AUTO Sampling Mode
        2. 24.3.7.2 MANUAL Sampling Mode
      8. 24.3.8  Sampling Period
      9. 24.3.9  Conversion Modes
      10. 24.3.10 ADC Data Format
      11. 24.3.11 Status Register
      12. 24.3.12 ADC Events
        1. 24.3.12.1 Generic Event Publishers (INT_EVENT0 & INT_EVENT1)
        2. 24.3.12.2 DMA Trigger Event Publisher (INT_EVENT2)
        3. 24.3.12.3 Generic Event Subscriber
      13. 24.3.13 Advanced Features
        1. 24.3.13.1 Window Comparator
        2. 24.3.13.2 DMA & FIFO Operation
          1. 24.3.13.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
          2. 24.3.13.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
          3. 24.3.13.2.3 DMA/CPU Operation Summary Matrix
        3. 24.3.13.3 Ad-hoc Single Conversion
    4. 24.4 ADC Registers
  26. 25Controller Area Network (CAN)
    1. 25.1 Introduction
    2. 25.2 Functions
    3. 25.3 DCAN Subsystem
    4. 25.4 DCAN Functional Description
      1. 25.4.1 Operating Modes
        1. 25.4.1.1 Software Initialization
        2. 25.4.1.2 Normal Operation
        3. 25.4.1.3 Restricted Operation Mode
        4. 25.4.1.4 Bus Monitoring Mode
        5. 25.4.1.5 Disabled Automatic Retransmission
          1. 25.4.1.5.1 Frame Transmission in DAR Mode
        6. 25.4.1.6 Power Down (Sleep Mode)
          1. 25.4.1.6.1 DCAN clock stop and wake operations
          2. 25.4.1.6.2 DCAN debug suspend operation
        7. 25.4.1.7 Test Modes
          1. 25.4.1.7.1 External Loop Back Mode
          2. 25.4.1.7.2 Internal Loop Back Mode
      2. 25.4.2 Timestamp Generation
        1. 25.4.2.1 Block Diagram
      3. 25.4.3 Timeout Counter
      4. 25.4.4 Rx Handling
        1. 25.4.4.1 Acceptance Filtering
          1. 25.4.4.1.1 Range Filter
          2. 25.4.4.1.2 Filter for specific IDs
          3. 25.4.4.1.3 Classic Bit Mask Filter
          4. 25.4.4.1.4 Standard Message ID Filtering
          5. 25.4.4.1.5 Extended Message ID Filtering
        2. 25.4.4.2 Rx FIFOs
          1. 25.4.4.2.1 Rx FIFO Blocking Mode
          2. 25.4.4.2.2 Rx FIFO Overwrite Mode
        3. 25.4.4.3 Dedicated Rx Buffers
          1. 25.4.4.3.1 Rx Buffer Handling
        4. 25.4.4.4 Debug on CAN Support
          1. 25.4.4.4.1 Filtering for Debug Messages
          2. 25.4.4.4.2 Debug Message Handling
      5. 25.4.5 Tx Handling
        1. 25.4.5.1 Transmit Pause
        2. 25.4.5.2 Dedicated Tx Buffers
        3. 25.4.5.3 Tx FIFO
        4. 25.4.5.4 Tx Queue
        5. 25.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 25.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 25.4.5.7 Transmit Cancellation
        8. 25.4.5.8 Tx Event Handling
      6. 25.4.6 FIFO Acknowledge Handling
      7. 25.4.7 DCAN Message RAM
        1. 25.4.7.1 Message RAM Configuration
        2. 25.4.7.2 Rx Buffer and FIFO Element
        3. 25.4.7.3 Tx Buffer Element
        4. 25.4.7.4 Tx Event FIFO Element
        5. 25.4.7.5 Standard Message ID Filter Element
        6. 25.4.7.6 Extended Message ID Filter Element
      8. 25.4.8 Interrupt Requests
    5. 25.5 DCAN Wrapper
    6. 25.6 DCAN Clock Enable
    7. 25.7 DCAN Registers
  27. 26Revision History

23.13 PDM Registers

Table 23-3 lists the memory-mapped registers for the PDM registers. All register offset addresses not listed in Table 23-3 should be considered as reserved locations and the register contents should not be modified.

Table 23-3 PDM Registers
OffsetAcronymRegister NameSection
0hDESCModule IdentitySection 23.13.1
4hDESCEXModule Configuration DetailsSection 23.13.2
44hIMASKInterrupt MaskSection 23.13.3
48hRISUnmasked Interrupt StatusSection 23.13.4
4ChMISMasked Interrupt StatusSection 23.13.5
50hISETInterrupt SetSection 23.13.6
54hICLRInterrupt clearSection 23.13.7
60hEMUDebug ControlSection 23.13.8
100hCTLPDM ControlSection 23.13.9
104hICLKCTLInput Clock ControlSection 23.13.10
108hFIFOCTL1FIFO Control 1Section 23.13.11
10ChFIFODATAFIFO DataSection 23.13.12
110hCCTLChannel ControlSection 23.13.13
114hOSROversampling ControlSection 23.13.14
118hSTAStatus RegisterSection 23.13.15
120hFIFOCTL2FIFO ControlSection 23.13.16
124hFIFOSRFIFO StatusSection 23.13.17
200hAVGVAL0Channel 0 AverageSection 23.13.18
204hPKVAL0Peak sample value for channel-0Section 23.13.19
208hAVGPOW0Average Power MeasurementSection 23.13.20
20ChAVGVAL1Channel-1 Average ValueSection 23.13.21
210hPKVAL1Peak ValueSection 23.13.22
214hAVGPOW1Channel 1 PowerSection 23.13.23
300hSTPCTLTimestamp ControlSection 23.13.24
304hSTPXCAPTReference Clock CaptureSection 23.13.25
308hSTPXPERReference Clock PeriodSection 23.13.26
30ChSTPSCAPTCaptured Ch 0 Sample Clock Counter ValueSection 23.13.27
310hSTPSPERSample Clock PeriodSection 23.13.28
314hSTPINTRGInput Pin Trigger ValueSection 23.13.29
318hSTPSSETCounter Set OperationSection 23.13.30
31ChSTPSADDStep Width AddSection 23.13.31
320hSTPXMINReference Clock MinimumSection 23.13.32
324hSTPWCNTSample Timer CountSection 23.13.33
328hSTPXCNTX-Position CounterSection 23.13.34
32ChSTPSTATTimestamp StatusSection 23.13.35
1000hCLKCFGClock ConfigurationSection 23.13.36
1004hADFSCTL1Antenna Diversity ControlSection 23.13.37
1008hADFSCTL2Adaptive Filter ControlSection 23.13.38

Complex bit access types are encoded to fit into small table cells. Table 23-4 shows the codes that are used for access types in this section.

Table 23-4 PDM Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
WmodifyW
modify		Write
Reset or Default Value
-nValue after reset or the default value

23.13.1 DESC Register (Offset = 0h) [Reset = 00000000h]

DESC is shown in Table 23-5.

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Description Register This register identifies the peripheral and its exact version.

Table 23-5 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR3342hModule identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
  • 0h = Smallest value
  • FFFFh = Highest possible value
15-12STDIPOFFR1hStandard IP offset 64 Bit standard IP MMR block (beginning with aggregated IRQ registers) 0: STDIP MMRs do not exist 1:15: These MMRs begin at offset 64*STDIPOFF from IP base address
  • 0h = Smallest value
  • Fh = Highest possible value
11-8INSTIDXR0hInstance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
  • 0h = Smallest value
  • Fh = Highest possible value
7-4MAJREVR1hMajor revision of the IP
  • 0h = Smallest value
  • Fh = Highest possible value
3-0MINREVR0hMinor revision of the IP
  • 0h = Smallest value
  • Fh = Highest possible value

23.13.2 DESCEX Register (Offset = 4h) [Reset = 00000000h]

DESCEX is shown in Table 23-6.

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This register reflects the configuration of this peripheral instance

Table 23-6 DESCEX Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0NUMCHANR0hNumber of available PDM Channels. Value 1 indicates two channels that can be used for stereo or dual mono microphone connections.
  • 0h = Smallest value
  • 7h = Highest possible value

23.13.3 IMASK Register (Offset = 44h) [Reset = 00000000h]

IMASK is shown in Table 23-7.

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Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in MIS.

Table 23-7 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9DMADONER/W0hDMA Done event mask.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
8STPTRIGR/W0hSamplestamp Trigger event mask
  • 0h = Clear Interrupt Mask
  • 1h = Interrrupt Enable
7UNFLR/W0hData Underflow event mask.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
6OVFLR/W0hData Overflow event mask.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
5-1RESERVEDR0hReserved
0PDMDATAR/W0h*PDM* data event mask
  • 0h = Interrupt disable
  • 1h = Interrupt Enable

23.13.4 RIS Register (Offset = 48h) [Reset = 00000000h]

RIS is shown in Table 23-8.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Table 23-8 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9DMADONER0hDMA Done event.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
8STPTRIGR0hSamplestamp Trigger event
  • 0h = Interrupt did not occur
  • 1h = Interrrupt Enable
7UNFLR0hData Underflow event. Data has been read from an emty FIFO. This flag gets set if one of the channel UNDERFLOW flags gets set.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
6OVFLR0hData Overflow event. Data has been written to the buffer before the previous values was read. This flag gets set if one of the channel OVERFLOW flags gets set
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
5-1RESERVEDR0hReserved
0PDMDATAR0hPDM DATA event
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable

23.13.5 MIS Register (Offset = 4Ch) [Reset = 00000000h]

MIS is shown in Table 23-9.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Table 23-9 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9DMADONER0hMasked DMA Done event.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
8STPTRIGR0hMasked Samplestamp Trigger event.
  • 0h = Interrupt did not occur
  • 1h = Interrrupt Enable
7UNFLR0hMasked Data Underflow event.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
6OVFLR0hMasked Data Overflow event.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
5-1RESERVEDR0hReserved
0PDMDATAR0hMasked PDMDATA event
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable

23.13.6 ISET Register (Offset = 50h) [Reset = 00000000h]

ISET is shown in Table 23-10.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Table 23-10 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9DMADONEW0hSet DMA Done event.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
8STPTRIGW0hSet Samplestamp Trigger event.
  • 0h = Writing 0 has no effect
  • 1h = Interrrupt Enable
7UNFLW0hSet Data Underflow event.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
6OVFLW0hSet Data Overflow event.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
5-1RESERVEDR0hReserved
0PDMDATAW0hSet PDMDATA event.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable

23.13.7 ICLR Register (Offset = 54h) [Reset = 00000000h]

ICLR is shown in Table 23-11.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 23-11 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9DMADONEW0hClear DMA Done event.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
8STPTRIGW0hClear Samplestamp Trigger event.
  • 0h = Writing 0 has no effect
  • 1h = Interrrupt Enable
7UNFLW0hClear Data Underflow event.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
6OVFLW0hClear Data Overflow event.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable
5-1RESERVEDR0hReserved
0PDMDATAW0hClear PDMDATA event.
  • 0h = Interrupt disable
  • 1h = Interrrupt Enable

23.13.8 EMU Register (Offset = 60h) [Reset = 00000000h]

EMU is shown in Table 23-12.

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This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input

Table 23-12 EMU Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0HALTR/W0hFree run control
  • 0h = The peripheral ignores the state of the Core Halted input
  • 1h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.

23.13.9 CTL Register (Offset = 100h) [Reset = 00000000h]

CTL is shown in Table 23-13.

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PDM control register

Table 23-13 CTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENPDMR/W0hEnable conversion on *PDM*
  • 0h = Disable Channel
  • 1h = Enable Channel

23.13.10 ICLKCTL Register (Offset = 104h) [Reset = 00000000h]

ICLKCTL is shown in Table 23-14.

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Input clock Control Register

Table 23-14 ICLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16BCLKENR/W0hThis bit is used to enable BCLK to Sigma-Delta Modulator on-chip.
  • 0h = BCLK is disabled
  • 1h = BCLK is enabled
15-10RESERVEDR0hReserved
9-0IDIVR/W0hDivider for ICLK iclk = PLLCLK/(ICLK +1)
  • 0h = Minimum value of BDIV
  • 3FFh = Maximum value of BDIV

23.13.11 FIFOCTL1 Register (Offset = 108h) [Reset = 00000000h]

FIFOCTL1 is shown in Table 23-15.

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PDM FIFO control register

Table 23-15 FIFOCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1ENFIFO1R/W0hEnable FIFO1 for DMA access through the FIFODATA Register
  • 0h = Disable Channel
  • 1h = Enable Channel
0ENFIFO0R/W0hEnable FIFO0 for DMA access through the FIFODATA Register
  • 0h = Disable Channel
  • 1h = Enable Channel

23.13.12 FIFODATA Register (Offset = 10Ch) [Reset = 00000000h]

FIFODATA is shown in Table 23-16.

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*FIFO* Data Register (FIFO read) This register provides the Data of the FIFO based on [FIFOCTL.ENFIFO0] and [FIFOCTL.ENFIFO1] This allows the DMA to just have single address to read all the FIFO content when triggered.

Table 23-16 FIFODATA Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER0hFIFO Read Register
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

23.13.13 CCTL Register (Offset = 110h) [Reset = 00700000h]

CCTL is shown in Table 23-17.

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PDM Channel control register

Table 23-17 CCTL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30-29CH1IPSELR/Wmodify0hChannel 1 Data Input Select
  • 0h = Data pin 0 selected as source for channel 1.
  • 1h = Data pin 1 selected as source for channel 1.
  • 2h = SDM output selected as source for channel 1.
  • 3h = Data pin 0 selected as source for channel 1.
28CH1CLKEGR/W0hSelect the clock edge for data channel 1
  • 0h = Rising edge is selected
  • 1h = Failing edge is selected
27RESERVEDR0hReserved
26-25CH0IPSELR/W0hChannel 0 Data Input Select
  • 0h = Data pin 0 selected as source for channel 0.
  • 1h = Data pin 1 selected as source for channel 0.
  • 2h = SDM output selected as source for channel 0.
  • 3h = Data pin 0 selected as source for channel 0.
24CH0CLKEGR/W0hSelect the clock edge for data channel 0
  • 0h = Rising edge is selected
  • 1h = Failing edge is selected
23RESERVEDR0hReserved
22-20SELSCALER/W7hSelect scaling factor for the averaging blocks. Selscale value used internally is 1/(23+VALUE) Ex: When value is 0, selscale is 1/8, and when value is 7, selscale is 1/1024
  • 0h = Scaling factor is 1/8
  • 1h = Scaling factor is 1/16
  • 2h = Scaling factor is 1/32
  • 3h = Scaling factor is 1/64
  • 4h = Scaling factor is 1/128
  • 5h = Scaling factor is 1/256
  • 6h = Scaling factor is 1/512
  • 7h = Scaling factor is 1/1024
19ENPOWCH1R/W0hEnables average power calculation for channel-1
  • 0h = Enables average power calculation for channel-1
  • 1h = Enables average power calculation for channel-1
18ENPOWCH0R/W0hEnables average power calculation for channel-0
  • 0h = Disables average power calculation for channel-0
  • 1h = Enables average power calculation for channel-0
17ENPKCH1R/W0hEnables peak value detection for channel-0
  • 0h = Enables peak value detection for channel-1
  • 1h = Enables peak value detection for channel-1
16ENPKCH0R/W0hEnables peak value detection for channel-0
  • 0h = Disables peak value detection for channel-0
  • 1h = Enables peak value detection for channel-0
15-12RESERVEDR0hReserved
11DATAFMTR/W0hData Format
  • 0h = Offset binary
  • 1h = Twos complement
10ALIGNR/W0hData alignment
  • 0h = Right-aligned. LSB of filter output is bit 0.
  • 1h = Left-aligned. MSB of filter output (depending on OSR) is bit 31.
9-8DFSR/W0hDigital Filter Select
  • 0h = SINC1 filter
  • 1h = SINC2 filter
  • 2h = SINC3 filter
  • 3h = SINC4 filter
7-3RESERVEDR0hReserved
2-0CHENR/W0hData Input Configuration
  • 0h = Both Channels are disabled.
  • 1h = Input channel 0 is enabled.
  • 2h = Input channel 1 is enabled.
  • 4h = Input from Manchester Decoder, also enables Manchester Coding of bitstream. CH0 is enabled by default as the operation and CH1 enable bit is discarded.

23.13.14 OSR Register (Offset = 114h) [Reset = 0000003Fh]

OSR is shown in Table 23-18.

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Oversampling Control Register

Table 23-18 OSR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0VALUER/W3FhOversampling rate. The oversampling rate is defined as OSRx + 1. Applicable oversampling rates are 2 to 256. Default is 64.
  • 1h = Smallest value
  • FFh = Highest possible value

23.13.15 STA Register (Offset = 118h) [Reset = 00000000h]

STA is shown in Table 23-19.

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PDM control register

Table 23-19 STA Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17MANCLKR0hManchester Clock status. Indicates that Manchester mode is in locked mode or not.
  • 0h = Manchester clock not locked.
  • 1h = Manchester clock locked.
16-1RESERVEDR0hReserved
0AGCRDYR1h*AGC* accelerator ready status. Software must read AGCVALx, PKVALx and AVGPOWx registers only when AGCRDY is '1'. Reading these registers while AGCRDY is 0 may provide incorrect values.
  • 0h = Not ready
  • 1h = Ready

23.13.16 FIFOCTL2 Register (Offset = 120h) [Reset = 00000000h]

FIFOCTL2 is shown in Table 23-20.

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FIFO Control

Table 23-20 FIFOCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7FIFOFLSHR/W0hFIFO Flush Setting this bit will Flush the FIFO. This bit will self-clear when the flush has completed.
  • 0h = Do not Flush FIFO
  • 1h = Flush FIFO
6-4RESERVEDR0hReserved
3-0TRGLVLR/W0hFIFO Trigger Level Select Sets the trigger points for the FIFO events. Note: FIFO depth is only 2 the level 1/4 and 3/4 default to 1/2.
  • 0h = Trigger when RX FIFO contains >= 1 byte
  • 1h = Trigger when RX FIFO contains >= 2 byte
  • 2h = Trigger when RX FIFO contains >= 3 byte
  • 3h = Trigger when RX FIFO contains >= 4 byte
  • 4h = Trigger when RX FIFO contains >= 5 byte
  • 5h = Trigger when RX FIFO contains >= 6 byte
  • 6h = Trigger when RX FIFO contains >= 7 byte
  • 7h = Trigger when RX FIFO contains >= 8 byte
  • 8h = Trigger when RX FIFO contains >= 9 byte
  • 9h = Trigger when RX FIFO contains >= 10 byte
  • Ah = Trigger when RX FIFO contains >= 11 byte
  • Bh = Trigger when RX FIFO contains >= 12 byte

23.13.17 FIFOSR Register (Offset = 124h) [Reset = 00000000h]

FIFOSR is shown in Table 23-21.

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FIFO Status Register.

Table 23-21 FIFOSR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15CH1FFULLR0hCH1 FIFO Full
  • 0h = The transmitter is not full.
  • 1h = If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
14CH1FEMPR1hCH1 FIFO Empty
  • 0h = The transmitter has data to transmit.
  • 1h = If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.
13-12RESERVEDR0hReserved
11-8CH1FCNTR0hNumber of Bytes which could be read from the CH1 FIFO
  • 0h = Smallest value
  • Fh = Highest possible value
7CH0FFULLR0hCH0 FIFO Full
  • 0h = The receiver can receive data.
  • 1h = If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full.
6CH0FEMPR1hCH0 FIFO Empty
  • 0h = The receiver is not empty.
  • 1h = If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty.
5-4RESERVEDR0hReserved
3-0CH0FCNTR0hNumber of Bytes which could be read from the CH0 FIFO
  • 0h = Smallest value
  • Fh = Highest possible value

23.13.18 AVGVAL0 Register (Offset = 200h) [Reset = 00000000h]

AVGVAL0 is shown in Table 23-22.

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Average sample value for channel-0, 32-bit register.

Table 23-22 AVGVAL0 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER0hAverage sample value for channel-0
  • 0h = Minimum value of register
  • FFFFFFFFh = Highest value

23.13.19 PKVAL0 Register (Offset = 204h) [Reset = 00000000h]

PKVAL0 is shown in Table 23-23.

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Peak sample value for channel-0

Table 23-23 PKVAL0 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0VALUER0hPeak sample value for channel-0. Bits [22:0] applicable for operation in 2's complement format and bits [23:0] applicable for operation in offset binary format.
  • 0h = Smallest value
  • 007FFFFFh = Largest value

23.13.20 AVGPOW0 Register (Offset = 208h) [Reset = 00000000h]

AVGPOW0 is shown in Table 23-24.

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Average sample power for channel-0

Table 23-24 AVGPOW0 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER0hAverage sample power for channel-0
  • 0h = Smallest value
  • FFFFFFFFh = Highest value

23.13.21 AVGVAL1 Register (Offset = 20Ch) [Reset = 00000000h]

AVGVAL1 is shown in Table 23-25.

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Average sample value for channel-1, 32-bit register.

Table 23-25 AVGVAL1 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER0hAverage sample value for channel-1
  • 0h = Minimum value of register
  • FFFFFFFFh = Highest value

23.13.22 PKVAL1 Register (Offset = 210h) [Reset = 00000000h]

PKVAL1 is shown in Table 23-26.

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Peak sample value for channel-1

Table 23-26 PKVAL1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0VALUER0hPeak sample value for channel-1. Bits [22:0] applicable for operation in 2's complement format and bits [23:0] applicable for operation in offset binary format.
  • 0h = Smallest value
  • 007FFFFFh = Largest value

23.13.23 AVGPOW1 Register (Offset = 214h) [Reset = 00000000h]

AVGPOW1 is shown in Table 23-27.

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Average sample power for channel-1

Table 23-27 AVGPOW1 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER0hAverage sample power for channel-1
  • 0h = Smallest value
  • FFFFFFFFh = Highest value

23.13.24 STPCTL Register (Offset = 300h) [Reset = 00000000h]

STPCTL is shown in Table 23-28.

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Samplestamp Generator Control Register

Table 23-28 STPCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0STPENR/W0hEnables the samplestamp generator. The samplestamp generator must only be enabled after it has been properly configured.;When cleared, all samplestamp generator counters and capture values are cleared.
  • 0h = Disable the samplestamp generator
  • 1h = Enable the samplestamp generator

23.13.25 STPXCAPT Register (Offset = 304h) [Reset = 00000000h]

STPXCAPT is shown in Table 23-29.

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Captured REFCLK Counter Value, Capture Channel 0

Table 23-29 STPXCAPT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CAPTVALR0hThe value of the samplestamp XOSC counter [STMPXCNT.CURR_VALUE] last time an event was pulsed. The value is cleared when [STMPCTL.STMP_EN] = 0. Note: When calculating the fractional part of the sample stamp, [STMPXPER] may be less than this bit field.
  • 0h = Smallest value
  • FFFFh = Highest possible value

23.13.26 STPXPER Register (Offset = 308h) [Reset = 00000000h]

STPXPER is shown in Table 23-30.

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REFCLK Period Value

Table 23-30 STPXPER Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUER0hThe number of REFCLK clock cycles in the previous Sample Clock period (that is - the next value of the REFCLK counter at the positive Sample Clock edge, had it not been reset to 0).;The value is cleared when [STMPCTL.STMP_EN] = 0.
  • 0h = Smallest value
  • FFFFh = Highest possible value

23.13.27 STPSCAPT Register (Offset = 30Ch) [Reset = 00000000h]

STPSCAPT is shown in Table 23-31.

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Captured Sample Clock Counter Value, Capture Channel 0

Table 23-31 STPSCAPT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CAPTVALR0hThe value of the samplestamp Sample Clock counter [STMPWCNT.CURR_VALUE] last time an event was pulsed. This number corresponds to the number of positive Sample Clock edges since the samplestamp generator was enabled;The value is cleared when [STMPCTL.STPEN] = 0.
  • 0h = Smallest value
  • FFFFh = Highest possible value

23.13.28 STPSPER Register (Offset = 310h) [Reset = 00000000h]

STPSPER is shown in Table 23-32.

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Sample Clock Counter Period Value

Table 23-32 STPSPER Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUER/W0hUsed to define when [STMPWCNT] is to be reset so number of Sample Clock edges are found for the size of the sample buffer. This is thus a modulo value for the Sample Clock counter. This number must correspond to the size of the sample buffer used by the system (that is the index of the last sample plus 1).
  • 0h = Smallest value
  • FFFFh = Highest possible value

23.13.29 STPINTRG Register (Offset = 314h) [Reset = 00000000h]

STPINTRG is shown in Table 23-33.

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WS Counter Trigger Value for Input Pins

Table 23-33 STPINTRG Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0INSTRWCTR/W0hIn Start W Count Compare value used to start the incoming audio streams.;This bit field must equal the Sample Clock counter value during the Sample Clock period in which the first input word(s) are sampled and stored to memory (that is the sample at the start of the very first DMA input buffer).;The value of this register takes effect when at least 32 PDMxCLK cycle ticks have happened.;Note: To avoid false triggers, this bit field must be set higher than VALUE.
  • 0h = Smallest value
  • FFFFh = Highest possible value

23.13.30 STPSSET Register (Offset = 318h) [Reset = 00000000h]

STPSSET is shown in Table 23-34.

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Sample Clock Counter Set Operation

Table 23-34 STPSSET Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUER/W0hSample Clock counter modification: Sets the running Sample Clock counter equal to the written value.
  • 0h = Smallest value
  • FFFFh = Highest possible value

23.13.31 STPSADD Register (Offset = 31Ch) [Reset = 00000000h]

STPSADD is shown in Table 23-35.

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Sample Clock Counter Add Operation

Table 23-35 STPSADD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALINCR/W0hSample Clock counter modification: Adds the written value to the running Sample Clock counter. If a positive edge of Sample Clock occurs at the same time as the operation, this will be taken into account.;To add a negative value, write "[STMPWPER.VALUE] - value".;
  • 0h = Smallest value
  • FFFFh = Highest possible value

23.13.32 STPXMIN Register (Offset = 320h) [Reset = 00000000h]

STPXMIN is shown in Table 23-36.

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REFCLK Minimum Period Value;Minimum Value of STPXPER

Table 23-36 STPXMIN Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUER/WFFFFhEach time [STMPXPER] is updated, the value is also loaded into this register, provided that the value is smaller than the current value in this register.;When written, the register is reset to 0xFFFF (65535), regardless of the value written.;The minimum value can be used to detect extra Sample Clock pulses (this registers value will be significantly smaller than [STMPXPER.VALUE]).
  • 0h = Smallest value
  • FFFFh = Highest possible value

23.13.33 STPWCNT Register (Offset = 324h) [Reset = 00000000h]

STPWCNT is shown in Table 23-37.

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Current Value of sample clock count This register is reset when STPEN = 0.

Table 23-37 STPWCNT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CURRVALR0hCurrent value of the Sample Clock counter
  • 0h = Smallest value
  • FFFFh = Highest possible value

23.13.34 STPXCNT Register (Offset = 328h) [Reset = 00000000h]

STPXCNT is shown in Table 23-38.

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Current Value of XCNT This register is reset when STPEN = 0.

Table 23-38 STPXCNT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CURRVALR0hCurrent value of the REFCLK counter, latched when reading [STMPWCNT].
  • 0h = Smallest value
  • FFFFh = Highest possible value

23.13.35 STPSTAT Register (Offset = 32Ch) [Reset = 00000000h]

STPSTAT is shown in Table 23-39.

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Samplestamp Generator Status Register

Table 23-39 STPSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1INRDYR0hLow until the input pins are ready to be started by the samplestamp generator. When started (that is [STMPINTRIG] equals the WCLK counter) the bit goes back low.
  • 0h = Clear
  • 1h = Set
0RESERVEDR0hReserved

23.13.36 CLKCFG Register (Offset = 1000h) [Reset = 00000000h]

CLKCFG is shown in Table 23-40.

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Clock configuration register Note: Disable the CLKCFG.MEM_CLK_EN and CLKCFG.ADFS_EN to change [CLK_CFG.MEM_CLK_SEL] or [ADFS_CTRL1]/[ADFS_CTRL2] After changing [CLK_CFG.MEM_CLK_SEL] or [ADFS_CTRL1]/[ADFS_CTRL2], enable CLKCFG.ADFS_EN followed by CLKCFG.MEM_CLK_EN

Table 23-40 CLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7ADFSENR/W0hADFS Enable bit
  • 0h = Disable ADFS
  • 1h = Enable ADFS
6-4CLKSELR/W0hClock Select
  • 0h = No Clock
  • 1h = SOC Clock(80MHz)
  • 2h = SOC PLL Clock(un-swallowed 80MHz)
  • 3h = HFXT
3-1RESERVEDR0hReserved
0CLKENR/W0hClock enable
  • 0h = Disable Clock
  • 1h = Enable Clock

23.13.37 ADFSCTL1 Register (Offset = 1004h) [Reset = 00000000h]

ADFSCTL1 is shown in Table 23-41.

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ADFS control register

Table 23-41 ADFSCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0hReserved
20-0TREFR/W0hReference clock time period

23.13.38 ADFSCTL2 Register (Offset = 1008h) [Reset = 00000000h]

ADFSCTL2 is shown in Table 23-42.

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ADFS control register 2

Table 23-42 ADFSCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-20DIVR/W0hValue of divider to be used for ADFS
19-18RESERVEDR0hReserved
17DLTASIGNR/W0hSign of delta value to be used.
  • 0h = Positive Sign
  • 1h = Negative sign
16-0DELTAR/W0hDifference in time periods of (reference clk/divisor) and required clock