SWRU626 User guide | 德州仪器 TI.com.cn

SWRU626 December 2025 CC3501E , CC3551E

1
1 Read This First
1. 1.1 About This Manual
2. 1.2 Register, Field, and Bit Calls
3. Trademarks
2 Architecture Overview
1. 2.1 Target Applications
2. 2.2 Introduction
3. 2.3 Internal System Diagram
4. 2.4 Arm Cortex M33
5. 2.5 Power Management
6. 2.6 Debug Subsystem (DEBUGSS)
7. 2.7 Memory Subsystem (MEMSS)
  1. 2.7.1 External Memory Interface
8. 2.8 Hardware Security Module
9. 2.9 General Purpose Timers (GPT)
10. 2.10 Real Time Clock (RTC)
11. 2.11 Direct Memory Access
12. 2.12 GPIOs
13. 2.13 Communication Peripherals
3 Arm Cortex-M33 Processor
1. 3.1 Arm Cortex-M33 Processor Introduction
2. 3.2 Block Diagram
3. 3.3 M33 instantiation parameters
4. 3.4 Arm Cortex-M33 System Peripheral Details
5. 3.5 CPU Sub-System Peripheral Details
6. 3.6 Programming Model
7. 3.7 TrustZone-M
8. 3.8 CC35xx Host MCU Registers
9. 3.9 Arm® Cortex®-M33 Registers
4 Memory Map
1. 4.1 Memory Map
5 Interrupts and Events
1. 5.1 Exception Model
2. 5.2 Fault Handling
3. 5.3 Security State Switches
4. 5.4 Event Manager
5. 5.5 SOC_IC Registers
6. 5.6 SOC_AON Registers
7. 5.7 SOC_AAON Registers
6 Debug Subsystem (DEBUGSS)
1. 6.1 Introduction
2. 6.2 Block Diagram
3. 6.3 Overview
4. 6.4 Physical Interface
5. 6.5 Debug Access Ports
6. 6.6 Debug Features
7. 6.7 Behavior in Low Power Modes
8. 6.8 Debug Access Control
9. 6.9 SOC_DEBUGSS Registers
7 Power, Reset, Clock Management
1. 7.1 Power Management
2. 7.2 Reset
  1. 7.2.1 Reset Cause
  2. 7.2.2 Watchdog Timer (WDT)
3. 7.3 Clocks
  1. 7.3.1 Fast Clock
  2. 7.3.2 Slow Clock
4. 7.4 PRCM_AON Registers
5. 7.5 PRCM_SCRATCHPAD Registers
8 Memory Subsystem (MEMSS)
1. 8.1 Introduction
2. 8.2 SRAM
3. 8.3 D-Cache
4. 8.4 Flash
5. 8.5 PSRAM
6. 8.6 XiP Memory Access
7. 8.7 ICACHE Registers
8. 8.8 DCACHE Registers
9. 8.9 OSPI Registers
10. 8.10 HOST_XIP Registers
9 Hardware Security Module (HSM)
1. 9.1 Introduction
2. 9.2 Overview
3. 9.3 Mailbox and Register Access Firewall
4. 9.4 DMA Firewall
5. 9.5 HSM Key Storage
6. 9.6 HSM Registers
7. 9.7 HSM_NON_SEC Registers
8. 9.8 HSM_SEC Registers
10Device Boot and Bootloader
1. 10.1 CC35xx Boot Concept
2. 10.2 Features
3. 10.3 Vendor Images Format and Processing
  1. 10.3.1 External Flash Arrangement
  2. 10.3.2 Vendor Images Format
4. 10.4 Boot Flows
5. 10.5 Chain of Trust
11Direct Memory Access (DMA)
1. 11.1 Overview
2. 11.2 Block Diagram
3. 11.3 Functional Description
4. 11.4 HOST_DMA Registers
12One Time Programming (OTP)
13General Purpose Timers (GPT)
1. 13.1 Overview
2. 13.2 Block Diagram
3. 13.3 Functional Description
4. 13.4 Timer Modes
5. 13.5 GPTIMER Registers
14System Timer (SysTimer)
1. 14.1 Overview
2. 14.2 Block Diagram
3. 14.3 Functional Description
  1. 14.3.1 Common Channel Features
  2. 14.3.2 Interrupts and Events
4. 14.4 SYSRESOURCES Registers
5. 14.5 SYSTIM Registers
15Real-Time Clock (RTC)
1. 15.1 Introduction
2. 15.2 Block Diagram
3. 15.3 Interrupts and Events
4. 15.4 CAPTURE and COMPARE Configurations
  1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
  2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
5. 15.5 RTC Registers
16General Purpose Input/Output (GPIOs)
1. 16.1 Introduction
2. 16.2 Block Diagram
3. 16.3 I/O Mapping and Configuration
  1. 16.3.1 Basic I/O Mapping
  2. 16.3.2 Pin Mapping
4. 16.4 Edge Detection
5. 16.5 GPIO
6. 16.6 I/O Pins
7. 16.7 Unused Pins
8. 16.8 IOMUX Registers
17Universal Asynchronous Receivers/Transmitters (UART)
1. 17.1 Introduction
2. 17.2 Block Diagram
3. 17.3 UART Functional Description
4. 17.4 UART-LIN Specification
5. 17.5 Interface to Host DMA
6. 17.6 Initialization and Configuration
7. 17.7 UART Registers
18Serial Peripheral Interface (SPI)
1. 18.1 Overview
  1. 18.1.1 Features
  2. 18.1.2 Block Diagram
2. 18.2 Signal Description
3. 18.3 Functional Description
4. 18.4 Host DMA Operation
5. 18.5 Initialization and Configuration
6. 18.6 SPI Registers
19Inter-Integrated Circuit (I2C) Interface
1. 19.1 Introduction
2. 19.2 Block Diagram
3. 19.3 Functional Description
  1. 19.3.1 Clock Control
    1. 19.3.1.1 Internal Clock
    2. 19.3.1.2 External Clock
  2. 19.3.2 General Architecture
4. 19.4 Initialization and Configuration
5. 19.5 Interrupts
6. 19.6 I2C Registers
20Secure Digital Multimedia Card (SDMMC)
1. 20.1 Introduction
  1. 20.1.1 SDMMC Features
  2. 20.1.2 Integration
2. 20.2 Functional Description
3. 20.3 Low-Level Programming Models
  1. 20.3.1 SDMMC Initialization Flow
  2. 20.3.2 Operational Modes Configuration
    1. 20.3.2.1 Basic Operations for SDMMC
    2. 20.3.2.2 Card Detection, Identification, and Selection
4. 20.4 SDMMC Registers
21Secure Digital Input/Output (SDIO)
1. 21.1 Introduction
2. 21.2 Block Diagram
3. 21.3 Functional Description
4. 21.4 SDIO_CORE Registers
5. 21.5 SDIO_CARD_FN1 Registers
22Inter-Integrated Circuit Sound (I2S)
1. 22.1 Introduction
2. 22.2 Block Diagram
3. 22.3 Signal Descriptions
4. 22.4 Functional Description
5. 22.5 Memory Interface
6. 22.6 Samplestamp Generator
7. 22.7 Error Detection
8. 22.8 Usage
  1. 22.8.1 Start-Up Sequence
  2. 22.8.2 Shutdown Sequence
9. 22.9 I2S Configuration Guideline
10. 22.10 I2S Registers
23Pulse Density Modulation (PDM)
1. 23.1 Introduction
2. 23.2 Block Diagram
3. 23.3 Input Selection
  1. 23.3.1 PDM Data Mode
  2. 23.3.2 Manchester Input Mode
4. 23.4 CIC Filter
5. 23.5 FIFO Organization in Different Modes
6. 23.6 Automatic Gain Control (AGC)
  1. 23.6.1 Operation in 2's Complement Format
  2. 23.6.2 Operation in Offset Binary Format
7. 23.7 Interrupts
8. 23.8 Clock Select and Control
9. 23.9 DMA Operation
10. 23.10 Samplestamp Generator
11. 23.11 Debug‑Mode Flag Behavior
12. 23.12 Software Guidelines
13. 23.13 PDM Registers
24Analog to Digital Converter (ADC)
1. 24.1 Overview
2. 24.2 Block Diagram
3. 24.3 Functional Description
4. 24.4 ADC Registers
25Controller Area Network (CAN)
1. 25.1 Introduction
2. 25.2 Functions
3. 25.3 DCAN Subsystem
4. 25.4 DCAN Functional Description
5. 25.5 DCAN Wrapper
6. 25.6 DCAN Clock Enable
7. 25.7 DCAN Registers
26Revision History

5.6 SOC_AON Registers

Table 5-22 lists the memory-mapped registers for the SOC_AON registers. All register offset addresses not listed in Table 5-22 should be considered as reserved locations and the register contents should not be modified.

Table 5-22 SOC_AON Registers

Offset	Acronym	Register Name	Section
Ch	SPEVTCTL	Peripheral Interrupt Control	Section 5.6.1
10h	TMEVTCTL	Timers Interrupt Control	Section 5.6.2
14h	GPT0EVTCTL0	GPTIMER0 Interrupt Control 0	Section 5.6.3
18h	GPT1EVTCTL0	GPTIMER1 Interrupt Control	Section 5.6.4
54h	DMEMSTART	Data Ram Start Adress	Section 5.6.5
58h	DMEMEND	Data Ram End Adress	Section 5.6.6
64h	TCMSTART	TCM Data Ram Start Adress	Section 5.6.7
68h	TCMEND	TCM Data Ram End Adress	Section 5.6.8
7Ch	GPIOEVTS0	GPIO Event Status 0	Section 5.6.9
80h	GPIOEVTS1	GPIO Event Status 1	Section 5.6.10
84h	MEMSSCTL0	MEMSS Control 0	Section 5.6.11
88h	MEMSSCTL1	MEMSS Control 1	Section 5.6.12
9Ch	VTORS	VTOR Host Secure Address	Section 5.6.13
A0h	VTORNS	VTOR Host Non-Secure Address	Section 5.6.14
A8h	CPULOCKS	CPU Locks	Section 5.6.15
ACh	HOSTLOCKS	Host Locks	Section 5.6.16
B0h	HOSTBOOT	Host Boot Done	Section 5.6.17
B4h	SECCFG	Security Configurations	Section 5.6.18
D4h	ERRSIMASK	Error Host Secured Interrupt Mask	Section 5.6.19
D8h	ERRSISET	Error Host Secured Interrupt Set	Section 5.6.20
DCh	ERRSICLR	Error Host Secured Interrupt Clear	Section 5.6.21
E0h	ERRSIMSET	Error Host Secured Masked Interrupt Set	Section 5.6.22
E4h	ERRSIMCLR	Error Host Secured Masked Interrupt Clear	Section 5.6.23
E8h	ERRSRIS	Error Host Secured Raw Interrupt Status	Section 5.6.24
ECh	ERRSMIS	Doorbell Host Secured Masked Interrupt Status	Section 5.6.25
F0h	GPT0EVTCTL1	GPTIMER0 Interrupt Control 1	Section 5.6.26
F4h	GPT1EVTCTL1	GPTIMER1 Interrupt Control 1	Section 5.6.27
104h	ESMSTACST	ESM's Status	Section 5.6.28
10Ch	MEMSSCFG	MEMSS Configurations	Section 5.6.29
138h	GPIOMIS0S	GPIO's Masked Interrupt Status 0	Section 5.6.30
13Ch	GPIOMIS1S	GPIO's Masked Interrupt Status 1	Section 5.6.31
140h	GPIOFNC0S	GPIO's Interrupt Mask 0	Section 5.6.32
144h	GPIOFNC1S	GPIO's Interrupt Mask 1	Section 5.6.33
14Ch	ESM1VAL2ND	ESM1 Second Magic Value	Section 5.6.34
150h	ESM2VAL2ND	ESM2 Second Magic Value	Section 5.6.35
154h	ESM1STA2ND	ESM1 Second Magic Value Status	Section 5.6.36
158h	ESM2STA2ND	ESM2 Second Magic Value Status	Section 5.6.37
15Ch	FWCFGHOST	Host Firewall Bypass	Section 5.6.38
160h	FWCFGDMA	DMA Firewall Bypass	Section 5.6.39
164h	FWCFGFPRPH	Peripherals Firewall Bypass	Section 5.6.40
168h	FWCFGM33	Cortex Firewall Bypass	Section 5.6.41
16Ch	FWCFGMEMSS	MEMSS Firewall Bypass	Section 5.6.42
170h	FWIOGENSEL	IOMUX Common Firewall Configuration	Section 5.6.43
174h	FWPRCMHOST	PRCM HOST Firewall Configuration	Section 5.6.44
178h	FWPRCMSPAD	PRCM Scratchpad Firewall Configuration	Section 5.6.45
17Ch	FWPRCMCMN	PRCM Common Firewall Configuration	Section 5.6.46
180h	FWCKM	Clock Manager Firewall Configuration	Section 5.6.47
184h	FWSOCIC	Interconnect Firewall Configuration	Section 5.6.48
188h	FWAONM33S	SOC AON Host Secure Aperture Firewall Configuration	Section 5.6.49
18Ch	FWAONM33NS	SOC AON Host Non-Secure Aperture Firewall Configuration	Section 5.6.50
190h	FWAAONM33S	SOC AAON Host Secure Aperture Firewall Configuration	Section 5.6.51
194h	FWAAONM33NS	SOC AAON Host Non-Secure Aperture Firewall Configuration	Section 5.6.52
198h	FWCMNRTC	RTC Firewall Configuration	Section 5.6.53
19Ch	FWMEMSS0	MEMSS Region 0 Firewall Configuration	Section 5.6.54
1A0h	FWMEMSS1	MEMSS Region 1 Firewall Configuration	Section 5.6.55
1A4h	FWMEMSS2	MEMSS Region 2 Firewall Configuration	Section 5.6.56
1A8h	FWHOSTAON	HOST AON Target Firewall Configuration	Section 5.6.57
1B0h	FWHIF	HIF Firewall Configuration	Section 5.6.58
1B4h	FWHOST0	HOST Target Region 0 Firewall Configuration	Section 5.6.59
1B8h	FWHOST1	HOST Target Region 1 Firewall Configuration	Section 5.6.60
1BCh	FWHOST2	HOST Target Region 2 Firewall Configuration	Section 5.6.61
1C0h	FWHOST3	HOST Target Region 3 Firewall Configuration	Section 5.6.62
1C4h	FWHOST4	HOST Target Region 4 Firewall Configuration	Section 5.6.63
1C8h	FWHOST5	HOST Target Region 5 Firewall Configuration	Section 5.6.64
1CCh	FWHOST6	HOST Target Region 6 Firewall Configuration	Section 5.6.65
1D0h	FWHOST7	HOST Target Region 7 Firewall Configuration	Section 5.6.66
1D4h	FWHOST8	HOST Target Region 8 Firewall Configuration	Section 5.6.67
1D8h	FWHOST9	HOST Target Region 9 Firewall Configuration	Section 5.6.68
1DCh	FWHOST10	HOST Target Region 10 Firewall Configuration	Section 5.6.69
1E0h	FWHOST11	HOST Target Region 11 Firewall Configuration	Section 5.6.70
1E4h	FWXIPOSPI	xSPI Registers Firewall Configuration	Section 5.6.71
1E8h	FWXIPINDAC	xSPI Indac Firewall Configuration	Section 5.6.72
1ECh	FWXIPGEN	xSPI General Firewall Configuration	Section 5.6.73
1F0h	FWXIPUDMAS	xSPI uDMA Secured Firewall Configuration	Section 5.6.74
1F4h	FWXIPUDMANS	xSPI uDMA Non-Secured Firewall Configuration	Section 5.6.75
1F8h	FWOTFDE0	xSPI OTFDE 0 Firewall Configuration	Section 5.6.76
1FCh	FWOTFDE1	xSPI OTFDE 1 Firewall Configuration	Section 5.6.77
200h	FWOTFDE2	xSPI OTFDE 2 Firewall Configuration	Section 5.6.78
204h	FWOTFDE3	xSPI OTFDE 3 Firewall Configuration	Section 5.6.79
208h	FWDMAGEN	DMA Target Common Firewall Configuration	Section 5.6.80
20Ch	FWDMA0	DMA Target Region 0 Firewall Configuration	Section 5.6.81
210h	FWDMA1	DMA Target Region 1 Firewall Configuration	Section 5.6.82
214h	FWDMA2	DMA Target Region 2 Firewall Configuration	Section 5.6.83
218h	FWDMA3	DMA Target Region 3 Firewall Configuration	Section 5.6.84
21Ch	FWDMA4	DMA Target Region 4 Firewall Configuration	Section 5.6.85
220h	FWDMA5	DMA Target Region 5 Firewall Configuration	Section 5.6.86
224h	FWDMA6	DMA Target Region 6 Firewall Configuration	Section 5.6.87
228h	FWDMA7	DMA Target Region 7 Firewall Configuration	Section 5.6.88
22Ch	FWDMA8	DMA Target Region 8 Firewall Configuration	Section 5.6.89
230h	FWDMA9	DMA Target Region 9 Firewall Configuration	Section 5.6.90
234h	FWDMA10	DMA Target Region 10 Firewall Configuration	Section 5.6.91
238h	FWDMA11	DMA Target Region 11 Firewall Configuration	Section 5.6.92
23Ch	FWHSMEIPNS	HSM EIP Non-Secured Registers Firewall Configuration	Section 5.6.93
240h	FWHSMEIPS	HSM EIP Secured Registers Firewall Configuration	Section 5.6.94
244h	FWHSMWRAPNS	HSM Non-Secured Wrapper Firewall Configuration	Section 5.6.95
248h	FWHSMWRAPS	HSM Secured Wrapper Firewall Configuration	Section 5.6.96
24Ch	FWHSMDBG	HSM Debug Memory Firewall Configuration	Section 5.6.97
250h	FWI2C0	I2C 0 Firewall Configuration	Section 5.6.98
254h	FWI2C1	I2C 1 Firewall Configuration	Section 5.6.99
258h	FWSPSPI0	SPI 0 Firewall Configuration	Section 5.6.100
25Ch	FWSPSPI1	SPI 1 Firewall Configuration	Section 5.6.101
260h	FWSPUART0	UART 0 Firewall Configuration	Section 5.6.102
264h	FWSPUART1	UART 1 Firewall Configuration	Section 5.6.103
268h	FWSPGPT0	GPTIMER0 Firewall Configuration	Section 5.6.104
26Ch	FWSPGPT1	GPTIMER1 Firewall Configuration	Section 5.6.105
270h	FWSPI2S	I2S Firewall Configuration	Section 5.6.106
274h	FWPDM	PDM Firewall Configuration	Section 5.6.107
278h	FWSPCAN	DCAN Firewall Configuration	Section 5.6.108
27Ch	FWSPADC	ADC Firewall Configuration	Section 5.6.109
280h	FWSPSDMMC	SDMMC Firewall Configuration	Section 5.6.110
284h	FWSPSDIO	SDIO CARD Firewall Configuration	Section 5.6.111
288h	FWSPUART2	UART 2 Firewall Configuration	Section 5.6.112
28Ch	UDMANSCTL	uDMA Non-Secured Channel Control	Section 5.6.113
290h	FWIOPAD0	IOMUX PAD 0 Firewall Configuration	Section 5.6.114
294h	FWIOPAD1	IOMUX PAD 1 Firewall Configuration	Section 5.6.115
298h	FWIOPAD2	IOMUX PAD 2 Firewall Configuration	Section 5.6.116
29Ch	FWIOPAD3	IOMUX PAD 3 Firewall Configuration	Section 5.6.117
2A0h	FWIOPAD4	IOMUX PAD 4 Firewall Configuration	Section 5.6.118
2A4h	FWIOPAD5	IOMUX PAD 5 Firewall Configuration	Section 5.6.119
2A8h	FWIOPAD6	IOMUX PAD 6 Firewall Configuration	Section 5.6.120
2ACh	FWIOPAD7	IOMUX PAD 7 Firewall Configuration	Section 5.6.121
2B0h	FWIOPAD8	IOMUX PAD 8 Firewall Configuration	Section 5.6.122
2B4h	FWIOPAD9	IOMUX PAD 9 Firewall Configuration	Section 5.6.123
2B8h	FWIOPAD10	IOMUX PAD 10 Firewall Configuration	Section 5.6.124
2BCh	FWIOPAD11	IOMUX PAD 11 Firewall Configuration	Section 5.6.125
2C0h	FWIOPAD12	IOMUX PAD 12 Firewall Configuration	Section 5.6.126
2C4h	FWIOPAD13	IOMUX PAD 13 Firewall Configuration	Section 5.6.127
2C8h	FWIOPAD14	IOMUX PAD 14 Firewall Configuration	Section 5.6.128
2CCh	FWIOPAD15	IOMUX PAD 15 Firewall Configuration	Section 5.6.129
2D0h	FWIOPAD16	IOMUX PAD 16 Firewall Configuration	Section 5.6.130
2D4h	FWIOPAD17	IOMUX PAD 17 Firewall Configuration	Section 5.6.131
2D8h	FWIOPAD18	IOMUX PAD 18 Firewall Configuration	Section 5.6.132
2DCh	FWIOPAD19	IOMUX PAD 19 Firewall Configuration	Section 5.6.133
2E0h	FWIOPAD20	IOMUX PAD 20 Firewall Configuration	Section 5.6.134
2E4h	FWIOPAD21	IOMUX PAD 21 Firewall Configuration	Section 5.6.135
2E8h	FWIOPAD22	IOMUX PAD 22 Firewall Configuration	Section 5.6.136
2ECh	FWIOPAD23	IOMUX PAD 23 Firewall Configuration	Section 5.6.137
2F0h	FWIOPAD24	IOMUX PAD 24 Firewall Configuration	Section 5.6.138
2F4h	FWIOPAD25	IOMUX PAD 25 Firewall Configuration	Section 5.6.139
2F8h	FWIOPAD26	IOMUX PAD 26 Firewall Configuration	Section 5.6.140
2FCh	FWIOPAD27	IOMUX PAD 27 Firewall Configuration	Section 5.6.141
300h	FWIOPAD28	IOMUX PAD 28 Firewall Configuration	Section 5.6.142
304h	FWIOPAD29	IOMUX PAD 29 Firewall Configuration	Section 5.6.143
308h	FWIOPAD30	IOMUX PAD 30 Firewall Configuration	Section 5.6.144
30Ch	FWIOPAD31	IOMUX PAD 31 Firewall Configuration	Section 5.6.145
310h	FWIOPAD32	IOMUX PAD 32 Firewall Configuration	Section 5.6.146
314h	FWIOPAD33	IOMUX PAD 33 Firewall Configuration	Section 5.6.147
318h	FWIOPAD34	IOMUX PAD 34 Firewall Configuration	Section 5.6.148
31Ch	FWIOPAD35	IOMUX PAD 35 Firewall Configuration	Section 5.6.149
320h	FWIOPAD36	IOMUX PAD 36 Firewall Configuration	Section 5.6.150
324h	FWIOPAD37	IOMUX PAD 37 Firewall Configuration	Section 5.6.151
328h	FWIOPAD38	IOMUX PAD 38 Firewall Configuration	Section 5.6.152
32Ch	FWIOPAD39	IOMUX PAD 39 Firewall Configuration	Section 5.6.153
330h	FWIOPAD40	IOMUX PAD 40 Firewall Configuration	Section 5.6.154
334h	FWIOPAD41	IOMUX PAD 41 Firewall Configuration	Section 5.6.155
338h	FWIOPAD42	IOMUX PAD 42 Firewall Configuration	Section 5.6.156
33Ch	FWIOPAD43	IOMUX PAD 43 Firewall Configuration	Section 5.6.157
340h	FWIOPAD44	IOMUX PAD 44 Firewall Configuration	Section 5.6.158
344h	FWIOPAD45	IOMUX PAD 45 Firewall Configuration	Section 5.6.159
348h	FWIOPAD46	IOMUX PAD 46 Firewall Configuration	Section 5.6.160
34Ch	FWIOPAD47	IOMUX PAD 47 Firewall Configuration	Section 5.6.161
350h	FWIOPAD48	IOMUX PAD 48 Firewall Configuration	Section 5.6.162
354h	FWDMA12	DMA Target Region 12 Firewall Configuration	Section 5.6.163
358h	FWDMA13	DMA Target Region 13 Firewall Configuration	Section 5.6.164
1000h	USECSTB	Micro Second STB	Section 5.6.165
1044h	GPIOEVT0NS	GPIO Event Status 0	Section 5.6.166
1048h	GPIOEVT1NS	GPIO Event Status 1	Section 5.6.167
1054h	DBM33NS0	Doorbell Host Non-Secured Interrupt Mask	Section 5.6.168
1058h	DBNSISET	Doorbell Host Non-Secured Interrupt Set	Section 5.6.169
105Ch	DBNSICLR	Doorbell Host Non-Secured Interrupt Clear	Section 5.6.170
1060h	DBNSIMSET	Doorbell Host Non-Secured Masked Interrupt Set	Section 5.6.171
1064h	DBNSIMCLR	Doorbell Host Non-Secured Masked Interrupt Clear	Section 5.6.172
1068h	DBNSRIS	Doorbell Host Non-Secured Raw Interrupt Status	Section 5.6.173
106Ch	DBNSMIS	Doorbell Host Non-Secured Masked Interrupt Status	Section 5.6.174
1070h	GPIOMIS0NS	GPIO's Non-Secured Masked Interrupt Status 0	Section 5.6.175
1074h	GPIOMIS1NS	GPIO's Non-Secured Masked Interrupt Status 1	Section 5.6.176
1078h	GPIOFNC0NS	GPIO's Non-Secured Function 0	Section 5.6.177
107Ch	GPIOFNC1NS	GPIO's Non-Secured Function 1	Section 5.6.178

Complex bit access types are encoded to fit into small table cells. Table 5-23 shows the codes that are used for access types in this section.

Table 5-23 SOC_AON Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

5.6.1 SPEVTCTL Register (Offset = Ch) [Reset = 00000000h]

SPEVTCTL is shown in Table 5-24.

Return to the Summary Table.

Shared Peripherals Event MUXs Selectors. This register selects events to ADC, I2S and PDM.

Table 5-24 SPEVTCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R	0h	Reserved
22-16	PDM	R/W	0h	PDM Event Selector. This field selects event to PDM.
15	RESERVED	R	0h	Reserved
14-8	I2S	R/W	0h	I2S Event Selector. This field selects event to I2S.
7-6	RESERVED	R	0h	Reserved
5-0	ADC	R/W	0h	ADC Event Selector. This field selects event to ADC.

5.6.2 TMEVTCTL Register (Offset = 10h) [Reset = 00000000h]

TMEVTCTL is shown in Table 5-25.

Return to the Summary Table.

Timers Event MUXs Selectors. This register selects events to SYSTIMER and RTC. There are two MUXs of SYSTIMER and one for RTC.

Table 5-25 TMEVTCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R	0h	Reserved
22-16	RTC	R/W	0h	RTC Event Selector. This field selects event to RTC.
15-14	RESERVED	R	0h	Reserved
13-8	SYSTM1	R/W	0h	SYSTIMER Event 2nd Selector. This field selects event to SYSTIMER.
7-6	RESERVED	R	0h	Reserved
5-0	SYSTM0	R/W	0h	SYSTIMER Event 1st Selector. This field selects event to SYSTIMER.

5.6.3 GPT0EVTCTL0 Register (Offset = 14h) [Reset = 00000000h]

GPT0EVTCTL0 is shown in Table 5-26.

Return to the Summary Table.

GPTIMER0 Channels Event MUXs Selectors. This register selects events to GPTIMER0. There are 4 event MUXs for GPTIMER Channels.

Table 5-26 GPT0EVTCTL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h	Reserved
27-21	CH3SEL	R/W	0h	This field selects MUX output to CH3 of GPTIMER0 IRQ.
20-14	CH2SEL	R/W	0h	This field selects MUX output to CH2 of GPTIMER0 IRQ.
13-7	CH1SEL	R/W	0h	This field selects MUX output to CH1 of GPTIMER0 IRQ.
6-0	CH0SEL	R/W	0h	This field selects MUX output to CH0 of GPTIMER0 IRQ.

5.6.4 GPT1EVTCTL0 Register (Offset = 18h) [Reset = 00000000h]

GPT1EVTCTL0 is shown in Table 5-27.

Return to the Summary Table.

GPTIMER1 Event MUXs Selectors. This register selects events to GPTIMER1. There are 4 event MUXs for GPTIMER Channels.

Table 5-27 GPT1EVTCTL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h	Reserved
27-21	CH3SEL	R/W	0h	This field selects MUX output to CH3 of GPTIMER1 IRQ.
20-14	CH2SEL	R/W	0h	This field selects MUX output to CH2 of GPTIMER1 IRQ.
13-7	CH1SEL	R/W	0h	This field selects MUX output to CH1 of GPTIMER1 IRQ.
6-0	CH0SEL	R/W	0h	This field selects MUX output to CH0 of GPTIMER1 IRQ.

5.6.5 DMEMSTART Register (Offset = 54h) [Reset = 28000000h]

DMEMSTART is shown in Table 5-28.

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DATA Memory MEMSS Start Address. DMEM Start Address-also define S/NS region split

Table 5-28 DMEMSTART Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	ADDR	R/W	00028000h	DMEM Start Address-also define S/NS region split
11-0	RESERVED	R	0h	Reserved

5.6.6 DMEMEND Register (Offset = 58h) [Reset = 2FFFFFFFh]

DMEMEND is shown in Table 5-29.

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DATA Memory MEMSS End Address. DMEM end Address-also define S/NS region split

Table 5-29 DMEMEND Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	ADDR	R/W	0002FFFFh	DMEM end Address-also define S/NS region split
11-0	RESERVED	R	0h	Reserved

5.6.7 TCMSTART Register (Offset = 64h) [Reset = 20000000h]

TCMSTART is shown in Table 5-30.

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TCM DATA Memory MEMSS Start Address. TCM data Start Address-also define S/NS region split

Table 5-30 TCMSTART Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	ADDR	R/W	00080000h	TCM data Start Address-also define S/NS region split
9-0	RESERVED	R	0h	Reserved

5.6.8 TCMEND Register (Offset = 68h) [Reset = 27FFFFFFh]

TCMEND is shown in Table 5-31.

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TCM DATA Memory MEMSS End Address. TCM data end Address-also define S/NS region split

Table 5-31 TCMEND Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	ADDR	R/W	0009FFFFh	TCM data end Address-also define S/NS region split
9-0	RESERVED	R	0h	Reserved

5.6.9 GPIOEVTS0 Register (Offset = 7Ch) [Reset = 00000000h]

GPIOEVTS0 is shown in Table 5-32.

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Secured GPIO Event Status, 1st Register. 45 bits status over two registers.

Table 5-32 GPIOEVTS0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	STA31TO0	R	0h	Secured event status , first 32 bits. ([31:0])

5.6.10 GPIOEVTS1 Register (Offset = 80h) [Reset = 00000000h]

GPIOEVTS1 is shown in Table 5-33.

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Secured GPIO Event Status, 2nd Register. 45 bits status over two registers.

Table 5-33 GPIOEVTS1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R	0h	Reserved
12-0	STA44TO32	R	0h	Secured event status , 13 MSBs. ([44:32])

5.6.11 MEMSSCTL0 Register (Offset = 84h) [Reset = 00000000h]

MEMSSCTL0 is shown in Table 5-34.

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MEMSS General Control Register. This register controls starvation mechanism counter value and MEMSS bus fault mask.

Table 5-34 MEMSSCTL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-4	BFLTMSTA	R	0h	Bus Fault Masked Status. Out of Memory Index: 0. No error 1. M33 Code 2. M33 Data #1 + #2 3. M3 Code 4. M3 Data 5. M3 PRAM 6. BLE Code 7. Global OCP
3	BFLTMASK	R/W	0h	MEMSS Bus Fault Mask 1. Mask 0. Do not mask
2-0	STRVCNTV	R/W	0h	Starvation Counter Value Configuration. That value reflect how long writing to mailbox can be delayed.

5.6.12 MEMSSCTL1 Register (Offset = 88h) [Reset = 00000000h]

MEMSSCTL1 is shown in Table 5-35.

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MEMSS General Control Register. This is a status register for bus fault raw status.

Table 5-35 MEMSSCTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	BFLTRWSTA	R	0h	Bus Fault Raw Status. Error indication from memss. Out of Memory Index: 0. No error 1. M33 Code 2. M33 Data #1 + #2 3. M3 Code 4. M3 Data 5. M3 PRAM 6. BLE Code 7. Global OCP Type: Read-Clear

5.6.13 VTORS Register (Offset = 9Ch) [Reset = 00000000h]

VTORS is shown in Table 5-36.

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M33 Secure Vector Table Base Address.

Table 5-36 VTORS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	ADDR	R/W	0h	init VTOR Secured Address.
6-0	RESERVED	R	0h	Reserved

5.6.14 VTORNS Register (Offset = A0h) [Reset = 00000000h]

VTORNS is shown in Table 5-37.

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M33 Non-Secure Vector Table Base Address.

Table 5-37 VTORNS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	ADDR	R/W	0h	init VTOR non Secured address
6-0	RESERVED	R	0h	Reserved

5.6.15 CPULOCKS Register (Offset = A8h) [Reset = 00000000h]

CPULOCKS is shown in Table 5-38.

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CPU Locks. This register contain 5 locks. Issued to M33 Cortex and used to lock internal cortex registers. LOCKSVTAIRCR, LOCKNSVTOR, LOCKSMPU, LOCKNSMPU, LOCKSAU.

Table 5-38 CPULOCKS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	SAU	R/W	0h	Locking this Cortex internal configuration
3	NSPMU	R/W	0h	Locking this Cortex internal configuration
2	SMPU	R/W	0h	Locking this Cortex internal configuration
1	NSVTOR	R/W	0h	Locking this Cortex internal configuration
0	SVTAIRCR	R/W	0h	Locking this Cortex internal configuration

5.6.16 HOSTLOCKS Register (Offset = ACh) [Reset = 00000000h]

HOSTLOCKS is shown in Table 5-39.

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Host Lock Signals. lock once. Do Not lock until written. When written Locked immediately, cleared only at soc aon reset or por reset. These are host security lock configurations (some can be also locked by TI)

Table 5-39 HOSTLOCKS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6	PERIPHEVT	R/W	0h	Locking the firewall configurations of: HIF, CORE, CORE AON, HSM, shared Periphs
5	M3EVT	R/W	0h	Locking the configurations of M3 Events
4	FLASH	R/W	0h	Locking the configurations of On The Fly Enc/Decryption Module Region Related Registers (four registers per region, four regions)
3	DMA	R/W	0h	Locking the configurations of System DMA
2	MEMSSANDFW	R/W	0h	Locking the configurations of Memory Sub System
1	M33	R/W	0h	Locking the configurations of Host MCU, both Secured and non Secured
0	CACHE	R/W	0h	Locking the configurations of ICACHE

5.6.17 HOSTBOOT Register (Offset = B0h) [Reset = 00000000h]

HOSTBOOT is shown in Table 5-40.

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Host Boot Done 1 lock. Write once. Asserted by FW by the end of soc boot done Or in elevated mode By either by TI of by the host and indicates device exit from secure boot mode. this signal also locks host security configurations , Locked immediately , cleared only at soc aon reset or por reset

Table 5-40 HOSTBOOT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	DONE	R/W	0h	Locking host security configurations

5.6.18 SECCFG Register (Offset = B4h) [Reset = 00000000h]

SECCFG is shown in Table 5-41.

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Security Configurations.

Table 5-41 SECCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	BLKSBSWR	R/W	0h	BLOCK SBUS WRITE LOCK Enable this field to block sbus write transactions
1	SELNSIRQ	R/W	0h	This field determine whether the 4 SW interrupts MSbits will be owned by secured/non secured. 0. Non-Secured 1. Secured
0	BLKDMA	R/W	0h	This Field blocks the uDMA transactions to CMEM. 0. un-Block 1. Block

5.6.19 ERRSIMASK Register (Offset = D4h) [Reset = 00000000h]

ERRSIMASK is shown in Table 5-42.

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M33 Secured Error IMASK. Mask Event. '0' - CLR - Clear Interrupt Mask '1' - SET - Set Interrupt Mask

Table 5-42 ERRSIMASK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8-0	IMASK	R/W	0h	Bits division to events: bit[8] - UDMA ERR IRQ bit[7] - CORE ELP WATCHDOG Timer bit[6] - SOC IC IRQs - Address Watch bit[5] - SOC IC IRQs - IC Timeout bit[4] - SOC IC IRQs - serror bit[3] - CORE to SDIO WATCHDOG bit[2] - PLL Unlock bit[1] - MEMss bus fault bit[0] - HSM fatal error

5.6.20 ERRSISET Register (Offset = D8h) [Reset = 00000000h]

ERRSISET is shown in Table 5-43.

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M33 Secured Error ISET. Sets event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Sets interrupt

Table 5-43 ERRSISET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8-0	ISET	W	0h	Bits division to events: bit[8] - UDMA ERR IRQ bit[7] - CORE ELP WATCHDOG Timer bit[6] - SOC IC IRQs - Address Watch bit[5] - SOC IC IRQs - IC Timeout bit[4] - SOC IC IRQs - serror bit[3] - CORE to SDIO WATCHDOG bit[2] - PLL Unlock bit[1] - MEMss bus fault bit[0] - HSM fatal error Type: Write-Clear

5.6.21 ERRSICLR Register (Offset = DCh) [Reset = 00000000h]

ERRSICLR is shown in Table 5-44.

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M33 Secured Error ICLR. Clears event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clears the Event

Table 5-44 ERRSICLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8-0	ICLR	W	0h	Bits division to events: bit[8] - UDMA ERR IRQ bit[7] - CORE ELP WATCHDOG Timer bit[6] - SOC IC IRQs - Address Watch bit[5] - SOC IC IRQs - IC Timeout bit[4] - SOC IC IRQs - serror bit[3] - CORE to SDIO WATCHDOG bit[2] - PLL Unlock bit[1] - MEMss bus fault bit[0] - HSM fatal error Type: Write-Clear

5.6.22 ERRSIMSET Register (Offset = E0h) [Reset = 00000000h]

ERRSIMSET is shown in Table 5-45.

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M33 Secured Error IMSET. Sets Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Set interrupt mask

Table 5-45 ERRSIMSET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8-0	IMSET	W	0h	Bits division to events: bit[8] - UDMA ERR IRQ bit[7] - CORE ELP WATCHDOG Timer bit[6] - SOC IC IRQs - Address Watch bit[5] - SOC IC IRQs - IC Timeout bit[4] - SOC IC IRQs - serror bit[3] - CORE to SDIO WATCHDOG bit[2] - PLL Unlock bit[1] - MEMss bus fault bit[0] - HSM fatal error Type: Write-Clear

5.6.23 ERRSIMCLR Register (Offset = E4h) [Reset = 00000000h]

ERRSIMCLR is shown in Table 5-46.

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M33 Secured Error IMCLR. Clears Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clear interrupt mask

Table 5-46 ERRSIMCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8-0	IMCLR	W	0h	Bits division to events: bit[8] - UDMA ERR IRQ bit[7] - CORE ELP WATCHDOG Timer bit[6] - SOC IC IRQs - Address Watch bit[5] - SOC IC IRQs - IC Timeout bit[4] - SOC IC IRQs - serror bit[3] - CORE to SDIO WATCHDOG bit[2] - PLL Unlock bit[1] - MEMss bus fault bit[0] - HSM fatal error Type: Write-Clear

5.6.24 ERRSRIS Register (Offset = E8h) [Reset = 00000000h]

ERRSRIS is shown in Table 5-47.

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M33 Secured Error RIS. Raw interrupt status for event. This bit is set to 1 when an event is received. when the corresponding bit in ICLR is set to 1, this bit will be cleared. Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred

Table 5-47 ERRSRIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8-0	RIS	R	0h	Bits division to events: bit[8] - UDMA ERR IRQ bit[7] - CORE ELP WATCHDOG Timer bit[6] - SOC IC IRQs - Address Watch bit[5] - SOC IC IRQs - IC Timeout bit[4] - SOC IC IRQs - serror bit[3] - CORE to SDIO WATCHDOG bit[2] - PLL Unlock bit[1] - MEMss bus fault bit[0] - HSM fatal error

5.6.25 ERRSMIS Register (Offset = ECh) [Reset = 00000000h]

ERRSMIS is shown in Table 5-48.

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M33 Secured Error MIS. Mask interrupt status for event Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred

Table 5-48 ERRSMIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8-0	MIS	R	0h	Bits division to events: bit[8] - UDMA ERR IRQ bit[7] - CORE ELP WATCHDOG Timer bit[6] - SOC IC IRQs - Address Watch bit[5] - SOC IC IRQs - IC Timeout bit[4] - SOC IC IRQs - serror bit[3] - CORE to SDIO WATCHDOG bit[2] - PLL Unlock bit[1] - MEMss bus fault bit[0] - HSM fatal error

5.6.26 GPT0EVTCTL1 Register (Offset = F0h) [Reset = 00000000h]

GPT0EVTCTL1 is shown in Table 5-49.

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GPTIMER0 Sync, Tick Enable and Fault Event MUXs Selectors. This register selects events to GPTIMER0.

Table 5-49 GPT0EVTCTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R	0h	Reserved
22-16	FAULT	R/W	0h	Selects fault MUX output to GPTIMER0 IRQ
15	RESERVED	R	0h	Reserved
14-8	TICKEN	R/W	0h	Selects tick enable MUX output to GPTIMER0 IRQ
7	RESERVED	R	0h	Reserved
6-0	SYNC	R/W	0h	Selects sync MUX output to GPTIMER0 IRQ

5.6.27 GPT1EVTCTL1 Register (Offset = F4h) [Reset = 00000000h]

GPT1EVTCTL1 is shown in Table 5-50.

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GPTIMER1 Sync, Tick Enable and Fault Event MUXs Selectors. This register selects events to GPTIMER1.

Table 5-50 GPT1EVTCTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R	0h	Reserved
22-16	FAULT	R/W	0h	Selects fault MUX output to GPTIMER0 IRQ
15	RESERVED	R	0h	Reserved
14-8	TICKEN	R/W	0h	Selects tick enable MUX output to GPTIMER0 IRQ
7	RESERVED	R	0h	Reserved
6-0	SYNC	R/W	0h	Selects sync MUX output to GPTIMER0 IRQ

5.6.28 ESMSTACST Register (Offset = 104h) [Reset = 00000000h]

ESMSTACST is shown in Table 5-51.

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Customer ESMs Status. status register , for each of the ESM (enable sequence monitor) what is the status (Done, violated, or None) Final ESM status for the entire ESM - ESM machine + magic value comparators

Table 5-51 ESMSTACST Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R	0h	Reserved
9	ESM2VIO	R	0h	This field indicates that ESM1 is violated.
8	ESM2DONE	R	0h	This field indicates that ESM2 is done.
7-2	RESERVED	R	0h	Reserved
1	ESM1VIO	R	0h	This field indicates that ESM1 is violated.
0	ESM1DONE	R	0h	This field indicates that ESM1 is done.

5.6.29 MEMSSCFG Register (Offset = 10Ch) [Reset = 00000000h]

MEMSSCFG is shown in Table 5-52.

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MEMSS Configurations. Supported Memory configurations: Functional Modes: 0x0. Baseline 0x1. Extended M3 0x2. Extended throughput 0x3. Extended throughput + WIFI features 0x4. Extended Host Execution 0x5. Extended M33 Data Debug Modes (OCLA Memory): 0x6. Core debug (<M33 Data) 0x7. Core debug Extended throughput (<M33 Data <M3 Exec) 0x8. Core debug PHY only (<M3,M33 Data) 0x9. Host debug (<M3 Exec) 0xA. Host debug extended Host Execution 0xB. Host debug extended M33 Data

Table 5-52 MEMSSCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-0	MODE	R/W	0h	MEMSS mode of bank ownership

5.6.30 GPIOMIS0S Register (Offset = 138h) [Reset = 00000000h]

GPIOMIS0S is shown in Table 5-53.

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Secured Gpio MIS.

Table 5-53 GPIOMIS0S Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	31TO0	R	0h	32 LSBs of MIS. (45 Total)

5.6.31 GPIOMIS1S Register (Offset = 13Ch) [Reset = 00000000h]

GPIOMIS1S is shown in Table 5-54.

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Secured Gpio MIS.

Table 5-54 GPIOMIS1S Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R	0h	Reserved
12-0	44TO32	R	0h	13 MSBs of MIS. (45 Total)

5.6.32 GPIOFNC0S Register (Offset = 140h) [Reset = 00000000h]

GPIOFNC0S is shown in Table 5-55.

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Secured GPIO Functional Mask. 0. Mask 1. Un-Mask

Table 5-55 GPIOFNC0S Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	MASK31TO0	R/W	0h	32 LSBs of MASK. (45 Total)

5.6.33 GPIOFNC1S Register (Offset = 144h) [Reset = 00000000h]

GPIOFNC1S is shown in Table 5-56.

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Secured GPIO Functional Mask. 0. Mask 1. Un-Mask

Table 5-56 GPIOFNC1S Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R	0h	Reserved
12-0	MASK44TO32	R/W	0h	13 MSBs of MASK. (45 Total)

5.6.34 ESM1VAL2ND Register (Offset = 14Ch) [Reset = 00000000h]

ESM1VAL2ND is shown in Table 5-57.

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ESM1 2nd Magic Value. This value is compared to hard coded value and unmask ESM only when value is matched. This additional compare allow additional protection on ESM and also allow vendor to unmask ESM only at the end of vendor secure boot (SBL) is completed

Table 5-57 ESM1VAL2ND Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	MGCVAL	R/W	0h	ESM 2nd magic value

5.6.35 ESM2VAL2ND Register (Offset = 150h) [Reset = 00000000h]

ESM2VAL2ND is shown in Table 5-58.

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ESM2 2nd Magic Value. This value is compared to hard coded value and unmask ESM only when value is matched. This additional compare allow additional protection on ESM and also allow vendor to unmask ESM only at the end of vendor secure boot (SBL) is completed

Table 5-58 ESM2VAL2ND Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	MGCVAL	R/W	0h	ESM 2nd magic value

5.6.36 ESM1STA2ND Register (Offset = 154h) [Reset = 00000000h]

ESM1STA2ND is shown in Table 5-59.

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ESM1 2nd Magic Value Status. ESM magic value match indication.

Table 5-59 ESM1STA2ND Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1	FAULT	R	0h	ESM 2nd magic val fault ( note: indicates fault before a write to the magic val register)
0	DONE	R	0h	ESM 2nd magic val match

5.6.37 ESM2STA2ND Register (Offset = 158h) [Reset = 00000000h]

ESM2STA2ND is shown in Table 5-60.

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ESM2 2nd Magic Value. ESM magic value match indication.

Table 5-60 ESM2STA2ND Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1	FAULT	R	0h	ESM 2nd magic val fault ( note: indicates fault before a write to the magic val register)
0	DONE	R	0h	ESM 2nd magic val match

5.6.38 FWCFGHOST Register (Offset = 15Ch) [Reset = 00000000h]

FWCFGHOST is shown in Table 5-61.

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HOST FW Bypass.

Table 5-61 FWCFGHOST Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	BYPASS	R/W	1h	bypass the following module's firewall configuration: IOMUX_COMMON_SEL PRCM_AON_HOST PRCM_AON_COMMON SCRATCHPAD PLLSHARING SOC_IC SOC_AON_M33_S SOC_AON_M33_NS SOC_AAON_M33_S SOC_AAON_M33_NS RTC XIP_OSPI XIP_OSPI_INDAC XIP_GENERAL XIP_UDMA_SEC XIP_UDMA_NON_SEC OTFDE_REGION0-3 HOST_DMA_GENERAL_CFG

5.6.39 FWCFGDMA Register (Offset = 160h) [Reset = 00000000h]

FWCFGDMA is shown in Table 5-62.

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DMA FW BYPASS

Table 5-62 FWCFGDMA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	BYPASS	R/W	1h	Bypass the firewall configuration for HOST_DMA module

5.6.40 FWCFGFPRPH Register (Offset = 164h) [Reset = 00000000h]

FWCFGFPRPH is shown in Table 5-63.

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Peripheral Firewall Bypass.

Table 5-63 FWCFGFPRPH Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	BYPASS	R/W	1h	bypass the following module's firewall configuration: HIF HSM CORE_AON I2C0/1 SPI0/1 UART0/1 GPTIMER0/1 I2S PDM CAN ADC SDMMC SDIO

5.6.41 FWCFGM33 Register (Offset = 168h) [Reset = 00000000h]

FWCFGM33 is shown in Table 5-64.

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HOST MCU Firewall Bypass

Table 5-64 FWCFGM33 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	BYPASS	R/W	1h	bypass the firewall configuration for HOST MCU module.

5.6.42 FWCFGMEMSS Register (Offset = 16Ch) [Reset = 00000000h]

FWCFGMEMSS is shown in Table 5-65.

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MEMSS Firewall Bypass

Table 5-65 FWCFGMEMSS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	BYPASS	R/W	1h	bypass the Firewall configuration for MEMSS module.

5.6.43 FWIOGENSEL Register (Offset = 170h) [Reset = 00000000h]

FWIOGENSEL is shown in Table 5-66.

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IOMUX General firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-66 FWIOGENSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.44 FWPRCMHOST Register (Offset = 174h) [Reset = 00000000h]

FWPRCMHOST is shown in Table 5-67.

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PRCM_HOST firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-67 FWPRCMHOST Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed
1	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
0	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed

5.6.45 FWPRCMSPAD Register (Offset = 178h) [Reset = 00000000h]

FWPRCMSPAD is shown in Table 5-68.

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M33 SCRATCHPAD firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-68 FWPRCMSPAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.46 FWPRCMCMN Register (Offset = 17Ch) [Reset = 00000000h]

FWPRCMCMN is shown in Table 5-69.

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PRCM_COMMON firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-69 FWPRCMCMN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h	Reserved
5	CORENSRD	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
4	CORENSWR	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
3	M33NSRD	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed
2	M33NSWR	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed
1	M33SRD	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33SWR	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed

5.6.47 FWCKM Register (Offset = 180h) [Reset = 00000000h]

FWCKM is shown in Table 5-70.

Return to the Summary Table.

CKM firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-70 FWCKM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.48 FWSOCIC Register (Offset = 184h) [Reset = 00000000h]

FWSOCIC is shown in Table 5-71.

Return to the Summary Table.

SOC_IC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-71 FWSOCIC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h	Reserved
5	CORENSRD	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
4	CORENSWR	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
3	M33SRD	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
2	M33SWR	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
1	M33NSRD	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed
0	M33NSWR	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.49 FWAONM33S Register (Offset = 188h) [Reset = 00000000h]

FWAONM33S is shown in Table 5-72.

Return to the Summary Table.

AON_M33_S firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-72 FWAONM33S Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.50 FWAONM33NS Register (Offset = 18Ch) [Reset = 00000000h]

FWAONM33NS is shown in Table 5-73.

Return to the Summary Table.

AON_M33_NS firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-73 FWAONM33NS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.51 FWAAONM33S Register (Offset = 190h) [Reset = 00000000h]

FWAAONM33S is shown in Table 5-74.

Return to the Summary Table.

AAON_M33_S firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-74 FWAAONM33S Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.52 FWAAONM33NS Register (Offset = 194h) [Reset = 00000000h]

FWAAONM33NS is shown in Table 5-75.

Return to the Summary Table.

AAON_M33_NS firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-75 FWAAONM33NS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.53 FWCMNRTC Register (Offset = 198h) [Reset = 00000000h]

FWCMNRTC is shown in Table 5-76.

Return to the Summary Table.

RTC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-76 FWCMNRTC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h	Reserved
5	CORENSRD	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
4	CORENSWR	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
3	M33SRD	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
2	M33SWR	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
1	M33NSRD	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed
0	M33NSWR	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.54 FWMEMSS0 Register (Offset = 19Ch) [Reset = 00000000h]

FWMEMSS0 is shown in Table 5-77.

Return to the Summary Table.

MEMSS region 0 firewall access permission for 3 controller id : 0 - M33 Non Secured (valid only in privilege mode) 1 - M33 Secured (valid only in privilege mode) 2 - Core (Non Secure) MEMSS address space: 0x41C00000 - 0x41CCFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max window size is 256Kb (M33D banks) + 10*32K (Flex) = 576Kb

Table 5-77 FWMEMSS0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25-16	LEN	R/W	0h	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id MEMSS address space: 0x41C00000 - 0x41CCFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max window size is 576Kb example: worker base address: 0x41C40000 current address to access: 0x41C41514 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x41C41514 --> ((0x41C41514 - 0x41C40000) >> 10) -->0x5 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules
15-14	RESERVED	R	0h	Reserved
13-4	BASE	R/W	0h	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id MEMSS address space: 0x41C00000 - 0x41CCFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max base value is 0x23F max window size is 576Kb example: worker base address: 0x41C40000 current address to access: 0x41C40504 region_base_address: 0x1 region_base_address_len: 0x1 0x41C40504 --> ((0x41C40504 - 0x41C40000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: (valid only in privilege mode) '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: (valid only in privilege mode) '0' - access not allowed '1' - access allowed

5.6.55 FWMEMSS1 Register (Offset = 1A0h) [Reset = 00000000h]

FWMEMSS1 is shown in Table 5-78.

Return to the Summary Table.

MEMSS region 1 firewall access permission for 3 controller id : 0 - M33 Non Secured (valid only in privilege mode) 1 - M33 Secured (valid only in privilege mode) 2 - Core (Non Secure) MEMSS address space: 0x41C00000 - 0x41CCFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max window size is 256Kb (M33D banks) + 10*32K (Flex) = 576Kb

Table 5-78 FWMEMSS1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25-16	LEN	R/W	0h	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id MEMSS address space: 0x41C00000 - 0x41CCFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max window size is 576Kb example: worker base address: 0x41C40000 current address to access: 0x41C41514 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x41C41514 --> ((0x41C41514 - 0x41C40000) >> 10) -->0x5 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules
15-14	RESERVED	R	0h	Reserved
13-4	BASE	R/W	0h	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id MEMSS address space: 0x41C00000 - 0x41DFFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max base value is 0x23F max window size is 576Kb example: worker base address: 0x41C40000 current address to access: 0x41C40504 region_base_address: 0x1 region_base_address_len: 0x1 0x41C40504 --> ((0x41C40504 - 0x41C40000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: (valid only in privilege mode) '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: (valid only in privilege mode) '0' - access not allowed '1' - access allowed

5.6.56 FWMEMSS2 Register (Offset = 1A4h) [Reset = 00000000h]

FWMEMSS2 is shown in Table 5-79.

Return to the Summary Table.

MEMSS region 2 firewall access permission for 3 controller id : 0 - M33 Non Secured (valid only in privilege mode) 1 - M33 Secured (valid only in privilege mode) 2 - Core (Non Secure) MEMSS address space: 0x41C00000 - 0x41CCFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max window size is 256Kb (M33D banks) + 10*32K (Flex) = 576Kb

Table 5-79 FWMEMSS2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25-16	LEN	R/W	0h	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id MEMSS address space: 0x41C00000 - 0x41CCFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max window size is 576Kb example: worker base address: 0x41C40000 current address to access: 0x41C41514 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x41C41514 --> ((0x41C41514 - 0x41C40000) >> 10) -->0x5 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules
15-14	RESERVED	R	0h	Reserved
13-4	BASE	R/W	0h	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id MEMSS address space: 0x41C00000 - 0x41DFFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max base value is 0x23F max window size is 576Kb example: worker base address: 0x41C40000 current address to access: 0x41C40504 region_base_address: 0x1 region_base_address_len: 0x1 0x41C40504 --> ((0x41C40504 - 0x41C40000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: (valid only in privilege mode) '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 non Secured: (valid only in privilege mode) '0' - access not allowed '1' - access allowed

5.6.57 FWHOSTAON Register (Offset = 1A8h) [Reset = 00000000h]

FWHOSTAON is shown in Table 5-80.

Return to the Summary Table.

HOST_AON_SLV firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-80 FWHOSTAON Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.58 FWHIF Register (Offset = 1B0h) [Reset = 00000000h]

FWHIF is shown in Table 5-81.

Return to the Summary Table.

HIF firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure) - Not in use , core always has access.

Table 5-81 FWHIF Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.59 FWHOST0 Register (Offset = 1B4h) [Reset = 00000000h]

FWHOST0 is shown in Table 5-82.

Return to the Summary Table.

HOST MCU region 0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-82 FWHOST0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25-16	LEN	R/W	0h	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_0 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_0 base_len can range from: ##register base_len value## 0x0 - 0x7F for HOST_MCU_REGION_0 the base address for security firewalls is 0x23F80000 ( HOST_MCU_REGION_0 ) max window size is 128Kb example: worker base address: 0x23F80000 current address to access: 0x23F81504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x23F81504 --> ((0x23F81504 - 0x23F80000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules
15	RESERVED	R	0h	Reserved
14-4	BASE	R/W	0h	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_0 is assigned to TCM DATA RAM HOST_MCU_REGION_0 base address can range from: ##register base value## 0x0 - 0x27F ##absolute equivalent value## 0x23F800000 - 0x2401FC00 for HOST_MCU_REGION_0 the base address for security firewalls is 0x23F80000 ( M33 TCM Data RAM ) max window size is 128Kb example: worker base address: 0x23F80000 current address to access: 0x23F80504 region_base_address: 0x1 region_base_address_len: 0x1 0x23F80504 --> ((0x23F80504 - 0x23F800000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.60 FWHOST1 Register (Offset = 1B8h) [Reset = 00000000h]

FWHOST1 is shown in Table 5-83.

Return to the Summary Table.

HOST MCU region 1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-83 FWHOST1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25-16	LEN	R/W	0h	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_0 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_0 base_len can range from: ##register base_len value## 0x0 - 0x7F for HOST_MCU_REGION_0 the base address for security firewalls is 0x23F80000 ( HOST_MCU_REGION_1 ) max window size is 128Kb example: worker base address: 0x23F80000 current address to access: 0x23F81504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x23F81504 --> ((0x23F81504 - 0x23F80000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules
15	RESERVED	R	0h	Reserved
14-4	BASE	R/W	0h	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_1 is assigned to TCM DATA RAM HOST_MCU_REGION_1 base address can range from: ##register base value## 0x0 - 0x27F ##absolute equivalent value## 0x23F800000 - 0x2401FC00 for HOST_MCU_REGION_0 the base address for security firewalls is 0x23F80000 ( M33 TCM Data RAM ) max window size is 128Kb example: worker base address: 0x23F80000 current address to access: 0x23F80504 region_base_address: 0x1 region_base_address_len: 0x1 0x23F80504 --> ((0x23F80504 - 0x23F800000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.61 FWHOST2 Register (Offset = 1BCh) [Reset = 00000000h]

FWHOST2 is shown in Table 5-84.

Return to the Summary Table.

HOST MCU region 2 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-84 FWHOST2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25-16	LEN	R/W	0h	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_2 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_2 base_len can range from: ##register base_len value## 0x0 - 0x240 for HOST_MCU_REGION_0 the base address for security firewalls is 0x2BF00000 ( HOST_MCU_REGION_2 ) max window size is 576Kb example: worker base address: 0x2BF00000 current address to access: 0x2BF01504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x2BF01504 --> ((0x2BF01504 - 0x2BF00000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules
15	RESERVED	R	0h	Reserved
14-4	BASE	R/W	0h	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_2 is assigned to M33 DATA RAM HOST_MCU_REGION_2 base address can range from: ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF00000 - 0x2C08FC00 for HOST_MCU_REGION_2 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF000000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF000000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.62 FWHOST3 Register (Offset = 1C0h) [Reset = 00000000h]

FWHOST3 is shown in Table 5-85.

Return to the Summary Table.

HOST MCU region 3 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-85 FWHOST3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25-16	LEN	R/W	0h	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_2 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_2 base_len can range from: ##register base_len value## 0x0 - 0x240 for HOST_MCU_REGION_0 the base address for security firewalls is 0x2BF00000 ( HOST_MCU_REGION_2 ) max window size is 576Kb example: worker base address: 0x2BF00000 current address to access: 0x2BF01504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x2BF01504 --> ((0x2BF01504 - 0x2BF00000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules
15	RESERVED	R	0h	Reserved
14-4	BASE	R/W	0h	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_3 is assigned to M33 DATA RAM HOST_MCU_REGION_3 base address can range from: ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF00000 - 0x2C08FC00 for HOST_MCU_REGION_2 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF000000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF000000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.63 FWHOST4 Register (Offset = 1C4h) [Reset = 00000000h]

FWHOST4 is shown in Table 5-86.

Return to the Summary Table.

access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-86 FWHOST4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26	BASESEL	R/W	0h	Base select for Reserved region defaulted to M33 TCM Data RAM (base_sel = 0): this select bit will assign this region to either TCM Data (base_sel = 0) ##register base value## 0x0 - 0x80 ##absolute equivalent value## 0x200000000 - 0x20001FFFF or Data RAM (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF00000 - 0x2C08FC00 for HOST_MCU_REGION_4 with base_sel = 0 the base address for security firewalls is 0x23F80000 ( M33 TCM Data RAM ) max window size is 128Kb (depending on the MEMSS mode) for HOST_MCU_REGION_4 with base_sel = 1 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF00000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
25-16	LEN	R/W	0h	address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_4 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_4 base_len can range from: base_sel = 0 ##register base_len value## 0x0 - 0x7F base_sel = 0 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM M33 Data RAM ) max window size is 128Kb ################# base_sel = 1 ##register base_len value## 0x0 - 0x240 base_sel = 1 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 (M33 Data RAM ) max window size is 576Kb ################# example: worker base address: 0x23F80000 current address to access: 0x23F81504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x23F81504 --> ((0x23F81504 - 0x23F80000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules
15	RESERVED	R	0h	Reserved
14-4	BASE	R/W	0h	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_4 is assigned to TCM DATA RAM (base_sel = 0) or M33 Data Ram (base_sel = 1) HOST_MCU_REGION_4 base address can range from: (base_sel = 0) ##register base value## 0x0 - 0x27F ##absolute equivalent value## 0x23F80000 - 0x2401FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM Data RAM ) max window size is 128Kb ################## (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF000000 - 0x2C08FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF000000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.64 FWHOST5 Register (Offset = 1C8h) [Reset = 00000000h]

FWHOST5 is shown in Table 5-87.

Return to the Summary Table.

HOST MCU region 5 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-87 FWHOST5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26	BASESEL	R/W	0h	Base select for Reserved region defaulted to M33 TCM Data RAM (base_sel = 0): this select bit will assign this region to either TCM Data (base_sel = 0) ##register base value## 0x0 - 0x80 ##absolute equivalent value## 0x200000000 - 0x20001FFFF or Data RAM (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF00000 - 0x2C08FC00 for HOST_MCU_REGION_4 with base_sel = 0 the base address for security firewalls is 0x23F80000 ( M33 TCM Data RAM ) max window size is 128Kb (depending on the MEMSS mode) for HOST_MCU_REGION_4 with base_sel = 1 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF00000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
25-16	LEN	R/W	0h	address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_4 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_4 base_len can range from: base_sel = 0 ##register base_len value## 0x0 - 0x7F base_sel = 0 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM M33 Data RAM ) max window size is 128Kb ################# base_sel = 1 ##register base_len value## 0x0 - 0x240 base_sel = 1 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 (M33 Data RAM ) max window size is 576Kb ################# example: worker base address: 0x23F80000 current address to access: 0x23F81504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x23F81504 --> ((0x23F81504 - 0x23F80000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules
15	RESERVED	R	0h	Reserved
14-4	BASE	R/W	0h	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_4 is assigned to TCM DATA RAM (base_sel = 0) or M33 Data Ram (base_sel = 1) HOST_MCU_REGION_4 base address can range from: (base_sel = 0) ##register base value## 0x0 - 0x27F ##absolute equivalent value## 0x23F80000 - 0x2401FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM Data RAM ) max window size is 128Kb ################## (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF000000 - 0x2C08FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF000000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.65 FWHOST6 Register (Offset = 1CCh) [Reset = 00000000h]

FWHOST6 is shown in Table 5-88.

Return to the Summary Table.

HOST MCU region 6 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-88 FWHOST6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26	BASESEL	R/W	1h	Base select for Reserved region defaulted to M33 TCM Data RAM (base_sel = 0): this select bit will assign this region to either TCM Data (base_sel = 0) ##register base value## 0x0 - 0x80 ##absolute equivalent value## 0x200000000 - 0x20001FFFF or Data RAM (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF00000 - 0x2C08FC00 for HOST_MCU_REGION_4 with base_sel = 0 the base address for security firewalls is 0x23F80000 ( M33 TCM Data RAM ) max window size is 128Kb (depending on the MEMSS mode) for HOST_MCU_REGION_4 with base_sel = 1 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF00000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
25-16	LEN	R/W	0h	address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_4 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_4 base_len can range from: base_sel = 0 ##register base_len value## 0x0 - 0x7F base_sel = 0 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM M33 Data RAM ) max window size is 128Kb ################# base_sel = 1 ##register base_len value## 0x0 - 0x240 base_sel = 1 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 (M33 Data RAM ) max window size is 576Kb ################# example: worker base address: 0x23F80000 current address to access: 0x23F81504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x23F81504 --> ((0x23F81504 - 0x23F80000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules
15	RESERVED	R	0h	Reserved
14-4	BASE	R/W	0h	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_4 is assigned to TCM DATA RAM (base_sel = 0) or M33 Data Ram (base_sel = 1) HOST_MCU_REGION_4 base address can range from: (base_sel = 0) ##register base value## 0x0 - 0x27F ##absolute equivalent value## 0x23F80000 - 0x2401FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM Data RAM ) max window size is 128Kb ################## (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF000000 - 0x2C08FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF000000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.66 FWHOST7 Register (Offset = 1D0h) [Reset = 00000000h]

FWHOST7 is shown in Table 5-89.

Return to the Summary Table.

HOST MCU region 7 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-89 FWHOST7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26	BASESEL	R/W	01h	Base select for Reserved region defaulted to M33 TCM Data RAM (base_sel = 0): this select bit will assign this region to either TCM Data (base_sel = 0) ##register base value## 0x0 - 0x80 ##absolute equivalent value## 0x200000000 - 0x20001FFFF or Data RAM (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF00000 - 0x2C08FC00 for HOST_MCU_REGION_4 with base_sel = 0 the base address for security firewalls is 0x23F80000 ( M33 TCM Data RAM ) max window size is 128Kb (depending on the MEMSS mode) for HOST_MCU_REGION_4 with base_sel = 1 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF00000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
25-16	LEN	R/W	0h	address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_4 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_4 base_len can range from: base_sel = 0 ##register base_len value## 0x0 - 0x7F base_sel = 0 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM M33 Data RAM ) max window size is 128Kb ################# base_sel = 1 ##register base_len value## 0x0 - 0x240 base_sel = 1 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 (M33 Data RAM ) max window size is 576Kb ################# example: worker base address: 0x23F80000 current address to access: 0x23F81504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x23F81504 --> ((0x23F81504 - 0x23F80000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules
15	RESERVED	R	0h	Reserved
14-4	BASE	R/W	0h	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_4 is assigned to TCM DATA RAM (base_sel = 0) or M33 Data Ram (base_sel = 1) HOST_MCU_REGION_4 base address can range from: (base_sel = 0) ##register base value## 0x0 - 0x27F ##absolute equivalent value## 0x23F80000 - 0x2401FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM Data RAM ) max window size is 128Kb ################## (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF000000 - 0x2C08FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF000000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.67 FWHOST8 Register (Offset = 1D4h) [Reset = 00000000h]

FWHOST8 is shown in Table 5-90.

Return to the Summary Table.

HOST MCU region 8 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-90 FWHOST8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.68 FWHOST9 Register (Offset = 1D8h) [Reset = 00000000h]

FWHOST9 is shown in Table 5-91.

Return to the Summary Table.

HOST MCU region 9 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-91 FWHOST9 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.69 FWHOST10 Register (Offset = 1DCh) [Reset = 00000000h]

FWHOST10 is shown in Table 5-92.

Return to the Summary Table.

HOST MCU region 10 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-92 FWHOST10 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.70 FWHOST11 Register (Offset = 1E0h) [Reset = 00000000h]

FWHOST11 is shown in Table 5-93.

Return to the Summary Table.

HOST MCU region 11 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-93 FWHOST11 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.71 FWXIPOSPI Register (Offset = 1E4h) [Reset = 00000000h]

FWXIPOSPI is shown in Table 5-94.

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XIP_OSPI firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-94 FWXIPOSPI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.72 FWXIPINDAC Register (Offset = 1E8h) [Reset = 00000000h]

FWXIPINDAC is shown in Table 5-95.

Return to the Summary Table.

OSPI_INDAC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-95 FWXIPINDAC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.73 FWXIPGEN Register (Offset = 1ECh) [Reset = 00000000h]

FWXIPGEN is shown in Table 5-96.

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XIP_GEN firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-96 FWXIPGEN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.74 FWXIPUDMAS Register (Offset = 1F0h) [Reset = 00000000h]

FWXIPUDMAS is shown in Table 5-97.

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XIP_UDMA_SEC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-97 FWXIPUDMAS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.75 FWXIPUDMANS Register (Offset = 1F4h) [Reset = 00000000h]

FWXIPUDMANS is shown in Table 5-98.

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UDMA_NONSEC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-98 FWXIPUDMANS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.76 FWOTFDE0 Register (Offset = 1F8h) [Reset = 00000000h]

FWOTFDE0 is shown in Table 5-99.

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OTFDE_REGION0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-99 FWOTFDE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.77 FWOTFDE1 Register (Offset = 1FCh) [Reset = 00000000h]

FWOTFDE1 is shown in Table 5-100.

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OTFDE_REGION1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-100 FWOTFDE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.78 FWOTFDE2 Register (Offset = 200h) [Reset = 00000000h]

FWOTFDE2 is shown in Table 5-101.

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OTFDE_REGION2 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-101 FWOTFDE2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.79 FWOTFDE3 Register (Offset = 204h) [Reset = 00000000h]

FWOTFDE3 is shown in Table 5-102.

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OTFDE_REGION3 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-102 FWOTFDE3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.80 FWDMAGEN Register (Offset = 208h) [Reset = 00000000h]

FWDMAGEN is shown in Table 5-103.

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DMA_GEN firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-103 FWDMAGEN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.81 FWDMA0 Register (Offset = 20Ch) [Reset = 00000000h]

FWDMA0 is shown in Table 5-104.

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DMA_CH_0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-104 FWDMA0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.82 FWDMA1 Register (Offset = 210h) [Reset = 00000000h]

FWDMA1 is shown in Table 5-105.

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DMA_CH_1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-105 FWDMA1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.83 FWDMA2 Register (Offset = 214h) [Reset = 00000000h]

FWDMA2 is shown in Table 5-106.

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DMA_CH_2 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-106 FWDMA2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.84 FWDMA3 Register (Offset = 218h) [Reset = 00000000h]

FWDMA3 is shown in Table 5-107.

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DMA_CH_3 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-107 FWDMA3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.85 FWDMA4 Register (Offset = 21Ch) [Reset = 00000000h]

FWDMA4 is shown in Table 5-108.

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DMA_CH_4 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-108 FWDMA4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.86 FWDMA5 Register (Offset = 220h) [Reset = 00000000h]

FWDMA5 is shown in Table 5-109.

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DMA_CH_5 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-109 FWDMA5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.87 FWDMA6 Register (Offset = 224h) [Reset = 00000000h]

FWDMA6 is shown in Table 5-110.

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DMA_CH_6 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-110 FWDMA6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.88 FWDMA7 Register (Offset = 228h) [Reset = 00000000h]

FWDMA7 is shown in Table 5-111.

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DMA_CH_7 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-111 FWDMA7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.89 FWDMA8 Register (Offset = 22Ch) [Reset = 00000000h]

FWDMA8 is shown in Table 5-112.

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DMA_CH_8 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-112 FWDMA8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.90 FWDMA9 Register (Offset = 230h) [Reset = 00000000h]

FWDMA9 is shown in Table 5-113.

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DMA_CH_9 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-113 FWDMA9 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.91 FWDMA10 Register (Offset = 234h) [Reset = 00000000h]

FWDMA10 is shown in Table 5-114.

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DMA_CH_10 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-114 FWDMA10 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.92 FWDMA11 Register (Offset = 238h) [Reset = 00000000h]

FWDMA11 is shown in Table 5-115.

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DMA_CH_11 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-115 FWDMA11 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.93 FWHSMEIPNS Register (Offset = 23Ch) [Reset = 00000000h]

FWHSMEIPNS is shown in Table 5-116.

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HSM EIP NONSEC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-116 FWHSMEIPNS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-21	RESERVED	R	0h	Reserved
20-16	LEN	R/W	0h	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HSM address space: 0x41B00000 - 0x41B3FFFF HSM_EIP_REGS base_len can range from: ##register base_len value## 0x0 - 0xF for HSM the base address for security firewalls is 0x41B00000 ( HSM_EIP_REGS ) max window size is 16Kb example: worker base address: 0x41B00000 current address to access: 0x41B01504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x41B01504 --> ((0x41B01504 - 0x41B00000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules
15-9	RESERVED	R	0h	Reserved
8-4	BASE	R/W	0h	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HSM address space: 0x41B00000 - 0x41B3FFFF HSM_EIP_REGS base address can range from: ##register base value## 0x0 - 0xF ##absolute equivalent value## 0x41B00000 - 0x41B03FFF for HSM the base address for security firewalls is 0x41B00000 ( HSM_EIP_REGS ) max window size is 16Kb example: worker base address: 0x41B00000 current address to access: 0x41B00504 region_base_address: 0x1 region_base_address_len: 0x1 0x41B00504 --> ((0x41B00504 - 0x41B00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.94 FWHSMEIPS Register (Offset = 240h) [Reset = 00000000h]

FWHSMEIPS is shown in Table 5-117.

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HSM EIP SEC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-117 FWHSMEIPS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-21	RESERVED	R	0h	Reserved
20-16	LEN	R/W	0h	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HSM address space: 0x41B00000 - 0x41B3FFFF HSM_EIP_REGS base_len can range from: ##register base_len value## 0x0 - 0xF for HSM the base address for security firewalls is 0x41B00000 ( HSM_EIP_REGS ) max window size is 16Kb example: worker base address: 0x41B00000 current address to access: 0x41B01504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x41B01504 --> ((0x41B01504 - 0x41B00000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules
15-9	RESERVED	R	0h	Reserved
8-4	BASE	R/W	0h	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HSM address space: 0x41B00000 - 0x41B3FFFF HSM_EIP_REGS base address can range from: ##register base value## 0x0 - ##absolute equivalent value## 0x41B00000 - 0x41B03FFF for HSM the base address for security firewalls is 0x41B00000 ( HSM_EIP_REGS ) max window size is 16Kb example: worker base address: 0x41B00000 current address to access: 0x41B00504 region_base_address: 0x1 region_base_address_len: 0x1 0x41B00504 --> ((0x41B00504 - 0x41B00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules
3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.95 FWHSMWRAPNS Register (Offset = 244h) [Reset = 00000000h]

FWHSMWRAPNS is shown in Table 5-118.

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HSM Wrapper NONSEC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-118 FWHSMWRAPNS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.96 FWHSMWRAPS Register (Offset = 248h) [Reset = 00000000h]

FWHSMWRAPS is shown in Table 5-119.

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HSM Wrapper SEC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-119 FWHSMWRAPS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.97 FWHSMDBG Register (Offset = 24Ch) [Reset = 00000000h]

FWHSMDBG is shown in Table 5-120.

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HSM DEBUG firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-120 FWHSMDBG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.98 FWI2C0 Register (Offset = 250h) [Reset = 00000000h]

FWI2C0 is shown in Table 5-121.

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I2C0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-121 FWI2C0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.99 FWI2C1 Register (Offset = 254h) [Reset = 00000000h]

FWI2C1 is shown in Table 5-122.

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I2C1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-122 FWI2C1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.100 FWSPSPI0 Register (Offset = 258h) [Reset = 00000000h]

FWSPSPI0 is shown in Table 5-123.

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SPI0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-123 FWSPSPI0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.101 FWSPSPI1 Register (Offset = 25Ch) [Reset = 00000000h]

FWSPSPI1 is shown in Table 5-124.

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SPI1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-124 FWSPSPI1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.102 FWSPUART0 Register (Offset = 260h) [Reset = 00000000h]

FWSPUART0 is shown in Table 5-125.

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UART0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-125 FWSPUART0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.103 FWSPUART1 Register (Offset = 264h) [Reset = 00000000h]

FWSPUART1 is shown in Table 5-126.

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UART1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-126 FWSPUART1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.104 FWSPGPT0 Register (Offset = 268h) [Reset = 00000000h]

FWSPGPT0 is shown in Table 5-127.

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GPTIMER0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-127 FWSPGPT0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.105 FWSPGPT1 Register (Offset = 26Ch) [Reset = 00000000h]

FWSPGPT1 is shown in Table 5-128.

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GPTIMER1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-128 FWSPGPT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.106 FWSPI2S Register (Offset = 270h) [Reset = 00000000h]

FWSPI2S is shown in Table 5-129.

Return to the Summary Table.

I2S firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-129 FWSPI2S Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.107 FWPDM Register (Offset = 274h) [Reset = 00000000h]

FWPDM is shown in Table 5-130.

Return to the Summary Table.

PDM firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-130 FWPDM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.108 FWSPCAN Register (Offset = 278h) [Reset = 00000000h]

FWSPCAN is shown in Table 5-131.

Return to the Summary Table.

CAN firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-131 FWSPCAN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.109 FWSPADC Register (Offset = 27Ch) [Reset = 00000000h]

FWSPADC is shown in Table 5-132.

Return to the Summary Table.

ADC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-132 FWSPADC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.110 FWSPSDMMC Register (Offset = 280h) [Reset = 00000000h]

FWSPSDMMC is shown in Table 5-133.

Return to the Summary Table.

SDMMC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-133 FWSPSDMMC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.111 FWSPSDIO Register (Offset = 284h) [Reset = 00000000h]

FWSPSDIO is shown in Table 5-134.

Return to the Summary Table.

SDIO firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-134 FWSPSDIO Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.112 FWSPUART2 Register (Offset = 288h) [Reset = 00000000h]

FWSPUART2 is shown in Table 5-135.

Return to the Summary Table.

UART2 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-135 FWSPUART2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.113 UDMANSCTL Register (Offset = 28Ch) [Reset = 00000000h]

UDMANSCTL is shown in Table 5-136.

Return to the Summary Table.

uDMA Non-secured Channel Control.

Table 5-136 UDMANSCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ACCPER	R/W	0h	Access Permission. Define uDMA non-sec channel access permission to secured flash address: '0' - access not allowed '1' - access allowed

5.6.114 FWIOPAD0 Register (Offset = 290h) [Reset = 00000000h]

FWIOPAD0 is shown in Table 5-137.

Return to the Summary Table.

IOMUX_PAD_0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-137 FWIOPAD0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.115 FWIOPAD1 Register (Offset = 294h) [Reset = 00000000h]

FWIOPAD1 is shown in Table 5-138.

Return to the Summary Table.

IOMUX_PAD_1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-138 FWIOPAD1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.116 FWIOPAD2 Register (Offset = 298h) [Reset = 00000000h]

FWIOPAD2 is shown in Table 5-139.

Return to the Summary Table.

IOMUX_PAD_2 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-139 FWIOPAD2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.117 FWIOPAD3 Register (Offset = 29Ch) [Reset = 00000000h]

FWIOPAD3 is shown in Table 5-140.

Return to the Summary Table.

IOMUX_PAD_3 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-140 FWIOPAD3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.118 FWIOPAD4 Register (Offset = 2A0h) [Reset = 00000000h]

FWIOPAD4 is shown in Table 5-141.

Return to the Summary Table.

IOMUX_PAD_4 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-141 FWIOPAD4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.119 FWIOPAD5 Register (Offset = 2A4h) [Reset = 00000000h]

FWIOPAD5 is shown in Table 5-142.

Return to the Summary Table.

IOMUX_PAD_5 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-142 FWIOPAD5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.120 FWIOPAD6 Register (Offset = 2A8h) [Reset = 00000000h]

FWIOPAD6 is shown in Table 5-143.

Return to the Summary Table.

IOMUX_PAD_6 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-143 FWIOPAD6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.121 FWIOPAD7 Register (Offset = 2ACh) [Reset = 00000000h]

FWIOPAD7 is shown in Table 5-144.

Return to the Summary Table.

IOMUX_PAD_7 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-144 FWIOPAD7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.122 FWIOPAD8 Register (Offset = 2B0h) [Reset = 00000000h]

FWIOPAD8 is shown in Table 5-145.

Return to the Summary Table.

IOMUX_PAD_8 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-145 FWIOPAD8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.123 FWIOPAD9 Register (Offset = 2B4h) [Reset = 00000000h]

FWIOPAD9 is shown in Table 5-146.

Return to the Summary Table.

IOMUX_PAD_9 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-146 FWIOPAD9 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.124 FWIOPAD10 Register (Offset = 2B8h) [Reset = 00000000h]

FWIOPAD10 is shown in Table 5-147.

Return to the Summary Table.

IOMUX_PAD_10 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-147 FWIOPAD10 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.125 FWIOPAD11 Register (Offset = 2BCh) [Reset = 00000000h]

FWIOPAD11 is shown in Table 5-148.

Return to the Summary Table.

IOMUX_PAD_11 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-148 FWIOPAD11 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.126 FWIOPAD12 Register (Offset = 2C0h) [Reset = 00000000h]

FWIOPAD12 is shown in Table 5-149.

Return to the Summary Table.

IOMUX_PAD_12 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-149 FWIOPAD12 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.127 FWIOPAD13 Register (Offset = 2C4h) [Reset = 00000000h]

FWIOPAD13 is shown in Table 5-150.

Return to the Summary Table.

IOMUX_PAD_13 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-150 FWIOPAD13 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.128 FWIOPAD14 Register (Offset = 2C8h) [Reset = 00000000h]

FWIOPAD14 is shown in Table 5-151.

Return to the Summary Table.

IOMUX_PAD_14 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-151 FWIOPAD14 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.129 FWIOPAD15 Register (Offset = 2CCh) [Reset = 00000000h]

FWIOPAD15 is shown in Table 5-152.

Return to the Summary Table.

IOMUX_PAD_15 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-152 FWIOPAD15 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.130 FWIOPAD16 Register (Offset = 2D0h) [Reset = 00000000h]

FWIOPAD16 is shown in Table 5-153.

Return to the Summary Table.

IOMUX_PAD_16 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-153 FWIOPAD16 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.131 FWIOPAD17 Register (Offset = 2D4h) [Reset = 00000000h]

FWIOPAD17 is shown in Table 5-154.

Return to the Summary Table.

IOMUX_PAD_17 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-154 FWIOPAD17 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.132 FWIOPAD18 Register (Offset = 2D8h) [Reset = 00000000h]

FWIOPAD18 is shown in Table 5-155.

Return to the Summary Table.

IOMUX_PAD_18 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-155 FWIOPAD18 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.133 FWIOPAD19 Register (Offset = 2DCh) [Reset = 00000000h]

FWIOPAD19 is shown in Table 5-156.

Return to the Summary Table.

IOMUX_PAD_19 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-156 FWIOPAD19 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.134 FWIOPAD20 Register (Offset = 2E0h) [Reset = 00000000h]

FWIOPAD20 is shown in Table 5-157.

Return to the Summary Table.

IOMUX_PAD_20 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-157 FWIOPAD20 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.135 FWIOPAD21 Register (Offset = 2E4h) [Reset = 00000000h]

FWIOPAD21 is shown in Table 5-158.

Return to the Summary Table.

IOMUX_PAD_21 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-158 FWIOPAD21 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.136 FWIOPAD22 Register (Offset = 2E8h) [Reset = 00000000h]

FWIOPAD22 is shown in Table 5-159.

Return to the Summary Table.

IOMUX_PAD_22 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-159 FWIOPAD22 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.137 FWIOPAD23 Register (Offset = 2ECh) [Reset = 00000000h]

FWIOPAD23 is shown in Table 5-160.

Return to the Summary Table.

IOMUX_PAD_23 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-160 FWIOPAD23 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.138 FWIOPAD24 Register (Offset = 2F0h) [Reset = 00000000h]

FWIOPAD24 is shown in Table 5-161.

Return to the Summary Table.

IOMUX_PAD_24 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-161 FWIOPAD24 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.139 FWIOPAD25 Register (Offset = 2F4h) [Reset = 00000000h]

FWIOPAD25 is shown in Table 5-162.

Return to the Summary Table.

IOMUX_PAD_25 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-162 FWIOPAD25 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.140 FWIOPAD26 Register (Offset = 2F8h) [Reset = 00000000h]

FWIOPAD26 is shown in Table 5-163.

Return to the Summary Table.

IOMUX_PAD_26 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-163 FWIOPAD26 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.141 FWIOPAD27 Register (Offset = 2FCh) [Reset = 00000000h]

FWIOPAD27 is shown in Table 5-164.

Return to the Summary Table.

IOMUX_PAD_27 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-164 FWIOPAD27 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.142 FWIOPAD28 Register (Offset = 300h) [Reset = 00000000h]

FWIOPAD28 is shown in Table 5-165.

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IOMUX_PAD_28 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-165 FWIOPAD28 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.143 FWIOPAD29 Register (Offset = 304h) [Reset = 00000000h]

FWIOPAD29 is shown in Table 5-166.

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IOMUX_PAD_29 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-166 FWIOPAD29 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.144 FWIOPAD30 Register (Offset = 308h) [Reset = 00000000h]

FWIOPAD30 is shown in Table 5-167.

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IOMUX_PAD_30 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-167 FWIOPAD30 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.145 FWIOPAD31 Register (Offset = 30Ch) [Reset = 00000000h]

FWIOPAD31 is shown in Table 5-168.

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IOMUX_PAD_31 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-168 FWIOPAD31 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.146 FWIOPAD32 Register (Offset = 310h) [Reset = 00000000h]

FWIOPAD32 is shown in Table 5-169.

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IOMUX_PAD_32 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-169 FWIOPAD32 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.147 FWIOPAD33 Register (Offset = 314h) [Reset = 00000000h]

FWIOPAD33 is shown in Table 5-170.

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IOMUX_PAD_33 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-170 FWIOPAD33 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.148 FWIOPAD34 Register (Offset = 318h) [Reset = 00000000h]

FWIOPAD34 is shown in Table 5-171.

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IOMUX_PAD_34 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-171 FWIOPAD34 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.149 FWIOPAD35 Register (Offset = 31Ch) [Reset = 00000000h]

FWIOPAD35 is shown in Table 5-172.

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IOMUX_PAD_35 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-172 FWIOPAD35 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.150 FWIOPAD36 Register (Offset = 320h) [Reset = 00000000h]

FWIOPAD36 is shown in Table 5-173.

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IOMUX_PAD_36 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-173 FWIOPAD36 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.151 FWIOPAD37 Register (Offset = 324h) [Reset = 00000000h]

FWIOPAD37 is shown in Table 5-174.

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IOMUX_PAD_37 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-174 FWIOPAD37 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.152 FWIOPAD38 Register (Offset = 328h) [Reset = 00000000h]

FWIOPAD38 is shown in Table 5-175.

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IOMUX_PAD_38 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-175 FWIOPAD38 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.153 FWIOPAD39 Register (Offset = 32Ch) [Reset = 00000000h]

FWIOPAD39 is shown in Table 5-176.

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IOMUX_PAD_39 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-176 FWIOPAD39 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.154 FWIOPAD40 Register (Offset = 330h) [Reset = 00000000h]

FWIOPAD40 is shown in Table 5-177.

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IOMUX_PAD_40 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-177 FWIOPAD40 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.155 FWIOPAD41 Register (Offset = 334h) [Reset = 00000000h]

FWIOPAD41 is shown in Table 5-178.

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IOMUX_PAD_41 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-178 FWIOPAD41 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.156 FWIOPAD42 Register (Offset = 338h) [Reset = 00000000h]

FWIOPAD42 is shown in Table 5-179.

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IOMUX_PAD_42 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-179 FWIOPAD42 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.157 FWIOPAD43 Register (Offset = 33Ch) [Reset = 00000000h]

FWIOPAD43 is shown in Table 5-180.

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IOMUX_PAD_43 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-180 FWIOPAD43 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.158 FWIOPAD44 Register (Offset = 340h) [Reset = 00000000h]

FWIOPAD44 is shown in Table 5-181.

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IOMUX_PAD_44 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-181 FWIOPAD44 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.159 FWIOPAD45 Register (Offset = 344h) [Reset = 00000000h]

FWIOPAD45 is shown in Table 5-182.

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IOMUX_PAD_45 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-182 FWIOPAD45 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.160 FWIOPAD46 Register (Offset = 348h) [Reset = 00000000h]

FWIOPAD46 is shown in Table 5-183.

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IOMUX_PAD_46 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-183 FWIOPAD46 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.161 FWIOPAD47 Register (Offset = 34Ch) [Reset = 00000000h]

FWIOPAD47 is shown in Table 5-184.

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IOMUX_PAD_47 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-184 FWIOPAD47 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.162 FWIOPAD48 Register (Offset = 350h) [Reset = 00000000h]

FWIOPAD48 is shown in Table 5-185.

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IOMUX_PAD_48 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-185 FWIOPAD48 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.163 FWDMA12 Register (Offset = 354h) [Reset = 00000000h]

FWDMA12 is shown in Table 5-186.

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DMA_CH_12 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-186 FWDMA12 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.164 FWDMA13 Register (Offset = 358h) [Reset = 00000000h]

FWDMA13 is shown in Table 5-187.

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DMA_CH_13 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)

Table 5-187 FWDMA13 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	CORENS	R/W	0h	Controller Core Non Secured: '0' - access not allowed '1' - access allowed
1	M33S	R/W	0h	Controller M33 Secured: '0' - access not allowed '1' - access allowed
0	M33NS	R/W	0h	Controller M33 None Secured: '0' - access not allowed '1' - access allowed

5.6.165 USECSTB Register (Offset = 1000h) [Reset = 00000000h]

USECSTB is shown in Table 5-188.

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Micro Second STB

Table 5-188 USECSTB Register Field Descriptions

Bit	Field	Type	Reset	Description
31-14	RESERVED	R	0h	Reserved
13-8	16US	R/W	Fh	Set how many micro second strobes are in 16 micro seconds, minus 1. Default: 16-1 =15.
7-0	US	R/W	4Fh	Set how many soc clk are in one micro second, minus 1. for 40mhz : should be 39. for 80mhz : should be 79. (Soc clock default is 80MHz)

5.6.166 GPIOEVT0NS Register (Offset = 1044h) [Reset = 00000000h]

GPIOEVT0NS is shown in Table 5-189.

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Non-Secured GPIO Event Status, 1st Register. 45 bits status over two registers.

Table 5-189 GPIOEVT0NS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	STA31TO0	R	0h	Non-Secured event status , first 32 bits. ([31:0])

5.6.167 GPIOEVT1NS Register (Offset = 1048h) [Reset = 00000000h]

GPIOEVT1NS is shown in Table 5-190.

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Non-Secured GPIO Event Status, 2nd Register. 45 bits status over two registers.

Table 5-190 GPIOEVT1NS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R	0h	Reserved
12-0	STA44TO32	R	0h	Non-Secured event status , 13 MSBs. ([44:32])

5.6.168 DBM33NS0 Register (Offset = 1054h) [Reset = 00000000h]

DBM33NS0 is shown in Table 5-191.

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M33 Non-Secured Doorbell IMASK. Mask Event. '0' - CLR - Clear Interrupt Mask '1' - SET - Set Interrupt Mask

Table 5-191 DBM33NS0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-0	IMASK	R/W	0h	bit3 - doorbell 7 M3 IRQ bit2 - doorbell 6 M3 IRQ bit1 - doorbell 3 M3 IRQ bit0 - doorbell 2 M3 IRQ

5.6.169 DBNSISET Register (Offset = 1058h) [Reset = 00000000h]

DBNSISET is shown in Table 5-192.

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M33 Non-Secured Doorbells ISET. Sets event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Sets interrupt

Table 5-192 DBNSISET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-0	ISET	W	0h	bit3 - doorbell 7 M3 IRQ bit2 - doorbell 6 M3 IRQ bit1 - doorbell 3 M3 IRQ bit0 - doorbell 2 M3 IRQ Type: Write-Clear

5.6.170 DBNSICLR Register (Offset = 105Ch) [Reset = 00000000h]

DBNSICLR is shown in Table 5-193.

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M33 Non-Secured Doorbell ICLR. Clears event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clears the Event

Table 5-193 DBNSICLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-0	ICLR	W	0h	bit3 - doorbell 7 M3 IRQ bit2 - doorbell 6 M3 IRQ bit1 - doorbell 3 M3 IRQ bit0 - doorbell 2 M3 IRQ Type: Write-Clear

5.6.171 DBNSIMSET Register (Offset = 1060h) [Reset = 00000000h]

DBNSIMSET is shown in Table 5-194.

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M33 Non-Secured Doorbell IMSET. Sets Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Set interrupt mask

Table 5-194 DBNSIMSET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-0	IMSET	W	0h	bit3 - doorbell 7 M3 IRQ bit2 - doorbell 6 M3 IRQ bit1 - doorbell 3 M3 IRQ bit0 - doorbell 2 M3 IRQ Type: Write-Clear

5.6.172 DBNSIMCLR Register (Offset = 1064h) [Reset = 00000000h]

DBNSIMCLR is shown in Table 5-195.

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M33 Non-Secured Doorbell IMCLR, Clears Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clear interrupt mask

Table 5-195 DBNSIMCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-0	IMCLR	W	0h	bit3 - doorbell 7 M3 IRQ bit2 - doorbell 6 M3 IRQ bit1 - doorbell 3 M3 IRQ bit0 - doorbell 2 M3 IRQ Type: Write-Clear

5.6.173 DBNSRIS Register (Offset = 1068h) [Reset = 00000000h]

DBNSRIS is shown in Table 5-196.

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M33 Non-Secured Doorbell RIS. Raw interrupt status for event. This bit is set to 1 when an event is received. when the corresponding bit in ICLR is set to 1, this bit will be cleared. Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred

Table 5-196 DBNSRIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-0	RIS	R	0h	bit3 - doorbell 7 M3 IRQ bit2 - doorbell 6 M3 IRQ bit1 - doorbell 3 M3 IRQ bit0 - doorbell 2 M3 IRQ

5.6.174 DBNSMIS Register (Offset = 106Ch) [Reset = 00000000h]

DBNSMIS is shown in Table 5-197.

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M33 Non-Secured Doorbell MIS. Mask interrupt status for event Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred

Table 5-197 DBNSMIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-0	MIS	R	0h	bit3 - doorbell 7 M3 IRQ bit2 - doorbell 6 M3 IRQ bit1 - doorbell 3 M3 IRQ bit0 - doorbell 2 M3 IRQ

5.6.175 GPIOMIS0NS Register (Offset = 1070h) [Reset = 00000000h]

GPIOMIS0NS is shown in Table 5-198.

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Non Secured GPIO MIS. 31-0

Table 5-198 GPIOMIS0NS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	31TO0	R	0h	32 LSBs of GPIO MIS

5.6.176 GPIOMIS1NS Register (Offset = 1074h) [Reset = 00000000h]

GPIOMIS1NS is shown in Table 5-199.

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Non Secure GPIO MIS. 44-32

Table 5-199 GPIOMIS1NS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R	0h	Reserved
12-0	44TO32	R	0h	13 MSBs of GPIO MIS. 44-32

5.6.177 GPIOFNC0NS Register (Offset = 1078h) [Reset = 00000000h]

GPIOFNC0NS is shown in Table 5-200.

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Non Secured GPIO Functional Mask. 31-0 0. Mask 1. Un-Mask

Table 5-200 GPIOFNC0NS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	MASK31TO0	R/W	0h	32 LSBs of non-secured functional mask for GPIO.

5.6.178 GPIOFNC1NS Register (Offset = 107Ch) [Reset = 00000000h]

GPIOFNC1NS is shown in Table 5-201.

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non secured gpio functional mask

Table 5-201 GPIOFNC1NS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R	0h	Reserved
12-0	MASK44TO32	R/W	0h	13 MSBs of non-secured functional mask for GPIO. 44-32