SWRU626 December   2025 CC3501E , CC3551E

 

  1.   1
  2. 1 Read This First
    1. 1.1 About This Manual
    2. 1.2 Register, Field, and Bit Calls
    3.     Trademarks
  3. 2 Architecture Overview
    1. 2.1  Target Applications
    2. 2.2  Introduction
    3. 2.3  Internal System Diagram
    4. 2.4  Arm Cortex M33
      1. 2.4.1 Processor Core
      2. 2.4.2 SysTick Timer
      3. 2.4.3 Nested Vectored Interrupt Controller
      4. 2.4.4 System Control Block (SCB)
      5. 2.4.5 TI AI instruction extensions
    5. 2.5  Power Management
      1. 2.5.1 VDD_MAIN
      2. 2.5.2 VDD_IO
      3. 2.5.3 VDDSF
      4. 2.5.4 VDD_PA
    6. 2.6  Debug Subsystem (DEBUGSS)
    7. 2.7  Memory Subsystem (MEMSS)
      1. 2.7.1 External Memory Interface
    8. 2.8  Hardware Security Module
    9. 2.9  General Purpose Timers (GPT)
    10. 2.10 Real Time Clock (RTC)
    11. 2.11 Direct Memory Access
    12. 2.12 GPIOs
    13. 2.13 Communication Peripherals
      1. 2.13.1 UART
      2. 2.13.2 I2C
      3. 2.13.3 SPI
      4. 2.13.4 I2S
      5. 2.13.5 SDMMC
      6. 2.13.6 SDIO
      7. 2.13.7 CAN
      8. 2.13.8 ADC
  4. 3  Arm Cortex-M33 Processor
    1. 3.1 Arm Cortex-M33 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 M33 instantiation parameters
    4. 3.4 Arm Cortex-M33 System Peripheral Details
      1. 3.4.1 Floating Point Unit (FPU)
      2. 3.4.2 Memory Protection Unit (MPU)
      3. 3.4.3 Digital Signal Processing (DSP)
      4. 3.4.4 Security Attribution Unit (SAU)
      5. 3.4.5 System Timer
      6. 3.4.6 Nested Vectored Interrupt Controller
      7. 3.4.7 System Control Block
      8. 3.4.8 System Control Space
    5. 3.5 CPU Sub-System Peripheral Details
      1. 3.5.1 Trace Port Interface Unit (TPIU)
      2. 3.5.2 DAP Bridge and Debug Authentication
      3. 3.5.3 Implementation Defined Attribution Unit (IDAU)
    6. 3.6 Programming Model
      1. 3.6.1 Modes of operation and execution
        1. 3.6.1.1 Security states
        2. 3.6.1.2 Operating modes
        3. 3.6.1.3 Operating states
        4. 3.6.1.4 Privileged access and unprivileged user access
      2. 3.6.2 Instruction set summary
      3. 3.6.3 Memory model
        1. 3.6.3.1 Private Peripheral Bus
        2. 3.6.3.2 Unaligned accesses
      4. 3.6.4 Processor core registers summary
      5. 3.6.5 Exceptions
        1. 3.6.5.1 Exception handling and prioritization
    7. 3.7 TrustZone-M
      1. 3.7.1 Overview
      2. 3.7.2 M33 Configuration
      3. 3.7.3 Description of elements
        1. 3.7.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 3.7.3.1.1 Expected use
    8. 3.8 CC35xx Host MCU Registers
      1. 3.8.1 HOSTMCU_AON Registers
      2. 3.8.2 HOST_MCU Registers
      3. 3.8.3 HOST_MCU_SEC Registers
    9. 3.9 Arm® Cortex®-M33 Registers
      1. 3.9.1  CPU_ROM_TABLE Registers
      2. 3.9.2  TPIU Registers
      3. 3.9.3  DCB Registers
      4. 3.9.4  DIB Registers
      5. 3.9.5  DWT Registers
      6. 3.9.6  FPB Registers
      7. 3.9.7  FPE Registers
      8. 3.9.8  ICB Registers
      9. 3.9.9  ITM Registers
      10. 3.9.10 MPU Registers
      11. 3.9.11 NVIC Registers
      12. 3.9.12 SAU Registers
      13. 3.9.13 SCB Registers
      14. 3.9.14 SYSTIMER Registers
      15. 3.9.15 SYSTICK Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation to HardFault
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Manager
      1. 5.4.1 Introduction
      2. 5.4.2 Interrupts List
      3. 5.4.3 Wakeup Sources
      4. 5.4.4 Shared Peripherals MUX Selector
        1. 5.4.4.1 ADC HW Event Selector Mux
        2. 5.4.4.2 I2S HW Event Selector Mux
        3. 5.4.4.3 PDM HW Event Selector Mux
      5. 5.4.5 Timers MUX Selector Mux
        1. 5.4.5.1 SysTimer0 HW Event Selector Mux
        2. 5.4.5.2 SysTimer1 HW Event Selector Mux
        3. 5.4.5.3 RTC HW Event Selector Mux
      6. 5.4.6 GPTIMERs MUX Selector Mux
        1. 5.4.6.1 GPTIMER0 HW Event Selector Mux
        2. 5.4.6.2 GPTIMER1 HW Event Selector Mux
    5. 5.5 SOC_IC Registers
    6. 5.6 SOC_AON Registers
    7. 5.7 SOC_AAON Registers
  7. 6 Debug Subsystem (DEBUGSS)
    1. 6.1 Introduction
    2. 6.2 Block Diagram
    3. 6.3 Overview
    4. 6.4 Physical Interface
    5. 6.5 Debug Access Ports
    6. 6.6 Debug Features
      1. 6.6.1 Processor Debug
      2. 6.6.2 Breakpoint Unit (BPU)
      3. 6.6.3 Peripheral Debug
    7. 6.7 Behavior in Low Power Modes
    8. 6.8 Debug Access Control
    9. 6.9 SOC_DEBUGSS Registers
  8. 7 Power, Reset, Clock Management
    1. 7.1 Power Management
      1. 7.1.1 Power Supply System
        1. 7.1.1.1 VDD_MAIN
        2. 7.1.1.2 VIO
        3. 7.1.1.3 VDDSF
        4. 7.1.1.4 VPA
      2. 7.1.2 Power States
      3. 7.1.3 Power Domains
      4. 7.1.4 Brownout (BOR)
      5. 7.1.5 Boot Sequence
    2. 7.2 Reset
      1. 7.2.1 Reset Cause
      2. 7.2.2 Watchdog Timer (WDT)
    3. 7.3 Clocks
      1. 7.3.1 Fast Clock
      2. 7.3.2 Slow Clock
        1. 7.3.2.1 Slow Clock Overview
        2. 7.3.2.2 Slow Clock Tree
        3. 7.3.2.3 Slow Clock Boot Process
    4. 7.4 PRCM_AON Registers
    5. 7.5 PRCM_SCRATCHPAD Registers
  9. 8 Memory Subsystem (MEMSS)
    1. 8.1  Introduction
    2. 8.2  SRAM
    3. 8.3  D-Cache
    4. 8.4  Flash
    5. 8.5  PSRAM
    6. 8.6  XiP Memory Access
      1. 8.6.1 OTFDE
      2. 8.6.2 xSPI
      3. 8.6.3 Topology
      4. 8.6.4 µDMA
      5. 8.6.5 Arbiter
    7. 8.7  ICACHE Registers
    8. 8.8  DCACHE Registers
    9. 8.9  OSPI Registers
    10. 8.10 HOST_XIP Registers
  10. 9 Hardware Security Module (HSM)
    1. 9.1 Introduction
    2. 9.2 Overview
    3. 9.3 Mailbox and Register Access Firewall
    4. 9.4 DMA Firewall
    5. 9.5 HSM Key Storage
    6. 9.6 HSM Registers
    7. 9.7 HSM_NON_SEC Registers
    8. 9.8 HSM_SEC Registers
  11. 10Device Boot and Bootloader
    1. 10.1 CC35xx Boot Concept
    2. 10.2 Features
    3. 10.3 Vendor Images Format and Processing
      1. 10.3.1 External Flash Arrangement
      2. 10.3.2 Vendor Images Format
    4. 10.4 Boot Flows
      1. 10.4.1 Application Execution Boot Flow
      2. 10.4.2 Activation Flow
      3. 10.4.3 Initial Programming Flow
      4. 10.4.4 Reprogramming Flow
      5. 10.4.5 Wireless Connectivity Testing Tool Flow
    5. 10.5 Chain of Trust
  12. 11Direct Memory Access (DMA)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Channels Assignment
      2. 11.3.2 Transfer Types
      3. 11.3.3 Addressing Modes
      4. 11.3.4 Transfer Modes
      5. 11.3.5 DMA Aligner Support
      6. 11.3.6 Initiating DMA Transfers
      7. 11.3.7 Stopping DMA Transfers
      8. 11.3.8 Channel Priorities
      9. 11.3.9 DMA Interrupts
    4. 11.4 HOST_DMA Registers
  13. 12One Time Programming (OTP)
  14. 13General Purpose Timers (GPT)
    1. 13.1 Overview
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1  Prescaler
      2. 13.3.2  Counter
      3. 13.3.3  Target
      4. 13.3.4  Channel Input Logic
      5. 13.3.5  Channel Output Logic
      6. 13.3.6  Channel Actions
        1. 13.3.6.1 Period and Pulse Width Measurement
        2. 13.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 13.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 13.3.7  Channel Capture Configuration
      8. 13.3.8  Channel Filters
        1. 13.3.8.1 Setting up the Channel Filters
      9. 13.3.9  Synchronize Multiple GPTimers
      10. 13.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 13.4 Timer Modes
      1. 13.4.1 Quadrature Decoder
      2. 13.4.2 DMA
      3. 13.4.3 IR Generation
      4. 13.4.4 Fault and Park
      5. 13.4.5 Dead-Band
      6. 13.4.6 Dead-Band, Fault and Park
      7. 13.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 13.5 GPTIMER Registers
  15. 14System Timer (SysTimer)
    1. 14.1 Overview
    2. 14.2 Block Diagram
    3. 14.3 Functional Description
      1. 14.3.1 Common Channel Features
        1. 14.3.1.1 Compare Mode
        2. 14.3.1.2 Capture Mode
        3. 14.3.1.3 Additional Channel Arming Methods
      2. 14.3.2 Interrupts and Events
    4. 14.4 SYSRESOURCES Registers
    5. 14.5 SYSTIM Registers
  16. 15Real-Time Clock (RTC)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Interrupts and Events
      1. 15.3.1 Input Event
      2. 15.3.2 Output Event
      3. 15.3.3 Arming and Disarming Channels
    4. 15.4 CAPTURE and COMPARE Configurations
      1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
    5. 15.5 RTC Registers
  17. 16General Purpose Input/Output (GPIOs)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 I/O Mapping and Configuration
      1. 16.3.1 Basic I/O Mapping
      2. 16.3.2 Pin Mapping
    4. 16.4 Edge Detection
    5. 16.5 GPIO
    6. 16.6 I/O Pins
    7. 16.7 Unused Pins
    8. 16.8 IOMUX Registers
  18. 17Universal Asynchronous Receivers/Transmitters (UART)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 UART Functional Description
      1. 17.3.1 Transmit and Receive Logic
      2. 17.3.2 Baud Rate Generation
      3. 17.3.3 FIFO Operation
        1. 17.3.3.1 FIFO Remapping
      4. 17.3.4 Data Transmission
      5. 17.3.5 Flow Control
      6. 17.3.6 IrDA Encoding and Decoding
      7. 17.3.7 Interrupts
      8. 17.3.8 Loopback Operation
    4. 17.4 UART-LIN Specification
      1. 17.4.1 Break transmission in UART mode
      2. 17.4.2 Break reception in UART mode
      3. 17.4.3 Break/Synch transmission in LIN mode
      4. 17.4.4 Break/Synch reception in LIN mode
      5. 17.4.5 Dormant mode operation
      6. 17.4.6 Event signal generation
      7. 17.4.7 Event signal detection when device is in active/idle modes
      8. 17.4.8 Event signal detection when device is in sleep mode
    5. 17.5 Interface to Host DMA
    6. 17.6 Initialization and Configuration
    7. 17.7 UART Registers
  19. 18Serial Peripheral Interface (SPI)
    1. 18.1 Overview
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Signal Description
    3. 18.3 Functional Description
      1. 18.3.1  Clock Control
      2. 18.3.2  FIFO Operation
        1. 18.3.2.1 Transmit FIFO
        2. 18.3.2.2 Repeated Transmit Operation
        3. 18.3.2.3 Receive FIFO
        4. 18.3.2.4 FIFO Flush
      3. 18.3.3  Interrupts
      4. 18.3.4  Data Format
      5. 18.3.5  Delayed Data Sampling
      6. 18.3.6  Chip Select Control
      7. 18.3.7  Command Data Control
      8. 18.3.8  Protocol Descriptions
        1. 18.3.8.1 Motorola SPI Frame Format
        2. 18.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 18.3.8.3 MICROWIRE Frame Format
      9. 18.3.9  CRC Configuration
      10. 18.3.10 Auto CRC Functionality
      11. 18.3.11 SPI Status
      12. 18.3.12 Debug Halt
    4. 18.4 Host DMA Operation
    5. 18.5 Initialization and Configuration
    6. 18.6 SPI Registers
  20. 19Inter-Integrated Circuit (I2C) Interface
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Clock Control
        1. 19.3.1.1 Internal Clock
        2. 19.3.1.2 External Clock
      2. 19.3.2 General Architecture
        1. 19.3.2.1  Start and Stop Conditions
        2. 19.3.2.2  Data Format with 7-Bit Address
        3. 19.3.2.3  Data Format with 10-Bit Addressing
          1. 19.3.2.3.1 Additional 10-Bit Scenarios
        4. 19.3.2.4  Acknowledge
        5. 19.3.2.5  Repeated Start
        6. 19.3.2.6  Clock Stretching
        7. 19.3.2.7  Arbitration
        8. 19.3.2.8  Multi-Controller mode
        9. 19.3.2.9  Glitch Suppression
        10. 19.3.2.10 FIFO Operation
        11. 19.3.2.11 Burst Mode Operation
        12. 19.3.2.12 DMA Operation
        13. 19.3.2.13 Flush Stale Tx Data in Target Mode
          1. 19.3.2.13.1 Recommended Sequence
        14. 19.3.2.14 SMBUS 3.0 Support
          1. 19.3.2.14.1 Quick Command
          2. 19.3.2.14.2 Acknowledge Control
          3. 19.3.2.14.3 Alert Response protocol
          4. 19.3.2.14.4 Address Resolution Protocol
          5. 19.3.2.14.5 Enhanced Acknowledge Control
    4. 19.4 Initialization and Configuration
    5. 19.5 Interrupts
    6. 19.6 I2C Registers
  21. 20Secure Digital Multimedia Card (SDMMC)
    1. 20.1 Introduction
      1. 20.1.1 SDMMC Features
      2. 20.1.2 Integration
    2. 20.2 Functional Description
      1. 20.2.1  SDMMC Functional Modes
        1. 20.2.1.1 SDMMC Connected to an SD Card
        2. 20.2.1.2 Protocol and Data Format
          1. 20.2.1.2.1 Protocol
          2. 20.2.1.2.2 Data Format
      2. 20.2.2  SD Card Feedback
      3. 20.2.3  Resets
        1. 20.2.3.1 Hardware Reset
        2. 20.2.3.2 Software Reset
      4. 20.2.4  Interrupt Requests
        1. 20.2.4.1 Interrupt-Driven Operation
        2. 20.2.4.2 Polling
      5. 20.2.5  DMA Modes
        1. 20.2.5.1 DMA Peripheral Mode Operations
          1. 20.2.5.1.1 DMA Receive Mode
          2. 20.2.5.1.2 DMA Transmit Mode
      6. 20.2.6  Buffer Management
        1. 20.2.6.1 Data Buffer
          1. 20.2.6.1.1 Memory Size and Block Length
          2. 20.2.6.1.2 Data Buffer Status
      7. 20.2.7  Transfer Process
        1. 20.2.7.1 Different Types of Commands
        2. 20.2.7.2 Different Types of Responses
      8. 20.2.8  Transfer or Command Status and Error Reporting
        1. 20.2.8.1 Busy Timeout for R1b, R5b Response Type
        2. 20.2.8.2 Busy Timeout After Write CRC Status
        3. 20.2.8.3 Write CRC Status Timeout
        4. 20.2.8.4 Read Data Timeout
      9. 20.2.9  Auto Command 12 Timings
        1. 20.2.9.1 Auto Command 12 Timings During Write Transfer
        2. 20.2.9.2 Auto Command 12 Timings During Read Transfer
      10. 20.2.10 Transfer Stop
      11. 20.2.11 Output Signals Generation
        1. 20.2.11.1 Generation on Falling Edge of SDMMC Clock
        2. 20.2.11.2 Generation on Rising Edge of SDMMC Clock
      12. 20.2.12 Test Registers
      13. 20.2.13 SDMMC Hardware Status Features
    3. 20.3 Low-Level Programming Models
      1. 20.3.1 SDMMC Initialization Flow
        1. 20.3.1.1 Enable OCP and CLKADPI Clocks
        2. 20.3.1.2 SD Soft Reset Flow
        3. 20.3.1.3 Set SD Default Capabilities
        4. 20.3.1.4 SDMMC Host and Bus Configuration
      2. 20.3.2 Operational Modes Configuration
        1. 20.3.2.1 Basic Operations for SDMMC
        2. 20.3.2.2 Card Detection, Identification, and Selection
    4. 20.4 SDMMC Registers
  22. 21Secure Digital Input/Output (SDIO)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 SDIO Interface Description
      2. 21.3.2 Protocol and Data Format
      3. 21.3.3 I/O Read/Write Command
        1. 21.3.3.1 IO_WR_DIRECT Command (CMD52)
        2. 21.3.3.2 IO_WR_EXTENDED Command (CMD53)
      4. 21.3.4 Reset
      5. 21.3.5 FIFO Operation
        1. 21.3.5.1 Rx FIFO (For Host Write)
        2. 21.3.5.2 Tx FIFO (For Host Read)
      6. 21.3.6 Interrupt Request
        1. 21.3.6.1 External Host IRQ
        2. 21.3.6.2 M33 IRQ
      7. 21.3.7 Transaction Details
        1. 21.3.7.1 Host write to SDIO IP (Rx FIFO)
          1. 21.3.7.1.1 Host write to SDIO IP (Rx FIFO) – Long SW latency case
          2. 21.3.7.1.2 Host write to SDIO IP (Rx FIFO) – CRC Error Case
        2. 21.3.7.2 Host reads from SDIO (TX buffer)
    4. 21.4 SDIO_CORE Registers
    5. 21.5 SDIO_CARD_FN1 Registers
  23. 22Inter-Integrated Circuit Sound (I2S)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  Signal Descriptions
    4. 22.4  Functional Description
      1. 22.4.1 Pin Configuration
      2. 22.4.2 Serial Format Configuration
        1. 22.4.2.1 Register Configuration
      3. 22.4.3 Left-Justified (LJF)
        1. 22.4.3.1 Register Configuration
      4. 22.4.4 Right-Justified (RJF)
        1. 22.4.4.1 Register Configuration
      5. 22.4.5 DSP
        1. 22.4.5.1 Register Configuration
      6. 22.4.6 Clock Configuration
    5. 22.5  Memory Interface
      1. 22.5.1 Sample Word Length
      2. 22.5.2 Padding Mechanism
      3. 22.5.3 Channel Mapping
      4. 22.5.4 Sample Storage in Memory
      5. 22.5.5 DMA Operation
        1. 22.5.5.1 Start-Up
        2. 22.5.5.2 Operation
        3. 22.5.5.3 Shutdown
    6. 22.6  Samplestamp Generator
      1. 22.6.1 Samplestamp Counters
      2. 22.6.2 Start-Up Triggers
      3. 22.6.3 Samplestamp Capture
      4. 22.6.4 Achieving constant audio latency
    7. 22.7  Error Detection
    8. 22.8  Usage
      1. 22.8.1 Start-Up Sequence
      2. 22.8.2 Shutdown Sequence
    9. 22.9  I2S Configuration Guideline
    10. 22.10 I2S Registers
  24. 23Pulse Density Modulation (PDM)
    1. 23.1  Introduction
    2. 23.2  Block Diagram
    3. 23.3  Input Selection
      1. 23.3.1 PDM Data Mode
      2. 23.3.2 Manchester Input Mode
    4. 23.4  CIC Filter
      1. 23.4.1 Filter Design
      2. 23.4.2 Digital Filter Output
      3. 23.4.3 Offset Binary Mode
      4. 23.4.4 Twos-Complement Mode
    5. 23.5  FIFO Organization in Different Modes
      1. 23.5.1 Single Mono Microphone Configuration
        1. 23.5.1.1 24-bit Sample Size
          1. 23.5.1.1.1 32-bit Data Read
        2. 23.5.1.2 16-bit Sample Size
          1. 23.5.1.2.1 32-bit Data Read
          2. 23.5.1.2.2 16-bit Data Read
        3. 23.5.1.3 8-bit Sample Size
          1. 23.5.1.3.1 32-bit Data Read
          2. 23.5.1.3.2 16-bit Data Read
          3. 23.5.1.3.3 8-bit Data Read
      2. 23.5.2 Stereo or Dual Mono Microphone Configuration
        1. 23.5.2.1 24-bit Sample Size
          1. 23.5.2.1.1 32-bit Data Read
        2. 23.5.2.2 16-bit Sample Size
          1. 23.5.2.2.1 32-bit Data Read
          2. 23.5.2.2.2 16-bit Data Read
        3. 23.5.2.3 8-bit Sample Size
          1. 23.5.2.3.1 32-bit Data Read
          2. 23.5.2.3.2 16-bit Data Read
          3. 23.5.2.3.3 8-bit Data Read
      3. 23.5.3 FIFO Threshold Setting
      4. 23.5.4 Reset FIFO
    6. 23.6  Automatic Gain Control (AGC)
      1. 23.6.1 Operation in 2's Complement Format
      2. 23.6.2 Operation in Offset Binary Format
    7. 23.7  Interrupts
    8. 23.8  Clock Select and Control
    9. 23.9  DMA Operation
    10. 23.10 Samplestamp Generator
      1. 23.10.1 Samplestamp Counters
      2. 23.10.2 Start-Up Triggers
      3. 23.10.3 Samplestamp Capture
      4. 23.10.4 Achieving Constant Audio Latency
    11. 23.11 Debug‑Mode Flag Behavior
    12. 23.12 Software Guidelines
    13. 23.13 PDM Registers
  25. 24Analog to Digital Converter (ADC)
    1. 24.1 Overview
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1  ADC Core
      2. 24.3.2  Voltage Reference Options
      3. 24.3.3  Internal Channels
      4. 24.3.4  Resolution Modes
      5. 24.3.5  ADC Clocking
      6. 24.3.6  Power Down Behavior
      7. 24.3.7  Sampling Trigger Sources and Sampling Modes
        1. 24.3.7.1 AUTO Sampling Mode
        2. 24.3.7.2 MANUAL Sampling Mode
      8. 24.3.8  Sampling Period
      9. 24.3.9  Conversion Modes
      10. 24.3.10 ADC Data Format
      11. 24.3.11 Status Register
      12. 24.3.12 ADC Events
        1. 24.3.12.1 Generic Event Publishers (INT_EVENT0 & INT_EVENT1)
        2. 24.3.12.2 DMA Trigger Event Publisher (INT_EVENT2)
        3. 24.3.12.3 Generic Event Subscriber
      13. 24.3.13 Advanced Features
        1. 24.3.13.1 Window Comparator
        2. 24.3.13.2 DMA & FIFO Operation
          1. 24.3.13.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
          2. 24.3.13.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
          3. 24.3.13.2.3 DMA/CPU Operation Summary Matrix
        3. 24.3.13.3 Ad-hoc Single Conversion
    4. 24.4 ADC Registers
  26. 25Controller Area Network (CAN)
    1. 25.1 Introduction
    2. 25.2 Functions
    3. 25.3 DCAN Subsystem
    4. 25.4 DCAN Functional Description
      1. 25.4.1 Operating Modes
        1. 25.4.1.1 Software Initialization
        2. 25.4.1.2 Normal Operation
        3. 25.4.1.3 Restricted Operation Mode
        4. 25.4.1.4 Bus Monitoring Mode
        5. 25.4.1.5 Disabled Automatic Retransmission
          1. 25.4.1.5.1 Frame Transmission in DAR Mode
        6. 25.4.1.6 Power Down (Sleep Mode)
          1. 25.4.1.6.1 DCAN clock stop and wake operations
          2. 25.4.1.6.2 DCAN debug suspend operation
        7. 25.4.1.7 Test Modes
          1. 25.4.1.7.1 External Loop Back Mode
          2. 25.4.1.7.2 Internal Loop Back Mode
      2. 25.4.2 Timestamp Generation
        1. 25.4.2.1 Block Diagram
      3. 25.4.3 Timeout Counter
      4. 25.4.4 Rx Handling
        1. 25.4.4.1 Acceptance Filtering
          1. 25.4.4.1.1 Range Filter
          2. 25.4.4.1.2 Filter for specific IDs
          3. 25.4.4.1.3 Classic Bit Mask Filter
          4. 25.4.4.1.4 Standard Message ID Filtering
          5. 25.4.4.1.5 Extended Message ID Filtering
        2. 25.4.4.2 Rx FIFOs
          1. 25.4.4.2.1 Rx FIFO Blocking Mode
          2. 25.4.4.2.2 Rx FIFO Overwrite Mode
        3. 25.4.4.3 Dedicated Rx Buffers
          1. 25.4.4.3.1 Rx Buffer Handling
        4. 25.4.4.4 Debug on CAN Support
          1. 25.4.4.4.1 Filtering for Debug Messages
          2. 25.4.4.4.2 Debug Message Handling
      5. 25.4.5 Tx Handling
        1. 25.4.5.1 Transmit Pause
        2. 25.4.5.2 Dedicated Tx Buffers
        3. 25.4.5.3 Tx FIFO
        4. 25.4.5.4 Tx Queue
        5. 25.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 25.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 25.4.5.7 Transmit Cancellation
        8. 25.4.5.8 Tx Event Handling
      6. 25.4.6 FIFO Acknowledge Handling
      7. 25.4.7 DCAN Message RAM
        1. 25.4.7.1 Message RAM Configuration
        2. 25.4.7.2 Rx Buffer and FIFO Element
        3. 25.4.7.3 Tx Buffer Element
        4. 25.4.7.4 Tx Event FIFO Element
        5. 25.4.7.5 Standard Message ID Filter Element
        6. 25.4.7.6 Extended Message ID Filter Element
      8. 25.4.8 Interrupt Requests
    5. 25.5 DCAN Wrapper
    6. 25.6 DCAN Clock Enable
    7. 25.7 DCAN Registers
  27. 26Revision History

16.8 IOMUX Registers

Table 16-1 lists the memory-mapped registers for the IOMUX registers. All register offset addresses not listed in Table 16-1 should be considered as reserved locations and the register contents should not be modified.

Table 16-1 IOMUX Registers
OffsetAcronymRegister NameSection
0hSCLKICFGSlow Clock ConfigurationSection 16.8.1
4hSCLKIPCTLSlow Clock Pull ControlSection 16.8.2
8hSCLKICTLSlow Clock InputSection 16.8.3
ChSCLKIECTLSlow Clock Event ConfigurationSection 16.8.4
1000hLFXTNCFGLow-Frequency Crystal Negative ConfigSection 16.8.5
1004hLFXTNPCTLLow-Frequency Crystal Negative ControlSection 16.8.6
1008hLFXTNCTLLow-Frequency Crystal ControlSection 16.8.7
100ChLFXTNECTLLow-Frequency Crystal InputSection 16.8.8
2000hGPIO2CFGGPIO2 ConfigurationSection 16.8.9
2004hGPIO2PCTLPull ControlSection 16.8.10
2008hGPIO2CTLGPIO2 ControlSection 16.8.11
200ChGPIO2ECTLGPIO2 Event ControlSection 16.8.12
3000hGPIO3CFGGPIO3 ConfigurationSection 16.8.13
3004hGPIO3PCTLPull ControlSection 16.8.14
3008hGPIO3CTLGPIO3 ControlSection 16.8.15
300ChGPIO3ECTLGPIO3 Event ControlSection 16.8.16
4000hGPIO4CFGGPIO4 ConfigurationSection 16.8.17
4004hGPIO4PCTLPull ControlSection 16.8.18
4008hGPIO4CTLGPIO4 ControlSection 16.8.19
400ChGPIO4ECTLGPIO4 Event ControlSection 16.8.20
5000hGPIO5CFGGPIO5 ConfigurationSection 16.8.21
5004hGPIO5PCTLPull ControlSection 16.8.22
5008hGPIO5CTLGPIO5 ControlSection 16.8.23
500ChGPIO5ECTLGPIO5 Event ControlSection 16.8.24
6000hGPIO6CFGGPIO6 ConfigurationSection 16.8.25
6004hGPIO6PCTLPull ControlSection 16.8.26
6008hGPIO6CTLGPIO6 ControlSection 16.8.27
600ChGPIO6ECTLGPIO6 Event ControlSection 16.8.28
7000hSWDIOCFGSWDIO ConfigurationSection 16.8.29
7004hSWDIOPCTLSWDIO Pull ControlSection 16.8.30
7008hSWDIOCTLSWDIO ControlSection 16.8.31
700ChSWDIOECTLSWDIO Event ControlSection 16.8.32
8000hSWCLKCFGJTAG Clock ConfigurationSection 16.8.33
8004hSWCLKPCTLSWCLK Pull ControlSection 16.8.34
8008hSWCLKCTLSWCLK ControlSection 16.8.35
800ChSWCLKECTLSWCLK Event ControlSection 16.8.36
9000hLOGGERCFGIO Logger ConfigurationSection 16.8.37
9004hLOGGERPCTLPull Control ConfigurationSection 16.8.38
9008hLOGGERCTLInput/Output Logger ControlSection 16.8.39
900ChLOGGERECTLLogger Event ControlSection 16.8.40
A000hGPIO10CFGGPIO10 ConfigurationSection 16.8.41
A004hGPIO10PCTLPull ControlSection 16.8.42
A008hGPIO10CTLGPIO10 ControlSection 16.8.43
A00ChGPIO10ECTLGPIO10 Event ControlSection 16.8.44
B000hGPIO11CFGGPIO11 ConfigurationSection 16.8.45
B004hGPIO11PCTLPull ControlSection 16.8.46
B008hGPIO11CTLGPIO11 ControlSection 16.8.47
B00ChGPIO11ECTLGPIO11 Event ControlSection 16.8.48
C000hGPIO12CFGGPIO12 ConfigurationSection 16.8.49
C004hGPIO12PCTLPull ControlSection 16.8.50
C008hGPIO12CTLGPIO12 ControlSection 16.8.51
C00ChGPIO12ECTLGPIO12 Event ControlSection 16.8.52
D000hGPIO13CFGGPIO13 ConfigurationSection 16.8.53
D004hGPIO13PCTLPull ControlSection 16.8.54
D008hGPIO13CTLGPIO13 ControlSection 16.8.55
D00ChGPIO13ECTLGPIO13 Event ControlSection 16.8.56
E000hGPIO14CFGGPIO14 ConfigurationSection 16.8.57
E004hGPIO14PCTLPull Control ConfigurationSection 16.8.58
E008hGPIO14CTLGPIO14 ControlSection 16.8.59
E00ChGPIO14ECTLGPIO14 Event ControlSection 16.8.60
F000hGPIO15CFGGPIO15 ConfigurationSection 16.8.61
F004hGPIO15PCTLPull Control ConfigurationSection 16.8.62
F008hGPIO15CTLGPIO15 ControlSection 16.8.63
F00ChGPIO15ECTLGPIO15 Event ControlSection 16.8.64
00010000hGPIO16CFGGPIO16 ConfigurationSection 16.8.65
00010004hGPIO16PCTLPull ControlSection 16.8.66
00010008hGPIO16CTLGPIO16 ControlSection 16.8.67
0001000ChGPIO16ECTLGPIO16 Event ControlSection 16.8.68
00011000hGPIO17CFGGPIO17 ConfigurationSection 16.8.69
00011004hGPIO17PCTLPull ControlSection 16.8.70
00011008hGPIO17CTLGPIO17 ControlSection 16.8.71
0001100ChGPIO17ECTLGPIO17 Event ControlSection 16.8.72
00012000hGPIO18CFGGPIO18 ConfigurationSection 16.8.73
00012004hGPIO18PCTLPull ControlSection 16.8.74
00012008hGPIO18CTLGPIO18 ControlSection 16.8.75
0001200ChGPIO18ECTLGPIO18 Event ControlSection 16.8.76
00013000hGPIO19CFGGPIO19 ConfigurationSection 16.8.77
00013004hGPIO19PCTLPull ControlSection 16.8.78
00013008hGPIO19CTLGPIO19 ControlSection 16.8.79
0001300ChGPIO19ECTLGPIO19 Event ControlSection 16.8.80
00014000hGPIO20CFGGPIO20 ConfigurationSection 16.8.81
00014004hGPIO20PCTLPull Control ConfigurationSection 16.8.82
00014008hGPIO20CTLGPIO20 ControlSection 16.8.83
0001400ChGPIO20ECTLGPIO20 Event ControlSection 16.8.84
00015000hGPIO21CFGGPIO21 ConfigurationSection 16.8.85
00015004hGPIO21PCTLPull ControlSection 16.8.86
00015008hGPIO21CTLGPIO21 ControlSection 16.8.87
0001500ChGPIO21ECTLGPIO21 Event ControlSection 16.8.88
00016000hGPIO22CFGGPIO22 ConfigurationSection 16.8.89
00016004hGPIO22PCTLPull ControlSection 16.8.90
00016008hGPIO22CTLGPIO22 ControlSection 16.8.91
0001600ChGPIO22ECTLGPIO22 Event ControlSection 16.8.92
00017000hGPIO23CFGGPIO23 ConfigurationSection 16.8.93
00017004hGPIO23PCTLPull ControlSection 16.8.94
00017008hGPIO23CTLGPIO23 ControlSection 16.8.95
0001700ChGPIO23ECTLGPIO23 Event ControlSection 16.8.96
00018000hGPIO24CFGGPIO24 ConfigurationSection 16.8.97
00018004hGPIO24PCTLPull ControlSection 16.8.98
00018008hGPIO24CTLGPIO 24 ControlSection 16.8.99
0001800ChGPIO24ECTLGPIO24 Event ControlSection 16.8.100
00019000hGPIO25CFGGPIO25 ConfigurationSection 16.8.101
00019004hGPIO25PCTLPull ControlSection 16.8.102
00019008hGPIO25CTLGPIO25 ControlSection 16.8.103
0001900ChGPIO25ECTLGPIO25 Event ControlSection 16.8.104
0001A000hGPIO26CFGGPIO26 ConfigurationSection 16.8.105
0001A004hGPIO26PCTLPull ControlSection 16.8.106
0001A008hGPIO26CTLGPIO26 ControlSection 16.8.107
0001A00ChGPIO26ECTLGPIO26 Event ControlSection 16.8.108
0001B000hGPIO27CFGGPIO27 ConfigurationSection 16.8.109
0001B004hGPIO27PCTLPull ControlSection 16.8.110
0001B008hGPIO27CTLGPIO27 ControlSection 16.8.111
0001B00ChGPIO27ECTLGPIO27 Event ControlSection 16.8.112
0001C000hGPIO28CFGGPIO28 ConfigurationSection 16.8.113
0001C004hGPIO28PCTLPull ControlSection 16.8.114
0001C008hGPIO28CTLGPIO28 ControlSection 16.8.115
0001C00ChGPIO28ECTLGPIO28 Event ControlSection 16.8.116
0001D000hGPIO29CFGGPIO29 ConfigurationSection 16.8.117
0001D004hGPIO29PCTLPull Control ConfigurationSection 16.8.118
0001D008hGPIO29CTLGPIO29 ControlSection 16.8.119
0001D00ChGPIO29ECTLGPIO29 Event ControlSection 16.8.120
0001E000hGPIO30CFGGPIO30 ConfigurationSection 16.8.121
0001E004hGPIO30PCTLPull Control ConfigurationSection 16.8.122
0001E008hGPIO30CTLGPIO30 ControlSection 16.8.123
0001E00ChGPIO30ECTLGPIO30 Event ControlSection 16.8.124
0001F000hGPIO31CFGGPIO31 ConfigurationSection 16.8.125
0001F004hGPIO31PCTLPull ControlSection 16.8.126
0001F008hGPIO31CTLGPIO31 ControlSection 16.8.127
0001F00ChGPIO31ECTLGPIO31 Event ControlSection 16.8.128
00020000hGPIO32CFGGPIO32 ConfigurationSection 16.8.129
00020004hGPIO32PCTLPull ControlSection 16.8.130
00020008hGPIO32CTLGPIO Pin ControlSection 16.8.131
0002000ChGPIO32ECTLGPIO32 Event ControlSection 16.8.132
00021000hGPIO33CFGGPIO33 ConfigurationSection 16.8.133
00021004hGPIO33PCTLPull ControlSection 16.8.134
00021008hGPIO33CTLGPIO33 ControlSection 16.8.135
0002100ChGPIO33ECTLGPIO33 Event ControlSection 16.8.136
00022000hGPIO34CFGGPIO34 ConfigurationSection 16.8.137
00022004hGPIO34PCTLPull ControlSection 16.8.138
00022008hGPIO34CTLGPIO34 ControlSection 16.8.139
0002200ChGPIO34ECTLGPIO34 Event ControlSection 16.8.140
00023000hGPIO35CFGGPIO35 ConfigurationSection 16.8.141
00023004hGPIO35PCTLPull ControlSection 16.8.142
00023008hGPIO35CTLGPIO35 ControlSection 16.8.143
0002300ChGPIO35ECTLGPIO35 Event ControlSection 16.8.144
00024000hGPIO36CFGGPIO36 ConfigurationSection 16.8.145
00024004hGPIO36PCTLPull ControlSection 16.8.146
00024008hGPIO36CTLGPIO36 ControlSection 16.8.147
0002400ChGPIO36ECTLGPIO36 Event ControlSection 16.8.148
00025000hGPIO37CFGGPIO37 ConfigurationSection 16.8.149
00025004hGPIO37PCTLPull ControlSection 16.8.150
00025008hGPIO37CTLGPIO37 ControlSection 16.8.151
0002500ChGPIO37ECTLGPIO37 Event ControlSection 16.8.152
00026000hGPIO38CFGGPIO38 ConfigurationSection 16.8.153
00026004hGPIO38PCTLPull ControlSection 16.8.154
00026008hGPIO38CTLGPIO38 ControlSection 16.8.155
0002600ChGPIO38ECTLGPIO38 Event ControlSection 16.8.156
00027000hGPIO39CFGGPIO39 ConfigurationSection 16.8.157
00027004hGPIO39PCTLGPIO39 Pull ControlSection 16.8.158
00027008hGPIO39CTLGPIO39 ControlSection 16.8.159
0002700ChGPIO39ECTLGPIO39 Event ControlSection 16.8.160
00028000hGPIO40CFGGPIO40 ConfigurationSection 16.8.161
00028004hGPIO40PCTLPull Control ConfigurationSection 16.8.162
00028008hGPIO40CTLGPIO40 ControlSection 16.8.163
0002800ChGPIO40ECTLGPIO40 Event ControlSection 16.8.164
00029000hGPIO41CFGGPIO41 ConfigurationSection 16.8.165
00029004hGPIO41PCTLPull ControlSection 16.8.166
00029008hGPIO41CTLGPIO41 ControlSection 16.8.167
0002900ChGPIO41ECTLGPIO41 Event ControlSection 16.8.168
0002A000hGPIO42CFGGPIO42 ConfigurationSection 16.8.169
0002A004hGPIO42PCTLPull ControlSection 16.8.170
0002A008hGPIO42CTLGPIO42 ControlSection 16.8.171
0002A00ChGPIO42ECTLGPIO42 Event ControlSection 16.8.172
0002B000hGPIO43CFGGPIO43 ConfigurationSection 16.8.173
0002B004hGPIO43PCTLPull ControlSection 16.8.174
0002B008hGPIO43CTLGPIO 43 ControlSection 16.8.175
0002B00ChGPIO43ECTLGPIO43 Event ControlSection 16.8.176
0002C000hGPIO44CFGGPIO44 ConfigurationSection 16.8.177
0002C004hGPIO44PCTLPul ControlSection 16.8.178
0002C008hGPIO44CTLGPIO44 ControlSection 16.8.179
0002C00ChGPIO44ECTLGPIO44 Event ControlSection 16.8.180
0002D004hSCLKIPCFGSlow Clock Port ConfigurationSection 16.8.181
0002D008hLFXTNPCFGLFXTALN Port ControlSection 16.8.182
0002D00ChGPIO2PCFGGPIO2 Port ConfigurationSection 16.8.183
0002D010hGPIO3PCFGGPIO3 Port ConfigurationSection 16.8.184
0002D014hGPIO4PCFGGPIO4 Port ConfigurationSection 16.8.185
0002D018hGPIO5PCFGGPIO5 Port ConfigurationSection 16.8.186
0002D01ChGPIO6PCFGGPIO6 Port ConfigurationSection 16.8.187
0002D020hSWDIOPCFGSerial Wire Debug controlSection 16.8.188
0002D024hSWCLKPCFGSWD Clock ConfigurationSection 16.8.189
0002D028hLOGGERPCFGLogger ConfigurationSection 16.8.190
0002D02ChGPIO10PCFGGPIO10 Port ConfigurationSection 16.8.191
0002D030hGPIO11PCFGGPIO11 Port ConfigurationSection 16.8.192
0002D034hGPIO12PCFGGPIO12 Port ConfigurationSection 16.8.193
0002D038hGPIO13PCFGGPIO13 Port ConfigurationSection 16.8.194
0002D03ChGPIO14PCFGGPIO14 ConfigurationSection 16.8.195
0002D040hGPIO15PCFGGPIO15 Port ConfigurationSection 16.8.196
0002D044hGPIO16PCFGGPIO16 Port ConfigurationSection 16.8.197
0002D048hGPIO17PCFGGPIO17 Port ConfigurationSection 16.8.198
0002D04ChGPIO18PCFGGPIO18 Port ConfigurationSection 16.8.199
0002D050hGPIO19PCFGGPIO19 Port ConfigurationSection 16.8.200
0002D054hGPIO20PCFGGPIO20 Port ConfigurationSection 16.8.201
0002D058hGPIO21PCFGGPIO21 Port ConfigurationSection 16.8.202
0002D05ChGPIO22PCFGGPIO22 Port ConfigurationSection 16.8.203
0002D060hGPIO23PCFGGPIO23 Port ConfigurationSection 16.8.204
0002D064hGPIO24PCFGGPIO24 Port ConfigurationSection 16.8.205
0002D068hGPIO25PCFGGPIO25 Port ConfigurationSection 16.8.206
0002D06ChGPIO26PCFGGPIO26 Port ConfigurationSection 16.8.207
0002D070hGPIO27PCFGGPIO27 Port ConfigurationSection 16.8.208
0002D074hGPIO28PCFGGPIO28 Port ConfigurationSection 16.8.209
0002D078hGPIO29PCFGGPIO29 Port ConfigurationSection 16.8.210
0002D07ChGPIO30PCFGGPIO30 Port ConfigurationSection 16.8.211
0002D080hGPIO31PCFGGPIO31 Port ConfigurationSection 16.8.212
0002D084hGPIO32PCFGGPIO32 Port ConfigurationSection 16.8.213
0002D088hGPIO33PCFGGPIO33 Port ConfigurationSection 16.8.214
0002D08ChGPIO34PCFGGPIO34 Port ConfigurationSection 16.8.215
0002D090hGPIO35PCFGGPIO35 Port ConfigurationSection 16.8.216
0002D094hGPIO36PCFGGPIO36 Port ConfigurationSection 16.8.217
0002D098hGPIO37PCFGGPIO37 Port ConfigurationSection 16.8.218
0002D09ChGPIO38PCFGGPIO39 Port ConfigurationSection 16.8.219
0002D0A0hGPIO39PCFGGPIO39 Port ConfigurationSection 16.8.220
0002D0A4hGPIO40PCFGGPIO40 Port ConfigurationSection 16.8.221
0002D0A8hGPIO41PCFGGPIO41 Port ConfigurationSection 16.8.222
0002D0AChGPIO42PCFGGPIO42 Port ConfigurationSection 16.8.223
0002D0B0hGPIO43PCFGGPIO43 Port ConfigurationSection 16.8.224
0002D0B4hGPIO44PCFGGPIO44 Port ConfigurationSection 16.8.225
0002D0C0hGPIO45PCFGGPIO45 Port ConfigurationSection 16.8.226
0002D0C4hGPIO46PCFGGPIO46 Port ConfigurationSection 16.8.227
0002D0C8hGPIO47PCFGGPIO47 Port ConfigurationSection 16.8.228
0002D0CChGPIO48PCFGGPIO48 Port ConfigurationSection 16.8.229
0002E000hGPIO45CFGGPIO45 ConfigurationSection 16.8.230
0002E004hGPIO45PCTLPull Control ConfigurationSection 16.8.231
0002E008hGPIO45CTLGPIO45 ControlSection 16.8.232
0002E00ChGPIO45ECTLGPIO45 Event ControlSection 16.8.233
0002F000hGPIO46CFGGPIO46 ConfigurationSection 16.8.234
0002F004hGPIO46PCTLPull Control ConfigurationSection 16.8.235
0002F008hGPIO46CTLGPIO46 ControlSection 16.8.236
0002F00ChGPIO46ECTLGPIO46 Event ControlSection 16.8.237
00030000hGPIO47CFGGPIO47 ConfigurationSection 16.8.238
00030004hGPIO47PCTLPull ControlSection 16.8.239
00030008hGPIO47CTLGPIO47 ControlSection 16.8.240
0003000ChGPIO47ECTLGPIO47 Event ControlSection 16.8.241
00031000hGPIO48CFGGPIO48 ConfigurationSection 16.8.242
00031004hGPIO48PCTLPull ControlSection 16.8.243
00031008hGPIO48CTLGPIO48 ControlSection 16.8.244
0003100ChGPIO48ECTLGPIO48 Event ControlSection 16.8.245

Complex bit access types are encoded to fit into small table cells. Table 16-2 shows the codes that are used for access types in this section.

Table 16-2 IOMUX Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

16.8.1 SCLKICFG Register (Offset = 0h) [Reset = 00000000h]

SCLKICFG is shown in Table 16-3.

Return to the Summary Table.

CFG register for IO SLOW_CLOCK_IN. This register configures the corresponding pad

Table 16-3 SCLKICFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
13RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
12RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.2 SCLKIPCTL Register (Offset = 4h) [Reset = 00000000h]

SCLKIPCTL is shown in Table 16-4.

Return to the Summary Table.

Pull control register of IO SLOW_CLOCK_IN This register configures the pull control

Table 16-4 SCLKIPCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W2hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = RESERVED
  • 3h = Pull disable

16.8.3 SCLKICTL Register (Offset = 8h) [Reset = 00000000h]

SCLKICTL is shown in Table 16-5.

Return to the Summary Table.

Control register of IO SLOW_CLOCK_IN This register controls the IO state

Table 16-5 SCLKICTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.4 SCLKIECTL Register (Offset = Ch) [Reset = 00000000h]

SCLKIECTL is shown in Table 16-6.

Return to the Summary Table.

Event control register for IO SLOW_CLOCK_IN This register controls the Event configuration and behaviour

Table 16-6 SCLKIECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.5 LFXTNCFG Register (Offset = 1000h) [Reset = 00000000h]

LFXTNCFG is shown in Table 16-7.

Return to the Summary Table.

CFG register for IO LFXTAL_N. This register configures the corresponding pad

Table 16-7 LFXTNCFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W0hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9ANASWOVRENR/W1hThis field controls the analog switch override
  • 0h = Analog switch is controlled by IP
  • 1h = Enable override on analog switch control
8ANASWR/W0hThis field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled
  • 0h = Analog switch open
  • 1h = Analog switch closed
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.6 LFXTNPCTL Register (Offset = 1004h) [Reset = 00000000h]

LFXTNPCTL is shown in Table 16-8.

Return to the Summary Table.

Pull control register of IO LFXTAL_N This register configures the pull control

Table 16-8 LFXTNPCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W2hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.7 LFXTNCTL Register (Offset = 1008h) [Reset = 00000000h]

LFXTNCTL is shown in Table 16-9.

Return to the Summary Table.

Control register of IO LFXTAL_N This register controls the IO state

Table 16-9 LFXTNCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.8 LFXTNECTL Register (Offset = 100Ch) [Reset = 00000000h]

LFXTNECTL is shown in Table 16-10.

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Event control register for IO LFXTAL_N This register controls the Event configuration and behaviour

Table 16-10 LFXTNECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.9 GPIO2CFG Register (Offset = 2000h) [Reset = 00000000h]

GPIO2CFG is shown in Table 16-11.

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CFG register for IO GPIO2. This register configures the corresponding pad

Table 16-11 GPIO2CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W0hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9ANASWOVRENR/W1hThis field controls the analog switch override
  • 0h = Analog switch is controlled by IP
  • 1h = Enable override on analog switch control
8ANASWR/W0hThis field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled
  • 0h = Analog switch open
  • 1h = Analog switch closed
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.10 GPIO2PCTL Register (Offset = 2004h) [Reset = 00000000h]

GPIO2PCTL is shown in Table 16-12.

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Pull control register of IO GPIO2 This register configures the pull control

Table 16-12 GPIO2PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.11 GPIO2CTL Register (Offset = 2008h) [Reset = 00000000h]

GPIO2CTL is shown in Table 16-13.

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Control register of IO GPIO2 This register controls the IO state

Table 16-13 GPIO2CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.12 GPIO2ECTL Register (Offset = 200Ch) [Reset = 00000000h]

GPIO2ECTL is shown in Table 16-14.

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Event control register for IO GPIO2 This register controls the Event configuration and behaviour

Table 16-14 GPIO2ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.13 GPIO3CFG Register (Offset = 3000h) [Reset = 00000000h]

GPIO3CFG is shown in Table 16-15.

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CFG register for IO GPIO3. This register configures the corresponding pad

Table 16-15 GPIO3CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W0hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9ANASWOVRENR/W1hThis field controls the analog switch override
  • 0h = Analog switch is controlled by IP
  • 1h = Enable override on analog switch control
8ANASWR/W0hThis field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled
  • 0h = Analog switch open
  • 1h = Analog switch closed
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.14 GPIO3PCTL Register (Offset = 3004h) [Reset = 00000000h]

GPIO3PCTL is shown in Table 16-16.

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Pull control register of IO GPIO3 This register configures the pull control

Table 16-16 GPIO3PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.15 GPIO3CTL Register (Offset = 3008h) [Reset = 00000000h]

GPIO3CTL is shown in Table 16-17.

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Control register of IO GPIO3 This register controls the IO state

Table 16-17 GPIO3CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.16 GPIO3ECTL Register (Offset = 300Ch) [Reset = 00000000h]

GPIO3ECTL is shown in Table 16-18.

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Event control register for IO GPIO3 This register controls the Event configuration and behaviour

Table 16-18 GPIO3ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.17 GPIO4CFG Register (Offset = 4000h) [Reset = 00000000h]

GPIO4CFG is shown in Table 16-19.

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CFG register for IO GPIO4. This register configures the corresponding pad

Table 16-19 GPIO4CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W0hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9ANASWOVRENR/W1hThis field controls the analog switch override
  • 0h = Analog switch is controlled by IP
  • 1h = Enable override on analog switch control
8ANASWR/W0hThis field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled
  • 0h = Analog switch open
  • 1h = Analog switch closed
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.18 GPIO4PCTL Register (Offset = 4004h) [Reset = 00000000h]

GPIO4PCTL is shown in Table 16-20.

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Pull control register of IO GPIO4 This register configures the pull control

Table 16-20 GPIO4PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.19 GPIO4CTL Register (Offset = 4008h) [Reset = 00000000h]

GPIO4CTL is shown in Table 16-21.

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Control register of IO GPIO4 This register controls the IO state

Table 16-21 GPIO4CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.20 GPIO4ECTL Register (Offset = 400Ch) [Reset = 00000000h]

GPIO4ECTL is shown in Table 16-22.

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Event control register for IO GPIO4 This register controls the Event configuration and behaviour

Table 16-22 GPIO4ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.21 GPIO5CFG Register (Offset = 5000h) [Reset = 00000000h]

GPIO5CFG is shown in Table 16-23.

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CFG register for IO GPIO5. This register configures the corresponding pad

Table 16-23 GPIO5CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W0hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9ANASWOVRENR/W1hThis field controls the analog switch override
  • 0h = Analog switch is controlled by IP
  • 1h = Enable override on analog switch control
8ANASWR/W0hThis field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled
  • 0h = Analog switch open
  • 1h = Analog switch closed
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.22 GPIO5PCTL Register (Offset = 5004h) [Reset = 00000000h]

GPIO5PCTL is shown in Table 16-24.

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Pull control register of IO GPIO5 This register configures the pull control

Table 16-24 GPIO5PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.23 GPIO5CTL Register (Offset = 5008h) [Reset = 00000000h]

GPIO5CTL is shown in Table 16-25.

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Control register of IO GPIO5 This register controls the IO state

Table 16-25 GPIO5CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.24 GPIO5ECTL Register (Offset = 500Ch) [Reset = 00000000h]

GPIO5ECTL is shown in Table 16-26.

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Event control register for IO GPIO5 This register controls the Event configuration and behaviour

Table 16-26 GPIO5ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.25 GPIO6CFG Register (Offset = 6000h) [Reset = 00000000h]

GPIO6CFG is shown in Table 16-27.

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CFG register for IO GPIO6. This register configures the corresponding pad

Table 16-27 GPIO6CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W0hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9ANASWOVRENR/W1hThis field controls the analog switch override
  • 0h = Analog switch is controlled by IP
  • 1h = Enable override on analog switch control
8ANASWR/W0hThis field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled
  • 0h = Analog switch open
  • 1h = Analog switch closed
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.26 GPIO6PCTL Register (Offset = 6004h) [Reset = 00000000h]

GPIO6PCTL is shown in Table 16-28.

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Pull control register of IO GPIO6 This register configures the pull control

Table 16-28 GPIO6PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.27 GPIO6CTL Register (Offset = 6008h) [Reset = 00000000h]

GPIO6CTL is shown in Table 16-29.

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Control register of IO GPIO6 This register controls the IO state

Table 16-29 GPIO6CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.28 GPIO6ECTL Register (Offset = 600Ch) [Reset = 00000000h]

GPIO6ECTL is shown in Table 16-30.

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Event control register for IO GPIO6 This register controls the Event configuration and behaviour

Table 16-30 GPIO6ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.29 SWDIOCFG Register (Offset = 7000h) [Reset = 00000000h]

SWDIOCFG is shown in Table 16-31.

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CFG register for IO SWDIO. This register configures the corresponding pad

Table 16-31 SWDIOCFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.30 SWDIOPCTL Register (Offset = 7004h) [Reset = 00000000h]

SWDIOPCTL is shown in Table 16-32.

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Pull control register of IO SWDIO This register configures the pull control

Table 16-32 SWDIOPCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.31 SWDIOCTL Register (Offset = 7008h) [Reset = 00000000h]

SWDIOCTL is shown in Table 16-33.

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Control register of IO SWDIO This register controls the IO state

Table 16-33 SWDIOCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.32 SWDIOECTL Register (Offset = 700Ch) [Reset = 00000000h]

SWDIOECTL is shown in Table 16-34.

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Event control register for IO SWDIO This register controls the Event configuration and behaviour

Table 16-34 SWDIOECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.33 SWCLKCFG Register (Offset = 8000h) [Reset = 00000000h]

SWCLKCFG is shown in Table 16-35.

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CFG register for IO SWCLK. This register configures the corresponding pad

Table 16-35 SWCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.34 SWCLKPCTL Register (Offset = 8004h) [Reset = 00000000h]

SWCLKPCTL is shown in Table 16-36.

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Pull control register of IO SWCLK This register configures the pull control

Table 16-36 SWCLKPCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W2hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.35 SWCLKCTL Register (Offset = 8008h) [Reset = 00000000h]

SWCLKCTL is shown in Table 16-37.

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Control register of IO SWCLK This register controls the IO state

Table 16-37 SWCLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.36 SWCLKECTL Register (Offset = 800Ch) [Reset = 00000000h]

SWCLKECTL is shown in Table 16-38.

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Event control register for IO SWCLK This register controls the Event configuration and behaviour

Table 16-38 SWCLKECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.37 LOGGERCFG Register (Offset = 9000h) [Reset = 00000000h]

LOGGERCFG is shown in Table 16-39.

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CFG register for IO LOGGER. This register configures the corresponding pad

Table 16-39 LOGGERCFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.38 LOGGERPCTL Register (Offset = 9004h) [Reset = 00000000h]

LOGGERPCTL is shown in Table 16-40.

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Pull control register of IO LOGGER This register configures the pull control

Table 16-40 LOGGERPCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.39 LOGGERCTL Register (Offset = 9008h) [Reset = 00000000h]

LOGGERCTL is shown in Table 16-41.

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Control register of IO LOGGER This register controls the IO state

Table 16-41 LOGGERCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.40 LOGGERECTL Register (Offset = 900Ch) [Reset = 00000000h]

LOGGERECTL is shown in Table 16-42.

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Event control register for IO LOGGER This register controls the Event configuration and behaviour

Table 16-42 LOGGERECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.41 GPIO10CFG Register (Offset = A000h) [Reset = 00000000h]

GPIO10CFG is shown in Table 16-43.

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CFG register for IO GPIO10. This register configures the corresponding pad

Table 16-43 GPIO10CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W0hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9ANASWOVRENR/W1hThis field controls the analog switch override
  • 0h = Analog switch is controlled by IP
  • 1h = Enable override on analog switch control
8ANASWR/W0hThis field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled
  • 0h = Analog switch open
  • 1h = Analog switch closed
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.42 GPIO10PCTL Register (Offset = A004h) [Reset = 00000000h]

GPIO10PCTL is shown in Table 16-44.

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Pull control register of IO GPIO10 This register configures the pull control

Table 16-44 GPIO10PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.43 GPIO10CTL Register (Offset = A008h) [Reset = 00000000h]

GPIO10CTL is shown in Table 16-45.

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Control register of IO GPIO10 This register controls the IO state

Table 16-45 GPIO10CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.44 GPIO10ECTL Register (Offset = A00Ch) [Reset = 00000000h]

GPIO10ECTL is shown in Table 16-46.

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Event control register for IO GPIO10 This register controls the Event configuration and behaviour

Table 16-46 GPIO10ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.45 GPIO11CFG Register (Offset = B000h) [Reset = 00000000h]

GPIO11CFG is shown in Table 16-47.

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CFG register for IO GPIO11. This register configures the corresponding pad

Table 16-47 GPIO11CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W0hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9ANASWOVRENR/W1hThis field controls the analog switch override
  • 0h = Analog switch is controlled by IP
  • 1h = Enable override on analog switch control
8ANASWR/W0hThis field defines the Ana switch state. If the switch is enabled, the analog signal is routed to the IO pad Note: This field is applicable when [ANASWOVREN] is enabled
  • 0h = Analog switch open
  • 1h = Analog switch closed
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.46 GPIO11PCTL Register (Offset = B004h) [Reset = 00000000h]

GPIO11PCTL is shown in Table 16-48.

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Pull control register of IO GPIO11 This register configures the pull control

Table 16-48 GPIO11PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.47 GPIO11CTL Register (Offset = B008h) [Reset = 00000000h]

GPIO11CTL is shown in Table 16-49.

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Control register of IO GPIO11 This register controls the IO state

Table 16-49 GPIO11CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.48 GPIO11ECTL Register (Offset = B00Ch) [Reset = 00000000h]

GPIO11ECTL is shown in Table 16-50.

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Event control register for IO GPIO11 This register controls the Event configuration and behaviour

Table 16-50 GPIO11ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.49 GPIO12CFG Register (Offset = C000h) [Reset = 00000000h]

GPIO12CFG is shown in Table 16-51.

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CFG register for IO GPIO12. This register configures the corresponding pad

Table 16-51 GPIO12CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.50 GPIO12PCTL Register (Offset = C004h) [Reset = 00000000h]

GPIO12PCTL is shown in Table 16-52.

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Pull control register of IO GPIO12 This register configures the pull control

Table 16-52 GPIO12PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.51 GPIO12CTL Register (Offset = C008h) [Reset = 00000000h]

GPIO12CTL is shown in Table 16-53.

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Control register of IO GPIO12 This register controls the IO state

Table 16-53 GPIO12CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.52 GPIO12ECTL Register (Offset = C00Ch) [Reset = 00000000h]

GPIO12ECTL is shown in Table 16-54.

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Event control register for IO GPIO12 This register controls the Event configuration and behaviour

Table 16-54 GPIO12ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.53 GPIO13CFG Register (Offset = D000h) [Reset = 00000000h]

GPIO13CFG is shown in Table 16-55.

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CFG register for IO GPIO13. This register configures the corresponding pad

Table 16-55 GPIO13CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.54 GPIO13PCTL Register (Offset = D004h) [Reset = 00000000h]

GPIO13PCTL is shown in Table 16-56.

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Pull control register of IO GPIO13 This register configures the pull control

Table 16-56 GPIO13PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.55 GPIO13CTL Register (Offset = D008h) [Reset = 00000000h]

GPIO13CTL is shown in Table 16-57.

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Control register of IO GPIO13 This register controls the IO state

Table 16-57 GPIO13CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.56 GPIO13ECTL Register (Offset = D00Ch) [Reset = 00000000h]

GPIO13ECTL is shown in Table 16-58.

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Event control register for IO GPIO13 This register controls the Event configuration and behaviour

Table 16-58 GPIO13ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.57 GPIO14CFG Register (Offset = E000h) [Reset = 00000000h]

GPIO14CFG is shown in Table 16-59.

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CFG register for IO GPIO14. This register configures the corresponding pad

Table 16-59 GPIO14CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.58 GPIO14PCTL Register (Offset = E004h) [Reset = 00000000h]

GPIO14PCTL is shown in Table 16-60.

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Pull control register of IO GPIO14 This register configures the pull control

Table 16-60 GPIO14PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.59 GPIO14CTL Register (Offset = E008h) [Reset = 00000000h]

GPIO14CTL is shown in Table 16-61.

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Control register of IO GPIO14 This register controls the IO state

Table 16-61 GPIO14CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.60 GPIO14ECTL Register (Offset = E00Ch) [Reset = 00000000h]

GPIO14ECTL is shown in Table 16-62.

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Event control register for IO GPIO14 This register controls the Event configuration and behaviour

Table 16-62 GPIO14ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.61 GPIO15CFG Register (Offset = F000h) [Reset = 00000000h]

GPIO15CFG is shown in Table 16-63.

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CFG register for IO GPIO15. This register configures the corresponding pad

Table 16-63 GPIO15CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.62 GPIO15PCTL Register (Offset = F004h) [Reset = 00000000h]

GPIO15PCTL is shown in Table 16-64.

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Pull control register of IO GPIO15 This register configures the pull control

Table 16-64 GPIO15PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.63 GPIO15CTL Register (Offset = F008h) [Reset = 00000000h]

GPIO15CTL is shown in Table 16-65.

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Control register of IO GPIO15 This register controls the IO state

Table 16-65 GPIO15CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.64 GPIO15ECTL Register (Offset = F00Ch) [Reset = 00000000h]

GPIO15ECTL is shown in Table 16-66.

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Event control register for IO GPIO15 This register controls the Event configuration and behaviour

Table 16-66 GPIO15ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.65 GPIO16CFG Register (Offset = 00010000h) [Reset = 00000000h]

GPIO16CFG is shown in Table 16-67.

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CFG register for IO GPIO16. This register configures the corresponding pad

Table 16-67 GPIO16CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.66 GPIO16PCTL Register (Offset = 00010004h) [Reset = 00000000h]

GPIO16PCTL is shown in Table 16-68.

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Pull control register of IO GPIO16 This register configures the pull control

Table 16-68 GPIO16PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.67 GPIO16CTL Register (Offset = 00010008h) [Reset = 00000000h]

GPIO16CTL is shown in Table 16-69.

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Control register of IO GPIO16 This register controls the IO state

Table 16-69 GPIO16CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.68 GPIO16ECTL Register (Offset = 0001000Ch) [Reset = 00000000h]

GPIO16ECTL is shown in Table 16-70.

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Event control register for IO GPIO16 This register controls the Event configuration and behaviour

Table 16-70 GPIO16ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.69 GPIO17CFG Register (Offset = 00011000h) [Reset = 00000000h]

GPIO17CFG is shown in Table 16-71.

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CFG register for IO GPIO17. This register configures the corresponding pad

Table 16-71 GPIO17CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.70 GPIO17PCTL Register (Offset = 00011004h) [Reset = 00000000h]

GPIO17PCTL is shown in Table 16-72.

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Pull control register of IO GPIO17 This register configures the pull control

Table 16-72 GPIO17PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.71 GPIO17CTL Register (Offset = 00011008h) [Reset = 00000000h]

GPIO17CTL is shown in Table 16-73.

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Control register of IO GPIO17 This register controls the IO state

Table 16-73 GPIO17CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.72 GPIO17ECTL Register (Offset = 0001100Ch) [Reset = 00000000h]

GPIO17ECTL is shown in Table 16-74.

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Event control register for IO GPIO17 This register controls the Event configuration and behaviour

Table 16-74 GPIO17ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.73 GPIO18CFG Register (Offset = 00012000h) [Reset = 00000000h]

GPIO18CFG is shown in Table 16-75.

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CFG register for IO GPIO18. This register configures the corresponding pad

Table 16-75 GPIO18CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.74 GPIO18PCTL Register (Offset = 00012004h) [Reset = 00000000h]

GPIO18PCTL is shown in Table 16-76.

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Pull control register of IO GPIO18 This register configures the pull control

Table 16-76 GPIO18PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.75 GPIO18CTL Register (Offset = 00012008h) [Reset = 00000000h]

GPIO18CTL is shown in Table 16-77.

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Control register of IO GPIO18 This register controls the IO state

Table 16-77 GPIO18CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.76 GPIO18ECTL Register (Offset = 0001200Ch) [Reset = 00000000h]

GPIO18ECTL is shown in Table 16-78.

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Event control register for IO GPIO18 This register controls the Event configuration and behaviour

Table 16-78 GPIO18ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.77 GPIO19CFG Register (Offset = 00013000h) [Reset = 00000000h]

GPIO19CFG is shown in Table 16-79.

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CFG register for IO GPIO19. This register configures the corresponding pad

Table 16-79 GPIO19CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.78 GPIO19PCTL Register (Offset = 00013004h) [Reset = 00000000h]

GPIO19PCTL is shown in Table 16-80.

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Pull control register of IO GPIO19 This register configures the pull control

Table 16-80 GPIO19PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.79 GPIO19CTL Register (Offset = 00013008h) [Reset = 00000000h]

GPIO19CTL is shown in Table 16-81.

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Control register of IO GPIO19 This register controls the IO state

Table 16-81 GPIO19CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.80 GPIO19ECTL Register (Offset = 0001300Ch) [Reset = 00000000h]

GPIO19ECTL is shown in Table 16-82.

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Event control register for IO GPIO19 This register controls the Event configuration and behaviour

Table 16-82 GPIO19ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.81 GPIO20CFG Register (Offset = 00014000h) [Reset = 00000000h]

GPIO20CFG is shown in Table 16-83.

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CFG register for IO GPIO20. This register configures the corresponding pad

Table 16-83 GPIO20CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W0hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.82 GPIO20PCTL Register (Offset = 00014004h) [Reset = 00000000h]

GPIO20PCTL is shown in Table 16-84.

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Pull control register of IO GPIO20 This register configures the pull control

Table 16-84 GPIO20PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.83 GPIO20CTL Register (Offset = 00014008h) [Reset = 00000000h]

GPIO20CTL is shown in Table 16-85.

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Control register of IO GPIO20 This register controls the IO state

Table 16-85 GPIO20CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.84 GPIO20ECTL Register (Offset = 0001400Ch) [Reset = 00000000h]

GPIO20ECTL is shown in Table 16-86.

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Event control register for IO GPIO20 This register controls the Event configuration and behaviour

Table 16-86 GPIO20ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.85 GPIO21CFG Register (Offset = 00015000h) [Reset = 00000000h]

GPIO21CFG is shown in Table 16-87.

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CFG register for IO GPIO21. This register configures the corresponding pad

Table 16-87 GPIO21CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.86 GPIO21PCTL Register (Offset = 00015004h) [Reset = 00000000h]

GPIO21PCTL is shown in Table 16-88.

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Pull control register of IO GPIO21 This register configures the pull control

Table 16-88 GPIO21PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.87 GPIO21CTL Register (Offset = 00015008h) [Reset = 00000000h]

GPIO21CTL is shown in Table 16-89.

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Control register of IO GPIO21 This register controls the IO state

Table 16-89 GPIO21CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.88 GPIO21ECTL Register (Offset = 0001500Ch) [Reset = 00000000h]

GPIO21ECTL is shown in Table 16-90.

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Event control register for IO GPIO21 This register controls the Event configuration and behaviour

Table 16-90 GPIO21ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.89 GPIO22CFG Register (Offset = 00016000h) [Reset = 00000000h]

GPIO22CFG is shown in Table 16-91.

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CFG register for IO GPIO22. This register configures the corresponding pad

Table 16-91 GPIO22CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.90 GPIO22PCTL Register (Offset = 00016004h) [Reset = 00000000h]

GPIO22PCTL is shown in Table 16-92.

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Pull control register of IO GPIO22 This register configures the pull control

Table 16-92 GPIO22PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.91 GPIO22CTL Register (Offset = 00016008h) [Reset = 00000000h]

GPIO22CTL is shown in Table 16-93.

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Control register of IO GPIO22 This register controls the IO state

Table 16-93 GPIO22CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.92 GPIO22ECTL Register (Offset = 0001600Ch) [Reset = 00000000h]

GPIO22ECTL is shown in Table 16-94.

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Event control register for IO GPIO22 This register controls the Event configuration and behaviour

Table 16-94 GPIO22ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.93 GPIO23CFG Register (Offset = 00017000h) [Reset = 00000000h]

GPIO23CFG is shown in Table 16-95.

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CFG register for IO GPIO23. This register configures the corresponding pad

Table 16-95 GPIO23CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.94 GPIO23PCTL Register (Offset = 00017004h) [Reset = 00000000h]

GPIO23PCTL is shown in Table 16-96.

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Pull control register of IO GPIO23 This register configures the pull control

Table 16-96 GPIO23PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.95 GPIO23CTL Register (Offset = 00017008h) [Reset = 00000000h]

GPIO23CTL is shown in Table 16-97.

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Control register of IO GPIO23 This register controls the IO state

Table 16-97 GPIO23CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.96 GPIO23ECTL Register (Offset = 0001700Ch) [Reset = 00000000h]

GPIO23ECTL is shown in Table 16-98.

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Event control register for IO GPIO23 This register controls the Event configuration and behaviour

Table 16-98 GPIO23ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.97 GPIO24CFG Register (Offset = 00018000h) [Reset = 00000000h]

GPIO24CFG is shown in Table 16-99.

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CFG register for IO GPIO24. This register configures the corresponding pad

Table 16-99 GPIO24CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W0hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.98 GPIO24PCTL Register (Offset = 00018004h) [Reset = 00000000h]

GPIO24PCTL is shown in Table 16-100.

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Pull control register of IO GPIO24 This register configures the pull control

Table 16-100 GPIO24PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.99 GPIO24CTL Register (Offset = 00018008h) [Reset = 00000000h]

GPIO24CTL is shown in Table 16-101.

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Control register of IO GPIO24 This register controls the IO state

Table 16-101 GPIO24CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.100 GPIO24ECTL Register (Offset = 0001800Ch) [Reset = 00000000h]

GPIO24ECTL is shown in Table 16-102.

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Event control register for IO GPIO24 This register controls the Event configuration and behaviour

Table 16-102 GPIO24ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.101 GPIO25CFG Register (Offset = 00019000h) [Reset = 00000000h]

GPIO25CFG is shown in Table 16-103.

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CFG register for IO GPIO25. This register configures the corresponding pad

Table 16-103 GPIO25CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.102 GPIO25PCTL Register (Offset = 00019004h) [Reset = 00000000h]

GPIO25PCTL is shown in Table 16-104.

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Pull control register of IO GPIO25 This register configures the pull control

Table 16-104 GPIO25PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.103 GPIO25CTL Register (Offset = 00019008h) [Reset = 00000000h]

GPIO25CTL is shown in Table 16-105.

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Control register of IO GPIO25 This register controls the IO state

Table 16-105 GPIO25CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.104 GPIO25ECTL Register (Offset = 0001900Ch) [Reset = 00000000h]

GPIO25ECTL is shown in Table 16-106.

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Event control register for IO GPIO25 This register controls the Event configuration and behaviour

Table 16-106 GPIO25ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.105 GPIO26CFG Register (Offset = 0001A000h) [Reset = 00000000h]

GPIO26CFG is shown in Table 16-107.

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CFG register for IO GPIO26. This register configures the corresponding pad

Table 16-107 GPIO26CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.106 GPIO26PCTL Register (Offset = 0001A004h) [Reset = 00000000h]

GPIO26PCTL is shown in Table 16-108.

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Pull control register of IO GPIO26 This register configures the pull control

Table 16-108 GPIO26PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.107 GPIO26CTL Register (Offset = 0001A008h) [Reset = 00000000h]

GPIO26CTL is shown in Table 16-109.

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Control register of IO GPIO26 This register controls the IO state

Table 16-109 GPIO26CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.108 GPIO26ECTL Register (Offset = 0001A00Ch) [Reset = 00000000h]

GPIO26ECTL is shown in Table 16-110.

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Event control register for IO GPIO26 This register controls the Event configuration and behaviour

Table 16-110 GPIO26ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.109 GPIO27CFG Register (Offset = 0001B000h) [Reset = 00000000h]

GPIO27CFG is shown in Table 16-111.

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CFG register for IO GPIO27. This register configures the corresponding pad

Table 16-111 GPIO27CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.110 GPIO27PCTL Register (Offset = 0001B004h) [Reset = 00000000h]

GPIO27PCTL is shown in Table 16-112.

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Pull control register of IO GPIO27 This register configures the pull control

Table 16-112 GPIO27PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.111 GPIO27CTL Register (Offset = 0001B008h) [Reset = 00000000h]

GPIO27CTL is shown in Table 16-113.

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Control register of IO GPIO27 This register controls the IO state

Table 16-113 GPIO27CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.112 GPIO27ECTL Register (Offset = 0001B00Ch) [Reset = 00000000h]

GPIO27ECTL is shown in Table 16-114.

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Event control register for IO GPIO27 This register controls the Event configuration and behaviour

Table 16-114 GPIO27ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.113 GPIO28CFG Register (Offset = 0001C000h) [Reset = 00000000h]

GPIO28CFG is shown in Table 16-115.

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CFG register for IO GPIO28. This register configures the corresponding pad

Table 16-115 GPIO28CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.114 GPIO28PCTL Register (Offset = 0001C004h) [Reset = 00000000h]

GPIO28PCTL is shown in Table 16-116.

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Pull control register of IO GPIO28 This register configures the pull control

Table 16-116 GPIO28PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.115 GPIO28CTL Register (Offset = 0001C008h) [Reset = 00000000h]

GPIO28CTL is shown in Table 16-117.

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Control register of IO GPIO28 This register controls the IO state

Table 16-117 GPIO28CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.116 GPIO28ECTL Register (Offset = 0001C00Ch) [Reset = 00000000h]

GPIO28ECTL is shown in Table 16-118.

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Event control register for IO GPIO28 This register controls the Event configuration and behaviour

Table 16-118 GPIO28ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.117 GPIO29CFG Register (Offset = 0001D000h) [Reset = 00000000h]

GPIO29CFG is shown in Table 16-119.

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CFG register for IO GPIO29. This register configures the corresponding pad

Table 16-119 GPIO29CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.118 GPIO29PCTL Register (Offset = 0001D004h) [Reset = 00000000h]

GPIO29PCTL is shown in Table 16-120.

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Pull control register of IO GPIO29 This register configures the pull control

Table 16-120 GPIO29PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.119 GPIO29CTL Register (Offset = 0001D008h) [Reset = 00000000h]

GPIO29CTL is shown in Table 16-121.

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Control register of IO GPIO29 This register controls the IO state

Table 16-121 GPIO29CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.120 GPIO29ECTL Register (Offset = 0001D00Ch) [Reset = 00000000h]

GPIO29ECTL is shown in Table 16-122.

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Event control register for IO GPIO29 This register controls the Event configuration and behaviour

Table 16-122 GPIO29ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.121 GPIO30CFG Register (Offset = 0001E000h) [Reset = 00000000h]

GPIO30CFG is shown in Table 16-123.

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CFG register for IO GPIO30. This register configures the corresponding pad

Table 16-123 GPIO30CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.122 GPIO30PCTL Register (Offset = 0001E004h) [Reset = 00000000h]

GPIO30PCTL is shown in Table 16-124.

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Pull control register of IO GPIO30 This register configures the pull control

Table 16-124 GPIO30PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.123 GPIO30CTL Register (Offset = 0001E008h) [Reset = 00000000h]

GPIO30CTL is shown in Table 16-125.

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Control register of IO GPIO30 This register controls the IO state

Table 16-125 GPIO30CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.124 GPIO30ECTL Register (Offset = 0001E00Ch) [Reset = 00000000h]

GPIO30ECTL is shown in Table 16-126.

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Event control register for IO GPIO30 This register controls the Event configuration and behaviour

Table 16-126 GPIO30ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.125 GPIO31CFG Register (Offset = 0001F000h) [Reset = 00000000h]

GPIO31CFG is shown in Table 16-127.

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CFG register for IO GPIO31. This register configures the corresponding pad

Table 16-127 GPIO31CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.126 GPIO31PCTL Register (Offset = 0001F004h) [Reset = 00000000h]

GPIO31PCTL is shown in Table 16-128.

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Pull control register of IO GPIO31 This register configures the pull control

Table 16-128 GPIO31PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.127 GPIO31CTL Register (Offset = 0001F008h) [Reset = 00000000h]

GPIO31CTL is shown in Table 16-129.

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Control register of IO GPIO31 This register controls the IO state

Table 16-129 GPIO31CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.128 GPIO31ECTL Register (Offset = 0001F00Ch) [Reset = 00000000h]

GPIO31ECTL is shown in Table 16-130.

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Event control register for IO GPIO31 This register controls the Event configuration and behaviour

Table 16-130 GPIO31ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.129 GPIO32CFG Register (Offset = 00020000h) [Reset = 00000000h]

GPIO32CFG is shown in Table 16-131.

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CFG register for IO GPIO32. This register configures the corresponding pad

Table 16-131 GPIO32CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.130 GPIO32PCTL Register (Offset = 00020004h) [Reset = 00000000h]

GPIO32PCTL is shown in Table 16-132.

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Pull control register of IO GPIO32 This register configures the pull control

Table 16-132 GPIO32PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.131 GPIO32CTL Register (Offset = 00020008h) [Reset = 00000000h]

GPIO32CTL is shown in Table 16-133.

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Control register of IO GPIO32 This register controls the IO state

Table 16-133 GPIO32CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.132 GPIO32ECTL Register (Offset = 0002000Ch) [Reset = 00000000h]

GPIO32ECTL is shown in Table 16-134.

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Event control register for IO GPIO32 This register controls the Event configuration and behaviour

Table 16-134 GPIO32ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.133 GPIO33CFG Register (Offset = 00021000h) [Reset = 00000000h]

GPIO33CFG is shown in Table 16-135.

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CFG register for IO GPIO33. This register configures the corresponding pad

Table 16-135 GPIO33CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.134 GPIO33PCTL Register (Offset = 00021004h) [Reset = 00000000h]

GPIO33PCTL is shown in Table 16-136.

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Pull control register of IO GPIO33 This register configures the pull control

Table 16-136 GPIO33PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.135 GPIO33CTL Register (Offset = 00021008h) [Reset = 00000000h]

GPIO33CTL is shown in Table 16-137.

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Control register of IO GPIO33 This register controls the IO state

Table 16-137 GPIO33CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.136 GPIO33ECTL Register (Offset = 0002100Ch) [Reset = 00000000h]

GPIO33ECTL is shown in Table 16-138.

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Event control register for IO GPIO33 This register controls the Event configuration and behaviour

Table 16-138 GPIO33ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.137 GPIO34CFG Register (Offset = 00022000h) [Reset = 00000000h]

GPIO34CFG is shown in Table 16-139.

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CFG register for IO GPIO34. This register configures the corresponding pad

Table 16-139 GPIO34CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.138 GPIO34PCTL Register (Offset = 00022004h) [Reset = 00000000h]

GPIO34PCTL is shown in Table 16-140.

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Pull control register of IO GPIO34 This register configures the pull control

Table 16-140 GPIO34PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.139 GPIO34CTL Register (Offset = 00022008h) [Reset = 00000000h]

GPIO34CTL is shown in Table 16-141.

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Control register of IO GPIO34 This register controls the IO state

Table 16-141 GPIO34CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.140 GPIO34ECTL Register (Offset = 0002200Ch) [Reset = 00000000h]

GPIO34ECTL is shown in Table 16-142.

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Event control register for IO GPIO34 This register controls the Event configuration and behaviour

Table 16-142 GPIO34ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.141 GPIO35CFG Register (Offset = 00023000h) [Reset = 00000000h]

GPIO35CFG is shown in Table 16-143.

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CFG register for IO GPIO35. This register configures the corresponding pad

Table 16-143 GPIO35CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.142 GPIO35PCTL Register (Offset = 00023004h) [Reset = 00000000h]

GPIO35PCTL is shown in Table 16-144.

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Pull control register of IO GPIO35 This register configures the pull control

Table 16-144 GPIO35PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.143 GPIO35CTL Register (Offset = 00023008h) [Reset = 00000000h]

GPIO35CTL is shown in Table 16-145.

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Control register of IO GPIO35 This register controls the IO state

Table 16-145 GPIO35CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.144 GPIO35ECTL Register (Offset = 0002300Ch) [Reset = 00000000h]

GPIO35ECTL is shown in Table 16-146.

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Event control register for IO GPIO35 This register controls the Event configuration and behaviour

Table 16-146 GPIO35ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.145 GPIO36CFG Register (Offset = 00024000h) [Reset = 00000000h]

GPIO36CFG is shown in Table 16-147.

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CFG register for IO GPIO36. This register configures the corresponding pad

Table 16-147 GPIO36CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.146 GPIO36PCTL Register (Offset = 00024004h) [Reset = 00000000h]

GPIO36PCTL is shown in Table 16-148.

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Pull control register of IO GPIO36 This register configures the pull control

Table 16-148 GPIO36PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W2hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.147 GPIO36CTL Register (Offset = 00024008h) [Reset = 00000000h]

GPIO36CTL is shown in Table 16-149.

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Control register of IO GPIO36 This register controls the IO state

Table 16-149 GPIO36CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.148 GPIO36ECTL Register (Offset = 0002400Ch) [Reset = 00000000h]

GPIO36ECTL is shown in Table 16-150.

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Event control register for IO GPIO36 This register controls the Event configuration and behaviour

Table 16-150 GPIO36ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.149 GPIO37CFG Register (Offset = 00025000h) [Reset = 00000000h]

GPIO37CFG is shown in Table 16-151.

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CFG register for IO GPIO37. This register configures the corresponding pad

Table 16-151 GPIO37CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.150 GPIO37PCTL Register (Offset = 00025004h) [Reset = 00000000h]

GPIO37PCTL is shown in Table 16-152.

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Pull control register of IO GPIO37 This register configures the pull control

Table 16-152 GPIO37PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W2hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.151 GPIO37CTL Register (Offset = 00025008h) [Reset = 00000000h]

GPIO37CTL is shown in Table 16-153.

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Control register of IO GPIO37 This register controls the IO state

Table 16-153 GPIO37CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.152 GPIO37ECTL Register (Offset = 0002500Ch) [Reset = 00000000h]

GPIO37ECTL is shown in Table 16-154.

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Event control register for IO GPIO37 This register controls the Event configuration and behaviour

Table 16-154 GPIO37ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.153 GPIO38CFG Register (Offset = 00026000h) [Reset = 00000000h]

GPIO38CFG is shown in Table 16-155.

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CFG register for IO GPIO38. This register configures the corresponding pad

Table 16-155 GPIO38CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.154 GPIO38PCTL Register (Offset = 00026004h) [Reset = 00000000h]

GPIO38PCTL is shown in Table 16-156.

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Pull control register of IO GPIO38 This register configures the pull control

Table 16-156 GPIO38PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.155 GPIO38CTL Register (Offset = 00026008h) [Reset = 00000000h]

GPIO38CTL is shown in Table 16-157.

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Control register of IO GPIO38 This register controls the IO state

Table 16-157 GPIO38CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.156 GPIO38ECTL Register (Offset = 0002600Ch) [Reset = 00000000h]

GPIO38ECTL is shown in Table 16-158.

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Event control register for IO GPIO38 This register controls the Event configuration and behaviour

Table 16-158 GPIO38ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.157 GPIO39CFG Register (Offset = 00027000h) [Reset = 00000000h]

GPIO39CFG is shown in Table 16-159.

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CFG register for IO GPIO39. This register configures the corresponding pad

Table 16-159 GPIO39CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.158 GPIO39PCTL Register (Offset = 00027004h) [Reset = 00000000h]

GPIO39PCTL is shown in Table 16-160.

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Pull control register of IO GPIO39 This register configures the pull control

Table 16-160 GPIO39PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.159 GPIO39CTL Register (Offset = 00027008h) [Reset = 00000000h]

GPIO39CTL is shown in Table 16-161.

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Control register of IO GPIO39 This register controls the IO state

Table 16-161 GPIO39CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.160 GPIO39ECTL Register (Offset = 0002700Ch) [Reset = 00000000h]

GPIO39ECTL is shown in Table 16-162.

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Event control register for IO GPIO39 This register controls the Event configuration and behaviour

Table 16-162 GPIO39ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.161 GPIO40CFG Register (Offset = 00028000h) [Reset = 00000000h]

GPIO40CFG is shown in Table 16-163.

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CFG register for IO GPIO40. This register configures the corresponding pad

Table 16-163 GPIO40CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.162 GPIO40PCTL Register (Offset = 00028004h) [Reset = 00000000h]

GPIO40PCTL is shown in Table 16-164.

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Pull control register of IO GPIO40 This register configures the pull control

Table 16-164 GPIO40PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.163 GPIO40CTL Register (Offset = 00028008h) [Reset = 00000000h]

GPIO40CTL is shown in Table 16-165.

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Control register of IO GPIO40 This register controls the IO state

Table 16-165 GPIO40CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.164 GPIO40ECTL Register (Offset = 0002800Ch) [Reset = 00000000h]

GPIO40ECTL is shown in Table 16-166.

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Event control register for IO GPIO40 This register controls the Event configuration and behaviour

Table 16-166 GPIO40ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.165 GPIO41CFG Register (Offset = 00029000h) [Reset = 00000000h]

GPIO41CFG is shown in Table 16-167.

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CFG register for IO GPIO41. This register configures the corresponding pad

Table 16-167 GPIO41CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.166 GPIO41PCTL Register (Offset = 00029004h) [Reset = 00000000h]

GPIO41PCTL is shown in Table 16-168.

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Pull control register of IO GPIO41 This register configures the pull control

Table 16-168 GPIO41PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.167 GPIO41CTL Register (Offset = 00029008h) [Reset = 00000000h]

GPIO41CTL is shown in Table 16-169.

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Control register of IO GPIO41 This register controls the IO state

Table 16-169 GPIO41CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.168 GPIO41ECTL Register (Offset = 0002900Ch) [Reset = 00000000h]

GPIO41ECTL is shown in Table 16-170.

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Event control register for IO GPIO41 This register controls the Event configuration and behaviour

Table 16-170 GPIO41ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.169 GPIO42CFG Register (Offset = 0002A000h) [Reset = 00000000h]

GPIO42CFG is shown in Table 16-171.

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CFG register for IO GPIO42. This register configures the corresponding pad

Table 16-171 GPIO42CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.170 GPIO42PCTL Register (Offset = 0002A004h) [Reset = 00000000h]

GPIO42PCTL is shown in Table 16-172.

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Pull control register of IO GPIO42 This register configures the pull control

Table 16-172 GPIO42PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.171 GPIO42CTL Register (Offset = 0002A008h) [Reset = 00000000h]

GPIO42CTL is shown in Table 16-173.

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Control register of IO GPIO42 This register controls the IO state

Table 16-173 GPIO42CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.172 GPIO42ECTL Register (Offset = 0002A00Ch) [Reset = 00000000h]

GPIO42ECTL is shown in Table 16-174.

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Event control register for IO GPIO42 This register controls the Event configuration and behaviour

Table 16-174 GPIO42ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.173 GPIO43CFG Register (Offset = 0002B000h) [Reset = 00000000h]

GPIO43CFG is shown in Table 16-175.

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CFG register for IO GPIO43. This register configures the corresponding pad

Table 16-175 GPIO43CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.174 GPIO43PCTL Register (Offset = 0002B004h) [Reset = 00000000h]

GPIO43PCTL is shown in Table 16-176.

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Pull control register of IO GPIO43 This register configures the pull control

Table 16-176 GPIO43PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.175 GPIO43CTL Register (Offset = 0002B008h) [Reset = 00000000h]

GPIO43CTL is shown in Table 16-177.

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Control register of IO GPIO43 This register controls the IO state

Table 16-177 GPIO43CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.176 GPIO43ECTL Register (Offset = 0002B00Ch) [Reset = 00000000h]

GPIO43ECTL is shown in Table 16-178.

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Event control register for IO GPIO43 This register controls the Event configuration and behaviour

Table 16-178 GPIO43ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.177 GPIO44CFG Register (Offset = 0002C000h) [Reset = 00000000h]

GPIO44CFG is shown in Table 16-179.

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CFG register for IO GPIO44. This register configures the corresponding pad

Table 16-179 GPIO44CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.178 GPIO44PCTL Register (Offset = 0002C004h) [Reset = 00000000h]

GPIO44PCTL is shown in Table 16-180.

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Pull control register of IO GPIO44 This register configures the pull control

Table 16-180 GPIO44PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.179 GPIO44CTL Register (Offset = 0002C008h) [Reset = 00000000h]

GPIO44CTL is shown in Table 16-181.

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Control register of IO GPIO44 This register controls the IO state

Table 16-181 GPIO44CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.180 GPIO44ECTL Register (Offset = 0002C00Ch) [Reset = 00000000h]

GPIO44ECTL is shown in Table 16-182.

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Event control register for IO GPIO44 This register controls the Event configuration and behaviour

Table 16-182 GPIO44ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.181 SCLKIPCFG Register (Offset = 0002D004h) [Reset = 00000000h]

SCLKIPCFG is shown in Table 16-183.

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Port configuration register for IO SLOW_CLOCK_IN

Table 16-183 SCLKIPCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- slow_clock_in sel 5'd2 -- wifi_gpio_0 sel 5'd9 -- gpt1_1 sel 5'd10 -- gpt0_1 sel 5'd21 -- coex_req
  • 0h = reserved
  • 1h = slow_clock_in
  • 2h = wifi_gpio_0
  • 3h = reserved
  • 4h = reserved
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = gpt1_1
  • Ah = gpt0_1
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = coex_req
  • 16h = reserved
  • 17h = reserved
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.182 LFXTNPCFG Register (Offset = 0002D008h) [Reset = 00000000h]

LFXTNPCFG is shown in Table 16-184.

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Port configuration register for IO LFXTAL_N

Table 16-184 LFXTNPCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- lfxt_n sel 5'd2 -- wifi_gpio_1 sel 5'd7 -- gpt1_pre_event sel 5'd8 -- gpt0_pre_event sel 5'd9 -- gpt1_0 sel 5'd10 -- gpt0_0 sel 5'd11 -- gpt_infrared sel 5'd19 -- sdio_oob_irq sel 5'd20 -- coex_grant sel 5'd21 -- coex_req sel 5'd23 -- ant_sel_0
  • 0h = lfxt_n
  • 1h = reserved
  • 2h = wifi_gpio_1
  • 3h = reserved
  • 4h = reserved
  • 5h = reserved
  • 6h = reserved
  • 7h = gpt1_pre_event
  • 8h = gpt0_pre_event
  • 9h = gpt1_0
  • Ah = gpt0_0
  • Bh = gpt_infrared
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = sdio_oob_irq
  • 14h = coex_grant
  • 15h = coex_req
  • 16h = reserved
  • 17h = ant_sel_0
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.183 GPIO2PCFG Register (Offset = 0002D00Ch) [Reset = 00000000h]

GPIO2PCFG is shown in Table 16-185.

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Port configuration register for IO GPIO2

Table 16-185 GPIO2PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_reset_ram sel 5'd2 -- wifi_gpio_2 sel 5'd3 -- sdio_mmc_cd sel 5'd6 -- i2c1_clk sel 5'd9 -- gpt1_3 sel 5'd10 -- dcan_tx sel 5'd11 -- wake_observe_bus_6 sel 5'd12 -- debug_bus_4 sel 5'd16 -- spi0_cs4 sel 5'd18 -- gpt1_pre_event sel 5'd19 -- sdio_oob_irq sel 5'd20 -- coex_grant sel 5'd21 -- coex_req sel 5'd22 -- ble_rftrc sel 5'd23 -- ant_sel_2 sel 5'd24 -- cca sel 5'd26 -- trclk
  • 0h = reserved
  • 1h = xspi_reset_ram
  • 2h = wifi_gpio_2
  • 3h = sdio_mmc_cd
  • 4h = reserved
  • 5h = reserved
  • 6h = i2c1_clk
  • 7h = reserved
  • 8h = reserved
  • 9h = gpt1_3
  • Ah = dcan_tx
  • Bh = wake_observe_bus_6
  • Ch = debug_bus_4
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi0_cs4
  • 11h = reserved
  • 12h = gpt1_pre_event
  • 13h = sdio_oob_irq
  • 14h = coex_grant
  • 15h = coex_req
  • 16h = ble_rftrc
  • 17h = ant_sel_2
  • 18h = cca
  • 19h = reserved
  • 1Ah = trclk
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.184 GPIO3PCFG Register (Offset = 0002D010h) [Reset = 00000000h]

GPIO3PCFG is shown in Table 16-186.

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Port configuration register for IO GPIO3

Table 16-186 GPIO3PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- uart1_tx sel 5'd2 -- wifi_gpio_3 sel 5'd3 -- sdio_mmc_wp sel 5'd4 -- spi1_clk sel 5'd5 -- uart1_rts sel 5'd6 -- i2s_mclk sel 5'd7 -- i2s_data0 sel 5'd8 -- pdm_data1 sel 5'd9 -- gpt1_0 sel 5'd10 -- dcan_rx sel 5'd11 -- wake_observe_bus_7 sel 5'd12 -- debug_bus_0 sel 5'd16 -- spi0_cs3 sel 5'd17 -- xspi_cs_ram sel 5'd18 -- gpt1_1_n sel 5'd19 -- sdio_clk sel 5'd20 -- coex_req sel 5'd21 -- gpt0_0_n sel 5'd22 -- gpt_infrared sel 5'd23 -- ant_sel_3 sel 5'd24 -- ble_rfc_gpo_7 sel 5'd25 -- swo_m3 sel 5'd27 -- swo_m33 sel 5'd28 -- i2c1_data sel 5'd30 -- uart2_tx
  • 0h = reserved
  • 1h = uart1_tx
  • 2h = wifi_gpio_3
  • 3h = sdio_mmc_wp
  • 4h = spi1_clk
  • 5h = uart1_rts
  • 6h = i2s_mclk
  • 7h = i2s_data0
  • 8h = pdm_data1
  • 9h = gpt1_0
  • Ah = dcan_rx
  • Bh = wake_observe_bus_7
  • Ch = debug_bus_0
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi0_cs3
  • 11h = xspi_cs_ram
  • 12h = gpt1_1_n
  • 13h = sdio_clk
  • 14h = coex_req
  • 15h = gpt0_0_n
  • 16h = gpt_infrared
  • 17h = ant_sel_3
  • 18h = ble_rfc_gpo_7
  • 19h = swo_m3
  • 1Ah = reserved
  • 1Bh = swo_m33
  • 1Ch = i2c1_data
  • 1Dh = reserved
  • 1Eh = uart2_tx
  • 1Fh = reserved

16.8.185 GPIO4PCFG Register (Offset = 0002D014h) [Reset = 00000000h]

GPIO4PCFG is shown in Table 16-187.

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Port configuration register for IO GPIO4

Table 16-187 GPIO4PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- uart1_rx sel 5'd2 -- wifi_gpio_4 sel 5'd3 -- sdio_mmc_cd sel 5'd4 -- spi1_cs1 sel 5'd5 -- uart1_cts sel 5'd6 -- i2s_bclk sel 5'd7 -- i2s_data1 sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt1_1 sel 5'd10 -- dcan_tx sel 5'd11 -- wake_observe_bus_8 sel 5'd12 -- debug_bus_1 sel 5'd16 -- spi0_cs2 sel 5'd17 -- ext_clk sel 5'd18 -- gpt1_0_n sel 5'd19 -- sdio_cmd sel 5'd20 -- coex_priority sel 5'd21 -- gpt0_1_n sel 5'd24 -- ble_rfc_gpo_6 sel 5'd28 -- i2c1_clk sel 5'd30 -- uart2_rx
  • 0h = reserved
  • 1h = uart1_rx
  • 2h = wifi_gpio_4
  • 3h = sdio_mmc_cd
  • 4h = spi1_cs1
  • 5h = uart1_cts
  • 6h = i2s_bclk
  • 7h = i2s_data1
  • 8h = pdm_bclk
  • 9h = gpt1_1
  • Ah = dcan_tx
  • Bh = wake_observe_bus_8
  • Ch = debug_bus_1
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi0_cs2
  • 11h = ext_clk
  • 12h = gpt1_0_n
  • 13h = sdio_cmd
  • 14h = coex_priority
  • 15h = gpt0_1_n
  • 16h = reserved
  • 17h = reserved
  • 18h = ble_rfc_gpo_6
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = i2c1_clk
  • 1Dh = reserved
  • 1Eh = uart2_rx
  • 1Fh = reserved

16.8.186 GPIO5PCFG Register (Offset = 0002D018h) [Reset = 00000000h]

GPIO5PCFG is shown in Table 16-188.

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Port configuration register for IO GPIO5

Table 16-188 GPIO5PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_reset_ram sel 5'd2 -- wifi_gpio_5 sel 5'd3 -- sdio_mmc_pow2 sel 5'd4 -- spi1_miso sel 5'd5 -- uart1_tx sel 5'd6 -- i2c0_clk sel 5'd7 -- i2s_mclk sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt1_2 sel 5'd10 -- dcan_tx sel 5'd11 -- jtag_tdi sel 5'd12 -- debug_bus_11 sel 5'd16 -- spi0_cs4 sel 5'd17 -- ext_clk sel 5'd18 -- gpt1_0_n sel 5'd19 -- sdio_d0 sel 5'd20 -- coex_req sel 5'd21 -- gpt0_2_n sel 5'd22 -- ble_rftrc sel 5'd23 -- ant_sel_1 sel 5'd25 -- ble_rfc_gpi_2 sel 5'd28 -- i2c1_data sel 5'd30 -- uart2_rts
  • 0h = reserved
  • 1h = xspi_reset_ram
  • 2h = wifi_gpio_5
  • 3h = sdio_mmc_pow2
  • 4h = spi1_miso
  • 5h = uart1_tx
  • 6h = i2c0_clk
  • 7h = i2s_mclk
  • 8h = pdm_bclk
  • 9h = gpt1_2
  • Ah = dcan_tx
  • Bh = jtag_tdi
  • Ch = debug_bus_11
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi0_cs4
  • 11h = ext_clk
  • 12h = gpt1_0_n
  • 13h = sdio_d0
  • 14h = coex_req
  • 15h = gpt0_2_n
  • 16h = ble_rftrc
  • 17h = ant_sel_1
  • 18h = reserved
  • 19h = ble_rfc_gpi_2
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = i2c1_data
  • 1Dh = reserved
  • 1Eh = uart2_rts
  • 1Fh = reserved

16.8.187 GPIO6PCFG Register (Offset = 0002D01Ch) [Reset = 00000000h]

GPIO6PCFG is shown in Table 16-189.

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Port configuration register for IO GPIO6

Table 16-189 GPIO6PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_6 sel 5'd3 -- sdio_mmc_pow1 sel 5'd4 -- spi1_mosi sel 5'd5 -- uart1_rx sel 5'd6 -- i2c0_data sel 5'd7 -- i2s_wclk sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt1_3 sel 5'd10 -- dcan_rx sel 5'd11 -- sdio_mmc_wp sel 5'd12 -- debug_bus_12 sel 5'd16 -- spi0_cs4 sel 5'd17 -- i2s_bclk sel 5'd18 -- gpt1_1_n sel 5'd19 -- sdio_d1 sel 5'd20 -- coex_priority sel 5'd21 -- gpt0_3_n sel 5'd22 -- gpt1_pre_event sel 5'd23 -- ant_sel_0 sel 5'd24 -- cca sel 5'd25 -- ble_rfc_gpi_3 sel 5'd26 -- coex_grant sel 5'd28 -- i2c1_clk sel 5'd29 -- sdio_mmc_pow2 sel 5'd30 -- uart2_cts
  • 0h = reserved
  • 1h = xspi_cs_ram
  • 2h = wifi_gpio_6
  • 3h = sdio_mmc_pow1
  • 4h = spi1_mosi
  • 5h = uart1_rx
  • 6h = i2c0_data
  • 7h = i2s_wclk
  • 8h = pdm_data0
  • 9h = gpt1_3
  • Ah = dcan_rx
  • Bh = sdio_mmc_wp
  • Ch = debug_bus_12
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi0_cs4
  • 11h = i2s_bclk
  • 12h = gpt1_1_n
  • 13h = sdio_d1
  • 14h = coex_priority
  • 15h = gpt0_3_n
  • 16h = gpt1_pre_event
  • 17h = ant_sel_0
  • 18h = cca
  • 19h = ble_rfc_gpi_3
  • 1Ah = coex_grant
  • 1Bh = reserved
  • 1Ch = i2c1_clk
  • 1Dh = sdio_mmc_pow2
  • 1Eh = uart2_cts
  • 1Fh = reserved

16.8.188 SWDIOPCFG Register (Offset = 0002D020h) [Reset = 00000000h]

SWDIOPCFG is shown in Table 16-190.

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Port configuration register for IO SWDIO

Table 16-190 SWDIOPCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- swdio sel 5'd2 -- wifi_gpio_7 sel 5'd3 -- sdio_mmc_pow2 sel 5'd4 -- jtag_tms sel 5'd23 -- ant_sel_0
  • 0h = swdio
  • 1h = reserved
  • 2h = wifi_gpio_7
  • 3h = sdio_mmc_pow2
  • 4h = jtag_tms
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = reserved
  • 16h = reserved
  • 17h = ant_sel_0
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.189 SWCLKPCFG Register (Offset = 0002D024h) [Reset = 00000000h]

SWCLKPCFG is shown in Table 16-191.

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Port configuration register for IO SWCLK

Table 16-191 SWCLKPCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- swclk sel 5'd2 -- wifi_gpio_8 sel 5'd3 -- sdio_mmc_pow1 sel 5'd4 -- jtag_tck sel 5'd23 -- ant_sel_1
  • 0h = swclk
  • 1h = reserved
  • 2h = wifi_gpio_8
  • 3h = sdio_mmc_pow1
  • 4h = jtag_tck
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = reserved
  • 16h = reserved
  • 17h = ant_sel_1
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.190 LOGGERPCFG Register (Offset = 0002D028h) [Reset = 00000000h]

LOGGERPCFG is shown in Table 16-192.

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Port configuration register for IO LOGGER

Table 16-192 LOGGERPCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- logger sel 5'd2 -- wifi_gpio_9 sel 5'd3 -- sdio_mmc_cd sel 5'd4 -- ble_rftrc sel 5'd11 -- jtag_tdo sel 5'd23 -- ant_sel_2 sel 5'd26 -- swo_m3 sel 5'd27 -- swo_m33
  • 0h = reserved
  • 1h = logger
  • 2h = wifi_gpio_9
  • 3h = sdio_mmc_cd
  • 4h = ble_rftrc
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = jtag_tdo
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = reserved
  • 16h = reserved
  • 17h = ant_sel_2
  • 18h = reserved
  • 19h = reserved
  • 1Ah = swo_m3
  • 1Bh = swo_m33
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.191 GPIO10PCFG Register (Offset = 0002D02Ch) [Reset = 00000000h]

GPIO10PCFG is shown in Table 16-193.

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Port configuration register for IO GPIO10

Table 16-193 GPIO10PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- uart1_tx sel 5'd2 -- wifi_gpio_10 sel 5'd3 -- sdio_mmc_data_3 sel 5'd4 -- spi1_clk sel 5'd5 -- uart1_rts sel 5'd6 -- i2c1_data sel 5'd7 -- i2s_data1 sel 5'd8 -- pdm_data1 sel 5'd9 -- gpt1_0 sel 5'd10 -- dcan_rx sel 5'd11 -- uart_rs232_rx sel 5'd12 -- debug_bus_10 sel 5'd16 -- spi0_cs3 sel 5'd18 -- gpt1_3_n sel 5'd19 -- sdio_d3 sel 5'd20 -- coex_priority sel 5'd21 -- coex_grant sel 5'd23 -- ant_sel_2 sel 5'd24 -- cca sel 5'd25 -- ble_rfc_gpi_1 sel 5'd26 -- trdata_0 sel 5'd30 -- uart2_rts sel 5'd31 -- uart2_tx
  • 0h = reserved
  • 1h = uart1_tx
  • 2h = wifi_gpio_10
  • 3h = sdio_mmc_data_3
  • 4h = spi1_clk
  • 5h = uart1_rts
  • 6h = i2c1_data
  • 7h = i2s_data1
  • 8h = pdm_data1
  • 9h = gpt1_0
  • Ah = dcan_rx
  • Bh = uart_rs232_rx
  • Ch = debug_bus_10
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi0_cs3
  • 11h = reserved
  • 12h = gpt1_3_n
  • 13h = sdio_d3
  • 14h = coex_priority
  • 15h = coex_grant
  • 16h = reserved
  • 17h = ant_sel_2
  • 18h = cca
  • 19h = ble_rfc_gpi_1
  • 1Ah = trdata_0
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = uart2_rts
  • 1Fh = uart2_tx

16.8.192 GPIO11PCFG Register (Offset = 0002D030h) [Reset = 00000000h]

GPIO11PCFG is shown in Table 16-194.

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Port configuration register for IO GPIO11

Table 16-194 GPIO11PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- uart1_rx sel 5'd2 -- wifi_gpio_11 sel 5'd3 -- sdio_mmc_data_2 sel 5'd4 -- spi1_cs1 sel 5'd5 -- uart1_cts sel 5'd6 -- i2c1_clk sel 5'd7 -- i2s_data0 sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt1_1 sel 5'd10 -- dcan_tx sel 5'd11 -- uart_rs232_tx sel 5'd12 -- debug_bus_9 sel 5'd16 -- spi0_cs2 sel 5'd17 -- ext_clk sel 5'd18 -- gpt1_2_n sel 5'd19 -- sdio_d2 sel 5'd20 -- coex_req sel 5'd23 -- ant_sel_3 sel 5'd24 -- cca sel 5'd25 -- swo_m3 sel 5'd26 -- trdata_1 sel 5'd30 -- uart2_cts sel 5'd31 -- uart2_rx
  • 0h = reserved
  • 1h = uart1_rx
  • 2h = wifi_gpio_11
  • 3h = sdio_mmc_data_2
  • 4h = spi1_cs1
  • 5h = uart1_cts
  • 6h = i2c1_clk
  • 7h = i2s_data0
  • 8h = pdm_data0
  • 9h = gpt1_1
  • Ah = dcan_tx
  • Bh = uart_rs232_tx
  • Ch = debug_bus_9
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi0_cs2
  • 11h = ext_clk
  • 12h = gpt1_2_n
  • 13h = sdio_d2
  • 14h = coex_req
  • 15h = reserved
  • 16h = reserved
  • 17h = ant_sel_3
  • 18h = cca
  • 19h = swo_m3
  • 1Ah = trdata_1
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = uart2_cts
  • 1Fh = uart2_rx

16.8.193 GPIO12PCFG Register (Offset = 0002D034h) [Reset = 00000000h]

GPIO12PCFG is shown in Table 16-195.

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Port configuration register for IO GPIO12

Table 16-195 GPIO12PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_12 sel 5'd3 -- sdio_mmc_data_1 sel 5'd4 -- spi1_cs1 sel 5'd5 -- uart1_rts sel 5'd6 -- uart0_rts sel 5'd7 -- i2s_wclk sel 5'd9 -- gpt1_2 sel 5'd10 -- uart_rs232_tx sel 5'd11 -- jtag_tdo sel 5'd12 -- debug_bus_8 sel 5'd16 -- gpt0_pre_event sel 5'd17 -- gpt1_pre_event sel 5'd18 -- gpt1_3_n sel 5'd19 -- sdio_clk sel 5'd22 -- ble_rfc_gpo_7 sel 5'd23 -- ant_sel_1 sel 5'd25 -- ble_rfc_gpi_2 sel 5'd26 -- trdata_2 sel 5'd31 -- uart2_tx
  • 0h = reserved
  • 1h = reserved
  • 2h = wifi_gpio_12
  • 3h = sdio_mmc_data_1
  • 4h = spi1_cs1
  • 5h = uart1_rts
  • 6h = uart0_rts
  • 7h = i2s_wclk
  • 8h = reserved
  • 9h = gpt1_2
  • Ah = uart_rs232_tx
  • Bh = jtag_tdo
  • Ch = debug_bus_8
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = gpt0_pre_event
  • 11h = gpt1_pre_event
  • 12h = gpt1_3_n
  • 13h = sdio_clk
  • 14h = reserved
  • 15h = reserved
  • 16h = ble_rfc_gpo_7
  • 17h = ant_sel_1
  • 18h = reserved
  • 19h = ble_rfc_gpi_2
  • 1Ah = trdata_2
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = uart2_tx

16.8.194 GPIO13PCFG Register (Offset = 0002D038h) [Reset = 00000000h]

GPIO13PCFG is shown in Table 16-196.

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Port configuration register for IO GPIO13

Table 16-196 GPIO13PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_13 sel 5'd3 -- sdio_mmc_data_0 sel 5'd4 -- spi1_mosi sel 5'd5 -- uart1_cts sel 5'd6 -- uart0_tx sel 5'd7 -- i2s_bclk sel 5'd8 -- i2s_mclk sel 5'd9 -- gpt1_3 sel 5'd11 -- wake_observe_bus_14 sel 5'd12 -- debug_bus_7 sel 5'd18 -- gpt1_2_n sel 5'd19 -- sdio_cmd sel 5'd20 -- coex_priority sel 5'd21 -- ble_rftrc sel 5'd22 -- ble_rfc_gpo_6 sel 5'd23 -- ant_sel_0 sel 5'd25 -- ble_rfc_gpi_1 sel 5'd26 -- trdata_3 sel 5'd31 -- uart2_rx
  • 0h = reserved
  • 1h = reserved
  • 2h = wifi_gpio_13
  • 3h = sdio_mmc_data_0
  • 4h = spi1_mosi
  • 5h = uart1_cts
  • 6h = uart0_tx
  • 7h = i2s_bclk
  • 8h = i2s_mclk
  • 9h = gpt1_3
  • Ah = reserved
  • Bh = wake_observe_bus_14
  • Ch = debug_bus_7
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = gpt1_2_n
  • 13h = sdio_cmd
  • 14h = coex_priority
  • 15h = ble_rftrc
  • 16h = ble_rfc_gpo_6
  • 17h = ant_sel_0
  • 18h = reserved
  • 19h = ble_rfc_gpi_1
  • 1Ah = trdata_3
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = uart2_rx

16.8.195 GPIO14PCFG Register (Offset = 0002D03Ch) [Reset = 00000000h]

GPIO14PCFG is shown in Table 16-197.

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Port configuration register for IO GPIO14

Table 16-197 GPIO14PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_14 sel 5'd3 -- sdio_mmc_clk sel 5'd4 -- spi1_clk sel 5'd5 -- uart1_tx sel 5'd6 -- uart0_rx sel 5'd9 -- gpt1_0 sel 5'd11 -- wake_observe_bus_15 sel 5'd12 -- debug_bus_clk sel 5'd16 -- spi0_cs2 sel 5'd17 -- gpt1_pre_event sel 5'd18 -- gpt1_1_n sel 5'd19 -- sdio_d0 sel 5'd20 -- coex_grant sel 5'd22 -- ble_rfc_gpo_4 sel 5'd24 -- ble_rfc_gpi_2 sel 5'd25 -- ble_rfc_gpi_1 sel 5'd26 -- trclk sel 5'd27 -- digital_fast_clk_in
  • 0h = reserved
  • 1h = reserved
  • 2h = wifi_gpio_14
  • 3h = sdio_mmc_clk
  • 4h = spi1_clk
  • 5h = uart1_tx
  • 6h = uart0_rx
  • 7h = reserved
  • 8h = reserved
  • 9h = gpt1_0
  • Ah = reserved
  • Bh = wake_observe_bus_15
  • Ch = debug_bus_clk
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi0_cs2
  • 11h = gpt1_pre_event
  • 12h = gpt1_1_n
  • 13h = sdio_d0
  • 14h = coex_grant
  • 15h = reserved
  • 16h = ble_rfc_gpo_4
  • 17h = reserved
  • 18h = ble_rfc_gpi_2
  • 19h = ble_rfc_gpi_1
  • 1Ah = trclk
  • 1Bh = digital_fast_clk_in
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.196 GPIO15PCFG Register (Offset = 0002D040h) [Reset = 00000000h]

GPIO15PCFG is shown in Table 16-198.

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Port configuration register for IO GPIO15

Table 16-198 GPIO15PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_15 sel 5'd3 -- sdio_mmc_cmd sel 5'd4 -- spi1_miso sel 5'd5 -- uart1_rx sel 5'd6 -- uart0_cts sel 5'd9 -- gpt1_1 sel 5'd10 -- uart_rs232_rx sel 5'd11 -- jtag_tdi sel 5'd12 -- debug_bus_6 sel 5'd16 -- spi1_cs2 sel 5'd17 -- gpt0_pre_event sel 5'd18 -- gpt1_0_n sel 5'd19 -- sdio_d1 sel 5'd20 -- coex_req sel 5'd21 -- ble_rftrc sel 5'd22 -- ble_rfc_gpo_5 sel 5'd25 -- ble_rfc_gpi_3 sel 5'd26 -- swo_m3 sel 5'd27 -- swo_m33
  • 0h = reserved
  • 1h = reserved
  • 2h = wifi_gpio_15
  • 3h = sdio_mmc_cmd
  • 4h = spi1_miso
  • 5h = uart1_rx
  • 6h = uart0_cts
  • 7h = reserved
  • 8h = reserved
  • 9h = gpt1_1
  • Ah = uart_rs232_rx
  • Bh = jtag_tdi
  • Ch = debug_bus_6
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi1_cs2
  • 11h = gpt0_pre_event
  • 12h = gpt1_0_n
  • 13h = sdio_d1
  • 14h = coex_req
  • 15h = ble_rftrc
  • 16h = ble_rfc_gpo_5
  • 17h = reserved
  • 18h = reserved
  • 19h = ble_rfc_gpi_3
  • 1Ah = swo_m3
  • 1Bh = swo_m33
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.197 GPIO16PCFG Register (Offset = 0002D044h) [Reset = 00000000h]

GPIO16PCFG is shown in Table 16-199.

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Port configuration register for IO GPIO16

Table 16-199 GPIO16PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_16 sel 5'd3 -- sdio_mmc_data_7 sel 5'd4 -- spi0_cs1 sel 5'd5 -- uart0_rts sel 5'd6 -- i2c1_data sel 5'd7 -- i2s_wclk sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt0_0 sel 5'd10 -- uart_rs232_rx sel 5'd11 -- wake_observe_bus_12 sel 5'd12 -- debug_bus_5 sel 5'd16 -- spi1_cs2 sel 5'd18 -- gpt0_1_n sel 5'd19 -- sdio_d2 sel 5'd21 -- gpt1_0_n sel 5'd22 -- gpt_infrared sel 5'd23 -- ant_sel_0 sel 5'd26 -- trdata_0 sel 5'd30 -- uart2_tx
  • 0h = reserved
  • 1h = reserved
  • 2h = wifi_gpio_16
  • 3h = sdio_mmc_data_7
  • 4h = spi0_cs1
  • 5h = uart0_rts
  • 6h = i2c1_data
  • 7h = i2s_wclk
  • 8h = pdm_bclk
  • 9h = gpt0_0
  • Ah = uart_rs232_rx
  • Bh = wake_observe_bus_12
  • Ch = debug_bus_5
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi1_cs2
  • 11h = reserved
  • 12h = gpt0_1_n
  • 13h = sdio_d2
  • 14h = reserved
  • 15h = gpt1_0_n
  • 16h = gpt_infrared
  • 17h = ant_sel_0
  • 18h = reserved
  • 19h = reserved
  • 1Ah = trdata_0
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = uart2_tx
  • 1Fh = reserved

16.8.198 GPIO17PCFG Register (Offset = 0002D048h) [Reset = 00000000h]

GPIO17PCFG is shown in Table 16-200.

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Port configuration register for IO GPIO17

Table 16-200 GPIO17PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- sdio_mmc_wp sel 5'd2 -- wifi_gpio_17 sel 5'd3 -- sdio_mmc_data_6 sel 5'd4 -- spi0_clk sel 5'd5 -- uart0_tx sel 5'd6 -- i2c0_clk sel 5'd7 -- i2s_data1 sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt0_1 sel 5'd10 -- uart_rs232_tx sel 5'd11 -- wake_observe_bus_9 sel 5'd12 -- debug_bus_2 sel 5'd16 -- spi1_cs3 sel 5'd17 -- sdio_oob_irq sel 5'd18 -- gpt0_0_n sel 5'd20 -- coex_grant sel 5'd21 -- gpt1_1_n sel 5'd23 -- ant_sel_1 sel 5'd26 -- trdata_1
  • 0h = reserved
  • 1h = sdio_mmc_wp
  • 2h = wifi_gpio_17
  • 3h = sdio_mmc_data_6
  • 4h = spi0_clk
  • 5h = uart0_tx
  • 6h = i2c0_clk
  • 7h = i2s_data1
  • 8h = pdm_data0
  • 9h = gpt0_1
  • Ah = uart_rs232_tx
  • Bh = wake_observe_bus_9
  • Ch = debug_bus_2
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi1_cs3
  • 11h = sdio_oob_irq
  • 12h = gpt0_0_n
  • 13h = reserved
  • 14h = coex_grant
  • 15h = gpt1_1_n
  • 16h = reserved
  • 17h = ant_sel_1
  • 18h = reserved
  • 19h = reserved
  • 1Ah = trdata_1
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.199 GPIO18PCFG Register (Offset = 0002D04Ch) [Reset = 00000000h]

GPIO18PCFG is shown in Table 16-201.

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Port configuration register for IO GPIO18

Table 16-201 GPIO18PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_18 sel 5'd3 -- sdio_mmc_data_5 sel 5'd4 -- spi0_miso sel 5'd5 -- uart0_rx sel 5'd6 -- i2c0_data sel 5'd7 -- i2s_data0 sel 5'd8 -- pdm_data1 sel 5'd9 -- gpt0_2 sel 5'd10 -- dcan_tx sel 5'd11 -- wake_observe_bus_10 sel 5'd12 -- debug_bus_3 sel 5'd16 -- spi1_cs4 sel 5'd17 -- sdio_oob_irq sel 5'd18 -- gpt0_0_n sel 5'd20 -- coex_req sel 5'd21 -- gpt1_2_n sel 5'd23 -- ant_sel_2 sel 5'd26 -- trdata_2
  • 0h = reserved
  • 1h = reserved
  • 2h = wifi_gpio_18
  • 3h = sdio_mmc_data_5
  • 4h = spi0_miso
  • 5h = uart0_rx
  • 6h = i2c0_data
  • 7h = i2s_data0
  • 8h = pdm_data1
  • 9h = gpt0_2
  • Ah = dcan_tx
  • Bh = wake_observe_bus_10
  • Ch = debug_bus_3
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi1_cs4
  • 11h = sdio_oob_irq
  • 12h = gpt0_0_n
  • 13h = reserved
  • 14h = coex_req
  • 15h = gpt1_2_n
  • 16h = reserved
  • 17h = ant_sel_2
  • 18h = reserved
  • 19h = reserved
  • 1Ah = trdata_2
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.200 GPIO19PCFG Register (Offset = 0002D050h) [Reset = 00000000h]

GPIO19PCFG is shown in Table 16-202.

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Port configuration register for IO GPIO19

Table 16-202 GPIO19PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_19 sel 5'd3 -- sdio_mmc_data_4 sel 5'd4 -- spi0_mosi sel 5'd5 -- uart0_cts sel 5'd6 -- i2c1_clk sel 5'd7 -- i2s_bclk sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt0_3 sel 5'd10 -- dcan_rx sel 5'd11 -- wake_observe_bus_11 sel 5'd12 -- debug_bus_4 sel 5'd16 -- gpt0_pre_event sel 5'd17 -- sdio_oob_irq sel 5'd18 -- gpt0_1_n sel 5'd19 -- sdio_d3 sel 5'd20 -- coex_priority sel 5'd21 -- gpt1_3_n sel 5'd22 -- gpt_infrared sel 5'd23 -- ant_sel_3 sel 5'd26 -- trdata_3 sel 5'd30 -- uart2_rx
  • 0h = reserved
  • 1h = reserved
  • 2h = wifi_gpio_19
  • 3h = sdio_mmc_data_4
  • 4h = spi0_mosi
  • 5h = uart0_cts
  • 6h = i2c1_clk
  • 7h = i2s_bclk
  • 8h = pdm_data0
  • 9h = gpt0_3
  • Ah = dcan_rx
  • Bh = wake_observe_bus_11
  • Ch = debug_bus_4
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = gpt0_pre_event
  • 11h = sdio_oob_irq
  • 12h = gpt0_1_n
  • 13h = sdio_d3
  • 14h = coex_priority
  • 15h = gpt1_3_n
  • 16h = gpt_infrared
  • 17h = ant_sel_3
  • 18h = reserved
  • 19h = reserved
  • 1Ah = trdata_3
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = uart2_rx
  • 1Fh = reserved

16.8.201 GPIO20PCFG Register (Offset = 0002D054h) [Reset = 00000000h]

GPIO20PCFG is shown in Table 16-203.

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Port configuration register for IO GPIO20

Table 16-203 GPIO20PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_cs_flash sel 5'd2 -- wifi_gpio_20
  • 0h = xspi_cs_flash
  • 1h = reserved
  • 2h = wifi_gpio_20
  • 3h = reserved
  • 4h = reserved
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = reserved
  • 16h = reserved
  • 17h = reserved
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.202 GPIO21PCFG Register (Offset = 0002D058h) [Reset = 00000000h]

GPIO21PCFG is shown in Table 16-204.

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Port configuration register for IO GPIO21

Table 16-204 GPIO21PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_1 sel 5'd2 -- wifi_gpio_21
  • 0h = xspi_data_1
  • 1h = reserved
  • 2h = wifi_gpio_21
  • 3h = reserved
  • 4h = reserved
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = reserved
  • 16h = reserved
  • 17h = reserved
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.203 GPIO22PCFG Register (Offset = 0002D05Ch) [Reset = 00000000h]

GPIO22PCFG is shown in Table 16-205.

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Port configuration register for IO GPIO22

Table 16-205 GPIO22PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_2 sel 5'd2 -- wifi_gpio_22
  • 0h = xspi_data_2
  • 1h = reserved
  • 2h = wifi_gpio_22
  • 3h = reserved
  • 4h = reserved
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = reserved
  • 16h = reserved
  • 17h = reserved
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.204 GPIO23PCFG Register (Offset = 0002D060h) [Reset = 00000000h]

GPIO23PCFG is shown in Table 16-206.

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Port configuration register for IO GPIO23

Table 16-206 GPIO23PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_3 sel 5'd2 -- wifi_gpio_23
  • 0h = xspi_data_3
  • 1h = reserved
  • 2h = wifi_gpio_23
  • 3h = reserved
  • 4h = reserved
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = reserved
  • 16h = reserved
  • 17h = reserved
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.205 GPIO24PCFG Register (Offset = 0002D064h) [Reset = 00000000h]

GPIO24PCFG is shown in Table 16-207.

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Port configuration register for IO GPIO24

Table 16-207 GPIO24PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_clk sel 5'd2 -- wifi_gpio_24
  • 0h = xspi_clk
  • 1h = reserved
  • 2h = wifi_gpio_24
  • 3h = reserved
  • 4h = reserved
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = reserved
  • 16h = reserved
  • 17h = reserved
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.206 GPIO25PCFG Register (Offset = 0002D068h) [Reset = 00000000h]

GPIO25PCFG is shown in Table 16-208.

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Port configuration register for IO GPIO25

Table 16-208 GPIO25PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_0 sel 5'd2 -- wifi_gpio_25
  • 0h = xspi_data_0
  • 1h = reserved
  • 2h = wifi_gpio_25
  • 3h = reserved
  • 4h = reserved
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = reserved
  • 16h = reserved
  • 17h = reserved
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.207 GPIO26PCFG Register (Offset = 0002D06Ch) [Reset = 00000000h]

GPIO26PCFG is shown in Table 16-209.

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Port configuration register for IO GPIO26

Table 16-209 GPIO26PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_data_4 sel 5'd2 -- wifi_gpio_26 sel 5'd4 -- spi0_cs1 sel 5'd5 -- uart0_rts sel 5'd6 -- i2c1_clk sel 5'd7 -- i2s_wclk sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt0_0 sel 5'd10 -- dcan_tx sel 5'd11 -- wake_observe_bus_0 sel 5'd12 -- debug_bus_13 sel 5'd16 -- spi1_cs2 sel 5'd17 -- ext_clk sel 5'd18 -- gpt0_1_n sel 5'd19 -- gpt1_0_n sel 5'd20 -- coex_grant sel 5'd21 -- coex_req sel 5'd22 -- ble_rfc_gpo_4 sel 5'd23 -- ant_sel_0 sel 5'd24 -- gpt_infrared sel 5'd25 -- ble_rfc_gpi_1 sel 5'd26 -- ble_rfc_gpi_3 sel 5'd30 -- sdio_oob_irq sel 5'd31 -- uart2_tx
  • 0h = reserved
  • 1h = xspi_data_4
  • 2h = wifi_gpio_26
  • 3h = reserved
  • 4h = spi0_cs1
  • 5h = uart0_rts
  • 6h = i2c1_clk
  • 7h = i2s_wclk
  • 8h = pdm_bclk
  • 9h = gpt0_0
  • Ah = dcan_tx
  • Bh = wake_observe_bus_0
  • Ch = debug_bus_13
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi1_cs2
  • 11h = ext_clk
  • 12h = gpt0_1_n
  • 13h = gpt1_0_n
  • 14h = coex_grant
  • 15h = coex_req
  • 16h = ble_rfc_gpo_4
  • 17h = ant_sel_0
  • 18h = gpt_infrared
  • 19h = ble_rfc_gpi_1
  • 1Ah = ble_rfc_gpi_3
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = sdio_oob_irq
  • 1Fh = uart2_tx

16.8.208 GPIO27PCFG Register (Offset = 0002D070h) [Reset = 00000000h]

GPIO27PCFG is shown in Table 16-210.

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Port configuration register for IO GPIO27

Table 16-210 GPIO27PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_data_5 sel 5'd2 -- wifi_gpio_27 sel 5'd4 -- spi0_clk sel 5'd5 -- uart0_tx sel 5'd6 -- i2c0_data sel 5'd7 -- i2s_data0 sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt0_1 sel 5'd11 -- wake_observe_bus_1 sel 5'd12 -- debug_bus_14 sel 5'd16 -- spi1_cs3 sel 5'd18 -- gpt0_0_n sel 5'd19 -- gpt1_1_n sel 5'd20 -- coex_req sel 5'd22 -- ble_rfc_gpo_5 sel 5'd23 -- ant_sel_1 sel 5'd25 -- ble_rfc_gpi_2 sel 5'd31 -- uart2_rts
  • 0h = reserved
  • 1h = xspi_data_5
  • 2h = wifi_gpio_27
  • 3h = reserved
  • 4h = spi0_clk
  • 5h = uart0_tx
  • 6h = i2c0_data
  • 7h = i2s_data0
  • 8h = pdm_data0
  • 9h = gpt0_1
  • Ah = reserved
  • Bh = wake_observe_bus_1
  • Ch = debug_bus_14
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi1_cs3
  • 11h = reserved
  • 12h = gpt0_0_n
  • 13h = gpt1_1_n
  • 14h = coex_req
  • 15h = reserved
  • 16h = ble_rfc_gpo_5
  • 17h = ant_sel_1
  • 18h = reserved
  • 19h = ble_rfc_gpi_2
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = uart2_rts

16.8.209 GPIO28PCFG Register (Offset = 0002D074h) [Reset = 00000000h]

GPIO28PCFG is shown in Table 16-211.

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Port configuration register for IO GPIO28

Table 16-211 GPIO28PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_data_6 sel 5'd2 -- wifi_gpio_28 sel 5'd4 -- spi0_miso sel 5'd5 -- uart0_rx sel 5'd6 -- i2c0_clk sel 5'd7 -- i2s_data1 sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt0_2 sel 5'd11 -- wake_observe_bus_2 sel 5'd12 -- debug_bus_15 sel 5'd16 -- spi1_cs4 sel 5'd18 -- gpt0_0_n sel 5'd19 -- gpt1_2_n sel 5'd20 -- coex_priority sel 5'd22 -- ble_rfc_gpo_6 sel 5'd23 -- ant_sel_2 sel 5'd24 -- gpt0_pre_event sel 5'd25 -- ble_rfc_gpi_3 sel 5'd31 -- uart2_cts
  • 0h = reserved
  • 1h = xspi_data_6
  • 2h = wifi_gpio_28
  • 3h = reserved
  • 4h = spi0_miso
  • 5h = uart0_rx
  • 6h = i2c0_clk
  • 7h = i2s_data1
  • 8h = pdm_bclk
  • 9h = gpt0_2
  • Ah = reserved
  • Bh = wake_observe_bus_2
  • Ch = debug_bus_15
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi1_cs4
  • 11h = reserved
  • 12h = gpt0_0_n
  • 13h = gpt1_2_n
  • 14h = coex_priority
  • 15h = reserved
  • 16h = ble_rfc_gpo_6
  • 17h = ant_sel_2
  • 18h = gpt0_pre_event
  • 19h = ble_rfc_gpi_3
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = uart2_cts

16.8.210 GPIO29PCFG Register (Offset = 0002D078h) [Reset = 00000000h]

GPIO29PCFG is shown in Table 16-212.

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Port configuration register for IO GPIO29

Table 16-212 GPIO29PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_data_7 sel 5'd2 -- wifi_gpio_29 sel 5'd4 -- spi0_mosi sel 5'd5 -- uart0_cts sel 5'd6 -- i2c1_data sel 5'd7 -- i2s_bclk sel 5'd8 -- pdm_data1 sel 5'd9 -- gpt0_3 sel 5'd10 -- dcan_rx sel 5'd11 -- wake_observe_bus_3 sel 5'd12 -- i2s_mclk sel 5'd16 -- spi1_cs4 sel 5'd17 -- ext_clk sel 5'd18 -- gpt0_1_n sel 5'd19 -- gpt1_3_n sel 5'd20 -- coex_grant sel 5'd22 -- ble_rfc_gpo_7 sel 5'd23 -- ant_sel_3 sel 5'd30 -- sdio_oob_irq sel 5'd31 -- uart2_rx
  • 0h = reserved
  • 1h = xspi_data_7
  • 2h = wifi_gpio_29
  • 3h = reserved
  • 4h = spi0_mosi
  • 5h = uart0_cts
  • 6h = i2c1_data
  • 7h = i2s_bclk
  • 8h = pdm_data1
  • 9h = gpt0_3
  • Ah = dcan_rx
  • Bh = wake_observe_bus_3
  • Ch = i2s_mclk
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi1_cs4
  • 11h = ext_clk
  • 12h = gpt0_1_n
  • 13h = gpt1_3_n
  • 14h = coex_grant
  • 15h = reserved
  • 16h = ble_rfc_gpo_7
  • 17h = ant_sel_3
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = sdio_oob_irq
  • 1Fh = uart2_rx

16.8.211 GPIO30PCFG Register (Offset = 0002D07Ch) [Reset = 00000000h]

GPIO30PCFG is shown in Table 16-213.

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Port configuration register for IO GPIO30

Table 16-213 GPIO30PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_dqs sel 5'd2 -- wifi_gpio_30 sel 5'd3 -- xspi_reset_flash sel 5'd4 -- xspi_reset_ram sel 5'd5 -- i2c1_clk sel 5'd6 -- i2c0_clk sel 5'd7 -- i2s_data0 sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt1_1 sel 5'd10 -- dcan_tx sel 5'd11 -- wake_observe_bus_4 sel 5'd12 -- xspi_cs_ram sel 5'd16 -- spi0_cs2 sel 5'd17 -- spi0_cs2 sel 5'd18 -- gpt0_2_n sel 5'd19 -- coex_grant sel 5'd20 -- coex_req sel 5'd21 -- ble_rftrc sel 5'd22 -- ble_rfc_gpo_4 sel 5'd23 -- ant_sel_0 sel 5'd24 -- cca sel 5'd25 -- ble_rfc_gpi_1 sel 5'd26 -- swo_m3 sel 5'd27 -- swo_m33 sel 5'd28 -- gpt1_pre_event sel 5'd29 -- gpt0_pre_event sel 5'd30 -- sdio_d3 sel 5'd31 -- uart2_tx
  • 0h = reserved
  • 1h = xspi_dqs
  • 2h = wifi_gpio_30
  • 3h = xspi_reset_flash
  • 4h = xspi_reset_ram
  • 5h = i2c1_clk
  • 6h = i2c0_clk
  • 7h = i2s_data0
  • 8h = pdm_data0
  • 9h = gpt1_1
  • Ah = dcan_tx
  • Bh = wake_observe_bus_4
  • Ch = xspi_cs_ram
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi0_cs2
  • 11h = spi0_cs2
  • 12h = gpt0_2_n
  • 13h = coex_grant
  • 14h = coex_req
  • 15h = ble_rftrc
  • 16h = ble_rfc_gpo_4
  • 17h = ant_sel_0
  • 18h = cca
  • 19h = ble_rfc_gpi_1
  • 1Ah = swo_m3
  • 1Bh = swo_m33
  • 1Ch = gpt1_pre_event
  • 1Dh = gpt0_pre_event
  • 1Eh = sdio_d3
  • 1Fh = uart2_tx

16.8.212 GPIO31PCFG Register (Offset = 0002D080h) [Reset = 00000000h]

GPIO31PCFG is shown in Table 16-214.

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Port configuration register for IO GPIO31

Table 16-214 GPIO31PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_31 sel 5'd3 -- xspi_reset_flash sel 5'd4 -- spi1_cs1 sel 5'd5 -- uart1_rts sel 5'd6 -- i2c1_clk sel 5'd7 -- i2s_wclk sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt1_0 sel 5'd10 -- dcan_tx sel 5'd16 -- spi0_cs3 sel 5'd17 -- ext_clk sel 5'd18 -- gpt1_1_n sel 5'd19 -- gpt0_0_n sel 5'd20 -- coex_grant sel 5'd22 -- ble_rfc_gpo_6 sel 5'd23 -- ant_sel_0 sel 5'd24 -- gpt_infrared sel 5'd25 -- ble_rfc_gpi_3 sel 5'd30 -- sdio_d2 sel 5'd31 -- uart2_tx
  • 0h = reserved
  • 1h = xspi_cs_ram
  • 2h = wifi_gpio_31
  • 3h = xspi_reset_flash
  • 4h = spi1_cs1
  • 5h = uart1_rts
  • 6h = i2c1_clk
  • 7h = i2s_wclk
  • 8h = pdm_bclk
  • 9h = gpt1_0
  • Ah = dcan_tx
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi0_cs3
  • 11h = ext_clk
  • 12h = gpt1_1_n
  • 13h = gpt0_0_n
  • 14h = coex_grant
  • 15h = reserved
  • 16h = ble_rfc_gpo_6
  • 17h = ant_sel_0
  • 18h = gpt_infrared
  • 19h = ble_rfc_gpi_3
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = sdio_d2
  • 1Fh = uart2_tx

16.8.213 GPIO32PCFG Register (Offset = 0002D084h) [Reset = 00000000h]

GPIO32PCFG is shown in Table 16-215.

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Port configuration register for IO GPIO32

Table 16-215 GPIO32PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_32 sel 5'd3 -- spi1_cs1 sel 5'd4 -- spi1_clk sel 5'd5 -- uart1_tx sel 5'd6 -- i2c0_data sel 5'd7 -- i2s_data1 sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt1_1 sel 5'd10 -- dcan_rx sel 5'd11 -- wake_observe_bus_5 sel 5'd16 -- spi0_cs3 sel 5'd18 -- gpt1_0_n sel 5'd19 -- gpt0_1_n sel 5'd20 -- coex_req sel 5'd23 -- ant_sel_1 sel 5'd30 -- sdio_d1 sel 5'd31 -- uart2_rts
  • 0h = reserved
  • 1h = xspi_cs_ram
  • 2h = wifi_gpio_32
  • 3h = spi1_cs1
  • 4h = spi1_clk
  • 5h = uart1_tx
  • 6h = i2c0_data
  • 7h = i2s_data1
  • 8h = pdm_bclk
  • 9h = gpt1_1
  • Ah = dcan_rx
  • Bh = wake_observe_bus_5
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi0_cs3
  • 11h = reserved
  • 12h = gpt1_0_n
  • 13h = gpt0_1_n
  • 14h = coex_req
  • 15h = reserved
  • 16h = reserved
  • 17h = ant_sel_1
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = sdio_d1
  • 1Fh = uart2_rts

16.8.214 GPIO33PCFG Register (Offset = 0002D088h) [Reset = 00000000h]

GPIO33PCFG is shown in Table 16-216.

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Port configuration register for IO GPIO33

Table 16-216 GPIO33PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd2 -- wifi_gpio_33 sel 5'd4 -- spi1_miso sel 5'd5 -- uart1_rx sel 5'd6 -- i2c0_clk sel 5'd7 -- i2s_data0 sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt1_2 sel 5'd10 -- dcan_tx sel 5'd16 -- spi0_cs4 sel 5'd18 -- gpt1_0_n sel 5'd19 -- gpt0_2_n sel 5'd20 -- coex_grant sel 5'd23 -- ant_sel_2 sel 5'd24 -- gpt1_pre_event sel 5'd25 -- ble_rfc_gpi_2 sel 5'd30 -- sdio_d0 sel 5'd31 -- uart2_cts
  • 0h = reserved
  • 1h = reserved
  • 2h = wifi_gpio_33
  • 3h = reserved
  • 4h = spi1_miso
  • 5h = uart1_rx
  • 6h = i2c0_clk
  • 7h = i2s_data0
  • 8h = pdm_data0
  • 9h = gpt1_2
  • Ah = dcan_tx
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi0_cs4
  • 11h = reserved
  • 12h = gpt1_0_n
  • 13h = gpt0_2_n
  • 14h = coex_grant
  • 15h = reserved
  • 16h = reserved
  • 17h = ant_sel_2
  • 18h = gpt1_pre_event
  • 19h = ble_rfc_gpi_2
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = sdio_d0
  • 1Fh = uart2_cts

16.8.215 GPIO34PCFG Register (Offset = 0002D08Ch) [Reset = 00000000h]

GPIO34PCFG is shown in Table 16-217.

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Port configuration register for IO GPIO34

Table 16-217 GPIO34PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_reset_ram sel 5'd2 -- wifi_gpio_34 sel 5'd4 -- spi1_mosi sel 5'd5 -- uart1_cts sel 5'd6 -- i2c1_data sel 5'd7 -- i2s_bclk sel 5'd8 -- pdm_data1 sel 5'd9 -- gpt1_3 sel 5'd10 -- dcan_rx sel 5'd16 -- spi0_cs2 sel 5'd18 -- gpt1_1_n sel 5'd19 -- gpt0_3_n sel 5'd20 -- coex_req sel 5'd22 -- ble_rfc_gpo_7 sel 5'd23 -- ant_sel_3 sel 5'd25 -- ble_rfc_gpi_1 sel 5'd30 -- sdio_clk sel 5'd31 -- uart2_rx
  • 0h = reserved
  • 1h = xspi_reset_ram
  • 2h = wifi_gpio_34
  • 3h = reserved
  • 4h = spi1_mosi
  • 5h = uart1_cts
  • 6h = i2c1_data
  • 7h = i2s_bclk
  • 8h = pdm_data1
  • 9h = gpt1_3
  • Ah = dcan_rx
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi0_cs2
  • 11h = reserved
  • 12h = gpt1_1_n
  • 13h = gpt0_3_n
  • 14h = coex_req
  • 15h = reserved
  • 16h = ble_rfc_gpo_7
  • 17h = ant_sel_3
  • 18h = reserved
  • 19h = ble_rfc_gpi_1
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = sdio_clk
  • 1Fh = uart2_rx

16.8.216 GPIO35PCFG Register (Offset = 0002D090h) [Reset = 00000000h]

GPIO35PCFG is shown in Table 16-218.

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Port configuration register for IO GPIO35

Table 16-218 GPIO35PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_reset_flash sel 5'd2 -- wifi_gpio_35 sel 5'd3 -- spi1_clk sel 5'd4 -- xspi_reset_ram sel 5'd5 -- uart1_rx sel 5'd6 -- i2c0_data sel 5'd7 -- i2s_data1 sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt0_1 sel 5'd10 -- dcan_rx sel 5'd11 -- i2c1_data sel 5'd12 -- xspi_cs_ram sel 5'd16 -- spi0_cs4 sel 5'd17 -- spi0_cs3 sel 5'd18 -- gpt0_2_n sel 5'd19 -- gpt1_2_n sel 5'd20 -- coex_priority sel 5'd21 -- ble_rftrc sel 5'd22 -- ble_rfc_gpo_5 sel 5'd23 -- ant_sel_0 sel 5'd24 -- gpt1_pre_event sel 5'd25 -- ble_rfc_gpi_2 sel 5'd26 -- swo_m3 sel 5'd27 -- swo_m33 sel 5'd28 -- xspi_dqs sel 5'd29 -- coex_req sel 5'd30 -- sdio_cmd sel 5'd31 -- uart2_rx
  • 0h = reserved
  • 1h = xspi_reset_flash
  • 2h = wifi_gpio_35
  • 3h = spi1_clk
  • 4h = xspi_reset_ram
  • 5h = uart1_rx
  • 6h = i2c0_data
  • 7h = i2s_data1
  • 8h = pdm_bclk
  • 9h = gpt0_1
  • Ah = dcan_rx
  • Bh = i2c1_data
  • Ch = xspi_cs_ram
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = spi0_cs4
  • 11h = spi0_cs3
  • 12h = gpt0_2_n
  • 13h = gpt1_2_n
  • 14h = coex_priority
  • 15h = ble_rftrc
  • 16h = ble_rfc_gpo_5
  • 17h = ant_sel_0
  • 18h = gpt1_pre_event
  • 19h = ble_rfc_gpi_2
  • 1Ah = swo_m3
  • 1Bh = swo_m33
  • 1Ch = xspi_dqs
  • 1Dh = coex_req
  • 1Eh = sdio_cmd
  • 1Fh = uart2_rx

16.8.217 GPIO36PCFG Register (Offset = 0002D094h) [Reset = 00000000h]

GPIO36PCFG is shown in Table 16-219.

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Port configuration register for IO GPIO36

Table 16-219 GPIO36PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- fast_clk_req sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_36 sel 5'd3 -- sdio_mmc_pow2 sel 5'd4 -- sdio_mmc_wp sel 5'd11 -- wake_observe_bus_13 sel 5'd12 -- debug_bus_1 sel 5'd19 -- coex_req sel 5'd20 -- coex_grant sel 5'd21 -- fast_clk_req sel 5'd22 -- ble_rfc_gpo_5 sel 5'd23 -- ant_sel_1 sel 5'd24 -- cca sel 5'd25 -- ble_rfc_gpi_2
  • 0h = fast_clk_req
  • 1h = xspi_cs_ram
  • 2h = wifi_gpio_36
  • 3h = sdio_mmc_pow2
  • 4h = sdio_mmc_wp
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = wake_observe_bus_13
  • Ch = debug_bus_1
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = coex_req
  • 14h = coex_grant
  • 15h = fast_clk_req
  • 16h = ble_rfc_gpo_5
  • 17h = ant_sel_1
  • 18h = cca
  • 19h = ble_rfc_gpi_2
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.218 GPIO37PCFG Register (Offset = 0002D098h) [Reset = 00000000h]

GPIO37PCFG is shown in Table 16-220.

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Port configuration register for IO GPIO37

Table 16-220 GPIO37PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_37 sel 5'd3 -- sdio_mmc_pow1 sel 5'd4 -- sdio_mmc_wp sel 5'd11 -- wake_observe_bus_12 sel 5'd12 -- debug_bus_0 sel 5'd18 -- coex_req sel 5'd19 -- sdio_oob_irq sel 5'd20 -- coex_grant sel 5'd21 -- fast_clk_req sel 5'd22 -- ble_rfc_gpo_4 sel 5'd23 -- ant_sel_0 sel 5'd24 -- cca sel 5'd25 -- ble_rfc_gpi_1
  • 0h = reserved
  • 1h = xspi_cs_ram
  • 2h = wifi_gpio_37
  • 3h = sdio_mmc_pow1
  • 4h = sdio_mmc_wp
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = wake_observe_bus_12
  • Ch = debug_bus_0
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = coex_req
  • 13h = sdio_oob_irq
  • 14h = coex_grant
  • 15h = fast_clk_req
  • 16h = ble_rfc_gpo_4
  • 17h = ant_sel_0
  • 18h = cca
  • 19h = ble_rfc_gpi_1
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.219 GPIO38PCFG Register (Offset = 0002D09Ch) [Reset = 00000000h]

GPIO38PCFG is shown in Table 16-221.

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Port configuration register for IO GPIO38

Table 16-221 GPIO38PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_38 sel 5'd3 -- ext_clk sel 5'd4 -- spi1_clk sel 5'd5 -- uart0_cts sel 5'd6 -- i2c1_clk sel 5'd7 -- i2s_bclk sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt1_0 sel 5'd10 -- dcan_tx sel 5'd18 -- gpt1_1_n sel 5'd20 -- coex_grant sel 5'd23 -- ant_sel_0 sel 5'd29 -- coex_req sel 5'd30 -- uart2_rx
  • 0h = reserved
  • 1h = xspi_cs_ram
  • 2h = wifi_gpio_38
  • 3h = ext_clk
  • 4h = spi1_clk
  • 5h = uart0_cts
  • 6h = i2c1_clk
  • 7h = i2s_bclk
  • 8h = pdm_bclk
  • 9h = gpt1_0
  • Ah = dcan_tx
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = gpt1_1_n
  • 13h = reserved
  • 14h = coex_grant
  • 15h = reserved
  • 16h = reserved
  • 17h = ant_sel_0
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = coex_req
  • 1Eh = uart2_rx
  • 1Fh = reserved

16.8.220 GPIO39PCFG Register (Offset = 0002D0A0h) [Reset = 00000000h]

GPIO39PCFG is shown in Table 16-222.

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Port configuration register for IO GPIO39

Table 16-222 GPIO39PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_reset_ram sel 5'd2 -- wifi_gpio_39 sel 5'd3 -- uart0_rx sel 5'd4 -- spi1_miso sel 5'd5 -- uart0_rts sel 5'd6 -- i2c1_data sel 5'd7 -- i2s_wclk sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt1_1 sel 5'd10 -- dcan_rx sel 5'd11 -- xspi_dqs sel 5'd18 -- gpt1_0_n sel 5'd20 -- coex_req sel 5'd21 -- coex_grant sel 5'd23 -- ant_sel_1 sel 5'd29 -- coex_priority sel 5'd30 -- uart2_tx
  • 0h = reserved
  • 1h = xspi_reset_ram
  • 2h = wifi_gpio_39
  • 3h = uart0_rx
  • 4h = spi1_miso
  • 5h = uart0_rts
  • 6h = i2c1_data
  • 7h = i2s_wclk
  • 8h = pdm_data0
  • 9h = gpt1_1
  • Ah = dcan_rx
  • Bh = xspi_dqs
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = gpt1_0_n
  • 13h = reserved
  • 14h = coex_req
  • 15h = coex_grant
  • 16h = reserved
  • 17h = ant_sel_1
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = coex_priority
  • 1Eh = uart2_tx
  • 1Fh = reserved

16.8.221 GPIO40PCFG Register (Offset = 0002D0A4h) [Reset = 00000000h]

GPIO40PCFG is shown in Table 16-223.

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Port configuration register for IO GPIO40

Table 16-223 GPIO40PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_40 sel 5'd4 -- spi1_mosi sel 5'd5 -- uart0_tx sel 5'd7 -- i2s_data0 sel 5'd8 -- pdm_data1 sel 5'd9 -- gpt1_2 sel 5'd16 -- gpt1_pre_event sel 5'd17 -- gpt0_pre_event sel 5'd18 -- gpt1_2_n sel 5'd20 -- coex_priority sel 5'd22 -- gpt_infrared sel 5'd23 -- ant_sel_2 sel 5'd29 -- coex_grant sel 5'd30 -- uart2_rts
  • 0h = reserved
  • 1h = xspi_cs_ram
  • 2h = wifi_gpio_40
  • 3h = reserved
  • 4h = spi1_mosi
  • 5h = uart0_tx
  • 6h = reserved
  • 7h = i2s_data0
  • 8h = pdm_data1
  • 9h = gpt1_2
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = gpt1_pre_event
  • 11h = gpt0_pre_event
  • 12h = gpt1_2_n
  • 13h = reserved
  • 14h = coex_priority
  • 15h = reserved
  • 16h = gpt_infrared
  • 17h = ant_sel_2
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = coex_grant
  • 1Eh = uart2_rts
  • 1Fh = reserved

16.8.222 GPIO41PCFG Register (Offset = 0002D0A8h) [Reset = 00000000h]

GPIO41PCFG is shown in Table 16-224.

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Port configuration register for IO GPIO41

Table 16-224 GPIO41PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_41 sel 5'd4 -- spi1_miso sel 5'd5 -- uart1_cts sel 5'd7 -- i2s_data0 sel 5'd9 -- gpt0_0 sel 5'd16 -- gpt1_pre_event sel 5'd17 -- gpt0_pre_event sel 5'd18 -- gpt0_1_n sel 5'd20 -- coex_grant sel 5'd22 -- gpt_infrared sel 5'd23 -- ant_sel_0 sel 5'd29 -- coex_grant sel 5'd30 -- uart2_rx
  • 0h = reserved
  • 1h = xspi_cs_ram
  • 2h = wifi_gpio_41
  • 3h = reserved
  • 4h = spi1_miso
  • 5h = uart1_cts
  • 6h = reserved
  • 7h = i2s_data0
  • 8h = reserved
  • 9h = gpt0_0
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = gpt1_pre_event
  • 11h = gpt0_pre_event
  • 12h = gpt0_1_n
  • 13h = reserved
  • 14h = coex_grant
  • 15h = reserved
  • 16h = gpt_infrared
  • 17h = ant_sel_0
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = coex_grant
  • 1Eh = uart2_rx
  • 1Fh = reserved

16.8.223 GPIO42PCFG Register (Offset = 0002D0ACh) [Reset = 00000000h]

GPIO42PCFG is shown in Table 16-225.

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Port configuration register for IO GPIO42

Table 16-225 GPIO42PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_reset_ram sel 5'd2 -- wifi_gpio_42 sel 5'd3 -- uart1_rx sel 5'd4 -- spi1_mosi sel 5'd5 -- uart1_rts sel 5'd6 -- i2c0_data sel 5'd7 -- i2s_wclk sel 5'd8 -- pdm_data0 sel 5'd9 -- gpt0_1 sel 5'd10 -- dcan_rx sel 5'd11 -- xspi_dqs sel 5'd18 -- gpt0_0_n sel 5'd20 -- coex_req sel 5'd21 -- coex_grant sel 5'd23 -- ant_sel_1 sel 5'd29 -- coex_req sel 5'd30 -- uart2_tx
  • 0h = reserved
  • 1h = xspi_reset_ram
  • 2h = wifi_gpio_42
  • 3h = uart1_rx
  • 4h = spi1_mosi
  • 5h = uart1_rts
  • 6h = i2c0_data
  • 7h = i2s_wclk
  • 8h = pdm_data0
  • 9h = gpt0_1
  • Ah = dcan_rx
  • Bh = xspi_dqs
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = gpt0_0_n
  • 13h = reserved
  • 14h = coex_req
  • 15h = coex_grant
  • 16h = reserved
  • 17h = ant_sel_1
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = coex_req
  • 1Eh = uart2_tx
  • 1Fh = reserved

16.8.224 GPIO43PCFG Register (Offset = 0002D0B0h) [Reset = 00000000h]

GPIO43PCFG is shown in Table 16-226.

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Port configuration register for IO GPIO43

Table 16-226 GPIO43PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd1 -- xspi_cs_ram sel 5'd2 -- wifi_gpio_43 sel 5'd4 -- spi1_clk sel 5'd5 -- uart1_tx sel 5'd6 -- i2c0_clk sel 5'd7 -- i2s_bclk sel 5'd8 -- pdm_bclk sel 5'd9 -- gpt0_2 sel 5'd10 -- dcan_tx sel 5'd18 -- gpt0_2_n sel 5'd20 -- coex_priority sel 5'd23 -- ant_sel_2 sel 5'd29 -- coex_priority sel 5'd30 -- uart2_rts
  • 0h = reserved
  • 1h = xspi_cs_ram
  • 2h = wifi_gpio_43
  • 3h = reserved
  • 4h = spi1_clk
  • 5h = uart1_tx
  • 6h = i2c0_clk
  • 7h = i2s_bclk
  • 8h = pdm_bclk
  • 9h = gpt0_2
  • Ah = dcan_tx
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = gpt0_2_n
  • 13h = reserved
  • 14h = coex_priority
  • 15h = reserved
  • 16h = reserved
  • 17h = ant_sel_2
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = coex_priority
  • 1Eh = uart2_rts
  • 1Fh = reserved

16.8.225 GPIO44PCFG Register (Offset = 0002D0B4h) [Reset = 00000000h]

GPIO44PCFG is shown in Table 16-227.

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Port configuration register for IO GPIO44

Table 16-227 GPIO44PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_clk_input sel 5'd2 -- wifi_gpio_44
  • 0h = xspi_clk_input
  • 1h = reserved
  • 2h = wifi_gpio_44
  • 3h = reserved
  • 4h = reserved
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = reserved
  • 16h = reserved
  • 17h = reserved
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.226 GPIO45PCFG Register (Offset = 0002D0C0h) [Reset = 00000000h]

GPIO45PCFG is shown in Table 16-228.

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Port configuration register for IO GPIO45

Table 16-228 GPIO45PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_0_ram
  • 0h = xspi_data_0_ram
  • 1h = reserved
  • 2h = reserved
  • 3h = reserved
  • 4h = reserved
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = reserved
  • 16h = reserved
  • 17h = reserved
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.227 GPIO46PCFG Register (Offset = 0002D0C4h) [Reset = 00000000h]

GPIO46PCFG is shown in Table 16-229.

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Port configuration register for IO GPIO46

Table 16-229 GPIO46PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_1_ram
  • 0h = xspi_data_1_ram
  • 1h = reserved
  • 2h = reserved
  • 3h = reserved
  • 4h = reserved
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = reserved
  • 16h = reserved
  • 17h = reserved
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.228 GPIO47PCFG Register (Offset = 0002D0C8h) [Reset = 00000000h]

GPIO47PCFG is shown in Table 16-230.

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Port configuration register for IO GPIO47

Table 16-230 GPIO47PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_2_ram
  • 0h = xspi_data_2_ram
  • 1h = reserved
  • 2h = reserved
  • 3h = reserved
  • 4h = reserved
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = reserved
  • 16h = reserved
  • 17h = reserved
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.229 GPIO48PCFG Register (Offset = 0002D0CCh) [Reset = 00000000h]

GPIO48PCFG is shown in Table 16-231.

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Port configuration register for IO GPIO48

Table 16-231 GPIO48PCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4-0IOSELR/W0hPinmux selection Control Mode can be used to select the IO functionality or drive 0/1/Hi-Z sel 5'd0 -- xspi_data_3_ram
  • 0h = xspi_data_3_ram
  • 1h = reserved
  • 2h = reserved
  • 3h = reserved
  • 4h = reserved
  • 5h = reserved
  • 6h = reserved
  • 7h = reserved
  • 8h = reserved
  • 9h = reserved
  • Ah = reserved
  • Bh = reserved
  • Ch = reserved
  • Dh = reserved
  • Eh = reserved
  • Fh = reserved
  • 10h = reserved
  • 11h = reserved
  • 12h = reserved
  • 13h = reserved
  • 14h = reserved
  • 15h = reserved
  • 16h = reserved
  • 17h = reserved
  • 18h = reserved
  • 19h = reserved
  • 1Ah = reserved
  • 1Bh = reserved
  • 1Ch = reserved
  • 1Dh = reserved
  • 1Eh = reserved
  • 1Fh = reserved

16.8.230 GPIO45CFG Register (Offset = 0002E000h) [Reset = 00000000h]

GPIO45CFG is shown in Table 16-232.

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CFG register for IO GPIO45. This register configures the corresponding pad

Table 16-232 GPIO45CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.231 GPIO45PCTL Register (Offset = 0002E004h) [Reset = 00000000h]

GPIO45PCTL is shown in Table 16-233.

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Pull control register of IO GPIO45 This register configures the pull control

Table 16-233 GPIO45PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.232 GPIO45CTL Register (Offset = 0002E008h) [Reset = 00000000h]

GPIO45CTL is shown in Table 16-234.

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Control register of IO GPIO45 This register controls the IO state

Table 16-234 GPIO45CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.233 GPIO45ECTL Register (Offset = 0002E00Ch) [Reset = 00000000h]

GPIO45ECTL is shown in Table 16-235.

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Event control register for IO GPIO45 This register controls the Event configuration and behaviour

Table 16-235 GPIO45ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.234 GPIO46CFG Register (Offset = 0002F000h) [Reset = 00000000h]

GPIO46CFG is shown in Table 16-236.

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CFG register for IO GPIO46. This register configures the corresponding pad

Table 16-236 GPIO46CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.235 GPIO46PCTL Register (Offset = 0002F004h) [Reset = 00000000h]

GPIO46PCTL is shown in Table 16-237.

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Pull control register of IO GPIO46 This register configures the pull control

Table 16-237 GPIO46PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.236 GPIO46CTL Register (Offset = 0002F008h) [Reset = 00000000h]

GPIO46CTL is shown in Table 16-238.

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Control register of IO GPIO46 This register controls the IO state

Table 16-238 GPIO46CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.237 GPIO46ECTL Register (Offset = 0002F00Ch) [Reset = 00000000h]

GPIO46ECTL is shown in Table 16-239.

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Event control register for IO GPIO46 This register controls the Event configuration and behaviour

Table 16-239 GPIO46ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.238 GPIO47CFG Register (Offset = 00030000h) [Reset = 00000000h]

GPIO47CFG is shown in Table 16-240.

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CFG register for IO GPIO47. This register configures the corresponding pad

Table 16-240 GPIO47CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.239 GPIO47PCTL Register (Offset = 00030004h) [Reset = 00000000h]

GPIO47PCTL is shown in Table 16-241.

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Pull control register of IO GPIO47 This register configures the pull control

Table 16-241 GPIO47PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.240 GPIO47CTL Register (Offset = 00030008h) [Reset = 00000000h]

GPIO47CTL is shown in Table 16-242.

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Control register of IO GPIO47 This register controls the IO state

Table 16-242 GPIO47CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.241 GPIO47ECTL Register (Offset = 0003000Ch) [Reset = 00000000h]

GPIO47ECTL is shown in Table 16-243.

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Event control register for IO GPIO47 This register controls the Event configuration and behaviour

Table 16-243 GPIO47ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection

16.8.242 GPIO48CFG Register (Offset = 00031000h) [Reset = 00000000h]

GPIO48CFG is shown in Table 16-244.

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CFG register for IO GPIO48. This register configures the corresponding pad

Table 16-244 GPIO48CFG Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
14IOSTRR/W0hThis field controls the IO drive strength
  • 0h = IO drives low power
  • 1h = IO drives high power
13OUTDISOVRENR/W0hThis field controls the [OUTDIS] override
  • 0h = Disable the override
  • 1h = Enable the override
12OUTDISR/W1hThis field configures the output from the pad Note:This field is applicable only if [OUTDISOVREN] is enabled
  • 0h = Output from the pad is enabled
  • 1h = Output from the pad is disabled
11IER/W1hThis field enables the receiver operation from the pad
  • 0h = Disable the receiver operation
  • 1h = Enable the receiver operation
10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
9-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6OUTDISVALR0hThe field gives the status of [OUTDIS]
  • 0h = Output is enabled
  • 1h = Output is disabled
5-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

16.8.243 GPIO48PCTL Register (Offset = 00031004h) [Reset = 00000000h]

GPIO48PCTL is shown in Table 16-245.

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Pull control register of IO GPIO48 This register configures the pull control

Table 16-245 GPIO48PCTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9PULLDWNSTAR0hThis field gives the IO pull down level status
  • 0h = Pull disabled
  • 1h = Pull down
8PULLUPSTAR0hThis field gives the IO pull up level status
  • 0h = Pull disabled
  • 1h = Pull up
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1-0CTLR/W1hThe fields defines the pull control
  • 0h = IP Pull Control
  • 1h = Pull up
  • 2h = Pull down
  • 3h = Pull disable

16.8.244 GPIO48CTL Register (Offset = 00031008h) [Reset = 00000000h]

GPIO48CTL is shown in Table 16-246.

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Control register of IO GPIO48 This register controls the IO state

Table 16-246 GPIO48CTL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9OUTOVRENR/W0h This field contols the override on output
  • 0h = Output controlled by IP
  • 1h = Enable override on output
8OUTR/W0hThis field configures the IO drive out value. This field is valid only when [OUTOVREN] is configured ENABLE
  • 0h = IO drives 0
  • 1h = IO drives 1
7-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1PADVALSYNCR0hThis field captures the sychronized(to SOC clock) received value
0PADVALR0hThis field captures the received value from pad

16.8.245 GPIO48ECTL Register (Offset = 0003100Ch) [Reset = 00000000h]

GPIO48ECTL is shown in Table 16-247.

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Event control register for IO GPIO48 This register controls the Event configuration and behaviour

Table 16-247 GPIO48ECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3CLRW0hThis bit is to be used to generate CLR pulse for the event
  • 0h = No effect
  • 1h = Clear the event
2TRGLVLR/W0hThis field configures the io event polarity. This field is applicable only when [EVTDETCFG] is configured LEVEL
  • 0h = Non Inverted polarity
  • 1h = Inverted polarity
1-0EVTDETCFGR/W0hThis field is to be configured to define the IO detection method
  • 0h = Masking the event
  • 1h = Rising edge/Positive edge detection
  • 2h = Falling edge/Negative edge detection
  • 3h = Level detection