SWRU626 User guide | 德州仪器 TI.com.cn

SWRU626 December 2025 CC3501E , CC3551E

1
1 Read This First
1. 1.1 About This Manual
2. 1.2 Register, Field, and Bit Calls
3. Trademarks
2 Architecture Overview
1. 2.1 Target Applications
2. 2.2 Introduction
3. 2.3 Internal System Diagram
4. 2.4 Arm Cortex M33
5. 2.5 Power Management
6. 2.6 Debug Subsystem (DEBUGSS)
7. 2.7 Memory Subsystem (MEMSS)
  1. 2.7.1 External Memory Interface
8. 2.8 Hardware Security Module
9. 2.9 General Purpose Timers (GPT)
10. 2.10 Real Time Clock (RTC)
11. 2.11 Direct Memory Access
12. 2.12 GPIOs
13. 2.13 Communication Peripherals
3 Arm Cortex-M33 Processor
1. 3.1 Arm Cortex-M33 Processor Introduction
2. 3.2 Block Diagram
3. 3.3 M33 instantiation parameters
4. 3.4 Arm Cortex-M33 System Peripheral Details
5. 3.5 CPU Sub-System Peripheral Details
6. 3.6 Programming Model
7. 3.7 TrustZone-M
8. 3.8 CC35xx Host MCU Registers
9. 3.9 Arm® Cortex®-M33 Registers
4 Memory Map
1. 4.1 Memory Map
5 Interrupts and Events
1. 5.1 Exception Model
2. 5.2 Fault Handling
3. 5.3 Security State Switches
4. 5.4 Event Manager
5. 5.5 SOC_IC Registers
6. 5.6 SOC_AON Registers
7. 5.7 SOC_AAON Registers
6 Debug Subsystem (DEBUGSS)
1. 6.1 Introduction
2. 6.2 Block Diagram
3. 6.3 Overview
4. 6.4 Physical Interface
5. 6.5 Debug Access Ports
6. 6.6 Debug Features
7. 6.7 Behavior in Low Power Modes
8. 6.8 Debug Access Control
9. 6.9 SOC_DEBUGSS Registers
7 Power, Reset, Clock Management
1. 7.1 Power Management
2. 7.2 Reset
  1. 7.2.1 Reset Cause
  2. 7.2.2 Watchdog Timer (WDT)
3. 7.3 Clocks
  1. 7.3.1 Fast Clock
  2. 7.3.2 Slow Clock
4. 7.4 PRCM_AON Registers
5. 7.5 PRCM_SCRATCHPAD Registers
8 Memory Subsystem (MEMSS)
1. 8.1 Introduction
2. 8.2 SRAM
3. 8.3 D-Cache
4. 8.4 Flash
5. 8.5 PSRAM
6. 8.6 XiP Memory Access
7. 8.7 ICACHE Registers
8. 8.8 DCACHE Registers
9. 8.9 OSPI Registers
10. 8.10 HOST_XIP Registers
9 Hardware Security Module (HSM)
1. 9.1 Introduction
2. 9.2 Overview
3. 9.3 Mailbox and Register Access Firewall
4. 9.4 DMA Firewall
5. 9.5 HSM Key Storage
6. 9.6 HSM Registers
7. 9.7 HSM_NON_SEC Registers
8. 9.8 HSM_SEC Registers
10Device Boot and Bootloader
1. 10.1 CC35xx Boot Concept
2. 10.2 Features
3. 10.3 Vendor Images Format and Processing
  1. 10.3.1 External Flash Arrangement
  2. 10.3.2 Vendor Images Format
4. 10.4 Boot Flows
5. 10.5 Chain of Trust
11Direct Memory Access (DMA)
1. 11.1 Overview
2. 11.2 Block Diagram
3. 11.3 Functional Description
4. 11.4 HOST_DMA Registers
12One Time Programming (OTP)
13General Purpose Timers (GPT)
1. 13.1 Overview
2. 13.2 Block Diagram
3. 13.3 Functional Description
4. 13.4 Timer Modes
5. 13.5 GPTIMER Registers
14System Timer (SysTimer)
1. 14.1 Overview
2. 14.2 Block Diagram
3. 14.3 Functional Description
  1. 14.3.1 Common Channel Features
  2. 14.3.2 Interrupts and Events
4. 14.4 SYSRESOURCES Registers
5. 14.5 SYSTIM Registers
15Real-Time Clock (RTC)
1. 15.1 Introduction
2. 15.2 Block Diagram
3. 15.3 Interrupts and Events
4. 15.4 CAPTURE and COMPARE Configurations
  1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
  2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
5. 15.5 RTC Registers
16General Purpose Input/Output (GPIOs)
1. 16.1 Introduction
2. 16.2 Block Diagram
3. 16.3 I/O Mapping and Configuration
  1. 16.3.1 Basic I/O Mapping
  2. 16.3.2 Pin Mapping
4. 16.4 Edge Detection
5. 16.5 GPIO
6. 16.6 I/O Pins
7. 16.7 Unused Pins
8. 16.8 IOMUX Registers
17Universal Asynchronous Receivers/Transmitters (UART)
1. 17.1 Introduction
2. 17.2 Block Diagram
3. 17.3 UART Functional Description
4. 17.4 UART-LIN Specification
5. 17.5 Interface to Host DMA
6. 17.6 Initialization and Configuration
7. 17.7 UART Registers
18Serial Peripheral Interface (SPI)
1. 18.1 Overview
  1. 18.1.1 Features
  2. 18.1.2 Block Diagram
2. 18.2 Signal Description
3. 18.3 Functional Description
4. 18.4 Host DMA Operation
5. 18.5 Initialization and Configuration
6. 18.6 SPI Registers
19Inter-Integrated Circuit (I2C) Interface
1. 19.1 Introduction
2. 19.2 Block Diagram
3. 19.3 Functional Description
  1. 19.3.1 Clock Control
    1. 19.3.1.1 Internal Clock
    2. 19.3.1.2 External Clock
  2. 19.3.2 General Architecture
4. 19.4 Initialization and Configuration
5. 19.5 Interrupts
6. 19.6 I2C Registers
20Secure Digital Multimedia Card (SDMMC)
1. 20.1 Introduction
  1. 20.1.1 SDMMC Features
  2. 20.1.2 Integration
2. 20.2 Functional Description
3. 20.3 Low-Level Programming Models
  1. 20.3.1 SDMMC Initialization Flow
  2. 20.3.2 Operational Modes Configuration
    1. 20.3.2.1 Basic Operations for SDMMC
    2. 20.3.2.2 Card Detection, Identification, and Selection
4. 20.4 SDMMC Registers
21Secure Digital Input/Output (SDIO)
1. 21.1 Introduction
2. 21.2 Block Diagram
3. 21.3 Functional Description
4. 21.4 SDIO_CORE Registers
5. 21.5 SDIO_CARD_FN1 Registers
22Inter-Integrated Circuit Sound (I2S)
1. 22.1 Introduction
2. 22.2 Block Diagram
3. 22.3 Signal Descriptions
4. 22.4 Functional Description
5. 22.5 Memory Interface
6. 22.6 Samplestamp Generator
7. 22.7 Error Detection
8. 22.8 Usage
  1. 22.8.1 Start-Up Sequence
  2. 22.8.2 Shutdown Sequence
9. 22.9 I2S Configuration Guideline
10. 22.10 I2S Registers
23Pulse Density Modulation (PDM)
1. 23.1 Introduction
2. 23.2 Block Diagram
3. 23.3 Input Selection
  1. 23.3.1 PDM Data Mode
  2. 23.3.2 Manchester Input Mode
4. 23.4 CIC Filter
5. 23.5 FIFO Organization in Different Modes
6. 23.6 Automatic Gain Control (AGC)
  1. 23.6.1 Operation in 2's Complement Format
  2. 23.6.2 Operation in Offset Binary Format
7. 23.7 Interrupts
8. 23.8 Clock Select and Control
9. 23.9 DMA Operation
10. 23.10 Samplestamp Generator
11. 23.11 Debug‑Mode Flag Behavior
12. 23.12 Software Guidelines
13. 23.13 PDM Registers
24Analog to Digital Converter (ADC)
1. 24.1 Overview
2. 24.2 Block Diagram
3. 24.3 Functional Description
4. 24.4 ADC Registers
25Controller Area Network (CAN)
1. 25.1 Introduction
2. 25.2 Functions
3. 25.3 DCAN Subsystem
4. 25.4 DCAN Functional Description
5. 25.5 DCAN Wrapper
6. 25.6 DCAN Clock Enable
7. 25.7 DCAN Registers
26Revision History

24.4 ADC Registers

Table 24-9 lists the memory-mapped registers for the ADC registers. All register offset addresses not listed in Table 24-9 should be considered as reserved locations and the register contents should not be modified.

Table 24-9 ADC Registers

Offset	Acronym	Register Name	Section
1020h	INTEVT0IDX	Interrupt Priority Index	Section 24.4.1
1028h	INTEVT0BM	Internal Event 0 Interrupt Mask	Section 24.4.2
1030h	INTEVT0RIS	Internal Event Raw Interrupt Status	Section 24.4.3
1038h	INTEVT0MIS	Masked Interrupt Status	Section 24.4.4
1040h	INTEVT0SET	Interrupt Set Register	Section 24.4.5
1048h	INTEVT0CLR	Interrupt Clear Register	Section 24.4.6
1050h	INTEVT1IDX	Interrupt Priority Index	Section 24.4.7
1058h	INTEVT1BM	Interrupt Mask Control	Section 24.4.8
1060h	INTEVT1RIS	Raw Interrupt Status	Section 24.4.9
1068h	INTEVT1MIS	Masked Interrupt Status	Section 24.4.10
1070h	INTEVT1SET	Interrupt Set Control	Section 24.4.11
1078h	INTEVT1CLR	Interrupt Clear Register	Section 24.4.12
1080h	INTEVT2IDX	Interrupt Priority Index	Section 24.4.13
1088h	INTEVT2BM	Event Interrupt Mask	Section 24.4.14
1090h	INTEVT2RIS	Raw Interrupt Status	Section 24.4.15
1098h	INTEVT2MIS	Masked Interrupt Status	Section 24.4.16
10A0h	INTEVT2SET	Interrupt Set Register	Section 24.4.17
10A8h	INTEVT2CLR	Interrupt Clear Register	Section 24.4.18
10E0h	EVTMOD	Event Handling Mode	Section 24.4.19
1100h	CTL0	Main Control	Section 24.4.20
1104h	CTL1	Control Register	Section 24.4.21
1108h	CTL2	Sequence Control Register	Section 24.4.22
110Ch	CTL3	Single Conversion Configuration	Section 24.4.23
1114h	SCOMP0	Sample Time Configuration	Section 24.4.24
1118h	SCOMP1	Sample Time Control	Section 24.4.25
111Ch	REFCFG	Reference Buffer Configuration	Section 24.4.26
1148h	WCLOW	Low Threshold Value	Section 24.4.27
1150h	WCHI	High Threshold Value	Section 24.4.28
1160h	FIFODATA	FIFO Data	Section 24.4.29
1170h	ASCRES	Analog Sequence Controller Result	Section 24.4.30
1180h	MEMCTL_0	Sequence memory 0 to memory 31 control registers.	Section 24.4.31
1184h	MEMCTL_1	Sequence memory 0 to memory 31 control registers.	Section 24.4.32
1188h	MEMCTL_2	Sequence memory 0 to memory 31 control registers.	Section 24.4.33
118Ch	MEMCTL_3	Sequence memory 0 to memory 31 control registers.	Section 24.4.34
1190h	MEMCTL_4	Sequence memory 0 to memory 31 control registers.	Section 24.4.35
1194h	MEMCTL_5	Sequence memory 0 to memory 31 control registers.	Section 24.4.36
1280h	MEMRES_0	Memory Results Register	Section 24.4.37
1284h	MEMRES_1	Memory Results Register	Section 24.4.38
1288h	MEMRES_2	Memory Results Register	Section 24.4.39
128Ch	MEMRES_3	Memory Results Register	Section 24.4.40
1290h	MEMRES_4	Memory Results Register	Section 24.4.41
1294h	MEMRES_5	Memory Results Register	Section 24.4.42
1298h	MEMRES_6	Memory Results Register	Section 24.4.43
129Ch	MEMRES_7	Memory Results Register	Section 24.4.44
12A0h	MEMRES_8	Memory Results Register	Section 24.4.45
12A4h	MEMRES_9	Memory Results Register	Section 24.4.46
12A8h	MEMRES_10	Memory Results Register	Section 24.4.47
12ACh	MEMRES_11	Memory Results Register	Section 24.4.48
12B0h	MEMRES_12	Memory Results Register	Section 24.4.49
12B4h	MEMRES_13	Memory Results Register	Section 24.4.50
12B8h	MEMRES_14	Memory Results Register	Section 24.4.51
12BCh	MEMRES_15	Memory Results Register	Section 24.4.52
1340h	STA	Status Register	Section 24.4.53
1F14h	CONVCTL	Conversion Control	Section 24.4.54
1F18h	CTRL	Fuse Control	Section 24.4.55
1F1Ch	MODCTL	Mode Control	Section 24.4.56
1F20h	INTCHCTL	Internal Channel Control	Section 24.4.57
2000h	CLKCFG	Clock Enable	Section 24.4.58

Complex bit access types are encoded to fit into small table cells. Table 24-10 shows the codes that are used for access types in this section.

Table 24-10 ADC Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RH	R H	Read Set or cleared by hardware
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

24.4.1 INTEVT0IDX Register (Offset = 1020h) [Reset = 00000000h]

INTEVT0IDX is shown in Table 24-11.

Return to the Summary Table.

INTERNAL EVENT 0 IRQ IDX This register provides the highest priority enabled interrupt index. 0x0 means no event pending. Interrupt 1 is the highest priority, 2 next highest, 4, 8, ... 2³¹ is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Table 24-11 INTEVT0IDX Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R	0h
9-0	STAT	R	0h	Interrupt index status 00h = No bit is set means there is no pending interrupt request 01h = MEMRESx overflow interrupt 02h = Sequence Conversion time overflow interrupt 03h = High threshold compare interrupt 04h = Low threshold compare interrupt 05h = Primary Sequence In range comparator interrupt 6h = DMA done interrupt, generated on DMA transfer completion, 07h = MEMRESx underflow interrupt 9h = MEMRES0 data loaded interrupt Ah = MEMRES1 data loaded interrupt Bh = MEMRES2 data loaded interrupt Ch = MEMRES3 data loaded interrupt Dh = MEMRES4 data loaded interrupt Eh = MEMRES5 data loaded interrupt Fh = MEMRES6 data loaded interrupt 10h = MEMRES7 data loaded interrupt 11h = MEMRES8 data loaded interrupt 12h = MEMRES9 data loaded interrupt 13h = MEMRES10 data loaded interrupt 14h = MEMRES11 data loaded interrupt 15h = MEMRES12 data loaded interrupt 16h = MEMRES13 data loaded interrupt 17h = MEMRES14 data loaded interrupt 18h = MEMRES15 data loaded interrupt 19h = MEMRES16 data loaded interrupt 1Ah = MEMRES17 data loaded interrupt 1Bh = MEMRES18 data loaded interrupt 1Ch = MEMRES19 data loaded interrupt 1Dh = MEMRES20 data loaded interrupt 1Eh = MEMRES21 data loaded interrupt 1Fh = MEMRES22 data loaded interrupt 20h = MEMRES23 data loaded interrupt

24.4.2 INTEVT0BM Register (Offset = 1028h) [Reset = 00000000h]

INTEVT0BM is shown in Table 24-12.

Return to the Summary Table.

INTERNAL EVENT 0 IRQ MASK Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Table 24-12 INTEVT0BM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	0h
23	MEMRESIFG15	R/W	0h	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
22	MEMRESIFG14	R/W	0h	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
21	MEMRESIFG13	R/W	0h	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
20	MEMRESIFG12	R/W	0h	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
19	MEMRESIFG11	R/W	0h	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
18	MEMRESIFG10	R/W	0h	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
17	MEMRESIFG9	R/W	0h	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
16	MEMRESIFG8	R/W	0h	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
15	MEMRESIFG7	R/W	0h	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
14	MEMRESIFG6	R/W	0h	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
13	MEMRESIFG5	R/W	0h	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
12	MEMRESIFG4	R/W	0h	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
11	MEMRESIFG3	R/W	0h	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
10	MEMRESIFG2	R/W	0h	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
9	MEMRESIFG1	R/W	0h	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
8	MEMRESIFG0	R/W	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
7	RESERVED	R/W	0h
6	UVIFG	R/W	0h	Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
5	DMADONE	R/W	0h	Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
4	INIFG	R/W	0h	Mask INIFG in MIS_EX register. 0h = Interrupt is not pending. 1h = Interrupt is pending.
3	LOFG	R/W	0h	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
2	HIFG	R/W	0h	Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
1	TOVIFG	R/W	0h	Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
0	OVIFG	R/W	0h	Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.

24.4.3 INTEVT0RIS Register (Offset = 1030h) [Reset = 00000000h]

INTEVT0RIS is shown in Table 24-13.

Return to the Summary Table.

INTERNAL EVENT 0 RAW IRQ STATUS Raw interrupt status. Reflects all pending interrupts, regardless of masking. The INT_EVENT0_RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Table 24-13 INTEVT0RIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h
23	MEMRESIFG15	R	0h	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
22	MEMRESIFG14	R	0h	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
21	MEMRESIFG13	R	0h	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
20	MEMRESIFG12	R	0h	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
19	MEMRESIFG11	R	0h	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
18	MEMRESIFG10	R	0h	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
17	MEMRESIFG9	R	0h	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
16	MEMRESIFG8	R	0h	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
15	MEMRESIFG7	R	0h	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
14	MEMRESIFG6	R	0h	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
13	MEMRESIFG5	R	0h	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
12	MEMRESIFG4	R	0h	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
11	MEMRESIFG3	R	0h	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
10	MEMRESIFG2	R	0h	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
9	MEMRESIFG1	R	0h	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
8	MEMRESIFG0	R	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
7	RESERVED	R	0h
6	UVIFG	R	0h	Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
5	DMADONE	R	0h	Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
4	INIFG	R	0h	Mask INIFG in MIS_EX register. 0h = Interrupt is not pending. 1h = Interrupt is pending.
3	LOFG	R	0h	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
2	HIFG	R	0h	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
1	TOVIFG	R	0h	Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
0	OVIFG	R	0h	Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.

24.4.4 INTEVT0MIS Register (Offset = 1038h) [Reset = 00000000h]

INTEVT0MIS is shown in Table 24-14.

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INTERNAL EVENT 0 MASKED IRQ STATUS Masked interrupt status. This is an AND of the IMASK and RIS registers.

Table 24-14 INTEVT0MIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h
23	MEMRESIFG15	R	0h	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
22	MEMRESIFG14	R	0h	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
21	MEMRESIFG13	R	0h	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
20	MEMRESIFG12	R	0h	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
19	MEMRESIFG11	R	0h	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
18	MEMRESIFG10	R	0h	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
17	MEMRESIFG9	R	0h	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
16	MEMRESIFG8	R	0h	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
15	MEMRESIFG7	R	0h	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
14	MEMRESIFG6	R	0h	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
13	MEMRESIFG5	R	0h	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
12	MEMRESIFG4	R	0h	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
11	MEMRESIFG3	R	0h	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
10	MEMRESIFG2	R	0h	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
9	MEMRESIFG1	R	0h	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
8	MEMRESIFG0	R	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 11 0h = No new data ready. 1h = A new data is ready to be read.
7	RESERVED	R	0h
6	UVIFG	R	0h	Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
5	DMADONE	R	0h	Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
4	INIFG	R	0h	Mask INIFG in MIS_EX register. 0h = Interrupt is not pending. 1h = Interrupt is pending.
3	LOFG	R	0h	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
2	HIFG	R	0h	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
1	TOVIFG	R	0h	Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
0	OVIFG	R	0h	Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.

24.4.5 INTEVT0SET Register (Offset = 1040h) [Reset = 00000000h]

INTEVT0SET is shown in Table 24-15.

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INTERNAL EVENT 0 IRQ SET Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in INT_EVENT0_ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Table 24-15 INTEVT0SET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	0h
23	MEMRESIFG15	W	0h	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
22	MEMRESIFG14	W	0h	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
21	MEMRESIFG13	W	0h	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
20	MEMRESIFG12	W	0h	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
19	MEMRESIFG11	W	0h	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
18	MEMRESIFG10	W	0h	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
17	MEMRESIFG9	W	0h	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
16	MEMRESIFG8	W	0h	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
15	MEMRESIFG7	W	0h	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
14	MEMRESIFG6	W	0h	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
13	MEMRESIFG5	W	0h	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
12	MEMRESIFG4	W	0h	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
11	MEMRESIFG3	W	0h	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
10	MEMRESIFG2	W	0h	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
9	MEMRESIFG1	W	0h	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
8	MEMRESIFG0	W	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
7	RESERVED	R/W	0h
6	UVIFG	W	0h	Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
5	DMADONE	W	0h	Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
4	INIFG	W	0h	Mask INIFG in MIS_EX register. 0h = Interrupt is not pending. 1h = Interrupt is pending.
3	LOFG	W	0h	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
2	HIFG	W	0h	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
1	TOVIFG	W	0h	Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
0	OVIFG	W	0h	Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.

24.4.6 INTEVT0CLR Register (Offset = 1048h) [Reset = 00000000h]

INTEVT0CLR is shown in Table 24-16.

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INTERNAL EVENT 0 IRQ CLEAR Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 24-16 INTEVT0CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	0h
23	MEMRESIFG15	W	0h	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
22	MEMRESIFG14	W	0h	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
21	MEMRESIFG13	W	0h	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
20	MEMRESIFG12	W	0h	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
19	MEMRESIFG11	W	0h	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
18	MEMRESIFG10	W	0h	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
17	MEMRESIFG9	W	0h	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
16	MEMRESIFG8	W	0h	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
15	MEMRESIFG7	W	0h	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
14	MEMRESIFG6	W	0h	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
13	MEMRESIFG5	W	0h	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
12	MEMRESIFG4	W	0h	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
11	MEMRESIFG3	W	0h	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
10	MEMRESIFG2	W	0h	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
9	MEMRESIFG1	W	0h	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
8	MEMRESIFG0	W	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
7	RESERVED	R/W	0h
6	UVIFG	W	0h	Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
5	DMADONE	W	0h	Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
4	INIFG	W	0h	Mask INIFG in MIS_EX register. 0h = Interrupt is not pending. 1h = Interrupt is pending.
3	LOFG	W	0h	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
2	HIFG	W	0h	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
1	TOVIFG	W	0h	Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
0	OVIFG	W	0h	Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.

24.4.7 INTEVT1IDX Register (Offset = 1050h) [Reset = 00000000h]

INTEVT1IDX is shown in Table 24-17.

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INTERNAL EVENT 1 IRQ IDX This register provides the highest priority enabled interrupt index. 0x0 means no event pending. Interrupt 1 is the highest priority, 2 next highest, 4, 8, ... 2³¹ is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Table 24-17 INTEVT1IDX Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R	0h
9-0	STAT	R	0h	Interrupt index status 00h = No bit is set means there is no pending interrupt request 03h = High threshold compare interrupt 04h = Low threshold compare interrupt 05h = Primary Sequence In range comparator interrupt 9h = MEMRES0 data loaded interrupt

24.4.8 INTEVT1BM Register (Offset = 1058h) [Reset = 00000000h]

INTEVT1BM is shown in Table 24-18.

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INTERNAL EVENT 1 IRQ MASK Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Table 24-18 INTEVT1BM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R/W	0h
8	MEMRESIFG0	R/W	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
7-5	RESERVED	R/W	0h
4	INIFG	R/W	0h	Mask INIFG in MIS_EX register. 0h = Interrupt is not pending. 1h = Interrupt is pending.
3	LOFG	R/W	0h	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
2	HIFG	R/W	0h	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
1-0	RESERVED	R/W	0h

24.4.9 INTEVT1RIS Register (Offset = 1060h) [Reset = 00000000h]

INTEVT1RIS is shown in Table 24-19.

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INTERNAL EVENT 1 RAW IRQ STATUS Raw interrupt status. Reflects all pending interrupts, regardless of masking. The INT_EVENT1_RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Table 24-19 INTEVT1RIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h
8	MEMRESIFG0	R	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
7-5	RESERVED	R	0h
4	INIFG	R	0h	Mask INIFG in MIS_EX register. 0h = Interrupt is not pending. 1h = Interrupt is pending.
3	LOFG	R	0h	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
2	HIFG	R	0h	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
1-0	RESERVED	R	0h

24.4.10 INTEVT1MIS Register (Offset = 1068h) [Reset = 00000000h]

INTEVT1MIS is shown in Table 24-20.

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INTERNAL EVENT 1 MASKED IRQ STATUS Masked interrupt status. This is an AND of the IMASK and RIS registers.

Table 24-20 INTEVT1MIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h
8	MEMRESIFG0	R	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
7-5	RESERVED	R	0h
4	INIFG	R	0h	Mask INIFG in MIS_EX register. 0h = Interrupt is not pending. 1h = Interrupt is pending.
3	LOFG	R	0h	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
2	HIFG	R	0h	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
1-0	RESERVED	R	0h

24.4.11 INTEVT1SET Register (Offset = 1070h) [Reset = 00000000h]

INTEVT1SET is shown in Table 24-21.

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INTERNAL EVENT 1 IRQ SET Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in INT_EVENT1_ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Table 24-21 INTEVT1SET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R/W	0h
8	MEMRESIFG0	W	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
7-5	RESERVED	R/W	0h
4	INIFG	W	0h	Mask INIFG in MIS_EX register. 0h = Interrupt is not pending. 1h = Interrupt is pending.
3	LOFG	W	0h	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
2	HIFG	W	0h	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
1-0	RESERVED	R/W	0h

24.4.12 INTEVT1CLR Register (Offset = 1078h) [Reset = 00000000h]

INTEVT1CLR is shown in Table 24-22.

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INTERNAL EVENT 1 IRQ CLEAR Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 24-22 INTEVT1CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R/W	0h
8	MEMRESIFG0	W	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
7-5	RESERVED	R/W	0h
4	INIFG	W	0h	Mask INIFG in MIS_EX register. 0h = Interrupt is not pending. 1h = Interrupt is pending.
3	LOFG	W	0h	LOW FG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
2	HIFG	W	0h	HIGH FG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0h = Interrupt is not pending. 1h = Interrupt is pending.
1-0	RESERVED	R/W	0h

24.4.13 INTEVT2IDX Register (Offset = 1080h) [Reset = 00000000h]

INTEVT2IDX is shown in Table 24-23.

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INTERNAL EVENT 2 IRQ IDX This register provides the highest priority enabled interrupt index. 0x0 means no event pending. Interrupt 1 is the highest priority, 2 next highest, 4, 8, ... 2³¹ is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Table 24-23 INTEVT2IDX Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R	0h
9-0	STAT	R	0h	Interrupt index status 00h = No bit is set means there is no pending interrupt request 9h = MEMRES0 data loaded interrupt Ah = MEMRES1 data loaded interrupt Bh = MEMRES2 data loaded interrupt Ch = MEMRES3 data loaded interrupt Dh = MEMRES4 data loaded interrupt Eh = MEMRES5 data loaded interrupt Fh = MEMRES6 data loaded interrupt 10h = MEMRES7 data loaded interrupt 11h = MEMRES8 data loaded interrupt 12h = MEMRES9 data loaded interrupt 13h = MEMRES10 data loaded interrupt 14h = MEMRES11 data loaded interrupt 15h = MEMRES12 data loaded interrupt 16h = MEMRES13 data loaded interrupt 17h = MEMRES14 data loaded interrupt 18h = MEMRES15 data loaded interrupt 19h = MEMRES16 data loaded interrupt 1Ah = MEMRES17 data loaded interrupt 1Bh = MEMRES18 data loaded interrupt 1Ch = MEMRES19 data loaded interrupt 1Dh = MEMRES20 data loaded interrupt 1Eh = MEMRES21 data loaded interrupt 1Fh = MEMRES22 data loaded interrupt 20h = MEMRES23 data loaded interrupt

24.4.14 INTEVT2BM Register (Offset = 1088h) [Reset = 00000000h]

INTEVT2BM is shown in Table 24-24.

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INTERNAL EVENT 2 IRQ MASK Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Table 24-24 INTEVT2BM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	0h
23	MEMRESIFG15	R/W	0h	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
22	MEMRESIFG14	R/W	0h	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
21	MEMRESIFG13	R/W	0h	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
20	MEMRESIFG12	R/W	0h	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
19	MEMRESIFG11	R/W	0h	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
18	MEMRESIFG10	R/W	0h	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
17	MEMRESIFG9	R/W	0h	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
16	MEMRESIFG8	R/W	0h	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
15	MEMRESIFG7	R/W	0h	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
14	MEMRESIFG6	R/W	0h	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
13	MEMRESIFG5	R/W	0h	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
12	MEMRESIFG4	R/W	0h	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
11	MEMRESIFG3	R/W	0h	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
10	MEMRESIFG2	R/W	0h	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
9	MEMRESIFG1	R/W	0h	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
8	MEMRESIFG0	R/W	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
7-0	RESERVED	R/W	0h

24.4.15 INTEVT2RIS Register (Offset = 1090h) [Reset = 00000000h]

INTEVT2RIS is shown in Table 24-25.

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INTERNAL EVENT 2 RAW IRQ STATUS Raw interrupt status. Reflects all pending interrupts, regardless of masking. The INT_EVENT2_RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Table 24-25 INTEVT2RIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h
23	MEMRESIFG15	R	0h	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
22	MEMRESIFG14	R	0h	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
21	MEMRESIFG13	R	0h	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
20	MEMRESIFG12	R	0h	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
19	MEMRESIFG11	R	0h	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
18	MEMRESIFG10	R	0h	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
17	MEMRESIFG9	R	0h	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
16	MEMRESIFG8	R	0h	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
15	MEMRESIFG7	R	0h	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
14	MEMRESIFG6	R	0h	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
13	MEMRESIFG5	R	0h	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
12	MEMRESIFG4	R	0h	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
11	MEMRESIFG3	R	0h	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
10	MEMRESIFG2	R	0h	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
9	MEMRESIFG1	R	0h	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
8	MEMRESIFG0	R	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
7-0	RESERVED	R	0h

24.4.16 INTEVT2MIS Register (Offset = 1098h) [Reset = 00000000h]

INTEVT2MIS is shown in Table 24-26.

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INTERNAL EVENT 2 MASKED IRQ STATUS Extension of Masked interrupt status. This is an AND of the IMASK and RIS registers.

Table 24-26 INTEVT2MIS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h
23	MEMRESIFG15	R	0h	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
22	MEMRESIFG14	R	0h	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
21	MEMRESIFG13	R	0h	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
20	MEMRESIFG12	R	0h	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
19	MEMRESIFG11	R	0h	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
18	MEMRESIFG10	R	0h	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
17	MEMRESIFG9	R	0h	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
16	MEMRESIFG8	R	0h	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
15	MEMRESIFG7	R	0h	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
14	MEMRESIFG6	R	0h	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
13	MEMRESIFG5	R	0h	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
12	MEMRESIFG4	R	0h	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
11	MEMRESIFG3	R	0h	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
10	MEMRESIFG2	R	0h	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
9	MEMRESIFG1	R	0h	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
8	MEMRESIFG0	R	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
7-0	RESERVED	R	0h

24.4.17 INTEVT2SET Register (Offset = 10A0h) [Reset = 00000000h]

INTEVT2SET is shown in Table 24-27.

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INTERNAL EVENT 2 IRQ SET Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in INT_EVENT2_ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Table 24-27 INTEVT2SET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	0h
23	MEMRESIFG15	W	0h	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
22	MEMRESIFG14	W	0h	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
21	MEMRESIFG13	W	0h	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
20	MEMRESIFG12	W	0h	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
19	MEMRESIFG11	W	0h	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
18	MEMRESIFG10	W	0h	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
17	MEMRESIFG9	W	0h	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
16	MEMRESIFG8	W	0h	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
15	MEMRESIFG7	W	0h	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
14	MEMRESIFG6	W	0h	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
13	MEMRESIFG5	W	0h	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
12	MEMRESIFG4	W	0h	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
11	MEMRESIFG3	W	0h	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
10	MEMRESIFG2	W	0h	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
9	MEMRESIFG1	W	0h	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
8	MEMRESIFG0	W	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
7-0	RESERVED	R/W	0h

24.4.18 INTEVT2CLR Register (Offset = 10A8h) [Reset = 00000000h]

INTEVT2CLR is shown in Table 24-28.

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INTERNAL EVENT 2 IRQ CLEAR Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 24-28 INTEVT2CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	0h
23	MEMRESIFG15	W	0h	Raw interrupt status for MEMRES15. This bit is set to 1 when MEMRES15 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
22	MEMRESIFG14	W	0h	Raw interrupt status for MEMRES14. This bit is set to 1 when MEMRES14 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
21	MEMRESIFG13	W	0h	Raw interrupt status for MEMRES13. This bit is set to 1 when MEMRES13 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
20	MEMRESIFG12	W	0h	Raw interrupt status for MEMRES12. This bit is set to 1 when MEMRES12 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
19	MEMRESIFG11	W	0h	Raw interrupt status for MEMRES11. This bit is set to 1 when MEMRES11 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
18	MEMRESIFG10	W	0h	Raw interrupt status for MEMRES10. This bit is set to 1 when MEMRES10 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
17	MEMRESIFG9	W	0h	Raw interrupt status for MEMRES9. This bit is set to 1 when MEMRES9 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
16	MEMRESIFG8	W	0h	Raw interrupt status for MEMRES8. This bit is set to 1 when MEMRES8 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
15	MEMRESIFG7	W	0h	Raw interrupt status for MEMRES7. This bit is set to 1 when MEMRES7 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
14	MEMRESIFG6	W	0h	Raw interrupt status for MEMRES6. This bit is set to 1 when MEMRES6 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
13	MEMRESIFG5	W	0h	Raw interrupt status for MEMRES5. This bit is set to 1 when MEMRES5 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
12	MEMRESIFG4	W	0h	Raw interrupt status for MEMRES4. This bit is set to 1 when MEMRES4 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
11	MEMRESIFG3	W	0h	Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
10	MEMRESIFG2	W	0h	Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
9	MEMRESIFG1	W	0h	Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
8	MEMRESIFG0	W	0h	Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. To clear this bit, corresponding bit in ICLR should be set to 1 0h = No new data ready. 1h = A new data is ready to be read.
7-0	RESERVED	R/W	0h

24.4.19 EVTMOD Register (Offset = 10E0h) [Reset = 00000000h]

EVTMOD is shown in Table 24-29.

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EVENT MODE Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Table 24-29 EVTMOD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R/W	0h
3-2	EVT1CFG	R/W	2h	EVENT 1 CONFIG Event line mode select for event corresponding to none.INT_EVENT1 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0	INT0CFG	R/W	1h	INTERNAL 0 CONFIG Event line mode select for event corresponding to none.INT_EVENT0 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

24.4.20 CTL0 Register (Offset = 1100h) [Reset = 00000000h]

CTL0 is shown in Table 24-30.

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ULP_ADCHP Control Register 0

Table 24-30 CTL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R/W	0h
26-24	SCLKDIV	R/W	0h	NU - should keep as '0'. Selects divide ratio of of sample clock. 0h = Do not divide clock source 1h = Divide clock source by 2 2h = Divide clock source by 3 3h = Divide clock source by 4 4h = Divide clock source by 5 5h = Divide clock source by 6 6h = Divide clock source by 7 7h = Divide clock source by 8
23-17	RESERVED	R/W	0h
16	PWRDN	R/W	0h	Auto or manual power down mode. 0h = ADC is powered down on completion of a conversion, if there isn't a pending trigger. 1h = ADC is kept powered up as long as ADCEN bit is set.
15-1	RESERVED	R/W	0h
0	ENC	RH/W	0h	ULP_ADCHP Enable Conversions. 0h = ULP_ADCHP primary sequencer is off Transition from ON to OFF will abort the primary single or repeat sequence on a MEMCTLx boundary. (The current conversion will finish and result stored in corresponding MEMRESx) 1h = ULP_ADCHP primary sequencer is ON. Waiting for valid trigger (Software or Hardware)

24.4.21 CTL1 Register (Offset = 1104h) [Reset = 00000000h]

CTL1 is shown in Table 24-31.

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Primary Sequence Control Register

Table 24-31 CTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	0h
30-28	AVGD	R/W	0h	Hardware average denominator. The number to divide the accumulated value by (this is a shift). Note results register is maximum of 16-bits long so if not shifted appropriately result will be truncated. 0h (R/W) = 0 bit shift 1h (R/W) = 1 bit shift 2h (R/W) = 2 bit shift 3h (R/W) = 3 bit shift 4h (R/W) = 4 bit shift 5h (R/W) = 5 bit shift 6h (R/W) = 6 bit shift 7h (R/W) = 7 bit shift
27	RESERVED	R/W	0h
26-24	AVGN	R/W	0h	Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then is get divided by AVGD. Result will be stored in MEMRESx. 0h (R/W) = Disables averager. 1h (R/W) = Averages 2 conversions before storing in MEMRES register. 2h (R/W) = Averages 4 conversions before storing in MEMRES register. 3h (R/W) = Averages 8 conversions before storing in MEMRES register. 4h (R/W) = Averages 16 conversions before storing in MEMRES register. 5h (R/W) = Averages 32 conversions before storing in MEMRES register. 6h (R/W) = Averages 64 conversions before storing in MEMRES register. 7h (R/W) = Averages 128 conversions before storing in MEMRES register.
23-21	RESERVED	R/W	0h
20	SAMPMODE	R/W	0h	ULP_ADCHP Primary Sequencer Sample Mode. This bit select the source of the sampling signal. 0h = The sample timer high phase is used as sample signal. 1h = The external or software trigger is used as sample signal.
19-18	RESERVED	R/W	0h
17-16	CONSEQ	R/W	0h	ULP_ADCHP Primary Sequencer Conversion Sequence Mode Select. 0h = The MEMCTLx pointed by PSTARTADD will be converted once. 1h = The primary sequence pointed by PSTARTADD will be converted once. 2h = The MEMCTLx pointed by PSTARTADD will be converted in repeat mode. 3h = Primary sequence pointed by PSTARTADD will be converted in repeat mode.
15-9	RESERVED	R/W	0h
8	SC	RH/W	0h	ULP_ADCHP Sequencer Start Of Conversion. If ULP_ADCHP is configured as FOLLOWER, this bit has no effect. 0h = When PSAMPMODE is set to MANUAL (1) mode, clearing this bit will end the sampling phase and the conversion phase will start. When PSAMPMODE is set to AUTO mode (0), writing 0 has no effect. This bit is automatically cleared at the end of the current conversion. 1h = When PSAMPMODE is set to MANUAL (1), setting this bit, will start the sampling phase. Sample phase will last as long as this bit is set. When PSAMPMODE is set to AUTO mode (0), setting this bit will trigger the timer based sample time.
7-1	RESERVED	R/W	0h
0	TRIGSRC	R/W	0h	ULP_ADCHP Primary Sequence Trigger Source. 0h = Primary sequence or single conversion is triggered by software. 1h = Primary sequence or single conversion is triggered by hardware event_0. (See device specific data-sheet for source for availability of this trigger)

24.4.22 CTL2 Register (Offset = 1108h) [Reset = 00000000h]

CTL2 is shown in Table 24-32.

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Primary Sequence Control Register

Table 24-32 CTL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	0h
28-24	ENDADD	R/W	0h	ULP_ADCHP Primary Sequence End Address. These bits select which MEMCTLx is the last MEMCTL for primary sequence mode. The value of PSTARTADD is 0x00 to 0x1F, corresponding to MEMRES0 to MEMRES31. 00h = MEMCTL0 is selected as end address of primary sequence. 01h = MEMCTL1 is selected as end address of primary sequence. 02h = MEMCTL2 is selected as end address of primary sequence. 03h = MEMCTL3 is selected as end address of primary sequence. 04h = MEMCTL4 is selected as end address of primary sequence. 05h = MEMCTL5 is selected as end address of primary sequence. 06h = MEMCTL6 is selected as end address of primary sequence. 07h = MEMCTL7 is selected as end address of primary sequence. 08h = MEMCTL8 is selected as end address of primary sequence. 09h = MEMCTL9 is selected as end address of primary sequence. 0Ah = MEMCTL10 is selected as end address of primary sequence. 0Bh = MEMCTL11 is selected as end address of primary sequence. 0Ch = MEMCTL12 is selected as end address of primary sequence. 0Dh = MEMCTL13 is selected as end address of primary sequence. 0Eh = MEMCTL14 is selected as end address of primary sequence. 0Fh = MEMCTL15 is selected as end address of primary sequence. 10h = MEMCTL16 is selected as end address of primary sequence. 11h = MEMCTL17 is selected as end address of primary sequence. 12h = MEMCTL18 is selected as end address of primary sequence. 13h = MEMCTL19 is selected as end address of primary sequence. 14h = MEMCTL20 is selected as end address of primary sequence. 15h = MEMCTL21 is selected as end address of primary sequence. 16h = MEMCTL22 is selected as end address of primary sequence. 17h = MEMCTL23 is selected as end address of primary sequence. 18h = MEMCTL24 is selected as end address of primary sequence. 19h = MEMCTL25 is selected as end address of primary sequence. 1Ah = MEMCTL26 is selected as end address of primary sequence. 1Bh = MEMCTL27 is selected as end address of primary sequence. 1Ch = MEMCTL28 is selected as end address of primary sequence. 1Dh = MEMCTL29 is selected as end address of primary sequence. 1Eh = MEMCTL30 is selected as end address of primary sequence. 1Fh = MEMCTL31 is selected as end address of primary sequence.
23-21	RESERVED	R/W	0h
20-16	STARTADD	R/W	0h	ULP_ADCHP Primary Sequence Start Address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for primary sequence mode. The value of PSTARTADD is 0x00 to 0x1F, corresponding to MEMRES0 to MEMRES31. 00h = MEMCTL0 is selected as start address of a primary sequence or as a single conversion. 01h = MEMCTL1 is selected as start address of a primary sequence or as a single conversion. 02h = MEMCTL2 is selected as start address of a primary sequence or as a single conversion. 03h = MEMCTL3 is selected as start address of a primary sequence or as a single conversion. 04h = MEMCTL4 is selected as start address of a primary sequence or as a single conversion. 05h = MEMCTL5 is selected as start address of a primary sequence or as a single conversion. 06h = MEMCTL6 is selected as start address of a primary sequence or as a single conversion. 07h = MEMCTL7 is selected as start address of a primary sequence or as a single conversion. 08h = MEMCTL8 is selected as start address of a primary sequence or as a single conversion. 09h = MEMCTL9 is selected as start address of a primary sequence or as a single conversion. 0Ah = MEMCTL10 is selected as start address of a primary sequence or as a single conversion. 0Bh = MEMCTL11 is selected as start address of a primary sequence or as a single conversion. 0Ch = MEMCTL12 is selected as start address of a primary sequence or as a single conversion. 0Dh = MEMCTL13 is selected as start address of a primary sequence or as a single conversion. 0Eh = MEMCTL14 is selected as start address of a primary sequence or as a single conversion. 0Fh = MEMCTL15 is selected as start address of a primary sequence or as a single conversion. 10h = MEMCTL16 is selected as start address of a primary sequence or as a single conversion. 11h = MEMCTL17 is selected as start address of a primary sequence or as a single conversion. 12h = MEMCTL18 is selected as start address of a primary sequence or as a single conversion. 13h = MEMCTL19 is selected as start address of a primary sequence or as a single conversion. 14h = MEMCTL20 is selected as start address of a primary sequence or as a single conversion. 15h = MEMCTL21 is selected as start address of a primary sequence or as a single conversion. 16h = MEMCTL22 is selected as start address of a primary sequence or as a single conversion. 17h = MEMCTL23 is selected as start address of a primary sequence or as a single conversion. 18h = MEMCTL24 is selected as start address of a primary sequence or as a single conversion. 19h = MEMCTL25 is selected as start address of a primary sequence or as a single conversion. 1Ah = MEMCTL26 is selected as start address of a primary sequence or as a single conversion. 1Bh = MEMCTL27 is selected as start address of a primary sequence or as a single conversion. 1Ch = MEMCTL28 is selected as start address of a primary sequence or as a single conversion. 1Dh = MEMCTL29 is selected as start address of a primary sequence or as a single conversion. 1Eh = MEMCTL30 is selected as start address of a primary sequence or as a single conversion. 1Fh = MEMCTL31 is selected as start address of a primary sequence or as a single conversion.
15-11	RESERVED	R/W	0h
10	FIFOEN	R/W	0h	Enables configuring of MEMRES register in FIFO mode. 0h = Disabled FIFO mode of operation, 1h = Enables FIFO mode of operation.
9	RESERVED	R/W	0h
8	DMAEN	RH/W	0h	Enable DMA for data transfer. 0h (R/W) = DMA triggers are not enabled. 1h (R/W) = Enable DMA.
7-3	RESERVED	R/W	0h
2-1	RES	R/W	0h	ULP_ADCHP resolution. This bits define the conversion result resolution. Note : A value of 3 defaults to 12 bit resolution. 0h = 16-bits resolution
0	DF	R/W	0h	ULP_ADCHP data read-back format. Data is always stored in binary unsigned format. 0h = Digital result reads as Binary Unsigned. 1h = Digital result reads Signed Binary. (2s complement), left aligned.

24.4.23 CTL3 Register (Offset = 110Ch) [Reset = 00000000h]

CTL3 is shown in Table 24-33.

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Control Register 3. This register is used to configure ADC for ad-hoc single conversion.

Table 24-33 CTL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R/W	0h
15	ASCMODE	R/W	0h	Single vs Differential
14	ASCFSR	R/W	0h	Full scale range of ADC limited to 1.8V or 3.3V *Exact range may be limited below the above mentioned voltages based on the design constraints
13-12	ASCVRSEL	R/W	0h	Selects the voltage reference for ASC operation. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF. 1h = EXTREF pin reference. 2h = Internal reference.
11-9	RESERVED	R/W	0h
8	ASCSTIME	R/W	0h	ASC sample time compare value select. This is used to select between SCOMP0 and SCOMP1 registers for ASC operation. 0h = Select SCOMP0 1h = Select SCOMP1
7-5	RESERVED	R/W	0h
4-0	ASCCHSEL	R/W	0h	ASC channel select 00h = Selects channel 0 01h = Selects channel 1 02h = Selects channel 2 03h = Selects channel 3 04h = Selects channel 4 05h = Selects channel 5 06h = Selects channel 6 07h = Selects channel 7 08h = Selects channel 8 09h = Selects channel 9 0Ah = Selects channel 10 0Bh = Selects channel 11 0Ch = Selects channel 12 0Dh = Selects channel 13 0Eh = Selects channel 14 0Fh = Selects channel 15 10h = Selects channel 16 11h = Selects channel 17 12h = Selects channel 18 13h = Selects channel 19 14h = Selects channel 20 15h = Selects channel 21 16h = Selects channel 22 17h = Selects channel 23 18h = Selects channel 24 19h = Selects channel 25 1Ah = Selects channel 26 1Bh = Selects channel 27 1Ch = Selects channel 28 1Dh = Selects channel 29 1Eh = Selects channel 30 1Fh = Selects channel 31

24.4.24 SCOMP0 Register (Offset = 1114h) [Reset = 00000000h]

SCOMP0 is shown in Table 24-34.

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ULP_ADCHP sample time register x Specifies the sample time, in number of ADCCLK cycles, when PSSM = 0 (AUTO) or SSSM = 0 (AUTO). CTL0.ENC must be set to 0 to write to this register.

Table 24-34 SCOMP0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-14	RESERVED	R/W	0h
13-0	SMP	R/W	0h	SAMPLE This bit-field specify the number of sample time clocks (SCOMPx +1) for a conversion when SAMPLE_TIME in MEMCTLx is set to SCOMPx.

24.4.25 SCOMP1 Register (Offset = 1118h) [Reset = 00000000h]

SCOMP1 is shown in Table 24-35.

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ULP_ADCHP sample time register x Specifies the sample time, in number of ADCCLK cycles, when PSSM = 0 (AUTO) or SSSM = 0 (AUTO). CTL0.ENC must be set to 0 to write to this register.

Table 24-35 SCOMP1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-14	RESERVED	R/W	0h
13-0	SMP	R/W	0h	SAMPLE This bitfield specify the number of sample time clocks (SCOMPx +1) for a conversion when SAMPLE_TIME in MEMCTLx is set to SCOMPx.

24.4.26 REFCFG Register (Offset = 111Ch) [Reset = 00000000h]

REFCFG is shown in Table 24-36.

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REFBUF configuration register

Table 24-36 REFCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R/W	0h
7-6	SPAR	R/W	0h	SPARE
5	PWRDN	R/W	0h	POWER DOWN Similar to ADC PWRDN control to save power in duty cycled mode of operation. 0 - AUTO, 1 - MANUAL In case of ADC, Sample time MMR needs to take into account time required to power on ADC. Since REF BUF may take time in us, recommendation is to use REFOKf th output oe buffer instead to start ADC conversion
4-3	IBPROG	R/W	0h	Configures REFBUF IBIAS current output value 0h = 1uA 1h = 0.5uA 2h = 2uA 3h = 0.67uA
2	IBEN	R/W	0h	REFBUF IBIAS enable 0h = Disable 1h = Enable
1	REFVSEL	R/W	0h	Configures REFBUF output voltage
0	REFEN	R/W	0h	REFBUF enable 0h = Disable 1h = Enable

24.4.27 WCLOW Register (Offset = 1148h) [Reset = 00000000h]

WCLOW is shown in Table 24-37.

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ULP_ADCHP Window Comparator Low Threshold 0 Register. The data format that is used to write and read WCLOW0 depends on the value of the DATAFORMAT bit in the CTL1 register. If DATAFORMAT = 0, the data is binary unsigned and right aligned. If DATAFORMAT = 1, the data is 2s complement and left aligned. Refer to the WCLOW0 bit-field description for details. CTL0.ENC must be set to 0 to write to this register. Design Note: To minimize cycles transforming data, the data written to WCLOW0 should be transformed into DATAFORMAT = 0 to match the MEMRESx register so a direct comparison can be done. Thus, there are extra cycles to write to this register but no penalty when a comparison is done.

Table 24-37 WCLOW Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R/W	0h
15-0	DATA	R/W	0h	Low threshold register 0. If DATAFORMAT = 0, unsigned binary format has to be used: The value based on the resolution has to be right aligned with the MSB on the left. For 14-bits and 12-bits resolution, unused bit have to be 0s Reset value is 0x0000. If DATAFORMAT = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 14-bits and 12-bits resolution, unused bit have to be 0s Reset value is 0x8000.

24.4.28 WCHI Register (Offset = 1150h) [Reset = 00000000h]

WCHI is shown in Table 24-38.

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WC HIGH ULP_ADCHP Window Comparator High Threshold 0 Register. The data format that is used to write and read WCHIGH0 depends on the value of the DATAFORMAT bit in the CTL1 register. If DATAFORMAT = 0, the data is binary unsigned and right aligned. If DATAFORMAT = 1, the data is 2s complement and left aligned. Refer to the WCHIGH0 bit-field description for details. CTL0.ENC must be set to 0 to write to this register. Design Note: To minimize cycles transforming data, the data written to WCHIGH0 should be transformed in DATAFORMAT = 0 to match the MEMRESx register so a direct comparison can be done. Thus, there are extra cycles to write to this register but no penalty when a comparison is done.

Table 24-38 WCHI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R/W	0h
15-0	DATA	R/W	0h	ULP_ADCHP Low threshold register 0. If DATAFORMAT = 0, unsigned binary format has to be used: The threshold value has to be right aligned, with the MSB on the left. Reset value are: 0xFFFF (16-bit), 0x3FFF (14-bit) or 0x0FFF (12-bit) If DATAFORMAT = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 14-bits and 12-bits resolution, unused bit have to be 0s Reset value are: 0x7FFF (16-bit), 0x7FFC (14-bit) or 0x7FF0 (12-bit)

24.4.29 FIFODATA Register (Offset = 1160h) [Reset = 00000000h]

FIFODATA is shown in Table 24-39.

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Virtual data register used to do a read from FIFO.

Table 24-39 FIFODATA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	DATA	R	0h	Read from data field returns the data from the top of FIFO.

24.4.30 ASCRES Register (Offset = 1170h) [Reset = 00000000h]

ASCRES is shown in Table 24-40.

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ASC result register.

Table 24-40 ASCRES Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	Data

24.4.31 MEMCTL_0 Register (Offset = 1180h) [Reset = 00000100h]

MEMCTL_0 is shown in Table 24-41.

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ULP_ADCHP Conversion Memory Control Register x (x=0 to 31) CTL0.ENC must be set to 0 to write to this register.

Table 24-41 MEMCTL_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	0h
30	MOD	R/W	0h	MODE Single vs Differential
29	FSR	R/W	0h	Full scale range of ADC limited to 1.8V or 3.3V '0' - 3.3V '1' - 1.8V * Exact range may be limited below the above mentioned voltages based on the design constraints
28	WINCOMP	R/W	0h	Window Comparator Enable. Select for the current conversion if the Window Comparator feature is used. 0h = Window Comparator is disabled. 1h = Window Comparator is enabled.
27-25	RESERVED	R/W	0h
24	TRIG	R/W	0h	TRIG. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence. 0h = Automatically step to next MEMCTL register. 1h = A valid trigger will step to next MEMCTL register.
23-17	RESERVED	R/W	0h
16	AVGEN	R/W	0h	Enable averaging. 0h (R/W) = Averaging disabled. 1h = Averaging enabled.
15-13	RESERVED	R/W	0h
12	STIME	R/W	0h	Selects the source of sample timer period. Can choose between SCOMP0 and SCOMP1. 0h = Select SCOMP0. 1h = Select SCOMP1.
11-10	RESERVED	R/W	0h
9-8	VRSEL	R/W	1h	Selects the combination of V(Rp) and V(Rn) sources. It is recommended to connect VeREFn0 to on-board ground when VeREFn is selected for V(Rn). Note: A value of 3 defaults to INTREF and value of 0 defaults to EXTREF. 1h = EXTREF pin reference. 2h = INTREF reference.
7-5	RESERVED	R/W	0h
4-0	CHANSEL	R/W	0h	ULP_ADCHP Input channel select. In single ended mode, any of the 32 channels can be selected. In differential mode, this field will select which EVEN channel to be connected to the vin+ input. The vin- is automatically set to the next ODD channel. (CHANSEL+1) 00h = If DIFIN= 0: Ain+ = A0. If DIFIN = 1: Ain+ = A0, Ain- = A1 01h = If DIFIN= 0: Ain+ = A1. If DIFIN = 1: Ain+ = A0, Ain- = A1 02h = If DIFIN = 0: Ain+ = A2. If DIFIN = 1: Ain+ = A2, Ain- = A3 03h = If DIFIN = 0: Ain+ = A3. If DIFIN = 1: Ain+ = A2, Ain- = A3 04h = If DIFIN = 0: Ain+ = A4. If DIFIN = 1: Ain+ = A4, Ain- = A5 05h = If DIFIN = 0: Ain+ = A5. If DIFIN = 1: Ain+ = A4, Ain- = A5 06h = If DIFIN = 0: Ain+ = A6. If DIFIN = 1: Ain+ = A6, Ain- = A7 07h = If DIFIN = 0: Ain+ = A7. If DIFIN = 1: Ain+ = A6, Ain- = A7 08h = If DIFIN = 0: Ain+ = A8. If DIFIN = 1: Ain+ = A8, Ain- = A9 09h = If DIFIN= 0: Ain+ = A9. If DIFIN = 1: Ain+ = A8, Ain- = A9 0Ah = If DIFIN= 0: Ain+ = A10. If DIFIN = 1: Ain+ = A10, Ain- = A11 0Bh = If DIFIN= 0: Ain+ = A11. If DIFIN = 1: Ain+ = A10, Ain- = A11 0Ch = If DIFIN= 0: Ain+ = A12. If DIFIN = 1: Ain+ = A12, Ain- = A13 0Dh = If DIFIN= 0: Ain+ = A13. If DIFIN = 1: Ain+ = A12, Ain- = A13 0Eh = If DIFIN= 0: Ain+ = A14. If DIFIN = 1: Ain+ = A14, Ain- = A15 0Fh = If DIFIN= 0: Ain+ = A15. If DIFIN = 1: Ain+ = A14, Ain- = A15 10h = If DIFIN= 0: Ain+ = A16. If DIFIN = 1: Ain+ = A16, Ain- = A17 11h = If DIFIN= 0: Ain+ = A17. If DIFIN = 1: Ain+ = A16, Ain- = A17 12h = If DIFIN= 0: Ain+ = A18. If DIFIN = 1: Ain+ = A18, Ain- = A19 13h = If DIFIN= 0: Ain+ = A19. If DIFIN = 1: Ain+ = A18, Ain- = A19 14h = If DIFIN= 0: Ain+ = A20. If DIFIN = 1: Ain+ = A20, Ain- = A21 15h = If DIFIN= 0: Ain+ = A21. If DIFIN = 1: Ain+ = A20, Ain- = A21 16h = If DIFIN= 0: Ain+ = A22. If DIFIN = 1: Ain+ = A22, Ain- = A23 17h = If DIFIN= 0: Ain+ = A23. If DIFIN = 1: Ain+ = A22, Ain- = A23 18h = If DIFIN= 0: Ain+ = A24. If DIFIN = 1: Ain+ = A24, Ain- = A25 19h = If DIFIN= 0: Ain+ = A25. If DIFIN = 1: Ain+ = A24, Ain- = A25 1Ah = If DIFIN= 0: Ain+ = A26. If DIFIN = 1: Ain+ = A26, Ain- = A27 1Bh = If DIFIN= 0: Ain+ = A27. If DIFIN = 1: Ain+ = A26, Ain- = A27 1Ch = If DIFIN= 0: Ain+ = A28. If DIFIN = 1: Ain+ = A28, Ain- = A29 1Dh = If DIFIN= 0: Ain+ = A29. If DIFIN = 1: Ain+ = A28, Ain- = A29 1Eh = If DIFIN= 0: Ain+ = A30. If DIFIN = 1: Ain+ = A30, Ain- = A31 1Fh = If DIFIN= 0: Ain+ = A31. If DIFIN = 1: Ain+ = A30, Ain- = A31

24.4.32 MEMCTL_1 Register (Offset = 1184h) [Reset = 00000100h]

MEMCTL_1 is shown in Table 24-42.

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ULP_ADCHP Conversion Memory Control Register x (x=0 to 31) CTL0.ENC must be set to 0 to write to this register.

Table 24-42 MEMCTL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	0h
30	MOD	R/W	0h	MODE Single vs Differential
29	FSR	R/W	0h	Full scale range of ADC limited to 1.8V or 3.3V '0' - 3.3V '1' - 1.8V * Exact range may be limited below the above mentioned voltages based on the design constraints
28	WINCOMP	R/W	0h	Window Comparator Enable. Select for the current conversion if the Window Comparator feature is used. 0h = Window Comparator is disabled. 1h = Window Comparator is enabled.
27-25	RESERVED	R/W	0h
24	TRIG	R/W	0h	TRIG. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence. 0h = Automatically step to next MEMCTL register. 1h = A valid trigger will step to next MEMCTL register.
23-17	RESERVED	R/W	0h
16	AVGEN	R/W	0h	Enable averaging. 0h (R/W) = Averaging disabled. 1h = Averaging enabled.
15-13	RESERVED	R/W	0h
12	STIME	R/W	0h	Selects the source of sample timer period. Can choose between SCOMP0 and SCOMP1. 0h = Select SCOMP0. 1h = Select SCOMP1.
11-10	RESERVED	R/W	0h
9-8	VRSEL	R/W	1h	Selects the combination of V(Rp) and V(Rn) sources. It is recommended to connect VeREFn0 to on-board ground when VeREFn is selected for V(Rn). Note: A value of 3 defaults to INTREF and value of 0 defaults to EXTREF. 1h = EXTREF pin reference. 2h = INTREF reference.
7-5	RESERVED	R/W	0h
4-0	CHANSEL	R/W	0h	ULP_ADCHP Input channel select. In single ended mode, any of the 32 channels can be selected. In differential mode, this field will select which EVEN channel to be connected to the vin+ input. The vin- is automatically set to the next ODD channel. (CHANSEL+1) 00h = If DIFIN= 0: Ain+ = A0. If DIFIN = 1: Ain+ = A0, Ain- = A1 01h = If DIFIN= 0: Ain+ = A1. If DIFIN = 1: Ain+ = A0, Ain- = A1 02h = If DIFIN = 0: Ain+ = A2. If DIFIN = 1: Ain+ = A2, Ain- = A3 03h = If DIFIN = 0: Ain+ = A3. If DIFIN = 1: Ain+ = A2, Ain- = A3 04h = If DIFIN = 0: Ain+ = A4. If DIFIN = 1: Ain+ = A4, Ain- = A5 05h = If DIFIN = 0: Ain+ = A5. If DIFIN = 1: Ain+ = A4, Ain- = A5 06h = If DIFIN = 0: Ain+ = A6. If DIFIN = 1: Ain+ = A6, Ain- = A7 07h = If DIFIN = 0: Ain+ = A7. If DIFIN = 1: Ain+ = A6, Ain- = A7 08h = If DIFIN = 0: Ain+ = A8. If DIFIN = 1: Ain+ = A8, Ain- = A9 09h = If DIFIN= 0: Ain+ = A9. If DIFIN = 1: Ain+ = A8, Ain- = A9 0Ah = If DIFIN= 0: Ain+ = A10. If DIFIN = 1: Ain+ = A10, Ain- = A11 0Bh = If DIFIN= 0: Ain+ = A11. If DIFIN = 1: Ain+ = A10, Ain- = A11 0Ch = If DIFIN= 0: Ain+ = A12. If DIFIN = 1: Ain+ = A12, Ain- = A13 0Dh = If DIFIN= 0: Ain+ = A13. If DIFIN = 1: Ain+ = A12, Ain- = A13 0Eh = If DIFIN= 0: Ain+ = A14. If DIFIN = 1: Ain+ = A14, Ain- = A15 0Fh = If DIFIN= 0: Ain+ = A15. If DIFIN = 1: Ain+ = A14, Ain- = A15 10h = If DIFIN= 0: Ain+ = A16. If DIFIN = 1: Ain+ = A16, Ain- = A17 11h = If DIFIN= 0: Ain+ = A17. If DIFIN = 1: Ain+ = A16, Ain- = A17 12h = If DIFIN= 0: Ain+ = A18. If DIFIN = 1: Ain+ = A18, Ain- = A19 13h = If DIFIN= 0: Ain+ = A19. If DIFIN = 1: Ain+ = A18, Ain- = A19 14h = If DIFIN= 0: Ain+ = A20. If DIFIN = 1: Ain+ = A20, Ain- = A21 15h = If DIFIN= 0: Ain+ = A21. If DIFIN = 1: Ain+ = A20, Ain- = A21 16h = If DIFIN= 0: Ain+ = A22. If DIFIN = 1: Ain+ = A22, Ain- = A23 17h = If DIFIN= 0: Ain+ = A23. If DIFIN = 1: Ain+ = A22, Ain- = A23 18h = If DIFIN= 0: Ain+ = A24. If DIFIN = 1: Ain+ = A24, Ain- = A25 19h = If DIFIN= 0: Ain+ = A25. If DIFIN = 1: Ain+ = A24, Ain- = A25 1Ah = If DIFIN= 0: Ain+ = A26. If DIFIN = 1: Ain+ = A26, Ain- = A27 1Bh = If DIFIN= 0: Ain+ = A27. If DIFIN = 1: Ain+ = A26, Ain- = A27 1Ch = If DIFIN= 0: Ain+ = A28. If DIFIN = 1: Ain+ = A28, Ain- = A29 1Dh = If DIFIN= 0: Ain+ = A29. If DIFIN = 1: Ain+ = A28, Ain- = A29 1Eh = If DIFIN= 0: Ain+ = A30. If DIFIN = 1: Ain+ = A30, Ain- = A31 1Fh = If DIFIN= 0: Ain+ = A31. If DIFIN = 1: Ain+ = A30, Ain- = A31

24.4.33 MEMCTL_2 Register (Offset = 1188h) [Reset = 00000100h]

MEMCTL_2 is shown in Table 24-43.

Return to the Summary Table.

ULP_ADCHP Conversion Memory Control Register x (x=0 to 31) CTL0.ENC must be set to 0 to write to this register.

Table 24-43 MEMCTL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	0h
30	MOD	R/W	0h	MODE Single vs Differential
29	FSR	R/W	0h	Full scale range of ADC limited to 1.8V or 3.3V '0' - 3.3V '1' - 1.8V * Exact range may be limited below the above mentioned voltages based on the design constraints
28	WINCOMP	R/W	0h	Window Comparator Enable. Select for the current conversion if the Window Comparator feature is used. 0h = Window Comparator is disabled. 1h = Window Comparator is enabled.
27-25	RESERVED	R/W	0h
24	TRIG	R/W	0h	TRIG. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence. 0h = Automatically step to next MEMCTL register. 1h = A valid trigger will step to next MEMCTL register.
23-17	RESERVED	R/W	0h
16	AVGEN	R/W	0h	Enable averaging. 0h (R/W) = Averaging disabled. 1h = Averaging enabled.
15-13	RESERVED	R/W	0h
12	STIME	R/W	0h	Selects the source of sample timer period. Can choose between SCOMP0 and SCOMP1. 0h = Select SCOMP0. 1h = Select SCOMP1.
11-10	RESERVED	R/W	0h
9-8	VRSEL	R/W	1h	Selects the combination of V(Rp) and V(Rn) sources. It is recommended to connect VeREFn0 to on-board ground when VeREFn is selected for V(Rn). Note: A value of 3 defaults to INTREF and value of 0 defaults to EXTREF. 1h = EXTREF pin reference. 2h = INTREF reference.
7-5	RESERVED	R/W	0h
4-0	CHANSEL	R/W	0h	ULP_ADCHP Input channel select. In single ended mode, any of the 32 channels can be selected. In differential mode, this field will select which EVEN channel to be connected to the vin+ input. The vin- is automatically set to the next ODD channel. (CHANSEL+1) 00h = If DIFIN= 0: Ain+ = A0. If DIFIN = 1: Ain+ = A0, Ain- = A1 01h = If DIFIN= 0: Ain+ = A1. If DIFIN = 1: Ain+ = A0, Ain- = A1 02h = If DIFIN = 0: Ain+ = A2. If DIFIN = 1: Ain+ = A2, Ain- = A3 03h = If DIFIN = 0: Ain+ = A3. If DIFIN = 1: Ain+ = A2, Ain- = A3 04h = If DIFIN = 0: Ain+ = A4. If DIFIN = 1: Ain+ = A4, Ain- = A5 05h = If DIFIN = 0: Ain+ = A5. If DIFIN = 1: Ain+ = A4, Ain- = A5 06h = If DIFIN = 0: Ain+ = A6. If DIFIN = 1: Ain+ = A6, Ain- = A7 07h = If DIFIN = 0: Ain+ = A7. If DIFIN = 1: Ain+ = A6, Ain- = A7 08h = If DIFIN = 0: Ain+ = A8. If DIFIN = 1: Ain+ = A8, Ain- = A9 09h = If DIFIN= 0: Ain+ = A9. If DIFIN = 1: Ain+ = A8, Ain- = A9 0Ah = If DIFIN= 0: Ain+ = A10. If DIFIN = 1: Ain+ = A10, Ain- = A11 0Bh = If DIFIN= 0: Ain+ = A11. If DIFIN = 1: Ain+ = A10, Ain- = A11 0Ch = If DIFIN= 0: Ain+ = A12. If DIFIN = 1: Ain+ = A12, Ain- = A13 0Dh = If DIFIN= 0: Ain+ = A13. If DIFIN = 1: Ain+ = A12, Ain- = A13 0Eh = If DIFIN= 0: Ain+ = A14. If DIFIN = 1: Ain+ = A14, Ain- = A15 0Fh = If DIFIN= 0: Ain+ = A15. If DIFIN = 1: Ain+ = A14, Ain- = A15 10h = If DIFIN= 0: Ain+ = A16. If DIFIN = 1: Ain+ = A16, Ain- = A17 11h = If DIFIN= 0: Ain+ = A17. If DIFIN = 1: Ain+ = A16, Ain- = A17 12h = If DIFIN= 0: Ain+ = A18. If DIFIN = 1: Ain+ = A18, Ain- = A19 13h = If DIFIN= 0: Ain+ = A19. If DIFIN = 1: Ain+ = A18, Ain- = A19 14h = If DIFIN= 0: Ain+ = A20. If DIFIN = 1: Ain+ = A20, Ain- = A21 15h = If DIFIN= 0: Ain+ = A21. If DIFIN = 1: Ain+ = A20, Ain- = A21 16h = If DIFIN= 0: Ain+ = A22. If DIFIN = 1: Ain+ = A22, Ain- = A23 17h = If DIFIN= 0: Ain+ = A23. If DIFIN = 1: Ain+ = A22, Ain- = A23 18h = If DIFIN= 0: Ain+ = A24. If DIFIN = 1: Ain+ = A24, Ain- = A25 19h = If DIFIN= 0: Ain+ = A25. If DIFIN = 1: Ain+ = A24, Ain- = A25 1Ah = If DIFIN= 0: Ain+ = A26. If DIFIN = 1: Ain+ = A26, Ain- = A27 1Bh = If DIFIN= 0: Ain+ = A27. If DIFIN = 1: Ain+ = A26, Ain- = A27 1Ch = If DIFIN= 0: Ain+ = A28. If DIFIN = 1: Ain+ = A28, Ain- = A29 1Dh = If DIFIN= 0: Ain+ = A29. If DIFIN = 1: Ain+ = A28, Ain- = A29 1Eh = If DIFIN= 0: Ain+ = A30. If DIFIN = 1: Ain+ = A30, Ain- = A31 1Fh = If DIFIN= 0: Ain+ = A31. If DIFIN = 1: Ain+ = A30, Ain- = A31

24.4.34 MEMCTL_3 Register (Offset = 118Ch) [Reset = 00000100h]

MEMCTL_3 is shown in Table 24-44.

Return to the Summary Table.

ULP_ADCHP Conversion Memory Control Register x (x=0 to 31) CTL0.ENC must be set to 0 to write to this register.

Table 24-44 MEMCTL_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	0h
30	MOD	R/W	0h	MODE Single vs Differential
29	FSR	R/W	0h	Full scale range of ADC limited to 1.8V or 3.3V '0' - 3.3V '1' - 1.8V * Exact range may be limited below the above mentioned voltages based on the design constraints
28	WINCOMP	R/W	0h	Window Comparator Enable. Select for the current conversion if the Window Comparator feature is used. 0h = Window Comparator is disabled. 1h = Window Comparator is enabled.
27-25	RESERVED	R/W	0h
24	TRIG	R/W	0h	TRIG. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence. 0h = Automatically step to next MEMCTL register. 1h = A valid trigger will step to next MEMCTL register.
23-17	RESERVED	R/W	0h
16	AVGEN	R/W	0h	Enable averaging. 0h (R/W) = Averaging disabled. 1h = Averaging enabled.
15-13	RESERVED	R/W	0h
12	STIME	R/W	0h	Selects the source of sample timer period. Can choose between SCOMP0 and SCOMP1. 0h = Select SCOMP0. 1h = Select SCOMP1.
11-10	RESERVED	R/W	0h
9-8	VRSEL	R/W	1h	Selects the combination of V(Rp) and V(Rn) sources. It is recommended to connect VeREFn0 to on-board ground when VeREFn is selected for V(Rn). Note: A value of 3 defaults to INTREF and value of 0 defaults to EXTREF. 1h = EXTREF pin reference. 2h = INTREF reference.
7-5	RESERVED	R/W	0h
4-0	CHANSEL	R/W	0h	ULP_ADCHP Input channel select. In single ended mode, any of the 32 channels can be selected. In differential mode, this field will select which EVEN channel to be connected to the vin+ input. The vin- is automatically set to the next ODD channel. (CHANSEL+1) 00h = If DIFIN= 0: Ain+ = A0. If DIFIN = 1: Ain+ = A0, Ain- = A1 01h = If DIFIN= 0: Ain+ = A1. If DIFIN = 1: Ain+ = A0, Ain- = A1 02h = If DIFIN = 0: Ain+ = A2. If DIFIN = 1: Ain+ = A2, Ain- = A3 03h = If DIFIN = 0: Ain+ = A3. If DIFIN = 1: Ain+ = A2, Ain- = A3 04h = If DIFIN = 0: Ain+ = A4. If DIFIN = 1: Ain+ = A4, Ain- = A5 05h = If DIFIN = 0: Ain+ = A5. If DIFIN = 1: Ain+ = A4, Ain- = A5 06h = If DIFIN = 0: Ain+ = A6. If DIFIN = 1: Ain+ = A6, Ain- = A7 07h = If DIFIN = 0: Ain+ = A7. If DIFIN = 1: Ain+ = A6, Ain- = A7 08h = If DIFIN = 0: Ain+ = A8. If DIFIN = 1: Ain+ = A8, Ain- = A9 09h = If DIFIN= 0: Ain+ = A9. If DIFIN = 1: Ain+ = A8, Ain- = A9 0Ah = If DIFIN= 0: Ain+ = A10. If DIFIN = 1: Ain+ = A10, Ain- = A11 0Bh = If DIFIN= 0: Ain+ = A11. If DIFIN = 1: Ain+ = A10, Ain- = A11 0Ch = If DIFIN= 0: Ain+ = A12. If DIFIN = 1: Ain+ = A12, Ain- = A13 0Dh = If DIFIN= 0: Ain+ = A13. If DIFIN = 1: Ain+ = A12, Ain- = A13 0Eh = If DIFIN= 0: Ain+ = A14. If DIFIN = 1: Ain+ = A14, Ain- = A15 0Fh = If DIFIN= 0: Ain+ = A15. If DIFIN = 1: Ain+ = A14, Ain- = A15 10h = If DIFIN= 0: Ain+ = A16. If DIFIN = 1: Ain+ = A16, Ain- = A17 11h = If DIFIN= 0: Ain+ = A17. If DIFIN = 1: Ain+ = A16, Ain- = A17 12h = If DIFIN= 0: Ain+ = A18. If DIFIN = 1: Ain+ = A18, Ain- = A19 13h = If DIFIN= 0: Ain+ = A19. If DIFIN = 1: Ain+ = A18, Ain- = A19 14h = If DIFIN= 0: Ain+ = A20. If DIFIN = 1: Ain+ = A20, Ain- = A21 15h = If DIFIN= 0: Ain+ = A21. If DIFIN = 1: Ain+ = A20, Ain- = A21 16h = If DIFIN= 0: Ain+ = A22. If DIFIN = 1: Ain+ = A22, Ain- = A23 17h = If DIFIN= 0: Ain+ = A23. If DIFIN = 1: Ain+ = A22, Ain- = A23 18h = If DIFIN= 0: Ain+ = A24. If DIFIN = 1: Ain+ = A24, Ain- = A25 19h = If DIFIN= 0: Ain+ = A25. If DIFIN = 1: Ain+ = A24, Ain- = A25 1Ah = If DIFIN= 0: Ain+ = A26. If DIFIN = 1: Ain+ = A26, Ain- = A27 1Bh = If DIFIN= 0: Ain+ = A27. If DIFIN = 1: Ain+ = A26, Ain- = A27 1Ch = If DIFIN= 0: Ain+ = A28. If DIFIN = 1: Ain+ = A28, Ain- = A29 1Dh = If DIFIN= 0: Ain+ = A29. If DIFIN = 1: Ain+ = A28, Ain- = A29 1Eh = If DIFIN= 0: Ain+ = A30. If DIFIN = 1: Ain+ = A30, Ain- = A31 1Fh = If DIFIN= 0: Ain+ = A31. If DIFIN = 1: Ain+ = A30, Ain- = A31

24.4.35 MEMCTL_4 Register (Offset = 1190h) [Reset = 00000100h]

MEMCTL_4 is shown in Table 24-45.

Return to the Summary Table.

ULP_ADCHP Conversion Memory Control Register x (x=0 to 31) CTL0.ENC must be set to 0 to write to this register.

Table 24-45 MEMCTL_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	0h
30	MOD	R/W	0h	MODE Single vs Differential
29	FSR	R/W	0h	Full scale range of ADC limited to 1.8V or 3.3V '0' - 3.3V '1' - 1.8V * Exact range may be limited below the above mentioned voltages based on the design constraints
28	WINCOMP	R/W	0h	Window Comparator Enable. Select for the current conversion if the Window Comparator feature is used. 0h = Window Comparator is disabled. 1h = Window Comparator is enabled.
27-25	RESERVED	R/W	0h
24	TRIG	R/W	0h	TRIG. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence. 0h = Automatically step to next MEMCTL register. 1h = A valid trigger will step to next MEMCTL register.
23-17	RESERVED	R/W	0h
16	AVGEN	R/W	0h	Enable averaging. 0h (R/W) = Averaging disabled. 1h = Averaging enabled.
15-13	RESERVED	R/W	0h
12	STIME	R/W	0h	Selects the source of sample timer period. Can choose between SCOMP0 and SCOMP1. 0h = Select SCOMP0. 1h = Select SCOMP1.
11-10	RESERVED	R/W	0h
9-8	VRSEL	R/W	1h	Selects the combination of V(Rp) and V(Rn) sources. It is recommended to connect VeREFn0 to on-board ground when VeREFn is selected for V(Rn). Note: A value of 3 defaults to INTREF and value of 0 defaults to EXTREF. 1h = EXTREF pin reference. 2h = INTREF reference.
7-5	RESERVED	R/W	0h
4-0	CHANSEL	R/W	0h	ULP_ADCHP Input channel select. In single ended mode, any of the 32 channels can be selected. In differential mode, this field will select which EVEN channel to be connected to the vin+ input. The vin- is automatically set to the next ODD channel. (CHANSEL+1) 00h = If DIFIN= 0: Ain+ = A0. If DIFIN = 1: Ain+ = A0, Ain- = A1 01h = If DIFIN= 0: Ain+ = A1. If DIFIN = 1: Ain+ = A0, Ain- = A1 02h = If DIFIN = 0: Ain+ = A2. If DIFIN = 1: Ain+ = A2, Ain- = A3 03h = If DIFIN = 0: Ain+ = A3. If DIFIN = 1: Ain+ = A2, Ain- = A3 04h = If DIFIN = 0: Ain+ = A4. If DIFIN = 1: Ain+ = A4, Ain- = A5 05h = If DIFIN = 0: Ain+ = A5. If DIFIN = 1: Ain+ = A4, Ain- = A5 06h = If DIFIN = 0: Ain+ = A6. If DIFIN = 1: Ain+ = A6, Ain- = A7 07h = If DIFIN = 0: Ain+ = A7. If DIFIN = 1: Ain+ = A6, Ain- = A7 08h = If DIFIN = 0: Ain+ = A8. If DIFIN = 1: Ain+ = A8, Ain- = A9 09h = If DIFIN= 0: Ain+ = A9. If DIFIN = 1: Ain+ = A8, Ain- = A9 0Ah = If DIFIN= 0: Ain+ = A10. If DIFIN = 1: Ain+ = A10, Ain- = A11 0Bh = If DIFIN= 0: Ain+ = A11. If DIFIN = 1: Ain+ = A10, Ain- = A11 0Ch = If DIFIN= 0: Ain+ = A12. If DIFIN = 1: Ain+ = A12, Ain- = A13 0Dh = If DIFIN= 0: Ain+ = A13. If DIFIN = 1: Ain+ = A12, Ain- = A13 0Eh = If DIFIN= 0: Ain+ = A14. If DIFIN = 1: Ain+ = A14, Ain- = A15 0Fh = If DIFIN= 0: Ain+ = A15. If DIFIN = 1: Ain+ = A14, Ain- = A15 10h = If DIFIN= 0: Ain+ = A16. If DIFIN = 1: Ain+ = A16, Ain- = A17 11h = If DIFIN= 0: Ain+ = A17. If DIFIN = 1: Ain+ = A16, Ain- = A17 12h = If DIFIN= 0: Ain+ = A18. If DIFIN = 1: Ain+ = A18, Ain- = A19 13h = If DIFIN= 0: Ain+ = A19. If DIFIN = 1: Ain+ = A18, Ain- = A19 14h = If DIFIN= 0: Ain+ = A20. If DIFIN = 1: Ain+ = A20, Ain- = A21 15h = If DIFIN= 0: Ain+ = A21. If DIFIN = 1: Ain+ = A20, Ain- = A21 16h = If DIFIN= 0: Ain+ = A22. If DIFIN = 1: Ain+ = A22, Ain- = A23 17h = If DIFIN= 0: Ain+ = A23. If DIFIN = 1: Ain+ = A22, Ain- = A23 18h = If DIFIN= 0: Ain+ = A24. If DIFIN = 1: Ain+ = A24, Ain- = A25 19h = If DIFIN= 0: Ain+ = A25. If DIFIN = 1: Ain+ = A24, Ain- = A25 1Ah = If DIFIN= 0: Ain+ = A26. If DIFIN = 1: Ain+ = A26, Ain- = A27 1Bh = If DIFIN= 0: Ain+ = A27. If DIFIN = 1: Ain+ = A26, Ain- = A27 1Ch = If DIFIN= 0: Ain+ = A28. If DIFIN = 1: Ain+ = A28, Ain- = A29 1Dh = If DIFIN= 0: Ain+ = A29. If DIFIN = 1: Ain+ = A28, Ain- = A29 1Eh = If DIFIN= 0: Ain+ = A30. If DIFIN = 1: Ain+ = A30, Ain- = A31 1Fh = If DIFIN= 0: Ain+ = A31. If DIFIN = 1: Ain+ = A30, Ain- = A31

24.4.36 MEMCTL_5 Register (Offset = 1194h) [Reset = 00000100h]

MEMCTL_5 is shown in Table 24-46.

Return to the Summary Table.

ULP_ADCHP Conversion Memory Control Register x (x=0 to 31) CTL0.ENC must be set to 0 to write to this register.

Table 24-46 MEMCTL_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	0h
30	MOD	R/W	0h	MODE Single vs Differential
29	FSR	R/W	0h	Full scale range of ADC limited to 1.8V or 3.3V '0' - 3.3V '1' - 1.8V * Exact range may be limited below the above mentioned voltages based on the design constraints
28	WINCOMP	R/W	0h	Window Comparator Enable. Select for the current conversion if the Window Comparator feature is used. 0h = Window Comparator is disabled. 1h = Window Comparator is enabled.
27-25	RESERVED	R/W	0h
24	TRIG	R/W	0h	TRIG. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence. 0h = Automatically step to next MEMCTL register. 1h = A valid trigger will step to next MEMCTL register.
23-17	RESERVED	R/W	0h
16	AVGEN	R/W	0h	Enable averaging. 0h (R/W) = Averaging disabled. 1h = Averaging enabled.
15-13	RESERVED	R/W	0h
12	STIME	R/W	0h	Selects the source of sample timer period. Can choose between SCOMP0 and SCOMP1. 0h = Select SCOMP0. 1h = Select SCOMP1.
11-10	RESERVED	R/W	0h
9-8	VRSEL	R/W	1h	Selects the combination of V(Rp) and V(Rn) sources. It is recommended to connect VeREFn0 to on-board ground when VeREFn is selected for V(Rn). Note: A value of 3 defaults to INTREF and value of 0 defaults to EXTREF. 1h = EXTREF pin reference. 2h = INTREF reference.
7-5	RESERVED	R/W	0h
4-0	CHANSEL	R/W	0h	ULP_ADCHP Input channel select. In single ended mode, any of the 32 channels can be selected. In differential mode, this field will select which EVEN channel to be connected to the vin+ input. The vin- is automatically set to the next ODD channel. (CHANSEL+1) 00h = If DIFIN= 0: Ain+ = A0. If DIFIN = 1: Ain+ = A0, Ain- = A1 01h = If DIFIN= 0: Ain+ = A1. If DIFIN = 1: Ain+ = A0, Ain- = A1 02h = If DIFIN = 0: Ain+ = A2. If DIFIN = 1: Ain+ = A2, Ain- = A3 03h = If DIFIN = 0: Ain+ = A3. If DIFIN = 1: Ain+ = A2, Ain- = A3 04h = If DIFIN = 0: Ain+ = A4. If DIFIN = 1: Ain+ = A4, Ain- = A5 05h = If DIFIN = 0: Ain+ = A5. If DIFIN = 1: Ain+ = A4, Ain- = A5 06h = If DIFIN = 0: Ain+ = A6. If DIFIN = 1: Ain+ = A6, Ain- = A7 07h = If DIFIN = 0: Ain+ = A7. If DIFIN = 1: Ain+ = A6, Ain- = A7 08h = If DIFIN = 0: Ain+ = A8. If DIFIN = 1: Ain+ = A8, Ain- = A9 09h = If DIFIN= 0: Ain+ = A9. If DIFIN = 1: Ain+ = A8, Ain- = A9 0Ah = If DIFIN= 0: Ain+ = A10. If DIFIN = 1: Ain+ = A10, Ain- = A11 0Bh = If DIFIN= 0: Ain+ = A11. If DIFIN = 1: Ain+ = A10, Ain- = A11 0Ch = If DIFIN= 0: Ain+ = A12. If DIFIN = 1: Ain+ = A12, Ain- = A13 0Dh = If DIFIN= 0: Ain+ = A13. If DIFIN = 1: Ain+ = A12, Ain- = A13 0Eh = If DIFIN= 0: Ain+ = A14. If DIFIN = 1: Ain+ = A14, Ain- = A15 0Fh = If DIFIN= 0: Ain+ = A15. If DIFIN = 1: Ain+ = A14, Ain- = A15 10h = If DIFIN= 0: Ain+ = A16. If DIFIN = 1: Ain+ = A16, Ain- = A17 11h = If DIFIN= 0: Ain+ = A17. If DIFIN = 1: Ain+ = A16, Ain- = A17 12h = If DIFIN= 0: Ain+ = A18. If DIFIN = 1: Ain+ = A18, Ain- = A19 13h = If DIFIN= 0: Ain+ = A19. If DIFIN = 1: Ain+ = A18, Ain- = A19 14h = If DIFIN= 0: Ain+ = A20. If DIFIN = 1: Ain+ = A20, Ain- = A21 15h = If DIFIN= 0: Ain+ = A21. If DIFIN = 1: Ain+ = A20, Ain- = A21 16h = If DIFIN= 0: Ain+ = A22. If DIFIN = 1: Ain+ = A22, Ain- = A23 17h = If DIFIN= 0: Ain+ = A23. If DIFIN = 1: Ain+ = A22, Ain- = A23 18h = If DIFIN= 0: Ain+ = A24. If DIFIN = 1: Ain+ = A24, Ain- = A25 19h = If DIFIN= 0: Ain+ = A25. If DIFIN = 1: Ain+ = A24, Ain- = A25 1Ah = If DIFIN= 0: Ain+ = A26. If DIFIN = 1: Ain+ = A26, Ain- = A27 1Bh = If DIFIN= 0: Ain+ = A27. If DIFIN = 1: Ain+ = A26, Ain- = A27 1Ch = If DIFIN= 0: Ain+ = A28. If DIFIN = 1: Ain+ = A28, Ain- = A29 1Dh = If DIFIN= 0: Ain+ = A29. If DIFIN = 1: Ain+ = A28, Ain- = A29 1Eh = If DIFIN= 0: Ain+ = A30. If DIFIN = 1: Ain+ = A30, Ain- = A31 1Fh = If DIFIN= 0: Ain+ = A31. If DIFIN = 1: Ain+ = A30, Ain- = A31

24.4.37 MEMRES_0 Register (Offset = 1280h) [Reset = 00000000h]

MEMRES_0 is shown in Table 24-47.

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Memory Results Register

Table 24-47 MEMRES_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.38 MEMRES_1 Register (Offset = 1284h) [Reset = 00000000h]

MEMRES_1 is shown in Table 24-48.

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Memory Results Register

Table 24-48 MEMRES_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.39 MEMRES_2 Register (Offset = 1288h) [Reset = 00000000h]

MEMRES_2 is shown in Table 24-49.

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Memory Results Register

Table 24-49 MEMRES_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.40 MEMRES_3 Register (Offset = 128Ch) [Reset = 00000000h]

MEMRES_3 is shown in Table 24-50.

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Memory Results Register

Table 24-50 MEMRES_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.41 MEMRES_4 Register (Offset = 1290h) [Reset = 00000000h]

MEMRES_4 is shown in Table 24-51.

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Memory Results Register

Table 24-51 MEMRES_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.42 MEMRES_5 Register (Offset = 1294h) [Reset = 00000000h]

MEMRES_5 is shown in Table 24-52.

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Memory Results Register

Table 24-52 MEMRES_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.43 MEMRES_6 Register (Offset = 1298h) [Reset = 00000000h]

MEMRES_6 is shown in Table 24-53.

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Memory Results Register

Table 24-53 MEMRES_6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.44 MEMRES_7 Register (Offset = 129Ch) [Reset = 00000000h]

MEMRES_7 is shown in Table 24-54.

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Memory Results Register

Table 24-54 MEMRES_7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.45 MEMRES_8 Register (Offset = 12A0h) [Reset = 00000000h]

MEMRES_8 is shown in Table 24-55.

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Memory Results Register

Table 24-55 MEMRES_8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.46 MEMRES_9 Register (Offset = 12A4h) [Reset = 00000000h]

MEMRES_9 is shown in Table 24-56.

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Memory Results Register

Table 24-56 MEMRES_9 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.47 MEMRES_10 Register (Offset = 12A8h) [Reset = 00000000h]

MEMRES_10 is shown in Table 24-57.

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Memory Results Register

Table 24-57 MEMRES_10 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.48 MEMRES_11 Register (Offset = 12ACh) [Reset = 00000000h]

MEMRES_11 is shown in Table 24-58.

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Memory Results Register

Table 24-58 MEMRES_11 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.49 MEMRES_12 Register (Offset = 12B0h) [Reset = 00000000h]

MEMRES_12 is shown in Table 24-59.

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Memory Results Register

Table 24-59 MEMRES_12 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.50 MEMRES_13 Register (Offset = 12B4h) [Reset = 00000000h]

MEMRES_13 is shown in Table 24-60.

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Memory Results Register

Table 24-60 MEMRES_13 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.51 MEMRES_14 Register (Offset = 12B8h) [Reset = 00000000h]

MEMRES_14 is shown in Table 24-61.

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Memory Results Register

Table 24-61 MEMRES_14 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.52 MEMRES_15 Register (Offset = 12BCh) [Reset = 00000000h]

MEMRES_15 is shown in Table 24-62.

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Memory Results Register

Table 24-62 MEMRES_15 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	DATA	R	0h	MEMRESx result register. If DATAFORMAT = 0, unsigned binary: The conversion results are right aligned. In 14 and 12 bit mode, the unused MSB bits are forced to 0. If DATAFORMAT = 1, 2s-complement format: The conversion results are left aligned. In 14 and 12 bit mode, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. Reading this register clears the corresponding bit in RIS.

24.4.53 STA Register (Offset = 1340h) [Reset = 00000000h]

STA is shown in Table 24-63.

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STATUS ULP_ADCHP Status Register 0

Table 24-63 STA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h
2	ASCACT	R	0h	ASC active 0h = Idle or done 1h = ASC active
1	REFBUFRDY	R	0h	Indicates reference buffer is powered up. 0h = REFBUF not ready. 1h = REFBUF is ready.
0	BUSY	R	0h	ULP_ADCHP busy. This bit indicates that an active sample or conversion operation is in progress. 0h = No sampling or conversion in progress. 1h = A sample or conversion is in progress.

24.4.54 CONVCTL Register (Offset = 1F14h) [Reset = 00000000h]

CONVCTL is shown in Table 24-64.

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Conversion Control

Table 24-64 CONVCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R/W	0h
18	CONVCLKEN	R/W	0h	CONV CLK ICG EN should be enabled after selecting CONV CLK
17-16	CONCLKSEL	R/W	0h	CONVERSION CLOCK SELECTOR ADC functional clock selection 0x0 - (Reset/Default) CLK_GATE 0x1 - SOC_CLK 0x2 - HFXT 0x3 - SOC_PLL_CLK_DIV note: not glitch free, therefore ICG should be enabled after selecting the right clk
15	OV	R/W	0h	OVERRIDE 1 : Override, 0 : Use LUT values LUT is mentioned since the proposal was to pick up values automatically based on Internal vs External reference
14-9	RESERVED	R/W	0h
8-5	HOLD	R/W	0h	000 : 1 Clock delay, ...., 111 : 8 Clock delay bit[3] - don't care and not used
4-3	PREAMP	R/W	0h	00 : 1 Clock delay, ..., 11 : 4 Clock delay
2-0	DAC	R/W	0h	000 : 1 Clock delay, ...., 111 : 8 Clock delay

24.4.55 CTRL Register (Offset = 1F18h) [Reset = 00000000h]

CTRL is shown in Table 24-65.

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Table 24-65 CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R/W	0h
16-9	FSBIT1	R/W	20h	FUSE BITS 1 values for fuse OV
8-0	FSBIT0	R/W	0h	FUSE BITS 0 values for fuse OV

24.4.56 MODCTL Register (Offset = 1F1Ch) [Reset = 00000000h]

MODCTL is shown in Table 24-66.

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MODE CONTROL

Table 24-66 MODCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R/W	0h
1	SCASEL	R/W	0h	SCALE SELECT 0 --> Normal output 1 --> scale 0-4223 in 0-4095 (efectively supporting 0-3.3V in 12 bit space)
0	VREFRAN	R/W	0h	VOLTAGE REFERENCE RANGE 0 --> 0 - 4095 in 0 - 3.2V 1 --> 0 - 4095 in 0.1 to 3.3V Only in Single Ended mode

24.4.57 INTCHCTL Register (Offset = 1F20h) [Reset = 00000000h]

INTCHCTL is shown in Table 24-67.

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INTERNAL CHANNEL CONTROL

Table 24-67 INTCHCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R/W	0h
1	RLOV	R/W	0h	RLADDER OVERRIDE Override Enable/Disable control for R-ladder inside RFCIO. This provides divided voltage to ADC by limiting the max. voltage. Default : 0 use value driven by ADC FSM
0	RLVAL	R/W	0h	RLADDER VALUE 0 --> 0 - 4095 in 0 - 3.2V 1 --> 0 - 4095 in 0.1 to 3.3V Only in Single Ended mode

24.4.58 CLKCFG Register (Offset = 2000h) [Reset = 00000000h]

CLKCFG is shown in Table 24-68.

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ADC CLK CONFIG

Table 24-68 CLKCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R/W	0h
0	EN	R/W	0h	ENABLE enables system clk to work with ADC '1' - enable adc clk '0' - disable adc clk