SWRU626 December   2025 CC3501E , CC3551E

 

  1.   1
  2. 1 Read This First
    1. 1.1 About This Manual
    2. 1.2 Register, Field, and Bit Calls
    3.     Trademarks
  3. 2 Architecture Overview
    1. 2.1  Target Applications
    2. 2.2  Introduction
    3. 2.3  Internal System Diagram
    4. 2.4  Arm Cortex M33
      1. 2.4.1 Processor Core
      2. 2.4.2 SysTick Timer
      3. 2.4.3 Nested Vectored Interrupt Controller
      4. 2.4.4 System Control Block (SCB)
      5. 2.4.5 TI AI instruction extensions
    5. 2.5  Power Management
      1. 2.5.1 VDD_MAIN
      2. 2.5.2 VDD_IO
      3. 2.5.3 VDDSF
      4. 2.5.4 VDD_PA
    6. 2.6  Debug Subsystem (DEBUGSS)
    7. 2.7  Memory Subsystem (MEMSS)
      1. 2.7.1 External Memory Interface
    8. 2.8  Hardware Security Module
    9. 2.9  General Purpose Timers (GPT)
    10. 2.10 Real Time Clock (RTC)
    11. 2.11 Direct Memory Access
    12. 2.12 GPIOs
    13. 2.13 Communication Peripherals
      1. 2.13.1 UART
      2. 2.13.2 I2C
      3. 2.13.3 SPI
      4. 2.13.4 I2S
      5. 2.13.5 SDMMC
      6. 2.13.6 SDIO
      7. 2.13.7 CAN
      8. 2.13.8 ADC
  4. 3  Arm Cortex-M33 Processor
    1. 3.1 Arm Cortex-M33 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 M33 instantiation parameters
    4. 3.4 Arm Cortex-M33 System Peripheral Details
      1. 3.4.1 Floating Point Unit (FPU)
      2. 3.4.2 Memory Protection Unit (MPU)
      3. 3.4.3 Digital Signal Processing (DSP)
      4. 3.4.4 Security Attribution Unit (SAU)
      5. 3.4.5 System Timer
      6. 3.4.6 Nested Vectored Interrupt Controller
      7. 3.4.7 System Control Block
      8. 3.4.8 System Control Space
    5. 3.5 CPU Sub-System Peripheral Details
      1. 3.5.1 Trace Port Interface Unit (TPIU)
      2. 3.5.2 DAP Bridge and Debug Authentication
      3. 3.5.3 Implementation Defined Attribution Unit (IDAU)
    6. 3.6 Programming Model
      1. 3.6.1 Modes of operation and execution
        1. 3.6.1.1 Security states
        2. 3.6.1.2 Operating modes
        3. 3.6.1.3 Operating states
        4. 3.6.1.4 Privileged access and unprivileged user access
      2. 3.6.2 Instruction set summary
      3. 3.6.3 Memory model
        1. 3.6.3.1 Private Peripheral Bus
        2. 3.6.3.2 Unaligned accesses
      4. 3.6.4 Processor core registers summary
      5. 3.6.5 Exceptions
        1. 3.6.5.1 Exception handling and prioritization
    7. 3.7 TrustZone-M
      1. 3.7.1 Overview
      2. 3.7.2 M33 Configuration
      3. 3.7.3 Description of elements
        1. 3.7.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 3.7.3.1.1 Expected use
    8. 3.8 CC35xx Host MCU Registers
      1. 3.8.1 HOSTMCU_AON Registers
      2. 3.8.2 HOST_MCU Registers
      3. 3.8.3 HOST_MCU_SEC Registers
    9. 3.9 Arm® Cortex®-M33 Registers
      1. 3.9.1  CPU_ROM_TABLE Registers
      2. 3.9.2  TPIU Registers
      3. 3.9.3  DCB Registers
      4. 3.9.4  DIB Registers
      5. 3.9.5  DWT Registers
      6. 3.9.6  FPB Registers
      7. 3.9.7  FPE Registers
      8. 3.9.8  ICB Registers
      9. 3.9.9  ITM Registers
      10. 3.9.10 MPU Registers
      11. 3.9.11 NVIC Registers
      12. 3.9.12 SAU Registers
      13. 3.9.13 SCB Registers
      14. 3.9.14 SYSTIMER Registers
      15. 3.9.15 SYSTICK Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation to HardFault
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Manager
      1. 5.4.1 Introduction
      2. 5.4.2 Interrupts List
      3. 5.4.3 Wakeup Sources
      4. 5.4.4 Shared Peripherals MUX Selector
        1. 5.4.4.1 ADC HW Event Selector Mux
        2. 5.4.4.2 I2S HW Event Selector Mux
        3. 5.4.4.3 PDM HW Event Selector Mux
      5. 5.4.5 Timers MUX Selector Mux
        1. 5.4.5.1 SysTimer0 HW Event Selector Mux
        2. 5.4.5.2 SysTimer1 HW Event Selector Mux
        3. 5.4.5.3 RTC HW Event Selector Mux
      6. 5.4.6 GPTIMERs MUX Selector Mux
        1. 5.4.6.1 GPTIMER0 HW Event Selector Mux
        2. 5.4.6.2 GPTIMER1 HW Event Selector Mux
    5. 5.5 SOC_IC Registers
    6. 5.6 SOC_AON Registers
    7. 5.7 SOC_AAON Registers
  7. 6 Debug Subsystem (DEBUGSS)
    1. 6.1 Introduction
    2. 6.2 Block Diagram
    3. 6.3 Overview
    4. 6.4 Physical Interface
    5. 6.5 Debug Access Ports
    6. 6.6 Debug Features
      1. 6.6.1 Processor Debug
      2. 6.6.2 Breakpoint Unit (BPU)
      3. 6.6.3 Peripheral Debug
    7. 6.7 Behavior in Low Power Modes
    8. 6.8 Debug Access Control
    9. 6.9 SOC_DEBUGSS Registers
  8. 7 Power, Reset, Clock Management
    1. 7.1 Power Management
      1. 7.1.1 Power Supply System
        1. 7.1.1.1 VDD_MAIN
        2. 7.1.1.2 VIO
        3. 7.1.1.3 VDDSF
        4. 7.1.1.4 VPA
      2. 7.1.2 Power States
      3. 7.1.3 Power Domains
      4. 7.1.4 Brownout (BOR)
      5. 7.1.5 Boot Sequence
    2. 7.2 Reset
      1. 7.2.1 Reset Cause
      2. 7.2.2 Watchdog Timer (WDT)
    3. 7.3 Clocks
      1. 7.3.1 Fast Clock
      2. 7.3.2 Slow Clock
        1. 7.3.2.1 Slow Clock Overview
        2. 7.3.2.2 Slow Clock Tree
        3. 7.3.2.3 Slow Clock Boot Process
    4. 7.4 PRCM_AON Registers
    5. 7.5 PRCM_SCRATCHPAD Registers
  9. 8 Memory Subsystem (MEMSS)
    1. 8.1  Introduction
    2. 8.2  SRAM
    3. 8.3  D-Cache
    4. 8.4  Flash
    5. 8.5  PSRAM
    6. 8.6  XiP Memory Access
      1. 8.6.1 OTFDE
      2. 8.6.2 xSPI
      3. 8.6.3 Topology
      4. 8.6.4 µDMA
      5. 8.6.5 Arbiter
    7. 8.7  ICACHE Registers
    8. 8.8  DCACHE Registers
    9. 8.9  OSPI Registers
    10. 8.10 HOST_XIP Registers
  10. 9 Hardware Security Module (HSM)
    1. 9.1 Introduction
    2. 9.2 Overview
    3. 9.3 Mailbox and Register Access Firewall
    4. 9.4 DMA Firewall
    5. 9.5 HSM Key Storage
    6. 9.6 HSM Registers
    7. 9.7 HSM_NON_SEC Registers
    8. 9.8 HSM_SEC Registers
  11. 10Device Boot and Bootloader
    1. 10.1 CC35xx Boot Concept
    2. 10.2 Features
    3. 10.3 Vendor Images Format and Processing
      1. 10.3.1 External Flash Arrangement
      2. 10.3.2 Vendor Images Format
    4. 10.4 Boot Flows
      1. 10.4.1 Application Execution Boot Flow
      2. 10.4.2 Activation Flow
      3. 10.4.3 Initial Programming Flow
      4. 10.4.4 Reprogramming Flow
      5. 10.4.5 Wireless Connectivity Testing Tool Flow
    5. 10.5 Chain of Trust
  12. 11Direct Memory Access (DMA)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Channels Assignment
      2. 11.3.2 Transfer Types
      3. 11.3.3 Addressing Modes
      4. 11.3.4 Transfer Modes
      5. 11.3.5 DMA Aligner Support
      6. 11.3.6 Initiating DMA Transfers
      7. 11.3.7 Stopping DMA Transfers
      8. 11.3.8 Channel Priorities
      9. 11.3.9 DMA Interrupts
    4. 11.4 HOST_DMA Registers
  13. 12One Time Programming (OTP)
  14. 13General Purpose Timers (GPT)
    1. 13.1 Overview
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1  Prescaler
      2. 13.3.2  Counter
      3. 13.3.3  Target
      4. 13.3.4  Channel Input Logic
      5. 13.3.5  Channel Output Logic
      6. 13.3.6  Channel Actions
        1. 13.3.6.1 Period and Pulse Width Measurement
        2. 13.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 13.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 13.3.7  Channel Capture Configuration
      8. 13.3.8  Channel Filters
        1. 13.3.8.1 Setting up the Channel Filters
      9. 13.3.9  Synchronize Multiple GPTimers
      10. 13.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 13.4 Timer Modes
      1. 13.4.1 Quadrature Decoder
      2. 13.4.2 DMA
      3. 13.4.3 IR Generation
      4. 13.4.4 Fault and Park
      5. 13.4.5 Dead-Band
      6. 13.4.6 Dead-Band, Fault and Park
      7. 13.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 13.5 GPTIMER Registers
  15. 14System Timer (SysTimer)
    1. 14.1 Overview
    2. 14.2 Block Diagram
    3. 14.3 Functional Description
      1. 14.3.1 Common Channel Features
        1. 14.3.1.1 Compare Mode
        2. 14.3.1.2 Capture Mode
        3. 14.3.1.3 Additional Channel Arming Methods
      2. 14.3.2 Interrupts and Events
    4. 14.4 SYSRESOURCES Registers
    5. 14.5 SYSTIM Registers
  16. 15Real-Time Clock (RTC)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Interrupts and Events
      1. 15.3.1 Input Event
      2. 15.3.2 Output Event
      3. 15.3.3 Arming and Disarming Channels
    4. 15.4 CAPTURE and COMPARE Configurations
      1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
    5. 15.5 RTC Registers
  17. 16General Purpose Input/Output (GPIOs)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 I/O Mapping and Configuration
      1. 16.3.1 Basic I/O Mapping
      2. 16.3.2 Pin Mapping
    4. 16.4 Edge Detection
    5. 16.5 GPIO
    6. 16.6 I/O Pins
    7. 16.7 Unused Pins
    8. 16.8 IOMUX Registers
  18. 17Universal Asynchronous Receivers/Transmitters (UART)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 UART Functional Description
      1. 17.3.1 Transmit and Receive Logic
      2. 17.3.2 Baud Rate Generation
      3. 17.3.3 FIFO Operation
        1. 17.3.3.1 FIFO Remapping
      4. 17.3.4 Data Transmission
      5. 17.3.5 Flow Control
      6. 17.3.6 IrDA Encoding and Decoding
      7. 17.3.7 Interrupts
      8. 17.3.8 Loopback Operation
    4. 17.4 UART-LIN Specification
      1. 17.4.1 Break transmission in UART mode
      2. 17.4.2 Break reception in UART mode
      3. 17.4.3 Break/Synch transmission in LIN mode
      4. 17.4.4 Break/Synch reception in LIN mode
      5. 17.4.5 Dormant mode operation
      6. 17.4.6 Event signal generation
      7. 17.4.7 Event signal detection when device is in active/idle modes
      8. 17.4.8 Event signal detection when device is in sleep mode
    5. 17.5 Interface to Host DMA
    6. 17.6 Initialization and Configuration
    7. 17.7 UART Registers
  19. 18Serial Peripheral Interface (SPI)
    1. 18.1 Overview
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Signal Description
    3. 18.3 Functional Description
      1. 18.3.1  Clock Control
      2. 18.3.2  FIFO Operation
        1. 18.3.2.1 Transmit FIFO
        2. 18.3.2.2 Repeated Transmit Operation
        3. 18.3.2.3 Receive FIFO
        4. 18.3.2.4 FIFO Flush
      3. 18.3.3  Interrupts
      4. 18.3.4  Data Format
      5. 18.3.5  Delayed Data Sampling
      6. 18.3.6  Chip Select Control
      7. 18.3.7  Command Data Control
      8. 18.3.8  Protocol Descriptions
        1. 18.3.8.1 Motorola SPI Frame Format
        2. 18.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 18.3.8.3 MICROWIRE Frame Format
      9. 18.3.9  CRC Configuration
      10. 18.3.10 Auto CRC Functionality
      11. 18.3.11 SPI Status
      12. 18.3.12 Debug Halt
    4. 18.4 Host DMA Operation
    5. 18.5 Initialization and Configuration
    6. 18.6 SPI Registers
  20. 19Inter-Integrated Circuit (I2C) Interface
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Clock Control
        1. 19.3.1.1 Internal Clock
        2. 19.3.1.2 External Clock
      2. 19.3.2 General Architecture
        1. 19.3.2.1  Start and Stop Conditions
        2. 19.3.2.2  Data Format with 7-Bit Address
        3. 19.3.2.3  Data Format with 10-Bit Addressing
          1. 19.3.2.3.1 Additional 10-Bit Scenarios
        4. 19.3.2.4  Acknowledge
        5. 19.3.2.5  Repeated Start
        6. 19.3.2.6  Clock Stretching
        7. 19.3.2.7  Arbitration
        8. 19.3.2.8  Multi-Controller mode
        9. 19.3.2.9  Glitch Suppression
        10. 19.3.2.10 FIFO Operation
        11. 19.3.2.11 Burst Mode Operation
        12. 19.3.2.12 DMA Operation
        13. 19.3.2.13 Flush Stale Tx Data in Target Mode
          1. 19.3.2.13.1 Recommended Sequence
        14. 19.3.2.14 SMBUS 3.0 Support
          1. 19.3.2.14.1 Quick Command
          2. 19.3.2.14.2 Acknowledge Control
          3. 19.3.2.14.3 Alert Response protocol
          4. 19.3.2.14.4 Address Resolution Protocol
          5. 19.3.2.14.5 Enhanced Acknowledge Control
    4. 19.4 Initialization and Configuration
    5. 19.5 Interrupts
    6. 19.6 I2C Registers
  21. 20Secure Digital Multimedia Card (SDMMC)
    1. 20.1 Introduction
      1. 20.1.1 SDMMC Features
      2. 20.1.2 Integration
    2. 20.2 Functional Description
      1. 20.2.1  SDMMC Functional Modes
        1. 20.2.1.1 SDMMC Connected to an SD Card
        2. 20.2.1.2 Protocol and Data Format
          1. 20.2.1.2.1 Protocol
          2. 20.2.1.2.2 Data Format
      2. 20.2.2  SD Card Feedback
      3. 20.2.3  Resets
        1. 20.2.3.1 Hardware Reset
        2. 20.2.3.2 Software Reset
      4. 20.2.4  Interrupt Requests
        1. 20.2.4.1 Interrupt-Driven Operation
        2. 20.2.4.2 Polling
      5. 20.2.5  DMA Modes
        1. 20.2.5.1 DMA Peripheral Mode Operations
          1. 20.2.5.1.1 DMA Receive Mode
          2. 20.2.5.1.2 DMA Transmit Mode
      6. 20.2.6  Buffer Management
        1. 20.2.6.1 Data Buffer
          1. 20.2.6.1.1 Memory Size and Block Length
          2. 20.2.6.1.2 Data Buffer Status
      7. 20.2.7  Transfer Process
        1. 20.2.7.1 Different Types of Commands
        2. 20.2.7.2 Different Types of Responses
      8. 20.2.8  Transfer or Command Status and Error Reporting
        1. 20.2.8.1 Busy Timeout for R1b, R5b Response Type
        2. 20.2.8.2 Busy Timeout After Write CRC Status
        3. 20.2.8.3 Write CRC Status Timeout
        4. 20.2.8.4 Read Data Timeout
      9. 20.2.9  Auto Command 12 Timings
        1. 20.2.9.1 Auto Command 12 Timings During Write Transfer
        2. 20.2.9.2 Auto Command 12 Timings During Read Transfer
      10. 20.2.10 Transfer Stop
      11. 20.2.11 Output Signals Generation
        1. 20.2.11.1 Generation on Falling Edge of SDMMC Clock
        2. 20.2.11.2 Generation on Rising Edge of SDMMC Clock
      12. 20.2.12 Test Registers
      13. 20.2.13 SDMMC Hardware Status Features
    3. 20.3 Low-Level Programming Models
      1. 20.3.1 SDMMC Initialization Flow
        1. 20.3.1.1 Enable OCP and CLKADPI Clocks
        2. 20.3.1.2 SD Soft Reset Flow
        3. 20.3.1.3 Set SD Default Capabilities
        4. 20.3.1.4 SDMMC Host and Bus Configuration
      2. 20.3.2 Operational Modes Configuration
        1. 20.3.2.1 Basic Operations for SDMMC
        2. 20.3.2.2 Card Detection, Identification, and Selection
    4. 20.4 SDMMC Registers
  22. 21Secure Digital Input/Output (SDIO)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 SDIO Interface Description
      2. 21.3.2 Protocol and Data Format
      3. 21.3.3 I/O Read/Write Command
        1. 21.3.3.1 IO_WR_DIRECT Command (CMD52)
        2. 21.3.3.2 IO_WR_EXTENDED Command (CMD53)
      4. 21.3.4 Reset
      5. 21.3.5 FIFO Operation
        1. 21.3.5.1 Rx FIFO (For Host Write)
        2. 21.3.5.2 Tx FIFO (For Host Read)
      6. 21.3.6 Interrupt Request
        1. 21.3.6.1 External Host IRQ
        2. 21.3.6.2 M33 IRQ
      7. 21.3.7 Transaction Details
        1. 21.3.7.1 Host write to SDIO IP (Rx FIFO)
          1. 21.3.7.1.1 Host write to SDIO IP (Rx FIFO) – Long SW latency case
          2. 21.3.7.1.2 Host write to SDIO IP (Rx FIFO) – CRC Error Case
        2. 21.3.7.2 Host reads from SDIO (TX buffer)
    4. 21.4 SDIO_CORE Registers
    5. 21.5 SDIO_CARD_FN1 Registers
  23. 22Inter-Integrated Circuit Sound (I2S)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  Signal Descriptions
    4. 22.4  Functional Description
      1. 22.4.1 Pin Configuration
      2. 22.4.2 Serial Format Configuration
        1. 22.4.2.1 Register Configuration
      3. 22.4.3 Left-Justified (LJF)
        1. 22.4.3.1 Register Configuration
      4. 22.4.4 Right-Justified (RJF)
        1. 22.4.4.1 Register Configuration
      5. 22.4.5 DSP
        1. 22.4.5.1 Register Configuration
      6. 22.4.6 Clock Configuration
    5. 22.5  Memory Interface
      1. 22.5.1 Sample Word Length
      2. 22.5.2 Padding Mechanism
      3. 22.5.3 Channel Mapping
      4. 22.5.4 Sample Storage in Memory
      5. 22.5.5 DMA Operation
        1. 22.5.5.1 Start-Up
        2. 22.5.5.2 Operation
        3. 22.5.5.3 Shutdown
    6. 22.6  Samplestamp Generator
      1. 22.6.1 Samplestamp Counters
      2. 22.6.2 Start-Up Triggers
      3. 22.6.3 Samplestamp Capture
      4. 22.6.4 Achieving constant audio latency
    7. 22.7  Error Detection
    8. 22.8  Usage
      1. 22.8.1 Start-Up Sequence
      2. 22.8.2 Shutdown Sequence
    9. 22.9  I2S Configuration Guideline
    10. 22.10 I2S Registers
  24. 23Pulse Density Modulation (PDM)
    1. 23.1  Introduction
    2. 23.2  Block Diagram
    3. 23.3  Input Selection
      1. 23.3.1 PDM Data Mode
      2. 23.3.2 Manchester Input Mode
    4. 23.4  CIC Filter
      1. 23.4.1 Filter Design
      2. 23.4.2 Digital Filter Output
      3. 23.4.3 Offset Binary Mode
      4. 23.4.4 Twos-Complement Mode
    5. 23.5  FIFO Organization in Different Modes
      1. 23.5.1 Single Mono Microphone Configuration
        1. 23.5.1.1 24-bit Sample Size
          1. 23.5.1.1.1 32-bit Data Read
        2. 23.5.1.2 16-bit Sample Size
          1. 23.5.1.2.1 32-bit Data Read
          2. 23.5.1.2.2 16-bit Data Read
        3. 23.5.1.3 8-bit Sample Size
          1. 23.5.1.3.1 32-bit Data Read
          2. 23.5.1.3.2 16-bit Data Read
          3. 23.5.1.3.3 8-bit Data Read
      2. 23.5.2 Stereo or Dual Mono Microphone Configuration
        1. 23.5.2.1 24-bit Sample Size
          1. 23.5.2.1.1 32-bit Data Read
        2. 23.5.2.2 16-bit Sample Size
          1. 23.5.2.2.1 32-bit Data Read
          2. 23.5.2.2.2 16-bit Data Read
        3. 23.5.2.3 8-bit Sample Size
          1. 23.5.2.3.1 32-bit Data Read
          2. 23.5.2.3.2 16-bit Data Read
          3. 23.5.2.3.3 8-bit Data Read
      3. 23.5.3 FIFO Threshold Setting
      4. 23.5.4 Reset FIFO
    6. 23.6  Automatic Gain Control (AGC)
      1. 23.6.1 Operation in 2's Complement Format
      2. 23.6.2 Operation in Offset Binary Format
    7. 23.7  Interrupts
    8. 23.8  Clock Select and Control
    9. 23.9  DMA Operation
    10. 23.10 Samplestamp Generator
      1. 23.10.1 Samplestamp Counters
      2. 23.10.2 Start-Up Triggers
      3. 23.10.3 Samplestamp Capture
      4. 23.10.4 Achieving Constant Audio Latency
    11. 23.11 Debug‑Mode Flag Behavior
    12. 23.12 Software Guidelines
    13. 23.13 PDM Registers
  25. 24Analog to Digital Converter (ADC)
    1. 24.1 Overview
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1  ADC Core
      2. 24.3.2  Voltage Reference Options
      3. 24.3.3  Internal Channels
      4. 24.3.4  Resolution Modes
      5. 24.3.5  ADC Clocking
      6. 24.3.6  Power Down Behavior
      7. 24.3.7  Sampling Trigger Sources and Sampling Modes
        1. 24.3.7.1 AUTO Sampling Mode
        2. 24.3.7.2 MANUAL Sampling Mode
      8. 24.3.8  Sampling Period
      9. 24.3.9  Conversion Modes
      10. 24.3.10 ADC Data Format
      11. 24.3.11 Status Register
      12. 24.3.12 ADC Events
        1. 24.3.12.1 Generic Event Publishers (INT_EVENT0 & INT_EVENT1)
        2. 24.3.12.2 DMA Trigger Event Publisher (INT_EVENT2)
        3. 24.3.12.3 Generic Event Subscriber
      13. 24.3.13 Advanced Features
        1. 24.3.13.1 Window Comparator
        2. 24.3.13.2 DMA & FIFO Operation
          1. 24.3.13.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
          2. 24.3.13.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
          3. 24.3.13.2.3 DMA/CPU Operation Summary Matrix
        3. 24.3.13.3 Ad-hoc Single Conversion
    4. 24.4 ADC Registers
  26. 25Controller Area Network (CAN)
    1. 25.1 Introduction
    2. 25.2 Functions
    3. 25.3 DCAN Subsystem
    4. 25.4 DCAN Functional Description
      1. 25.4.1 Operating Modes
        1. 25.4.1.1 Software Initialization
        2. 25.4.1.2 Normal Operation
        3. 25.4.1.3 Restricted Operation Mode
        4. 25.4.1.4 Bus Monitoring Mode
        5. 25.4.1.5 Disabled Automatic Retransmission
          1. 25.4.1.5.1 Frame Transmission in DAR Mode
        6. 25.4.1.6 Power Down (Sleep Mode)
          1. 25.4.1.6.1 DCAN clock stop and wake operations
          2. 25.4.1.6.2 DCAN debug suspend operation
        7. 25.4.1.7 Test Modes
          1. 25.4.1.7.1 External Loop Back Mode
          2. 25.4.1.7.2 Internal Loop Back Mode
      2. 25.4.2 Timestamp Generation
        1. 25.4.2.1 Block Diagram
      3. 25.4.3 Timeout Counter
      4. 25.4.4 Rx Handling
        1. 25.4.4.1 Acceptance Filtering
          1. 25.4.4.1.1 Range Filter
          2. 25.4.4.1.2 Filter for specific IDs
          3. 25.4.4.1.3 Classic Bit Mask Filter
          4. 25.4.4.1.4 Standard Message ID Filtering
          5. 25.4.4.1.5 Extended Message ID Filtering
        2. 25.4.4.2 Rx FIFOs
          1. 25.4.4.2.1 Rx FIFO Blocking Mode
          2. 25.4.4.2.2 Rx FIFO Overwrite Mode
        3. 25.4.4.3 Dedicated Rx Buffers
          1. 25.4.4.3.1 Rx Buffer Handling
        4. 25.4.4.4 Debug on CAN Support
          1. 25.4.4.4.1 Filtering for Debug Messages
          2. 25.4.4.4.2 Debug Message Handling
      5. 25.4.5 Tx Handling
        1. 25.4.5.1 Transmit Pause
        2. 25.4.5.2 Dedicated Tx Buffers
        3. 25.4.5.3 Tx FIFO
        4. 25.4.5.4 Tx Queue
        5. 25.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 25.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 25.4.5.7 Transmit Cancellation
        8. 25.4.5.8 Tx Event Handling
      6. 25.4.6 FIFO Acknowledge Handling
      7. 25.4.7 DCAN Message RAM
        1. 25.4.7.1 Message RAM Configuration
        2. 25.4.7.2 Rx Buffer and FIFO Element
        3. 25.4.7.3 Tx Buffer Element
        4. 25.4.7.4 Tx Event FIFO Element
        5. 25.4.7.5 Standard Message ID Filter Element
        6. 25.4.7.6 Extended Message ID Filter Element
      8. 25.4.8 Interrupt Requests
    5. 25.5 DCAN Wrapper
    6. 25.6 DCAN Clock Enable
    7. 25.7 DCAN Registers
  27. 26Revision History

8.10 HOST_XIP Registers

Table 8-81 lists the memory-mapped registers for the HOST_XIP registers. All register offset addresses not listed in Table 8-81 should be considered as reserved locations and the register contents should not be modified.

Table 8-81 HOST_XIP Registers
OffsetAcronymRegister NameSection
14hSWCHDLYRegister to configure the extra delay added before the device switchSection 8.10.1
28hRCMCLKSTAClock StatusSection 8.10.2
1000hUDSCFG0Secure Source AddressSection 8.10.3
1004hUDSCFG1Secure Destination AddressSection 8.10.4
1008hUDSCFG2Secured Length ConfigurationSection 8.10.5
100ChUDSCFG3Security Mode ConfigurationSection 8.10.6
1010hUDSCTL0Secure Transfer StartSection 8.10.7
1014hUDSCTL1Secure Operation Cancellation ControlSection 8.10.8
1020hUDSSTASecure Status FlagsSection 8.10.9
1024hUDSIRQSecured Interrupt StatusSection 8.10.10
102ChUDSSTA1uDMA secured Status bits in addition to [UDMSSTA] registerSection 8.10.11
1040hUDSPERCFGPeripheral Security ConfigurationSection 8.10.12
1060hUDSPERSELRegister to select the peripheral to be served on secured channelSection 8.10.13
1064hUDNSPERSELRegister to select the peripheral to be served on non secured channelSection 8.10.14
2000hUDNSCFG0Nonsecure Source AddressSection 8.10.15
2004hUDNSCFG1Non-Secure Destination AddressSection 8.10.16
2008hUDNSCFG2uDMA non-secured job LengthSection 8.10.17
200ChUDNSCFG3DMA Security ModeSection 8.10.18
2010hUDNSCTL0uDMA non-secured job kickSection 8.10.19
2014hUDNSCTL1Non-Secure Job TerminationSection 8.10.20
2020hUDNSSTANon-Secure StatusSection 8.10.21
2024hUDNSIRQNon-Secure Interrupt StatusSection 8.10.22
2028hUTHRCNFThreshold ConfigurationSection 8.10.23
202ChUDNSSTA1Non-Secure Status ExtensionSection 8.10.24
2040hUDNSPERCFGNon secure peirpheral job configurationSection 8.10.25
3000hOTOSMEMOSPI ConfigurationSection 8.10.26

Complex bit access types are encoded to fit into small table cells. Table 8-82 shows the codes that are used for access types in this section.

Table 8-82 HOST_XIP Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.10.1 SWCHDLY Register (Offset = 14h) [Reset = 00000001h]

SWCHDLY is shown in Table 8-83.

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Register to configure the extra delay added before the device switch

Table 8-83 SWCHDLY Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1-0DEVSWCHDLYR/W1hThis field configures the extra delay added before the device switch
  • 0h = No extra delay
  • 1h = Extra delay of 16 cycles
  • 2h = Extra delay of 32 cycles
  • 3h = Extra delay of 64 cycles

8.10.2 RCMCLKSTA Register (Offset = 28h) [Reset = 00000000h]

RCMCLKSTA is shown in Table 8-84.

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(ICG) Clock Status from HOST_XIP_RCM Module

Table 8-84 RCMCLKSTA Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2OSPIREFR0h1 - Force clk (even if sw_disable_clk is 1 or clk_req is 0) 0 - Clock is not forced, but gated with clk_req input port
1SOCR0h1 - Force clk (even if sw_disable_clk is 1 or clk_req is 0) 0 - Clock is not forced, but gated with clk_req input port
0HOSTXIPR0h1 - Force clk (even if sw_disable_clk is 1 or clk_req is 0) 0 - Clock is not forced, but gated with clk_req input port

8.10.3 UDSCFG0 Register (Offset = 1000h) [Reset = 00000000h]

UDSCFG0 is shown in Table 8-85.

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uDMA source address for secured read controller. Must be Word aligned.

Table 8-85 UDSCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-0JSRCADDRR/W0hDMA SEC JOB SRC ADDR: Specifies source address for secured read controller. Source address must comply with bit.26 to enable Sec/Non-Sec accesses, otherwise transactions will be blocked.

8.10.4 UDSCFG1 Register (Offset = 1004h) [Reset = 00000000h]

UDSCFG1 is shown in Table 8-86.

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uDMA destination address for secured write controller. Must be Word aligned.

Table 8-86 UDSCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-0JDESTADDRR/W0hDMA SEC JOB DST ADDR: Specifies destination address for secured write controller. Destination address must comply with bit.26 to enable Sec/Non-Sec accesses, otherwise transactions will be blocked.

8.10.5 UDSCFG2 Register (Offset = 1008h) [Reset = 00000000h]

UDSCFG2 is shown in Table 8-87.

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uDMA secured job Length

Table 8-87 UDSCFG2 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17-0JLENR/W0hDMA SEC JOB LENGTH: Resolution - 32 bits/4 bytes Maximum configurable job size - 1 Mega byte (256K Words). (Maximum available size in MEMSS is 1MB).

8.10.6 UDSCFG3 Register (Offset = 100Ch) [Reset = 00000000h]

UDSCFG3 is shown in Table 8-88.

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uDMA Direction

Table 8-88 UDSCFG3 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1SMODER/W0hSecure channel mode 0: Memory Mode 1: Peripheral Mode
0JDIRR/W0hDMA SEC JOB MODE: 0 - Data movement from External memory to Internal memory/Peripheral 1 - Data movement from Internal memory/Peripheral to External memory.

8.10.7 UDSCTL0 Register (Offset = 1010h) [Reset = 00000000h]

UDSCTL0 is shown in Table 8-89.

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uDMA secured job kick

Table 8-89 UDSCTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0JSTARTW0hDMA SEC JOB START WRCL: Start command for uDMA to start working on secured configured job.

8.10.8 UDSCTL1 Register (Offset = 1014h) [Reset = 00000000h]

UDSCTL1 is shown in Table 8-90.

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uDMA secured job abort

Table 8-90 UDSCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0JCLRW0hDMA SEC JOB CLEAR WRCL: Clear command for uDMA to stop working and clear configuration.

8.10.9 UDSSTA Register (Offset = 1020h) [Reset = 00000000h]

UDSSTA is shown in Table 8-91.

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uDMA secured Status bits

Table 8-91 UDSSTA Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0h
27-8RDWRDSLFTR0hDMA SEC JOB READ WORDS LEFT: number of read words left in sec job. Note: This value would be updated on a read to this register. [UDSSTA1.WRWRDSLFT] is updated on a read to this register This register value shows number of words in 32 bit when field [UDSCFG3.JDIR] is configured '0' else shows number of words in 8/16/32 bit based on the configuration of [UDSCFG3.SMODE] and [UDPERCFG.SWORDSZ] fields
7-5RESERVEDR0hReserved
4JINPROGR0hDMA SEC JOB IN PROGRESS: 1- sec job is currently in progress and being executed by uDMA
3-1RESERVEDR0hReserved
0JSTAR0hDMA SEC JOB ACTIVE: Status bit to indicate that DMA is processing a secured job. When this bit is set, SW has written all the job parameters and also provided a start_pulse to HW, and cannot change job parameters without clear_pulse. Job will wait to be executed (indicated by job_in_progress)

8.10.10 UDSIRQ Register (Offset = 1024h) [Reset = 00000000h]

UDSIRQ is shown in Table 8-92.

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uDMA secured IRQ Status bits

Table 8-92 UDSIRQ Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2JIRQBEDIRR0hBus Error direction 0: Source bus 1: Destination bus Note: Source and destination is determined based on JDIR configuration
1-0JIRQSTAR0hStatus vector for IRQ indication for secured DMA IRQ: 2'd0 - DMA done. 2'd1 - DMA Internal bus error occurred. check SEC_STATUS in order to recovers

8.10.11 UDSSTA1 Register (Offset = 102Ch) [Reset = 00000000h]

UDSSTA1 is shown in Table 8-93.

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uDMA secured Status bits in addition to [UDMSSTA] register

Table 8-93 UDSSTA1 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0h
27-8WRWRDSLFTR0hDMA SEC JOB WRITE WORDS LEFT: Number of write words left in sec job. Note: This value would be updated only on a read to [UDSSTA] register. This register value shows number of words in 32 bit when field [UDSCFG3.JDIR] is configured '1' else shows number of words in 8/16/32 bit based on the configuration of [UDSCFG3.SMODE] and [UDPERCFG.SWORDSZ] fields
7-0WRDOFSTR0hDMA SEC PERIPH WORD OFFSET: Number of words left in a peripheral block. Note: This value would be updated only on a read to [UDSSTA] register. This register value shows number of words in 8/16/32 bit based on the configuration of [UDSCFG3.SMODE] and [UDPERCFG.SWORDSZ] fields

8.10.12 UDSPERCFG Register (Offset = 1040h) [Reset = 00000000h]

UDSPERCFG is shown in Table 8-94.

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uDMA Secure channel peripheral config register

Table 8-94 UDSPERCFG Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8SENCLRSRTR/W0hEnable uDMA to set a rd/wr clear pulse at the beginning of a job
7-2SPERBLKSZR/W0hSecure channel peripheral block size(in 32bits/4bytes) Multiplication of Word size Upto 64 words based on the word size selected Block = block_size * word_size
1-0SPERWDSZR/W0hSecure channel peripheral job word size 8/16/32 (Word Size of 1/2/4 bytes) Sel_0 - 32 bit Sel_1 - 16 bit Sel_2 - 8 bit

8.10.13 UDSPERSEL Register (Offset = 1060h) [Reset = 00000000h]

UDSPERSEL is shown in Table 8-95.

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Register to select the peripheral to be served on secured channel

Table 8-95 UDSPERSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-0SPERSELR/W0hSelect the peripheral to serve job. This field along with [UDMA_SEC_MODE.MEM_SEC_MODE] selects the peripheral to the channel 0x0 UART0 0x1 UART1 0x2 SPI0 0x3 SPI1 0x4 I2C0 0x5 I2C1 0x6 SDMMC 0x7 SDIO 0x8 MCAN 0x9 ADC 0xA PDM 0xB HIF

8.10.14 UDNSPERSEL Register (Offset = 1064h) [Reset = 00000000h]

UDNSPERSEL is shown in Table 8-96.

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Register to select the peripheral to be served on non secured channel

Table 8-96 UDNSPERSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-0NSPERSELR/W0hSelect the peripheral to serve job. This field along with [UDMA_NONSEC_MODE.MEM_NON_SEC_MODE] selects the peripheral to the channel 0x0 UART0 0x1 UART1 0x2 SPI0 0x3 SPI1 0x4 I2C0 0x5 I2C1 0x6 SDMMC 0x7 SDIO 0x8 MCAN 0x9 ADC 0xA PDM 0xB HIF

8.10.15 UDNSCFG0 Register (Offset = 2000h) [Reset = 00000000h]

UDNSCFG0 is shown in Table 8-97.

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uDMA source address for non-secured read controller. Must be Word aligned.

Table 8-97 UDNSCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-0JSRCADDRR/W0hDMA NONSEC JOB SRC ADDR: Specifies source address for non-secured read controller. Source address must comply with bit.26 to enable Sec/Non-Sec accesses, otherwise transactions will be blocked. In case using SAU to define secured memory region 'inside' the non-secured, this channel will allow this.

8.10.16 UDNSCFG1 Register (Offset = 2004h) [Reset = 00000000h]

UDNSCFG1 is shown in Table 8-98.

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uDMA destination address for non-secured write controller. Must be Word aligned.

Table 8-98 UDNSCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-0JDESTADDRR/W0hDMA NONSEC JOB DST ADDR: Specifies destination address for non-secured write controller. Destination address must comply with bit.26 to enable Sec/Non-Sec accesses, otherwise transactions will be blocked. In case using SAU to define secured memory region 'inside' the non-secured, this channel will allow this.

8.10.17 UDNSCFG2 Register (Offset = 2008h) [Reset = 00000000h]

UDNSCFG2 is shown in Table 8-99.

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uDMA non-secured job Length

Table 8-99 UDNSCFG2 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17-0JLENR/W0hDMA NONSEC JOB LENGTH: Resolution - 32 bits/4bytes Maximum configurable job size - 1 Mega byte (256K Words). (Maximum available size in MEMSS is 1MB).

8.10.18 UDNSCFG3 Register (Offset = 200Ch) [Reset = 00000000h]

UDNSCFG3 is shown in Table 8-100.

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uDMA Direction

Table 8-100 UDNSCFG3 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1NSMODER/W0hNon secure channel mode 0: Memory Mode 1: Peripheral Mode
0JDIRR/W0hDMA NONSEC JOB MODE: 0 - Data movement from External memory to Internal memory. 1 - Data movement from Internal memory to External memory.

8.10.19 UDNSCTL0 Register (Offset = 2010h) [Reset = 00000000h]

UDNSCTL0 is shown in Table 8-101.

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uDMA non-secured job kick

Table 8-101 UDNSCTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0JSTARTW0hDMA NONSEC JOB START WRCL: Start command for uDMA to start working on non-secured configured job.

8.10.20 UDNSCTL1 Register (Offset = 2014h) [Reset = 00000000h]

UDNSCTL1 is shown in Table 8-102.

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uDMA non-secured job abort

Table 8-102 UDNSCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0JCLRW0hDMA NONSEC JOB CLEAR WRCL: Clear command for uDMA to stop working and clear configuration.

8.10.21 UDNSSTA Register (Offset = 2020h) [Reset = 00000000h]

UDNSSTA is shown in Table 8-103.

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uDMA non-secured Status bits

Table 8-103 UDNSSTA Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0h
27-8RDWRDSLFTR0hDMA NONSEC JOB READ WORDS LEFT: Number of read words left in nonsec job Note: This value would be updated on a read to this register. [UDNSSTA1.WRWRDSLFT] is updated on a read to this register This register value shows number of words in 32 bit when field [UDNSCFG3.JDIR] is configured '0' else shows number of words in 8/16/32 bit based on the configuration of [UDNSCFG3.NSMODE] and [UDPERCFG.NSWORDSZ] fields
7-5RESERVEDR0hReserved
4JINPROGR0hDMA NONSEC JOB IN PROGRESS: 1- nonsec job is currently in progress and being executed by uDMA
3-1RESERVEDR0hReserved
0JSTAR0hDMA NONSEC JOB ACTIVE: Status bit to indicate that DMA is processing a non-secured job. When this bit is set, SW has written all the job parameters and also provided a start_pulse to HW, and cannot change job parameters without clear_pulse. Job will wait to be executed (indicated by job_in_progress)

8.10.22 UDNSIRQ Register (Offset = 2024h) [Reset = 00000000h]

UDNSIRQ is shown in Table 8-104.

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uDMA non-secured IRQ Status bits

Table 8-104 UDNSIRQ Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2JIRQBEDIRR0hBus Error direction 0: Source bus 1: Destination bus Note: Source and destination is determined based on JDIR configuration
1-0JIRQSTAR0hStatus vector for IRQ indication for non-secured DMA IRQ: 2'd0 - DMA done. 2'd1 - DMA bus error occurred. check NONSEC_STATUS in order to recovers

8.10.23 UTHRCNF Register (Offset = 2028h) [Reset = 00000090h]

UTHRCNF is shown in Table 8-105.

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uDMA threshold configuration

Table 8-105 UTHRCNF Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-5BURSTVALR/W0hFIFO WRITE BURST LEN: After uDMA will reached the threshold, uDMA will sent the data in blocks. 0x0 : block size = 4 word 0x1 : block size = 8 word 0x2 : block size = 16 word 0x3 : block size = 32 word
4-0THRVALR/W10hFIFO WRITE THRESHOLD: In case of write to ext mem, uDMA will reach the threshold and after that will send the data to the ext mem Note: 0(Zero) is not allowed

8.10.24 UDNSSTA1 Register (Offset = 202Ch) [Reset = 00000000h]

UDNSSTA1 is shown in Table 8-106.

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uDMA non-secured Status bits in addition to [UDNSSTA] register

Table 8-106 UDNSSTA1 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0h
27-8WRDOFSTR0hDMA NONSEC JOB WRITE WORDS LEFT: Number of write words left in nonsec job. Note: This value would be updated only on a read to [UDNSSTA] register. This register value shows number of words in 32 bit when field [UDNSCFG3.JDIR] is configured '1' else shows number of words in 8/16/32 bit based on the configuration of [UDNSCFG3.NSMODE] and [UDPERCFG.NSWORDSZ] fields
7-0WRWRDSLFTR0hDMA NONSEC PERIPH WORD OFFSET: Number of words left in a peripheral block. Note: This value would be updated only on a read to [UDNSSTA] register. This register value shows number of words in 8/16/32 bit based on the configuration of [UDNSCFG3.NSMODE] and [UDPERCFG.NSWORDSZ] fields

8.10.25 UDNSPERCFG Register (Offset = 2040h) [Reset = 00000000h]

UDNSPERCFG is shown in Table 8-107.

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Non secure peirpheral job configuration

Table 8-107 UDNSPERCFG Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8NSENCLRSRTR/W0hEnable uDMA to set a rd/wr clear pulse at the beginning of a job
7-2NSPERBLSZR/W0hNon-secure channel peripheral job block size(in 32bits/4bytes) Multiplication of Word size. Upto 64 words based on Word size Block = block_size * word_size
1-0NSPERWDSZR/W0hNon-secure channel peripheral job word size 8/16/32 (Word Size of 1/2/4 bytes) Sel_0 - 32 bit Sel_1 - 16 bit Sel_2 - 8 bit

8.10.26 OTOSMEM Register (Offset = 3000h) [Reset = 00000000h]

OTOSMEM is shown in Table 8-108.

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For Load/Read xSPI config job in OTFDE memory

Table 8-108 OTOSMEM Register Field Descriptions
BitFieldTypeResetDescription
31-0WDATACFGR/W0hOTFDE CFG OSPI 81FC WR MEM xSPI config Memory wr/rd access (under OTFDE module)