SWRU626 December   2025 CC3501E , CC3551E

 

  1.   1
  2. 1 Read This First
    1. 1.1 About This Manual
    2. 1.2 Register, Field, and Bit Calls
    3.     Trademarks
  3. 2 Architecture Overview
    1. 2.1  Target Applications
    2. 2.2  Introduction
    3. 2.3  Internal System Diagram
    4. 2.4  Arm Cortex M33
      1. 2.4.1 Processor Core
      2. 2.4.2 SysTick Timer
      3. 2.4.3 Nested Vectored Interrupt Controller
      4. 2.4.4 System Control Block (SCB)
      5. 2.4.5 TI AI instruction extensions
    5. 2.5  Power Management
      1. 2.5.1 VDD_MAIN
      2. 2.5.2 VDD_IO
      3. 2.5.3 VDDSF
      4. 2.5.4 VDD_PA
    6. 2.6  Debug Subsystem (DEBUGSS)
    7. 2.7  Memory Subsystem (MEMSS)
      1. 2.7.1 External Memory Interface
    8. 2.8  Hardware Security Module
    9. 2.9  General Purpose Timers (GPT)
    10. 2.10 Real Time Clock (RTC)
    11. 2.11 Direct Memory Access
    12. 2.12 GPIOs
    13. 2.13 Communication Peripherals
      1. 2.13.1 UART
      2. 2.13.2 I2C
      3. 2.13.3 SPI
      4. 2.13.4 I2S
      5. 2.13.5 SDMMC
      6. 2.13.6 SDIO
      7. 2.13.7 CAN
      8. 2.13.8 ADC
  4. 3  Arm Cortex-M33 Processor
    1. 3.1 Arm Cortex-M33 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 M33 instantiation parameters
    4. 3.4 Arm Cortex-M33 System Peripheral Details
      1. 3.4.1 Floating Point Unit (FPU)
      2. 3.4.2 Memory Protection Unit (MPU)
      3. 3.4.3 Digital Signal Processing (DSP)
      4. 3.4.4 Security Attribution Unit (SAU)
      5. 3.4.5 System Timer
      6. 3.4.6 Nested Vectored Interrupt Controller
      7. 3.4.7 System Control Block
      8. 3.4.8 System Control Space
    5. 3.5 CPU Sub-System Peripheral Details
      1. 3.5.1 Trace Port Interface Unit (TPIU)
      2. 3.5.2 DAP Bridge and Debug Authentication
      3. 3.5.3 Implementation Defined Attribution Unit (IDAU)
    6. 3.6 Programming Model
      1. 3.6.1 Modes of operation and execution
        1. 3.6.1.1 Security states
        2. 3.6.1.2 Operating modes
        3. 3.6.1.3 Operating states
        4. 3.6.1.4 Privileged access and unprivileged user access
      2. 3.6.2 Instruction set summary
      3. 3.6.3 Memory model
        1. 3.6.3.1 Private Peripheral Bus
        2. 3.6.3.2 Unaligned accesses
      4. 3.6.4 Processor core registers summary
      5. 3.6.5 Exceptions
        1. 3.6.5.1 Exception handling and prioritization
    7. 3.7 TrustZone-M
      1. 3.7.1 Overview
      2. 3.7.2 M33 Configuration
      3. 3.7.3 Description of elements
        1. 3.7.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 3.7.3.1.1 Expected use
    8. 3.8 CC35xx Host MCU Registers
      1. 3.8.1 HOSTMCU_AON Registers
      2. 3.8.2 HOST_MCU Registers
      3. 3.8.3 HOST_MCU_SEC Registers
    9. 3.9 Arm® Cortex®-M33 Registers
      1. 3.9.1  CPU_ROM_TABLE Registers
      2. 3.9.2  TPIU Registers
      3. 3.9.3  DCB Registers
      4. 3.9.4  DIB Registers
      5. 3.9.5  DWT Registers
      6. 3.9.6  FPB Registers
      7. 3.9.7  FPE Registers
      8. 3.9.8  ICB Registers
      9. 3.9.9  ITM Registers
      10. 3.9.10 MPU Registers
      11. 3.9.11 NVIC Registers
      12. 3.9.12 SAU Registers
      13. 3.9.13 SCB Registers
      14. 3.9.14 SYSTIMER Registers
      15. 3.9.15 SYSTICK Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation to HardFault
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Manager
      1. 5.4.1 Introduction
      2. 5.4.2 Interrupts List
      3. 5.4.3 Wakeup Sources
      4. 5.4.4 Shared Peripherals MUX Selector
        1. 5.4.4.1 ADC HW Event Selector Mux
        2. 5.4.4.2 I2S HW Event Selector Mux
        3. 5.4.4.3 PDM HW Event Selector Mux
      5. 5.4.5 Timers MUX Selector Mux
        1. 5.4.5.1 SysTimer0 HW Event Selector Mux
        2. 5.4.5.2 SysTimer1 HW Event Selector Mux
        3. 5.4.5.3 RTC HW Event Selector Mux
      6. 5.4.6 GPTIMERs MUX Selector Mux
        1. 5.4.6.1 GPTIMER0 HW Event Selector Mux
        2. 5.4.6.2 GPTIMER1 HW Event Selector Mux
    5. 5.5 SOC_IC Registers
    6. 5.6 SOC_AON Registers
    7. 5.7 SOC_AAON Registers
  7. 6 Debug Subsystem (DEBUGSS)
    1. 6.1 Introduction
    2. 6.2 Block Diagram
    3. 6.3 Overview
    4. 6.4 Physical Interface
    5. 6.5 Debug Access Ports
    6. 6.6 Debug Features
      1. 6.6.1 Processor Debug
      2. 6.6.2 Breakpoint Unit (BPU)
      3. 6.6.3 Peripheral Debug
    7. 6.7 Behavior in Low Power Modes
    8. 6.8 Debug Access Control
    9. 6.9 SOC_DEBUGSS Registers
  8. 7 Power, Reset, Clock Management
    1. 7.1 Power Management
      1. 7.1.1 Power Supply System
        1. 7.1.1.1 VDD_MAIN
        2. 7.1.1.2 VIO
        3. 7.1.1.3 VDDSF
        4. 7.1.1.4 VPA
      2. 7.1.2 Power States
      3. 7.1.3 Power Domains
      4. 7.1.4 Brownout (BOR)
      5. 7.1.5 Boot Sequence
    2. 7.2 Reset
      1. 7.2.1 Reset Cause
      2. 7.2.2 Watchdog Timer (WDT)
    3. 7.3 Clocks
      1. 7.3.1 Fast Clock
      2. 7.3.2 Slow Clock
        1. 7.3.2.1 Slow Clock Overview
        2. 7.3.2.2 Slow Clock Tree
        3. 7.3.2.3 Slow Clock Boot Process
    4. 7.4 PRCM_AON Registers
    5. 7.5 PRCM_SCRATCHPAD Registers
  9. 8 Memory Subsystem (MEMSS)
    1. 8.1  Introduction
    2. 8.2  SRAM
    3. 8.3  D-Cache
    4. 8.4  Flash
    5. 8.5  PSRAM
    6. 8.6  XiP Memory Access
      1. 8.6.1 OTFDE
      2. 8.6.2 xSPI
      3. 8.6.3 Topology
      4. 8.6.4 µDMA
      5. 8.6.5 Arbiter
    7. 8.7  ICACHE Registers
    8. 8.8  DCACHE Registers
    9. 8.9  OSPI Registers
    10. 8.10 HOST_XIP Registers
  10. 9 Hardware Security Module (HSM)
    1. 9.1 Introduction
    2. 9.2 Overview
    3. 9.3 Mailbox and Register Access Firewall
    4. 9.4 DMA Firewall
    5. 9.5 HSM Key Storage
    6. 9.6 HSM Registers
    7. 9.7 HSM_NON_SEC Registers
    8. 9.8 HSM_SEC Registers
  11. 10Device Boot and Bootloader
    1. 10.1 CC35xx Boot Concept
    2. 10.2 Features
    3. 10.3 Vendor Images Format and Processing
      1. 10.3.1 External Flash Arrangement
      2. 10.3.2 Vendor Images Format
    4. 10.4 Boot Flows
      1. 10.4.1 Application Execution Boot Flow
      2. 10.4.2 Activation Flow
      3. 10.4.3 Initial Programming Flow
      4. 10.4.4 Reprogramming Flow
      5. 10.4.5 Wireless Connectivity Testing Tool Flow
    5. 10.5 Chain of Trust
  12. 11Direct Memory Access (DMA)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Channels Assignment
      2. 11.3.2 Transfer Types
      3. 11.3.3 Addressing Modes
      4. 11.3.4 Transfer Modes
      5. 11.3.5 DMA Aligner Support
      6. 11.3.6 Initiating DMA Transfers
      7. 11.3.7 Stopping DMA Transfers
      8. 11.3.8 Channel Priorities
      9. 11.3.9 DMA Interrupts
    4. 11.4 HOST_DMA Registers
  13. 12One Time Programming (OTP)
  14. 13General Purpose Timers (GPT)
    1. 13.1 Overview
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1  Prescaler
      2. 13.3.2  Counter
      3. 13.3.3  Target
      4. 13.3.4  Channel Input Logic
      5. 13.3.5  Channel Output Logic
      6. 13.3.6  Channel Actions
        1. 13.3.6.1 Period and Pulse Width Measurement
        2. 13.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 13.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 13.3.7  Channel Capture Configuration
      8. 13.3.8  Channel Filters
        1. 13.3.8.1 Setting up the Channel Filters
      9. 13.3.9  Synchronize Multiple GPTimers
      10. 13.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 13.4 Timer Modes
      1. 13.4.1 Quadrature Decoder
      2. 13.4.2 DMA
      3. 13.4.3 IR Generation
      4. 13.4.4 Fault and Park
      5. 13.4.5 Dead-Band
      6. 13.4.6 Dead-Band, Fault and Park
      7. 13.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 13.5 GPTIMER Registers
  15. 14System Timer (SysTimer)
    1. 14.1 Overview
    2. 14.2 Block Diagram
    3. 14.3 Functional Description
      1. 14.3.1 Common Channel Features
        1. 14.3.1.1 Compare Mode
        2. 14.3.1.2 Capture Mode
        3. 14.3.1.3 Additional Channel Arming Methods
      2. 14.3.2 Interrupts and Events
    4. 14.4 SYSRESOURCES Registers
    5. 14.5 SYSTIM Registers
  16. 15Real-Time Clock (RTC)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Interrupts and Events
      1. 15.3.1 Input Event
      2. 15.3.2 Output Event
      3. 15.3.3 Arming and Disarming Channels
    4. 15.4 CAPTURE and COMPARE Configurations
      1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
    5. 15.5 RTC Registers
  17. 16General Purpose Input/Output (GPIOs)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 I/O Mapping and Configuration
      1. 16.3.1 Basic I/O Mapping
      2. 16.3.2 Pin Mapping
    4. 16.4 Edge Detection
    5. 16.5 GPIO
    6. 16.6 I/O Pins
    7. 16.7 Unused Pins
    8. 16.8 IOMUX Registers
  18. 17Universal Asynchronous Receivers/Transmitters (UART)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 UART Functional Description
      1. 17.3.1 Transmit and Receive Logic
      2. 17.3.2 Baud Rate Generation
      3. 17.3.3 FIFO Operation
        1. 17.3.3.1 FIFO Remapping
      4. 17.3.4 Data Transmission
      5. 17.3.5 Flow Control
      6. 17.3.6 IrDA Encoding and Decoding
      7. 17.3.7 Interrupts
      8. 17.3.8 Loopback Operation
    4. 17.4 UART-LIN Specification
      1. 17.4.1 Break transmission in UART mode
      2. 17.4.2 Break reception in UART mode
      3. 17.4.3 Break/Synch transmission in LIN mode
      4. 17.4.4 Break/Synch reception in LIN mode
      5. 17.4.5 Dormant mode operation
      6. 17.4.6 Event signal generation
      7. 17.4.7 Event signal detection when device is in active/idle modes
      8. 17.4.8 Event signal detection when device is in sleep mode
    5. 17.5 Interface to Host DMA
    6. 17.6 Initialization and Configuration
    7. 17.7 UART Registers
  19. 18Serial Peripheral Interface (SPI)
    1. 18.1 Overview
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Signal Description
    3. 18.3 Functional Description
      1. 18.3.1  Clock Control
      2. 18.3.2  FIFO Operation
        1. 18.3.2.1 Transmit FIFO
        2. 18.3.2.2 Repeated Transmit Operation
        3. 18.3.2.3 Receive FIFO
        4. 18.3.2.4 FIFO Flush
      3. 18.3.3  Interrupts
      4. 18.3.4  Data Format
      5. 18.3.5  Delayed Data Sampling
      6. 18.3.6  Chip Select Control
      7. 18.3.7  Command Data Control
      8. 18.3.8  Protocol Descriptions
        1. 18.3.8.1 Motorola SPI Frame Format
        2. 18.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 18.3.8.3 MICROWIRE Frame Format
      9. 18.3.9  CRC Configuration
      10. 18.3.10 Auto CRC Functionality
      11. 18.3.11 SPI Status
      12. 18.3.12 Debug Halt
    4. 18.4 Host DMA Operation
    5. 18.5 Initialization and Configuration
    6. 18.6 SPI Registers
  20. 19Inter-Integrated Circuit (I2C) Interface
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Clock Control
        1. 19.3.1.1 Internal Clock
        2. 19.3.1.2 External Clock
      2. 19.3.2 General Architecture
        1. 19.3.2.1  Start and Stop Conditions
        2. 19.3.2.2  Data Format with 7-Bit Address
        3. 19.3.2.3  Data Format with 10-Bit Addressing
          1. 19.3.2.3.1 Additional 10-Bit Scenarios
        4. 19.3.2.4  Acknowledge
        5. 19.3.2.5  Repeated Start
        6. 19.3.2.6  Clock Stretching
        7. 19.3.2.7  Arbitration
        8. 19.3.2.8  Multi-Controller mode
        9. 19.3.2.9  Glitch Suppression
        10. 19.3.2.10 FIFO Operation
        11. 19.3.2.11 Burst Mode Operation
        12. 19.3.2.12 DMA Operation
        13. 19.3.2.13 Flush Stale Tx Data in Target Mode
          1. 19.3.2.13.1 Recommended Sequence
        14. 19.3.2.14 SMBUS 3.0 Support
          1. 19.3.2.14.1 Quick Command
          2. 19.3.2.14.2 Acknowledge Control
          3. 19.3.2.14.3 Alert Response protocol
          4. 19.3.2.14.4 Address Resolution Protocol
          5. 19.3.2.14.5 Enhanced Acknowledge Control
    4. 19.4 Initialization and Configuration
    5. 19.5 Interrupts
    6. 19.6 I2C Registers
  21. 20Secure Digital Multimedia Card (SDMMC)
    1. 20.1 Introduction
      1. 20.1.1 SDMMC Features
      2. 20.1.2 Integration
    2. 20.2 Functional Description
      1. 20.2.1  SDMMC Functional Modes
        1. 20.2.1.1 SDMMC Connected to an SD Card
        2. 20.2.1.2 Protocol and Data Format
          1. 20.2.1.2.1 Protocol
          2. 20.2.1.2.2 Data Format
      2. 20.2.2  SD Card Feedback
      3. 20.2.3  Resets
        1. 20.2.3.1 Hardware Reset
        2. 20.2.3.2 Software Reset
      4. 20.2.4  Interrupt Requests
        1. 20.2.4.1 Interrupt-Driven Operation
        2. 20.2.4.2 Polling
      5. 20.2.5  DMA Modes
        1. 20.2.5.1 DMA Peripheral Mode Operations
          1. 20.2.5.1.1 DMA Receive Mode
          2. 20.2.5.1.2 DMA Transmit Mode
      6. 20.2.6  Buffer Management
        1. 20.2.6.1 Data Buffer
          1. 20.2.6.1.1 Memory Size and Block Length
          2. 20.2.6.1.2 Data Buffer Status
      7. 20.2.7  Transfer Process
        1. 20.2.7.1 Different Types of Commands
        2. 20.2.7.2 Different Types of Responses
      8. 20.2.8  Transfer or Command Status and Error Reporting
        1. 20.2.8.1 Busy Timeout for R1b, R5b Response Type
        2. 20.2.8.2 Busy Timeout After Write CRC Status
        3. 20.2.8.3 Write CRC Status Timeout
        4. 20.2.8.4 Read Data Timeout
      9. 20.2.9  Auto Command 12 Timings
        1. 20.2.9.1 Auto Command 12 Timings During Write Transfer
        2. 20.2.9.2 Auto Command 12 Timings During Read Transfer
      10. 20.2.10 Transfer Stop
      11. 20.2.11 Output Signals Generation
        1. 20.2.11.1 Generation on Falling Edge of SDMMC Clock
        2. 20.2.11.2 Generation on Rising Edge of SDMMC Clock
      12. 20.2.12 Test Registers
      13. 20.2.13 SDMMC Hardware Status Features
    3. 20.3 Low-Level Programming Models
      1. 20.3.1 SDMMC Initialization Flow
        1. 20.3.1.1 Enable OCP and CLKADPI Clocks
        2. 20.3.1.2 SD Soft Reset Flow
        3. 20.3.1.3 Set SD Default Capabilities
        4. 20.3.1.4 SDMMC Host and Bus Configuration
      2. 20.3.2 Operational Modes Configuration
        1. 20.3.2.1 Basic Operations for SDMMC
        2. 20.3.2.2 Card Detection, Identification, and Selection
    4. 20.4 SDMMC Registers
  22. 21Secure Digital Input/Output (SDIO)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 SDIO Interface Description
      2. 21.3.2 Protocol and Data Format
      3. 21.3.3 I/O Read/Write Command
        1. 21.3.3.1 IO_WR_DIRECT Command (CMD52)
        2. 21.3.3.2 IO_WR_EXTENDED Command (CMD53)
      4. 21.3.4 Reset
      5. 21.3.5 FIFO Operation
        1. 21.3.5.1 Rx FIFO (For Host Write)
        2. 21.3.5.2 Tx FIFO (For Host Read)
      6. 21.3.6 Interrupt Request
        1. 21.3.6.1 External Host IRQ
        2. 21.3.6.2 M33 IRQ
      7. 21.3.7 Transaction Details
        1. 21.3.7.1 Host write to SDIO IP (Rx FIFO)
          1. 21.3.7.1.1 Host write to SDIO IP (Rx FIFO) – Long SW latency case
          2. 21.3.7.1.2 Host write to SDIO IP (Rx FIFO) – CRC Error Case
        2. 21.3.7.2 Host reads from SDIO (TX buffer)
    4. 21.4 SDIO_CORE Registers
    5. 21.5 SDIO_CARD_FN1 Registers
  23. 22Inter-Integrated Circuit Sound (I2S)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  Signal Descriptions
    4. 22.4  Functional Description
      1. 22.4.1 Pin Configuration
      2. 22.4.2 Serial Format Configuration
        1. 22.4.2.1 Register Configuration
      3. 22.4.3 Left-Justified (LJF)
        1. 22.4.3.1 Register Configuration
      4. 22.4.4 Right-Justified (RJF)
        1. 22.4.4.1 Register Configuration
      5. 22.4.5 DSP
        1. 22.4.5.1 Register Configuration
      6. 22.4.6 Clock Configuration
    5. 22.5  Memory Interface
      1. 22.5.1 Sample Word Length
      2. 22.5.2 Padding Mechanism
      3. 22.5.3 Channel Mapping
      4. 22.5.4 Sample Storage in Memory
      5. 22.5.5 DMA Operation
        1. 22.5.5.1 Start-Up
        2. 22.5.5.2 Operation
        3. 22.5.5.3 Shutdown
    6. 22.6  Samplestamp Generator
      1. 22.6.1 Samplestamp Counters
      2. 22.6.2 Start-Up Triggers
      3. 22.6.3 Samplestamp Capture
      4. 22.6.4 Achieving constant audio latency
    7. 22.7  Error Detection
    8. 22.8  Usage
      1. 22.8.1 Start-Up Sequence
      2. 22.8.2 Shutdown Sequence
    9. 22.9  I2S Configuration Guideline
    10. 22.10 I2S Registers
  24. 23Pulse Density Modulation (PDM)
    1. 23.1  Introduction
    2. 23.2  Block Diagram
    3. 23.3  Input Selection
      1. 23.3.1 PDM Data Mode
      2. 23.3.2 Manchester Input Mode
    4. 23.4  CIC Filter
      1. 23.4.1 Filter Design
      2. 23.4.2 Digital Filter Output
      3. 23.4.3 Offset Binary Mode
      4. 23.4.4 Twos-Complement Mode
    5. 23.5  FIFO Organization in Different Modes
      1. 23.5.1 Single Mono Microphone Configuration
        1. 23.5.1.1 24-bit Sample Size
          1. 23.5.1.1.1 32-bit Data Read
        2. 23.5.1.2 16-bit Sample Size
          1. 23.5.1.2.1 32-bit Data Read
          2. 23.5.1.2.2 16-bit Data Read
        3. 23.5.1.3 8-bit Sample Size
          1. 23.5.1.3.1 32-bit Data Read
          2. 23.5.1.3.2 16-bit Data Read
          3. 23.5.1.3.3 8-bit Data Read
      2. 23.5.2 Stereo or Dual Mono Microphone Configuration
        1. 23.5.2.1 24-bit Sample Size
          1. 23.5.2.1.1 32-bit Data Read
        2. 23.5.2.2 16-bit Sample Size
          1. 23.5.2.2.1 32-bit Data Read
          2. 23.5.2.2.2 16-bit Data Read
        3. 23.5.2.3 8-bit Sample Size
          1. 23.5.2.3.1 32-bit Data Read
          2. 23.5.2.3.2 16-bit Data Read
          3. 23.5.2.3.3 8-bit Data Read
      3. 23.5.3 FIFO Threshold Setting
      4. 23.5.4 Reset FIFO
    6. 23.6  Automatic Gain Control (AGC)
      1. 23.6.1 Operation in 2's Complement Format
      2. 23.6.2 Operation in Offset Binary Format
    7. 23.7  Interrupts
    8. 23.8  Clock Select and Control
    9. 23.9  DMA Operation
    10. 23.10 Samplestamp Generator
      1. 23.10.1 Samplestamp Counters
      2. 23.10.2 Start-Up Triggers
      3. 23.10.3 Samplestamp Capture
      4. 23.10.4 Achieving Constant Audio Latency
    11. 23.11 Debug‑Mode Flag Behavior
    12. 23.12 Software Guidelines
    13. 23.13 PDM Registers
  25. 24Analog to Digital Converter (ADC)
    1. 24.1 Overview
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1  ADC Core
      2. 24.3.2  Voltage Reference Options
      3. 24.3.3  Internal Channels
      4. 24.3.4  Resolution Modes
      5. 24.3.5  ADC Clocking
      6. 24.3.6  Power Down Behavior
      7. 24.3.7  Sampling Trigger Sources and Sampling Modes
        1. 24.3.7.1 AUTO Sampling Mode
        2. 24.3.7.2 MANUAL Sampling Mode
      8. 24.3.8  Sampling Period
      9. 24.3.9  Conversion Modes
      10. 24.3.10 ADC Data Format
      11. 24.3.11 Status Register
      12. 24.3.12 ADC Events
        1. 24.3.12.1 Generic Event Publishers (INT_EVENT0 & INT_EVENT1)
        2. 24.3.12.2 DMA Trigger Event Publisher (INT_EVENT2)
        3. 24.3.12.3 Generic Event Subscriber
      13. 24.3.13 Advanced Features
        1. 24.3.13.1 Window Comparator
        2. 24.3.13.2 DMA & FIFO Operation
          1. 24.3.13.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
          2. 24.3.13.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
          3. 24.3.13.2.3 DMA/CPU Operation Summary Matrix
        3. 24.3.13.3 Ad-hoc Single Conversion
    4. 24.4 ADC Registers
  26. 25Controller Area Network (CAN)
    1. 25.1 Introduction
    2. 25.2 Functions
    3. 25.3 DCAN Subsystem
    4. 25.4 DCAN Functional Description
      1. 25.4.1 Operating Modes
        1. 25.4.1.1 Software Initialization
        2. 25.4.1.2 Normal Operation
        3. 25.4.1.3 Restricted Operation Mode
        4. 25.4.1.4 Bus Monitoring Mode
        5. 25.4.1.5 Disabled Automatic Retransmission
          1. 25.4.1.5.1 Frame Transmission in DAR Mode
        6. 25.4.1.6 Power Down (Sleep Mode)
          1. 25.4.1.6.1 DCAN clock stop and wake operations
          2. 25.4.1.6.2 DCAN debug suspend operation
        7. 25.4.1.7 Test Modes
          1. 25.4.1.7.1 External Loop Back Mode
          2. 25.4.1.7.2 Internal Loop Back Mode
      2. 25.4.2 Timestamp Generation
        1. 25.4.2.1 Block Diagram
      3. 25.4.3 Timeout Counter
      4. 25.4.4 Rx Handling
        1. 25.4.4.1 Acceptance Filtering
          1. 25.4.4.1.1 Range Filter
          2. 25.4.4.1.2 Filter for specific IDs
          3. 25.4.4.1.3 Classic Bit Mask Filter
          4. 25.4.4.1.4 Standard Message ID Filtering
          5. 25.4.4.1.5 Extended Message ID Filtering
        2. 25.4.4.2 Rx FIFOs
          1. 25.4.4.2.1 Rx FIFO Blocking Mode
          2. 25.4.4.2.2 Rx FIFO Overwrite Mode
        3. 25.4.4.3 Dedicated Rx Buffers
          1. 25.4.4.3.1 Rx Buffer Handling
        4. 25.4.4.4 Debug on CAN Support
          1. 25.4.4.4.1 Filtering for Debug Messages
          2. 25.4.4.4.2 Debug Message Handling
      5. 25.4.5 Tx Handling
        1. 25.4.5.1 Transmit Pause
        2. 25.4.5.2 Dedicated Tx Buffers
        3. 25.4.5.3 Tx FIFO
        4. 25.4.5.4 Tx Queue
        5. 25.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 25.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 25.4.5.7 Transmit Cancellation
        8. 25.4.5.8 Tx Event Handling
      6. 25.4.6 FIFO Acknowledge Handling
      7. 25.4.7 DCAN Message RAM
        1. 25.4.7.1 Message RAM Configuration
        2. 25.4.7.2 Rx Buffer and FIFO Element
        3. 25.4.7.3 Tx Buffer Element
        4. 25.4.7.4 Tx Event FIFO Element
        5. 25.4.7.5 Standard Message ID Filter Element
        6. 25.4.7.6 Extended Message ID Filter Element
      8. 25.4.8 Interrupt Requests
    5. 25.5 DCAN Wrapper
    6. 25.6 DCAN Clock Enable
    7. 25.7 DCAN Registers
  27. 26Revision History

22.10 I2S Registers

Table 22-1 lists the memory-mapped registers for the I2S registers. All register offset addresses not listed in Table 22-1 should be considered as reserved locations and the register contents should not be modified.

Table 22-1 I2S Registers
OffsetAcronymRegister NameSection
0hAIFWCLKSRCWordclock Source SelectionSection 22.10.1
4hAIFDMACFGDMA Buffer Size ConfigurationSection 22.10.2
8hAIFDIRCFGPin Direction ConfigurationSection 22.10.3
ChAIFFMTCFGFormat ConfigurationSection 22.10.4
10hAIFWMASK0Word Selection MaskSection 22.10.5
14hAIFWMASK1Audio Input MaskSection 22.10.6
20hAIFINPTNXTInput Buffer PointerSection 22.10.7
24hAIFINPTRInput Buffer PointerSection 22.10.8
28hAIFOPTNXTOutput Buffer PointerSection 22.10.9
2ChAIFOUTPTROutput Buffer PointerSection 22.10.10
34hSTMPCTLTimestamp ControlSection 22.10.11
38hSTMPXCPT0Capture Value Ch0Section 22.10.12
3ChSTMPXPERCrystal Oscillator PeriodSection 22.10.13
40hSTMPWCPT0Clock Counter CaptureSection 22.10.14
44hSTMPWPERClock Counter PeriodSection 22.10.15
48hSTMPINTRIGWord Clock Counter ValueSection 22.10.16
4ChSTMPOTRIGOutput Trigger ValueSection 22.10.17
50hSTMPWSETTimestamp SetSection 22.10.18
54hSTMPWADDClock Counter AddSection 22.10.19
58hSTMPXPRMINOscillator Minimum PeriodSection 22.10.20
5ChSTMPWCNTWatch Counter ValueSection 22.10.21
60hSTMPXCNTX Counter ValueSection 22.10.22
70hIRQMASKInterrupt MaskSection 22.10.23
74hIRQFLAGSInterrupt StatusSection 22.10.24
78hIRQSETInterrupt SetSection 22.10.25
7ChIRQCLRInterrupt ClearSection 22.10.26
80hAIFMCLKDIVMain Clock DividerSection 22.10.27
84hAIFBCLKDIVBit Clock DividerSection 22.10.28
88hAIFWCLKDIVWCLK Division RatioSection 22.10.29
8ChAIFCLKCTLInternal Audio Clock ControlSection 22.10.30
1000hCLKCFGClock ConfigurationSection 22.10.31
1004hADFSCTRL1Reference Time ControlSection 22.10.32
1008hADFSCTRL2Configuration ControlSection 22.10.33

Complex bit access types are encoded to fit into small table cells. Table 22-2 shows the codes that are used for access types in this section.

Table 22-2 I2S Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

22.10.1 AIFWCLKSRC Register (Offset = 0h) [Reset = 00000000h]

AIFWCLKSRC is shown in Table 22-3.

Return to the Summary Table.

WCLK Source Selection

Table 22-3 AIFWCLKSRC Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2WCLKINVR/W0hInverts **WCLK** source (pad or internal) when set. 0: Not inverted 1: Inverted
1-0WBCLKSRCR/W0hSelects **WCLK**/**BCLK** source for **AIF**.
  • 0h = None ('0')
  • 1h = External **WCLK** generator, from pad
  • 2h = Internal **WCLK** generator, from module PRCM
  • 3h = Not supported. Will give same **WCLK** as 'NONE' ('00')

22.10.2 AIFDMACFG Register (Offset = 4h) [Reset = 00000000h]

AIFDMACFG is shown in Table 22-4.

Return to the Summary Table.

DMA Buffer Size Configuration

Table 22-4 AIFDMACFG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0ENDFRAMIDXR/W0hDefines the length of the DMA buffer. Writing a non-zero value to this register field enables and initializes AIF. Note that before doing so, all other configuration must have been done, and [AIFINPTRNEXT.*]/[AIFOUTPTRNEXT.*] must have been loaded.

22.10.3 AIFDIRCFG Register (Offset = 8h) [Reset = 00000000h]

AIFDIRCFG is shown in Table 22-5.

Return to the Summary Table.

Pin Direction

Table 22-5 AIFDIRCFG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-6RESERVEDR0hReserved
5-4AD1R/W0hConfigures the **AD1** audio data pin usage: 0x3: Reserved
  • 0h = Not in use (disabled)
  • 1h = Input mode
  • 2h = Output mode
3-2RESERVEDR0hReserved
1-0AD0R/W0hConfigures the **AD0** audio data pin usage: 0x3: Reserved
  • 0h = Not in use (disabled)
  • 1h = Input mode
  • 2h = Output mode

22.10.4 AIFFMTCFG Register (Offset = Ch) [Reset = 00000000h]

AIFFMTCFG is shown in Table 22-6.

Return to the Summary Table.

Serial Interface Format Configuration

Table 22-6 AIFFMTCFG Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8DATADELAYR/W1hThe number of **BCLK** periods between a **WCLK** edge and **MSB** of the first word in a phase: 0x00: **LJF** and **DSP** format 0x01: **I2S** and **DSP** format 0x02: **RJF** format ... 0xFF: **RJF** format Note: When 0, **MSB** of the next word will be output in the idle period between **LSB** of the previous word and the start of the next word. Otherwise logical 0 will be output until the data delay has expired.
7LEN32R/W0hThe size of each word stored to or loaded from memory:
  • 0h = 16BIT : 16-bit (one 16 bit access per sample)
  • 1h = 32BIT : 32-bit(one 32-bit access per sample)
6SMPLEDGER/W1hOn the serial audio interface, data (and wclk) is sampled and clocked out on opposite edges of BCLK.
  • 0h = Data is sampled on the negative edge and clocked out on the positive edge.
  • 1h = Data is sampled on the positive edge and clocked out on the negative edge.
5DUALPHASER/W1hSelects dual- or single-phase format. 0: Single-phase: **DSP** format 1: Dual-phase: **I2S**, **LJF** and **RJF** formats
4-0WORDLENR/W10hNumber of bits per word (8-24): In single-phase format, this is the exact number of bits per word. In dual-phase format, this is the maximum number of bits per word. Values below 8 and above 24 give undefined behavior. Data written to memory is always aligned to 16 or 24 bits as defined by [MEM_LEN_24]. Bit widths that differ from this alignment will either be truncated or zero padded.

22.10.5 AIFWMASK0 Register (Offset = 10h) [Reset = 00000000h]

AIFWMASK0 is shown in Table 22-7.

Return to the Summary Table.

Word Selection Bit Mask for Pin 0

Table 22-7 AIFWMASK0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0MASKR/W3hBit-mask indicating valid channels in a frame on AD0. In single-phase mode, each bit represents one channel, starting with **LSB** for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'. In dual-phase mode, only the two **LSB**s are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out. If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when **PWM** debug output is desired without any actively used output pins.

22.10.6 AIFWMASK1 Register (Offset = 14h) [Reset = 00000000h]

AIFWMASK1 is shown in Table 22-8.

Return to the Summary Table.

Word Selection Bit Mask for Pin 1

Table 22-8 AIFWMASK1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0MASKR/W3hBit-mask indicating valid channels in a frame on AD1. In single-phase mode, each bit represents one channel, starting with **LSB** for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'. In dual-phase mode, only the two **LSB**s are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out. If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when **PWM** debug output is desired without any actively used output pins.

22.10.7 AIFINPTNXT Register (Offset = 20h) [Reset = 00000000h]

AIFINPTNXT is shown in Table 22-9.

Return to the Summary Table.

DMA Input Buffer Next Pointer

Table 22-9 AIFINPTNXT Register Field Descriptions
BitFieldTypeResetDescription
31-0PTRR/W0hPointer to the first byte in the next **DMA** input buffer. The read value equals the last written value until the currently used **DMA** input buffer is completed, and then becomes null when the last written value is transferred to the **DMA** controller to start on the next buffer. This event is signalized by [IRQFLAGS-AIF_DMA_IN]. At startup, the value must be written once before and once after configuring the **DMA** buffer size in [AIFDMACFG.*]. The next pointer must be written to this register while the **DMA** function uses the previously written pointer. If not written in time, PTRERR will be raised and all input pins will be disabled.

22.10.8 AIFINPTR Register (Offset = 24h) [Reset = 00000000h]

AIFINPTR is shown in Table 22-10.

Return to the Summary Table.

DMA Input Buffer Current Pointer

Table 22-10 AIFINPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0PTRR0hValue of the **DMA** input buffer pointer currently used by the **DMA** controller. Incremented by 1 (byte) or 2 (word) for each **AHB** access.

22.10.9 AIFOPTNXT Register (Offset = 28h) [Reset = 00000000h]

AIFOPTNXT is shown in Table 22-11.

Return to the Summary Table.

DMA Output Buffer Next Pointer

Table 22-11 AIFOPTNXT Register Field Descriptions
BitFieldTypeResetDescription
31-0PTRR/W0hPointer to the first byte in the next **DMA** output buffer. The read value equals the last written value until the currently used **DMA** output buffer is completed, and then becomes null when the last written value is transferred to the **DMA** controller to start on the next buffer. This event is signalized by AIFDMAOUT. At startup, the value must be written once before and once after configuring the **DMA** buffer size in [AIFDMACFG.*]. At this time, the first two samples will be fetched from memory. The next pointer must be written to this register while the **DMA** function uses the previously written pointer. If not written in time, PTRERR will be raised and all output pins will be disabled.

22.10.10 AIFOUTPTR Register (Offset = 2Ch) [Reset = 00000000h]

AIFOUTPTR is shown in Table 22-12.

Return to the Summary Table.

DMA Output Buffer Current Pointer

Table 22-12 AIFOUTPTR Register Field Descriptions
BitFieldTypeResetDescription
31-0PTRR0hValue of the **DMA** output buffer pointer currently used by the **DMA** controller Incremented by 1 (byte) or 2 (word) for each **AHB** access.

22.10.11 STMPCTL Register (Offset = 34h) [Reset = 00000000h]

STMPCTL is shown in Table 22-13.

Return to the Summary Table.

Samplestamp Generator Control Register

Table 22-13 STMPCTL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2OUTRDYR0hLow until the output pins are ready to be started by the samplestamp generator. When started (that is [STMPOUTTRIG.*] equals the **WCLK** counter) the bit goes back low.
1INRDYR0hLow until the input pins are ready to be started by the samplestamp generator. When started (that is [STMPINTRIG.*] equals the **WCLK** counter) the bit goes back low.
0STMPENR/W0hEnables the samplestamp generator. The samplestamp generator must only be enabled after it has been properly configured. When cleared, all samplestamp generator counters and capture values are cleared.

22.10.12 STMPXCPT0 Register (Offset = 38h) [Reset = 00000000h]

STMPXCPT0 is shown in Table 22-14.

Return to the Summary Table.

Captured **XOSC** Counter Value, Capture Channel 0

Table 22-14 STMPXCPT0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CAPTVALR0hThe value of the samplestamp **XOSC** counter (CURRVAL) last time an event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for channel 0). This number corresponds to the number of 24 MHz clock cycles since the last positive edge of the selected **WCLK**. The value is cleared when STMPEN = 0. Note: Due to buffering and synchronization, **WCLK** is delayed by a small number of **BCLK** periods and clk periods. Note: When calculating the fractional part of the sample stamp, [STMPXPER.*] may be less than this bit field.

22.10.13 STMPXPER Register (Offset = 3Ch) [Reset = 00000000h]

STMPXPER is shown in Table 22-15.

Return to the Summary Table.

XOSC Period Value

Table 22-15 STMPXPER Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUER0hThe number of 24 MHz clock cycles in the previous **WCLK** period (that is - the next value of the **XOSC** counter at the positive **WCLK** edge, had it not been reset to 0). The value is cleared when STMPEN = 0.

22.10.14 STMPWCPT0 Register (Offset = 40h) [Reset = 00000000h]

STMPWCPT0 is shown in Table 22-16.

Return to the Summary Table.

Captured **WCLK** Counter Value, Capture Channel 0

Table 22-16 STMPWCPT0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CAPTVALR0hThe value of the samplestamp **WCLK** counter (CURRVAL) last time an event was pulsed (event source selected in [EVENT:I2SSTMPSEL0.EV] for channel 0). This number corresponds to the number of positive **WCLK** edges since the samplestamp generator was enabled (not taking modification through [STMPWADD.*]/[STMPWSET.*] into account). The value is cleared when STMPEN = 0.

22.10.15 STMPWPER Register (Offset = 44h) [Reset = 00000000h]

STMPWPER is shown in Table 22-17.

Return to the Summary Table.

**WCLK** Counter Period Value

Table 22-17 STMPWPER Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUER/W0hUsed to define when [STMPWCNT.*] is to be reset so number of **WCLK** edges are found for the size of the sample buffer. This is thus a modulo value for the **WCLK** counter. This number must correspond to the size of the sample buffer used by the system (that is the index of the last sample plus 1).

22.10.16 STMPINTRIG Register (Offset = 48h) [Reset = 00000000h]

STMPINTRIG is shown in Table 22-18.

Return to the Summary Table.

WCLK Counter Trigger Value for Input Pins

Table 22-18 STMPINTRIG Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0INSTRTWCNTR/W0hCompare value used to start the incoming audio streams. This bit field shall equal the **WCLK** counter value during the **WCLK** period in which the first input word(s) are sampled and stored to memory (that is the sample at the start of the very first **DMA** input buffer). The value of this register takes effect when the following conditions are met: - One or more pins are configured as inputs in [AIFDIRCFG.*]. - [AIFDMACFG.*] has been configured for the correct buffer size, and at least 32 **BCLK** cycle ticks have happened. Note: To avoid false triggers, this bit field should be set higher than VALUE.

22.10.17 STMPOTRIG Register (Offset = 4Ch) [Reset = 00000000h]

STMPOTRIG is shown in Table 22-19.

Return to the Summary Table.

WCLK Counter Trigger Value for Output Pins

Table 22-19 STMPOTRIG Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0OSTRTWCNTR/W0hOUT START WCNT: Compare value used to start the outgoing audio streams. This bit field must equal the **WCLK** counter value during the **WCLK** period in which the first output word(s) read from memory are clocked out (that is the sample at the start of the very first **DMA** output buffer). The value of this register takes effect when the following conditions are met: - One or more pins are configured as outputs in [AIFDIRCFG.*]. - [AIFDMACFG.*] has been configured for the correct buffer size, and 32 **BCLK** cycle ticks have happened. - 2 samples have been preloaded from memory (examine the [AIFOUTPTR.*] register if necessary). Note: The memory read access is only performed when required, that is channels 0/1 must be selected in [AIFWMASK0.*]/[AIFWMASK1.*]. Note: To avoid false triggers, this bit field should be set higher than VALUE.

22.10.18 STMPWSET Register (Offset = 50h) [Reset = 00000000h]

STMPWSET is shown in Table 22-20.

Return to the Summary Table.

WCLK Counter Set Operation

Table 22-20 STMPWSET Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUEW0h**WCLK** counter modification: Sets the running **WCLK** counter equal to the written value.

22.10.19 STMPWADD Register (Offset = 54h) [Reset = 00000000h]

STMPWADD is shown in Table 22-21.

Return to the Summary Table.

WCLK Counter Add Operation

Table 22-21 STMPWADD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALINCW0h**WCLK** counter modification: Adds the written value to the running **WCLK** counter. If a positive edge of **WCLK** occurs at the same time as the operation, this will be taken into account. To add a negative value, write 'VALUE - value'.

22.10.20 STMPXPRMIN Register (Offset = 58h) [Reset = 00000000h]

STMPXPRMIN is shown in Table 22-22.

Return to the Summary Table.

XOSC Minimum Period Value Minimum Value of [STMPXPER.*]

Table 22-22 STMPXPRMIN Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUER/WFFFFhEach time [STMPXPER.*] is updated, the value is also loaded into this register, provided that the value is smaller than the current value in this register. When written, the register is reset to 0xFFFF (65535), regardless of the value written. The minimum value can be used to detect extra **WCLK** pulses (this registers value will be significantly smaller than VALUE).

22.10.21 STMPWCNT Register (Offset = 5Ch) [Reset = 00000000h]

STMPWCNT is shown in Table 22-23.

Return to the Summary Table.

Current Value of WCNT

Table 22-23 STMPWCNT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CURRVALR0hCurrent value of the **WCLK** counter

22.10.22 STMPXCNT Register (Offset = 60h) [Reset = 00000000h]

STMPXCNT is shown in Table 22-24.

Return to the Summary Table.

Current Value of XCNT

Table 22-24 STMPXCNT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CURRVALR0hCurrent value of the **XOSC** counter, latched when reading [STMPWCNT.*].

22.10.23 IRQMASK Register (Offset = 70h) [Reset = 00000000h]

IRQMASK is shown in Table 22-25.

Return to the Summary Table.

Interrupt Mask Register Selects mask states of the flags in [IRQFLAGS.*] that contribute to the **I2S_IRQ** event.

Table 22-25 IRQMASK Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6XCNTCPTR/W0hXCNTCPT interrupt mask 0: Disable 1: Enable
5AIFDMAINR/W0hAIFDMAIN interrupt mask 0: Disable 1: Enable
4AIFDMAOUTR/W0hAIFDMAOUT interrupt mask 0: Disable 1: Enable
3WCLKTOUTR/W0hWCLKTOUT interrupt mask 0: Disable 1: Enable
2BUSERRR/W0hBUSERR interrupt mask 0: Disable 1: Enable
1WCLKERRR/W0hWCLKERR interrupt mask 0: Disable 1: Enable
0PTRERRR/W0hPTRERR interrupt mask. 0: Disable 1: Enable

22.10.24 IRQFLAGS Register (Offset = 74h) [Reset = 00000000h]

IRQFLAGS is shown in Table 22-26.

Return to the Summary Table.

Raw Interrupt Status Register

Table 22-26 IRQFLAGS Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6XCNTCPTR0hWill be set when xcnt counter is captured either by events or software. Needs to be cleared by software.
5AIFDMAINR0hSet when condition for this bit field event occurs (auto cleared when input pointer is updated - [AIFINPTRNEXT.*]), see description of [AIFINPTRNEXT.*] register for details.
4AIFDMAOUTR0hSet when condition for this bit field event occurs (auto cleared when output pointer is updated - [AIFOUTPTRNEXT.*]), see description of [AIFOUTPTRNEXT.*] register for details
3WCLKTOUTR0hSet when the sample stamp generator does not detect a positive **WCLK** edge for 65535 clk periods. This signalizes that the internal or external **BCLK** and **WCLK** generator source has been disabled. The bit is sticky and may only be cleared by software (by writing '1' to WCLKTOUT).
2BUSERRR0hSet when a **DMA** operation is not completed in time (that is audio output buffer underflow, or audio input buffer overflow). This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to BUSERR). Note that DMA initiated transactions to illegal addresses will not trigger an interrupt. The response to such transactions is undefined. INTERNAL_NOTE: The I2S module is not monitoring the AHB bus error response, hence bus faults resulting from access to illegal addresses are not generated. It is best practice to detect and report such errors and, therefore, a ticket has been entered into the CDDS bug tracking database for the I2S module. The reference is CC26_I2S--BUG00011. All versions of CC13xx/CC26xx Chameleon and Lizard are impacted, and there is no plans to change this behavior.
1WCLKERRR0hSet when: - An unexpected **WCLK** edge occurs during the data delay period of a phase. Note unexpected **WCLK** edges during the word and idle periods of the phase are not detected. - In dual-phase mode, when two **WCLK** edges are less than 4 **BCLK** cycles apart. - In single-phase mode, when a **WCLK** pulse occurs before the last channel. This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to WCLKERR).
0PTRERRR0hSet when [AIFINPTRNEXT.*] or [AIFOUTPTRNEXT.*] has not been loaded with the next block address in time. This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to PTRERR).

22.10.25 IRQSET Register (Offset = 78h) [Reset = 00000000h]

IRQSET is shown in Table 22-27.

Return to the Summary Table.

Interrupt Set Register

Table 22-27 IRQSET Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6XCNTCPTW0h1: Sets the interrupt of XCNTCPT (unless a auto clear criteria was given at the same time, in which the set will be ignored)
5AIFDMAINW0h1: Sets the interrupt of AIFDMAIN (unless a auto clear criteria was given at the same time, in which the set will be ignored)
4AIFDMAOUTW0h1: Sets the interrupt of AIFDMAOUT (unless a auto clear criteria was given at the same time, in which the set will be ignored)
3WCLKTOUTW0h1: Sets the interrupt of WCLKTOUT
2BUSERRW0h1: Sets the interrupt of BUSERR
1WCLKERRW0h1: Sets the interrupt of WCLKERR
0PTRERRW0h1: Sets the interrupt of PTRERR

22.10.26 IRQCLR Register (Offset = 7Ch) [Reset = 00000000h]

IRQCLR is shown in Table 22-28.

Return to the Summary Table.

Interrupt Clear Register

Table 22-28 IRQCLR Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6XCNTCPTW0h1: Clears the interrupt of XCNTCPT (unless a set criteria was given at the same time in which the clear will be ignored)
5AIFDMAINW0h1: Clears the interrupt of AIFDMAIN (unless a set criteria was given at the same time in which the clear will be ignored)
4AIFDMAOUTW0h1: Clears the interrupt of AIFDMAOUT (unless a set criteria was given at the same time in which the clear will be ignored)
3WCLKTOUTW0h1: Clears the interrupt of WCLKTOUT (unless a set criteria was given at the same time in which the clear will be ignored)
2BUSERRW0h1: Clears the interrupt of BUSERR (unless a set criteria was given at the same time in which the clear will be ignored)
1WCLKERRW0h1: Clears the interrupt of WCLKERR (unless a set criteria was given at the same time in which the clear will be ignored)
0PTRERRW0h1: Clears the interrupt of PTRERR (unless a set criteria was given at the same time in which the clear will be ignored)

22.10.27 AIFMCLKDIV Register (Offset = 80h) [Reset = 00000000h]

AIFMCLKDIV is shown in Table 22-29.

Return to the Summary Table.

**MCLK** Division Ratio

Table 22-29 AIFMCLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-0MDIVR/W0h An unsigned factor of the division ratio used to generate **MCLK** [2-1024]: **MCLK** = MCUCLK/MDIV[Hz] **MCUCLK** is upto 96MHz. A value of 0 is interpreted as 1024. A value of 1 is invalid. If MDIV is odd the low phase of the clock is one **MCUCLK** period longer than the high phase.

22.10.28 AIFBCLKDIV Register (Offset = 84h) [Reset = 00000000h]

AIFBCLKDIV is shown in Table 22-30.

Return to the Summary Table.

**BCLK** Division Ratio

Table 22-30 AIFBCLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-0BDIVR/W0h An unsigned factor of the division ratio used to generate **BCLK** [2-1024]: **BCLK** = MCUCLK/BDIV[Hz] **MCUCLK** can be upto 96MHz. A value of 0 is interpreted as 1024. A value of 1 is invalid. If BDIV is odd and [AIFCLKCTL.SMPL_ON_POSEDGE.*] = 0, the low phase of the clock is one **MCUCLK** period longer than the high phase. If BDIV is odd and [AIFCLKCTL.SMPL_ON_POSEDGE.*] = 1 , the high phase of the clock is one **MCUCLK** period longer than the low phase.

22.10.29 AIFWCLKDIV Register (Offset = 88h) [Reset = 00000000h]

AIFWCLKDIV is shown in Table 22-31.

Return to the Summary Table.

**WCLK** Division Ratio

Table 22-31 AIFWCLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0WDIVR/W0h If WCLKPHASE = 0, Single phase. **WCLK** is high one **BCLK** period and low WDIV[9:0] (unsigned, [1-1023]) **BCLK** periods. **WCLK** = **MCUCLK** / BDIV*(WDIV[9:0] + 1) [Hz] **MCUCLK** upto 96MHz. If WCLKPHASE = 1, Dual phase. Each phase on **WCLK** (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) **BCLK** periods. **WCLK **= **MCUCLK **/ BDIV*(2*WDIV[9:0]) [Hz] If WCLKPHASE = 2, User defined. **WCLK** is high WDIV[7:0] (unsigned, [1-255]) **BCLK** periods and low WDIV[15:8] (unsigned, [1-255]) **BCLK** periods. **WCLK** = **MCUCLK **/ (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz]

22.10.30 AIFCLKCTL Register (Offset = 8Ch) [Reset = 00000000h]

AIFCLKCTL is shown in Table 22-32.

Return to the Summary Table.

Internal Audio Clock Control

Table 22-32 AIFCLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3MENR/W0h0: **MCLK** geneartion disabled, 1: **MCLK** generation enabled
2-1WCLKPHASER/W0hDecides how the WCLK division ratio is calculated and used to generate different duty cycles (See WDIV).
0WBENR/W0h0: WCLK/BCLK geneartion disabled, 1: WCLK/BCLK generation enabled

22.10.31 CLKCFG Register (Offset = 1000h) [Reset = 00000000h]

CLKCFG is shown in Table 22-33.

Return to the Summary Table.

Audio clock source selection and **I2S** enable register Note: Disable the [CLKCFG.MEM_CLK_EN] and [CLKCFG.ADFS_EN] to change CLKSEL After changing CLKSEL, enable [CLKCFG.ADFS_EN] followed by [CLKCFG.MEM_CLK_EN]

Table 22-33 CLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7ADFSENR/W0hADFS enable field
6-4CLKSELR/W0hAudio clock selection
  • 0h = No Clock
  • 1h = SOC Clock(80MHz)
  • 2h = SOC PLL Clock(un-swallowed 80MHz)
  • 3h = HFXT
3-1RESERVEDR0hReserved
0ENR/W0h 0: **I2S** clock disabled 1: **I2S** clock enabled

22.10.32 ADFSCTRL1 Register (Offset = 1004h) [Reset = 00000000h]

ADFSCTRL1 is shown in Table 22-34.

Return to the Summary Table.

ADFS TREF control register

Table 22-34 ADFSCTRL1 Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0hReserved
20-0TREFR/W0hTREF value for ADFS

22.10.33 ADFSCTRL2 Register (Offset = 1008h) [Reset = 00000000h]

ADFSCTRL2 is shown in Table 22-35.

Return to the Summary Table.

ADFS general configuration register

Table 22-35 ADFSCTRL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-20DIVR/W0hADFS div value field
19-18RESERVEDR0hReserved
17DELTASIGNR/W0hADFS delta sign field
16-0DELTAR/W0hADFS delta value field