SWRU626 December   2025 CC3501E , CC3551E

 

  1.   1
  2. 1 Read This First
    1. 1.1 About This Manual
    2. 1.2 Register, Field, and Bit Calls
    3.     Trademarks
  3. 2 Architecture Overview
    1. 2.1  Target Applications
    2. 2.2  Introduction
    3. 2.3  Internal System Diagram
    4. 2.4  Arm Cortex M33
      1. 2.4.1 Processor Core
      2. 2.4.2 SysTick Timer
      3. 2.4.3 Nested Vectored Interrupt Controller
      4. 2.4.4 System Control Block (SCB)
      5. 2.4.5 TI AI instruction extensions
    5. 2.5  Power Management
      1. 2.5.1 VDD_MAIN
      2. 2.5.2 VDD_IO
      3. 2.5.3 VDDSF
      4. 2.5.4 VDD_PA
    6. 2.6  Debug Subsystem (DEBUGSS)
    7. 2.7  Memory Subsystem (MEMSS)
      1. 2.7.1 External Memory Interface
    8. 2.8  Hardware Security Module
    9. 2.9  General Purpose Timers (GPT)
    10. 2.10 Real Time Clock (RTC)
    11. 2.11 Direct Memory Access
    12. 2.12 GPIOs
    13. 2.13 Communication Peripherals
      1. 2.13.1 UART
      2. 2.13.2 I2C
      3. 2.13.3 SPI
      4. 2.13.4 I2S
      5. 2.13.5 SDMMC
      6. 2.13.6 SDIO
      7. 2.13.7 CAN
      8. 2.13.8 ADC
  4. 3  Arm Cortex-M33 Processor
    1. 3.1 Arm Cortex-M33 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 M33 instantiation parameters
    4. 3.4 Arm Cortex-M33 System Peripheral Details
      1. 3.4.1 Floating Point Unit (FPU)
      2. 3.4.2 Memory Protection Unit (MPU)
      3. 3.4.3 Digital Signal Processing (DSP)
      4. 3.4.4 Security Attribution Unit (SAU)
      5. 3.4.5 System Timer
      6. 3.4.6 Nested Vectored Interrupt Controller
      7. 3.4.7 System Control Block
      8. 3.4.8 System Control Space
    5. 3.5 CPU Sub-System Peripheral Details
      1. 3.5.1 Trace Port Interface Unit (TPIU)
      2. 3.5.2 DAP Bridge and Debug Authentication
      3. 3.5.3 Implementation Defined Attribution Unit (IDAU)
    6. 3.6 Programming Model
      1. 3.6.1 Modes of operation and execution
        1. 3.6.1.1 Security states
        2. 3.6.1.2 Operating modes
        3. 3.6.1.3 Operating states
        4. 3.6.1.4 Privileged access and unprivileged user access
      2. 3.6.2 Instruction set summary
      3. 3.6.3 Memory model
        1. 3.6.3.1 Private Peripheral Bus
        2. 3.6.3.2 Unaligned accesses
      4. 3.6.4 Processor core registers summary
      5. 3.6.5 Exceptions
        1. 3.6.5.1 Exception handling and prioritization
    7. 3.7 TrustZone-M
      1. 3.7.1 Overview
      2. 3.7.2 M33 Configuration
      3. 3.7.3 Description of elements
        1. 3.7.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 3.7.3.1.1 Expected use
    8. 3.8 CC35xx Host MCU Registers
      1. 3.8.1 HOSTMCU_AON Registers
      2. 3.8.2 HOST_MCU Registers
      3. 3.8.3 HOST_MCU_SEC Registers
    9. 3.9 Arm® Cortex®-M33 Registers
      1. 3.9.1  CPU_ROM_TABLE Registers
      2. 3.9.2  TPIU Registers
      3. 3.9.3  DCB Registers
      4. 3.9.4  DIB Registers
      5. 3.9.5  DWT Registers
      6. 3.9.6  FPB Registers
      7. 3.9.7  FPE Registers
      8. 3.9.8  ICB Registers
      9. 3.9.9  ITM Registers
      10. 3.9.10 MPU Registers
      11. 3.9.11 NVIC Registers
      12. 3.9.12 SAU Registers
      13. 3.9.13 SCB Registers
      14. 3.9.14 SYSTIMER Registers
      15. 3.9.15 SYSTICK Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation to HardFault
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Manager
      1. 5.4.1 Introduction
      2. 5.4.2 Interrupts List
      3. 5.4.3 Wakeup Sources
      4. 5.4.4 Shared Peripherals MUX Selector
        1. 5.4.4.1 ADC HW Event Selector Mux
        2. 5.4.4.2 I2S HW Event Selector Mux
        3. 5.4.4.3 PDM HW Event Selector Mux
      5. 5.4.5 Timers MUX Selector Mux
        1. 5.4.5.1 SysTimer0 HW Event Selector Mux
        2. 5.4.5.2 SysTimer1 HW Event Selector Mux
        3. 5.4.5.3 RTC HW Event Selector Mux
      6. 5.4.6 GPTIMERs MUX Selector Mux
        1. 5.4.6.1 GPTIMER0 HW Event Selector Mux
        2. 5.4.6.2 GPTIMER1 HW Event Selector Mux
    5. 5.5 SOC_IC Registers
    6. 5.6 SOC_AON Registers
    7. 5.7 SOC_AAON Registers
  7. 6 Debug Subsystem (DEBUGSS)
    1. 6.1 Introduction
    2. 6.2 Block Diagram
    3. 6.3 Overview
    4. 6.4 Physical Interface
    5. 6.5 Debug Access Ports
    6. 6.6 Debug Features
      1. 6.6.1 Processor Debug
      2. 6.6.2 Breakpoint Unit (BPU)
      3. 6.6.3 Peripheral Debug
    7. 6.7 Behavior in Low Power Modes
    8. 6.8 Debug Access Control
    9. 6.9 SOC_DEBUGSS Registers
  8. 7 Power, Reset, Clock Management
    1. 7.1 Power Management
      1. 7.1.1 Power Supply System
        1. 7.1.1.1 VDD_MAIN
        2. 7.1.1.2 VIO
        3. 7.1.1.3 VDDSF
        4. 7.1.1.4 VPA
      2. 7.1.2 Power States
      3. 7.1.3 Power Domains
      4. 7.1.4 Brownout (BOR)
      5. 7.1.5 Boot Sequence
    2. 7.2 Reset
      1. 7.2.1 Reset Cause
      2. 7.2.2 Watchdog Timer (WDT)
    3. 7.3 Clocks
      1. 7.3.1 Fast Clock
      2. 7.3.2 Slow Clock
        1. 7.3.2.1 Slow Clock Overview
        2. 7.3.2.2 Slow Clock Tree
        3. 7.3.2.3 Slow Clock Boot Process
    4. 7.4 PRCM_AON Registers
    5. 7.5 PRCM_SCRATCHPAD Registers
  9. 8 Memory Subsystem (MEMSS)
    1. 8.1  Introduction
    2. 8.2  SRAM
    3. 8.3  D-Cache
    4. 8.4  Flash
    5. 8.5  PSRAM
    6. 8.6  XiP Memory Access
      1. 8.6.1 OTFDE
      2. 8.6.2 xSPI
      3. 8.6.3 Topology
      4. 8.6.4 µDMA
      5. 8.6.5 Arbiter
    7. 8.7  ICACHE Registers
    8. 8.8  DCACHE Registers
    9. 8.9  OSPI Registers
    10. 8.10 HOST_XIP Registers
  10. 9 Hardware Security Module (HSM)
    1. 9.1 Introduction
    2. 9.2 Overview
    3. 9.3 Mailbox and Register Access Firewall
    4. 9.4 DMA Firewall
    5. 9.5 HSM Key Storage
    6. 9.6 HSM Registers
    7. 9.7 HSM_NON_SEC Registers
    8. 9.8 HSM_SEC Registers
  11. 10Device Boot and Bootloader
    1. 10.1 CC35xx Boot Concept
    2. 10.2 Features
    3. 10.3 Vendor Images Format and Processing
      1. 10.3.1 External Flash Arrangement
      2. 10.3.2 Vendor Images Format
    4. 10.4 Boot Flows
      1. 10.4.1 Application Execution Boot Flow
      2. 10.4.2 Activation Flow
      3. 10.4.3 Initial Programming Flow
      4. 10.4.4 Reprogramming Flow
      5. 10.4.5 Wireless Connectivity Testing Tool Flow
    5. 10.5 Chain of Trust
  12. 11Direct Memory Access (DMA)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Channels Assignment
      2. 11.3.2 Transfer Types
      3. 11.3.3 Addressing Modes
      4. 11.3.4 Transfer Modes
      5. 11.3.5 DMA Aligner Support
      6. 11.3.6 Initiating DMA Transfers
      7. 11.3.7 Stopping DMA Transfers
      8. 11.3.8 Channel Priorities
      9. 11.3.9 DMA Interrupts
    4. 11.4 HOST_DMA Registers
  13. 12One Time Programming (OTP)
  14. 13General Purpose Timers (GPT)
    1. 13.1 Overview
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1  Prescaler
      2. 13.3.2  Counter
      3. 13.3.3  Target
      4. 13.3.4  Channel Input Logic
      5. 13.3.5  Channel Output Logic
      6. 13.3.6  Channel Actions
        1. 13.3.6.1 Period and Pulse Width Measurement
        2. 13.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 13.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 13.3.7  Channel Capture Configuration
      8. 13.3.8  Channel Filters
        1. 13.3.8.1 Setting up the Channel Filters
      9. 13.3.9  Synchronize Multiple GPTimers
      10. 13.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 13.4 Timer Modes
      1. 13.4.1 Quadrature Decoder
      2. 13.4.2 DMA
      3. 13.4.3 IR Generation
      4. 13.4.4 Fault and Park
      5. 13.4.5 Dead-Band
      6. 13.4.6 Dead-Band, Fault and Park
      7. 13.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 13.5 GPTIMER Registers
  15. 14System Timer (SysTimer)
    1. 14.1 Overview
    2. 14.2 Block Diagram
    3. 14.3 Functional Description
      1. 14.3.1 Common Channel Features
        1. 14.3.1.1 Compare Mode
        2. 14.3.1.2 Capture Mode
        3. 14.3.1.3 Additional Channel Arming Methods
      2. 14.3.2 Interrupts and Events
    4. 14.4 SYSRESOURCES Registers
    5. 14.5 SYSTIM Registers
  16. 15Real-Time Clock (RTC)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Interrupts and Events
      1. 15.3.1 Input Event
      2. 15.3.2 Output Event
      3. 15.3.3 Arming and Disarming Channels
    4. 15.4 CAPTURE and COMPARE Configurations
      1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
    5. 15.5 RTC Registers
  17. 16General Purpose Input/Output (GPIOs)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 I/O Mapping and Configuration
      1. 16.3.1 Basic I/O Mapping
      2. 16.3.2 Pin Mapping
    4. 16.4 Edge Detection
    5. 16.5 GPIO
    6. 16.6 I/O Pins
    7. 16.7 Unused Pins
    8. 16.8 IOMUX Registers
  18. 17Universal Asynchronous Receivers/Transmitters (UART)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 UART Functional Description
      1. 17.3.1 Transmit and Receive Logic
      2. 17.3.2 Baud Rate Generation
      3. 17.3.3 FIFO Operation
        1. 17.3.3.1 FIFO Remapping
      4. 17.3.4 Data Transmission
      5. 17.3.5 Flow Control
      6. 17.3.6 IrDA Encoding and Decoding
      7. 17.3.7 Interrupts
      8. 17.3.8 Loopback Operation
    4. 17.4 UART-LIN Specification
      1. 17.4.1 Break transmission in UART mode
      2. 17.4.2 Break reception in UART mode
      3. 17.4.3 Break/Synch transmission in LIN mode
      4. 17.4.4 Break/Synch reception in LIN mode
      5. 17.4.5 Dormant mode operation
      6. 17.4.6 Event signal generation
      7. 17.4.7 Event signal detection when device is in active/idle modes
      8. 17.4.8 Event signal detection when device is in sleep mode
    5. 17.5 Interface to Host DMA
    6. 17.6 Initialization and Configuration
    7. 17.7 UART Registers
  19. 18Serial Peripheral Interface (SPI)
    1. 18.1 Overview
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Signal Description
    3. 18.3 Functional Description
      1. 18.3.1  Clock Control
      2. 18.3.2  FIFO Operation
        1. 18.3.2.1 Transmit FIFO
        2. 18.3.2.2 Repeated Transmit Operation
        3. 18.3.2.3 Receive FIFO
        4. 18.3.2.4 FIFO Flush
      3. 18.3.3  Interrupts
      4. 18.3.4  Data Format
      5. 18.3.5  Delayed Data Sampling
      6. 18.3.6  Chip Select Control
      7. 18.3.7  Command Data Control
      8. 18.3.8  Protocol Descriptions
        1. 18.3.8.1 Motorola SPI Frame Format
        2. 18.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 18.3.8.3 MICROWIRE Frame Format
      9. 18.3.9  CRC Configuration
      10. 18.3.10 Auto CRC Functionality
      11. 18.3.11 SPI Status
      12. 18.3.12 Debug Halt
    4. 18.4 Host DMA Operation
    5. 18.5 Initialization and Configuration
    6. 18.6 SPI Registers
  20. 19Inter-Integrated Circuit (I2C) Interface
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Clock Control
        1. 19.3.1.1 Internal Clock
        2. 19.3.1.2 External Clock
      2. 19.3.2 General Architecture
        1. 19.3.2.1  Start and Stop Conditions
        2. 19.3.2.2  Data Format with 7-Bit Address
        3. 19.3.2.3  Data Format with 10-Bit Addressing
          1. 19.3.2.3.1 Additional 10-Bit Scenarios
        4. 19.3.2.4  Acknowledge
        5. 19.3.2.5  Repeated Start
        6. 19.3.2.6  Clock Stretching
        7. 19.3.2.7  Arbitration
        8. 19.3.2.8  Multi-Controller mode
        9. 19.3.2.9  Glitch Suppression
        10. 19.3.2.10 FIFO Operation
        11. 19.3.2.11 Burst Mode Operation
        12. 19.3.2.12 DMA Operation
        13. 19.3.2.13 Flush Stale Tx Data in Target Mode
          1. 19.3.2.13.1 Recommended Sequence
        14. 19.3.2.14 SMBUS 3.0 Support
          1. 19.3.2.14.1 Quick Command
          2. 19.3.2.14.2 Acknowledge Control
          3. 19.3.2.14.3 Alert Response protocol
          4. 19.3.2.14.4 Address Resolution Protocol
          5. 19.3.2.14.5 Enhanced Acknowledge Control
    4. 19.4 Initialization and Configuration
    5. 19.5 Interrupts
    6. 19.6 I2C Registers
  21. 20Secure Digital Multimedia Card (SDMMC)
    1. 20.1 Introduction
      1. 20.1.1 SDMMC Features
      2. 20.1.2 Integration
    2. 20.2 Functional Description
      1. 20.2.1  SDMMC Functional Modes
        1. 20.2.1.1 SDMMC Connected to an SD Card
        2. 20.2.1.2 Protocol and Data Format
          1. 20.2.1.2.1 Protocol
          2. 20.2.1.2.2 Data Format
      2. 20.2.2  SD Card Feedback
      3. 20.2.3  Resets
        1. 20.2.3.1 Hardware Reset
        2. 20.2.3.2 Software Reset
      4. 20.2.4  Interrupt Requests
        1. 20.2.4.1 Interrupt-Driven Operation
        2. 20.2.4.2 Polling
      5. 20.2.5  DMA Modes
        1. 20.2.5.1 DMA Peripheral Mode Operations
          1. 20.2.5.1.1 DMA Receive Mode
          2. 20.2.5.1.2 DMA Transmit Mode
      6. 20.2.6  Buffer Management
        1. 20.2.6.1 Data Buffer
          1. 20.2.6.1.1 Memory Size and Block Length
          2. 20.2.6.1.2 Data Buffer Status
      7. 20.2.7  Transfer Process
        1. 20.2.7.1 Different Types of Commands
        2. 20.2.7.2 Different Types of Responses
      8. 20.2.8  Transfer or Command Status and Error Reporting
        1. 20.2.8.1 Busy Timeout for R1b, R5b Response Type
        2. 20.2.8.2 Busy Timeout After Write CRC Status
        3. 20.2.8.3 Write CRC Status Timeout
        4. 20.2.8.4 Read Data Timeout
      9. 20.2.9  Auto Command 12 Timings
        1. 20.2.9.1 Auto Command 12 Timings During Write Transfer
        2. 20.2.9.2 Auto Command 12 Timings During Read Transfer
      10. 20.2.10 Transfer Stop
      11. 20.2.11 Output Signals Generation
        1. 20.2.11.1 Generation on Falling Edge of SDMMC Clock
        2. 20.2.11.2 Generation on Rising Edge of SDMMC Clock
      12. 20.2.12 Test Registers
      13. 20.2.13 SDMMC Hardware Status Features
    3. 20.3 Low-Level Programming Models
      1. 20.3.1 SDMMC Initialization Flow
        1. 20.3.1.1 Enable OCP and CLKADPI Clocks
        2. 20.3.1.2 SD Soft Reset Flow
        3. 20.3.1.3 Set SD Default Capabilities
        4. 20.3.1.4 SDMMC Host and Bus Configuration
      2. 20.3.2 Operational Modes Configuration
        1. 20.3.2.1 Basic Operations for SDMMC
        2. 20.3.2.2 Card Detection, Identification, and Selection
    4. 20.4 SDMMC Registers
  22. 21Secure Digital Input/Output (SDIO)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 SDIO Interface Description
      2. 21.3.2 Protocol and Data Format
      3. 21.3.3 I/O Read/Write Command
        1. 21.3.3.1 IO_WR_DIRECT Command (CMD52)
        2. 21.3.3.2 IO_WR_EXTENDED Command (CMD53)
      4. 21.3.4 Reset
      5. 21.3.5 FIFO Operation
        1. 21.3.5.1 Rx FIFO (For Host Write)
        2. 21.3.5.2 Tx FIFO (For Host Read)
      6. 21.3.6 Interrupt Request
        1. 21.3.6.1 External Host IRQ
        2. 21.3.6.2 M33 IRQ
      7. 21.3.7 Transaction Details
        1. 21.3.7.1 Host write to SDIO IP (Rx FIFO)
          1. 21.3.7.1.1 Host write to SDIO IP (Rx FIFO) – Long SW latency case
          2. 21.3.7.1.2 Host write to SDIO IP (Rx FIFO) – CRC Error Case
        2. 21.3.7.2 Host reads from SDIO (TX buffer)
    4. 21.4 SDIO_CORE Registers
    5. 21.5 SDIO_CARD_FN1 Registers
  23. 22Inter-Integrated Circuit Sound (I2S)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  Signal Descriptions
    4. 22.4  Functional Description
      1. 22.4.1 Pin Configuration
      2. 22.4.2 Serial Format Configuration
        1. 22.4.2.1 Register Configuration
      3. 22.4.3 Left-Justified (LJF)
        1. 22.4.3.1 Register Configuration
      4. 22.4.4 Right-Justified (RJF)
        1. 22.4.4.1 Register Configuration
      5. 22.4.5 DSP
        1. 22.4.5.1 Register Configuration
      6. 22.4.6 Clock Configuration
    5. 22.5  Memory Interface
      1. 22.5.1 Sample Word Length
      2. 22.5.2 Padding Mechanism
      3. 22.5.3 Channel Mapping
      4. 22.5.4 Sample Storage in Memory
      5. 22.5.5 DMA Operation
        1. 22.5.5.1 Start-Up
        2. 22.5.5.2 Operation
        3. 22.5.5.3 Shutdown
    6. 22.6  Samplestamp Generator
      1. 22.6.1 Samplestamp Counters
      2. 22.6.2 Start-Up Triggers
      3. 22.6.3 Samplestamp Capture
      4. 22.6.4 Achieving constant audio latency
    7. 22.7  Error Detection
    8. 22.8  Usage
      1. 22.8.1 Start-Up Sequence
      2. 22.8.2 Shutdown Sequence
    9. 22.9  I2S Configuration Guideline
    10. 22.10 I2S Registers
  24. 23Pulse Density Modulation (PDM)
    1. 23.1  Introduction
    2. 23.2  Block Diagram
    3. 23.3  Input Selection
      1. 23.3.1 PDM Data Mode
      2. 23.3.2 Manchester Input Mode
    4. 23.4  CIC Filter
      1. 23.4.1 Filter Design
      2. 23.4.2 Digital Filter Output
      3. 23.4.3 Offset Binary Mode
      4. 23.4.4 Twos-Complement Mode
    5. 23.5  FIFO Organization in Different Modes
      1. 23.5.1 Single Mono Microphone Configuration
        1. 23.5.1.1 24-bit Sample Size
          1. 23.5.1.1.1 32-bit Data Read
        2. 23.5.1.2 16-bit Sample Size
          1. 23.5.1.2.1 32-bit Data Read
          2. 23.5.1.2.2 16-bit Data Read
        3. 23.5.1.3 8-bit Sample Size
          1. 23.5.1.3.1 32-bit Data Read
          2. 23.5.1.3.2 16-bit Data Read
          3. 23.5.1.3.3 8-bit Data Read
      2. 23.5.2 Stereo or Dual Mono Microphone Configuration
        1. 23.5.2.1 24-bit Sample Size
          1. 23.5.2.1.1 32-bit Data Read
        2. 23.5.2.2 16-bit Sample Size
          1. 23.5.2.2.1 32-bit Data Read
          2. 23.5.2.2.2 16-bit Data Read
        3. 23.5.2.3 8-bit Sample Size
          1. 23.5.2.3.1 32-bit Data Read
          2. 23.5.2.3.2 16-bit Data Read
          3. 23.5.2.3.3 8-bit Data Read
      3. 23.5.3 FIFO Threshold Setting
      4. 23.5.4 Reset FIFO
    6. 23.6  Automatic Gain Control (AGC)
      1. 23.6.1 Operation in 2's Complement Format
      2. 23.6.2 Operation in Offset Binary Format
    7. 23.7  Interrupts
    8. 23.8  Clock Select and Control
    9. 23.9  DMA Operation
    10. 23.10 Samplestamp Generator
      1. 23.10.1 Samplestamp Counters
      2. 23.10.2 Start-Up Triggers
      3. 23.10.3 Samplestamp Capture
      4. 23.10.4 Achieving Constant Audio Latency
    11. 23.11 Debug‑Mode Flag Behavior
    12. 23.12 Software Guidelines
    13. 23.13 PDM Registers
  25. 24Analog to Digital Converter (ADC)
    1. 24.1 Overview
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1  ADC Core
      2. 24.3.2  Voltage Reference Options
      3. 24.3.3  Internal Channels
      4. 24.3.4  Resolution Modes
      5. 24.3.5  ADC Clocking
      6. 24.3.6  Power Down Behavior
      7. 24.3.7  Sampling Trigger Sources and Sampling Modes
        1. 24.3.7.1 AUTO Sampling Mode
        2. 24.3.7.2 MANUAL Sampling Mode
      8. 24.3.8  Sampling Period
      9. 24.3.9  Conversion Modes
      10. 24.3.10 ADC Data Format
      11. 24.3.11 Status Register
      12. 24.3.12 ADC Events
        1. 24.3.12.1 Generic Event Publishers (INT_EVENT0 & INT_EVENT1)
        2. 24.3.12.2 DMA Trigger Event Publisher (INT_EVENT2)
        3. 24.3.12.3 Generic Event Subscriber
      13. 24.3.13 Advanced Features
        1. 24.3.13.1 Window Comparator
        2. 24.3.13.2 DMA & FIFO Operation
          1. 24.3.13.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
          2. 24.3.13.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
          3. 24.3.13.2.3 DMA/CPU Operation Summary Matrix
        3. 24.3.13.3 Ad-hoc Single Conversion
    4. 24.4 ADC Registers
  26. 25Controller Area Network (CAN)
    1. 25.1 Introduction
    2. 25.2 Functions
    3. 25.3 DCAN Subsystem
    4. 25.4 DCAN Functional Description
      1. 25.4.1 Operating Modes
        1. 25.4.1.1 Software Initialization
        2. 25.4.1.2 Normal Operation
        3. 25.4.1.3 Restricted Operation Mode
        4. 25.4.1.4 Bus Monitoring Mode
        5. 25.4.1.5 Disabled Automatic Retransmission
          1. 25.4.1.5.1 Frame Transmission in DAR Mode
        6. 25.4.1.6 Power Down (Sleep Mode)
          1. 25.4.1.6.1 DCAN clock stop and wake operations
          2. 25.4.1.6.2 DCAN debug suspend operation
        7. 25.4.1.7 Test Modes
          1. 25.4.1.7.1 External Loop Back Mode
          2. 25.4.1.7.2 Internal Loop Back Mode
      2. 25.4.2 Timestamp Generation
        1. 25.4.2.1 Block Diagram
      3. 25.4.3 Timeout Counter
      4. 25.4.4 Rx Handling
        1. 25.4.4.1 Acceptance Filtering
          1. 25.4.4.1.1 Range Filter
          2. 25.4.4.1.2 Filter for specific IDs
          3. 25.4.4.1.3 Classic Bit Mask Filter
          4. 25.4.4.1.4 Standard Message ID Filtering
          5. 25.4.4.1.5 Extended Message ID Filtering
        2. 25.4.4.2 Rx FIFOs
          1. 25.4.4.2.1 Rx FIFO Blocking Mode
          2. 25.4.4.2.2 Rx FIFO Overwrite Mode
        3. 25.4.4.3 Dedicated Rx Buffers
          1. 25.4.4.3.1 Rx Buffer Handling
        4. 25.4.4.4 Debug on CAN Support
          1. 25.4.4.4.1 Filtering for Debug Messages
          2. 25.4.4.4.2 Debug Message Handling
      5. 25.4.5 Tx Handling
        1. 25.4.5.1 Transmit Pause
        2. 25.4.5.2 Dedicated Tx Buffers
        3. 25.4.5.3 Tx FIFO
        4. 25.4.5.4 Tx Queue
        5. 25.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 25.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 25.4.5.7 Transmit Cancellation
        8. 25.4.5.8 Tx Event Handling
      6. 25.4.6 FIFO Acknowledge Handling
      7. 25.4.7 DCAN Message RAM
        1. 25.4.7.1 Message RAM Configuration
        2. 25.4.7.2 Rx Buffer and FIFO Element
        3. 25.4.7.3 Tx Buffer Element
        4. 25.4.7.4 Tx Event FIFO Element
        5. 25.4.7.5 Standard Message ID Filter Element
        6. 25.4.7.6 Extended Message ID Filter Element
      8. 25.4.8 Interrupt Requests
    5. 25.5 DCAN Wrapper
    6. 25.6 DCAN Clock Enable
    7. 25.7 DCAN Registers
  27. 26Revision History

20.4 SDMMC Registers

Table 20-12 lists the memory-mapped registers for the SDMMC registers. All register offset addresses not listed in Table 20-12 should be considered as reserved locations and the register contents should not be modified.

Table 20-12 SDMMC Registers
OffsetAcronymRegister NameSection
110hSYSCFGSystem ConfigurationSection 20.4.1
114hSYSSTAModule StatusSection 20.4.2
124hCSREStatus Error DetectionSection 20.4.3
128hSYSTESTSystem Test ControlSection 20.4.4
12ChCONSD ConfigurationSection 20.4.5
130hPWCNTPower Delay CounterSection 20.4.6
200hSDMASADMA System AddressSection 20.4.7
204hBLKTransfer Size ConfigurationSection 20.4.8
208hARGCommand ArgumentSection 20.4.9
20ChCMDCommand Transfer ControlSection 20.4.10
210hRSP10Command Response RegisterSection 20.4.11
214hRSP32Command Response UpperSection 20.4.12
218hRSP54Command Response BitsSection 20.4.13
21ChRSP76Response Data 4Section 20.4.14
220hDATAData BufferSection 20.4.15
224hPSTATEController StatusSection 20.4.16
228hHCTLHost Control SettingsSection 20.4.17
22ChSYSCTLClock and TimeoutSection 20.4.18
230hSTATInterrupt StatusSection 20.4.19
234hIEInterrupt EnableSection 20.4.20
238hISEInterrupt Signal EnableSection 20.4.21
23ChAC12Auto Command 12 ErrorSection 20.4.22
240hCAPAController CapabilitiesSection 20.4.23
248hCURCAPACurrent CapabilitiesSection 20.4.24
250hFEForce Error InterruptSection 20.4.25
2FChREVVersion InformationSection 20.4.26
1040hTPSELTest Port SelectionSection 20.4.27
1048hDMAMODEDMA Mode ConfigurationSection 20.4.28
1050hDMAINDDMA Trigger SelectionSection 20.4.29
1054hCLKSELMemory Clock SelectionSection 20.4.30
10E0hEVTMODEEvent ModeSection 20.4.31
10FChDESCModule Identification RegisterSection 20.4.32
1100hSDMMCSTATStatus RegisterSection 20.4.33
1110h + formulaBUFIF_yBuffer InterfaceSection 20.4.34
4000hCLKCFGPrimary ConfigurationSection 20.4.35

Complex bit access types are encoded to fit into small table cells. Table 20-13 shows the codes that are used for access types in this section.

Table 20-13 SDMMC Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

20.4.1 SYSCFG Register (Offset = 110h) [Reset = 00002015h]

SYSCFG is shown in Table 20-14.

Return to the Summary Table.

This register allows controlling various parameters of the OCP interface.

Table 20-14 SYSCFG Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-12RESERVEDR0hReserved
11-10RESERVEDR0hReserved
9-8RESERVEDR0hReserved
7-5RESERVEDR0hReserved
4-3RESERVEDR0hReserved
2RESERVEDR0hReserved
1SOFTRSTR/W0hSoftware reset. The bit is automatically reset by the hardware. During reset, it always returns 0.
0RESERVEDR0hReserved

20.4.2 SYSSTA Register (Offset = 114h) [Reset = 00000000h]

SYSSTA is shown in Table 20-15.

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This register provides status information about the module excluding the interrupt status information.

Table 20-15 SYSSTA Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0RSTDONER0hInternal Reset Monitoring Note: The debounce clock , the interface clock and the functional clock must be provided to the SDMMC host controller to allow the internal reset monitoring.
  • 0h = Internal module reset is on-going
  • 1h = Reset completed

20.4.3 CSRE Register (Offset = 124h) [Reset = 00000000h]

CSRE is shown in Table 20-16.

Return to the Summary Table.

Card Status Response Error Detection This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit SD_SD_CSRE[i] is set to 1, if the corresponding bit at the same position in the response RSP10[i] is set to 1, the host controller indicates a card error (SD_STAT.CERR bit) interrupt status to avoid the host driver reading the response register (RSP10). No automatic card error detection for autoCMD12 is implemented; the host system has to check autoCMD12 response register (RSP76) for possible card errors.

Table 20-16 CSRE Register Field Descriptions
BitFieldTypeResetDescription
31-0STAR/W0hCard status response error
  • 0h = Minimum value
  • FFFFFFFFh = Maximum value

20.4.4 SYSTEST Register (Offset = 128h) [Reset = 00000000h]

SYSTEST is shown in Table 20-17.

Return to the Summary Table.

SDMMC System Test Register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SD_SYSTEST) mode for boundary connectivity verification. In SD_SYSTEST mode, a write into SD_CMD register will not start a transfer.

Table 20-17 SYSTEST Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16OBIR0hOut-Of-Band Interrupt (OBI) data value Note: Out-Of-Band Interrupt (OBI) is not supported.
15SDCDR0hCard detect input signal (SDCD) data value
  • 0h = The card detect pin is driven low
  • 1h = The card detect pin is driven high
14SDWPR0hWrite protect input signal (SDWP) data value
  • 0h = The write protect pin SDWP is driven low
  • 1h = The write protect pin SDWP is driven high
13WAKDR/W0hWake request output signal data value
  • 0h = The pin SWAKEUP is driven low
  • 1h = The pin SWAKEUP is driven high
12SSBR/W0hSet status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (SD_STAT).
  • 0h = Clears this SSB bit field. Writing 0 does not clear already set status bits
  • 1h = Force to 1 all status bits of the interrupt status register (SD_STAT) only if the corresponding bit field in the Interrupt signal enable register (SD_ISE) is set.
11D7DR/W0hDAT7 input/output signal data value
  • 0h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT7 line is driven low. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
  • 1h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT7 line is driven high. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
10D6DR/W0hDAT6 input/output signal data value
  • 0h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT6 line is driven low. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
  • 1h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT6 line is driven high. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
9D5DR/W0hDAT5 input/output signal data value
  • 0h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT5 line is driven low. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
  • 1h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT5 line is driven high. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
8D4DR/W0hDAT4 input/output signal data value
  • 0h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT4 line is driven low. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
  • 1h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT4 line is driven high. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
7D3DR/W0hDAT3 input/output signal data value
  • 0h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT3 line is driven low. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
  • 1h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT3 line is driven high. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
6D2DR/W0hDAT2 input/output signal data value
  • 0h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT2 line is driven low. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
  • 1h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT2 line is driven high. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
5D1DR/W0hDAT1 input/output signal data value
  • 0h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT1 line is driven low. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
  • 1h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT1 line is driven high. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
4D0DR/W0hDAT0 input/output signal data value
  • 0h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT0 line is driven low. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
  • 1h = If SD_SYSTEST.DDIR bit = 0 (output mode direction), the DAT0 line is driven high. If SD_SYSTEST.DDIR bit = 1 (input mode direction), no effect.
3DDIRR/W0hControl of the DAT[7:0] pins direction
  • 0h = The DAT lines are outputs (host to card)
  • 1h = The DAT lines are inputs (card to host)
2CDATR/W0hCMD input/output signal data value
  • 0h = If SD_SYSTEST.CDIR bit = 0 (output mode direction), the CMD line is driven low. If SD_SYSTEST.CDIR bit = 1 (input mode direction), no effect.
  • 1h = If SD_SYSTEST.CDIR bit = 0 (output mode direction), the CMD line is driven high. If SD_SYSTEST.CDIR bit = 1 (input mode direction), no effect.
1CDIRR/W0hControl of the CMD pin direction
  • 0h = The CMD line is an output (host to card)
  • 1h = The CMD line is an input (card to host)
0MCKDR/W0hMMC clock output signal data value
  • 0h = The output clock is driven low
  • 1h = The output clock is driven high

20.4.5 CON Register (Offset = 12Ch) [Reset = 00000600h]

CON is shown in Table 20-18.

Return to the Summary Table.

SDMMC Configuration Register. This register is used: - to select the functional mode or the SYSTEST mode for any card. - to send an initialization sequence to any card. - to enable the detection on DAT[1] of a card interrupt for SDIO cards only. and also to configure : - specific data and command transfers for MMC cards only. - the parameters related to the card detect and write protect input signals.

Table 20-18 CON Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0hReserved
21SDMALNER/W0hPeripheral DMA Level/Edge Request The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to SD_DATA register or late de-assertion, request remains active until last allowed data written into SD_DATA.
  • 0h = peripheral DMA edge sensitive
  • 1h = peripheral DMA level sensitive
20REVERVEDR/W0hDMA Master or Slave selection Note: these bit fields are *not used*, since the IP not support MDMA.
19RESERVEDR/W0hDual Data Rate mode Note: these bit fields are *not used*, Only Standard mode is supported.
18-17RESERVEDR/W0hNote: these bit fields are *not used*.
16CLKEXTFREER/W0hExternal clock free running This register is used to maintain card clock out of transfer transaction to enable peripheral module (for example to generate a synchronous interrupt on mmc_dat[1] ). The Clock will be maintained only if SD_SYSCTL.CEN bit is set.
  • 0h = External card clock is cut off outside active transaction period
  • 1h = External card clock is maintained even out of active transaction period only if SD_SYSCTL.CEN bit is set.
15PADENR/W0hControl Power for MMC Lines. Note: Power control is not supported using this bit.
  • 0h = Minimum value
  • 1h = Maximum value
14OBIER/W0hOut-of-Band Interrupt Enable. Note: The Out-of-Band (OBI) interrupt is not supported.
  • 0h = Minimum value
  • 1h = Maximum value
13OBIPR/W0hOut-of-Band Interrupt Polarity Note: The Out-of-Band (OBI) interrupt is not supported.
  • 0h = Minimum value
  • 1h = Maximum value
12CEATAR/W0hCE-ATA control mode (MMC cards compliant with CE-ATA) This bit is used to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features.
  • 0h = Standard MMC/SD/SDIO mode
  • 1h = CE-ATA mode. Next commands are considered as CE-ATA commands.
11CTPLR/W0hControl Power for DAT[1] line MMC and SD cards: By default, this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO cards: When this bit is set to 1, the host controller automatically disables all the input buffers except the buffer of DAT[1] outside of a transaction in order to detect asynchronous card interrupt on DAT[1] line and minimize the leakage current of the buffers.
  • 0h = Disable all the input buffers outside of a transaction
  • 1h = Disable all the input buffers except the buffer of DAT[1] outside of a transaction
10-9DVALR/W3hDebounce filter value (all cards) This register is used to define a debounce period to filter the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the system integration and the type of the connector housing that accommodates the card.
  • 0h = 33 us debounce period
  • 1h = 231 us debounce period
  • 2h = 1 ms debounce period
  • 3h = 8.4 ms debounce period
8WPPR/W0hWrite protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (SDWP). The usage of the write protect input signal (SDWP) is optional and depends on the system integration and the type of the connector housing that accommodates the card.
  • 0h = Active low level
  • 1h = Active high level
7CDPR/W0hCard detect polarity All cards This bit selects the active level of the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the system integration and the type of the connector housing that accommodates the card.
  • 0h = Active low level
  • 1h = Active high level
6MITR/W0hMMC interrupt command (MMC cards only). This bit must be set to 1, when the next write access to the command register (SD_CMD) is for writing a MMC interrupt command (CMD40) requiring the command timeout detection to be disabled for the command response.
  • 0h = MMC interrupt command not possible, command timeout enabled
  • 1h = MMC interrupt command possible, Command timeout disabled
5DW8R/W0h8-bit mode MMC select (MMC cards only) For SD/SDIO cards, this bit must be cleared to 0. For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliancy with MMC standard specification.
  • 0h = 1-bit or 4-bit data width
  • 1h = Open drain or broadcast host response
4MODER/W0hMode select (all cards) This bit selects the functional mode.
  • 0h = Functional mode. Transfers to the MMC/SD/SDIO cards follow the card protocol. The MMC clock is enabled. MMC/SD transfers are operated under the control of the SD_CMD register.
  • 1h = SYSTEST mode. The signal pins are configured as general-purpose input/output and the 1024-byte buffer is configured as a stack memory accessible only by the local host or system DMA. The pins retain their default type (input, output or inout). SYSTEST mode is operated under the control of the SD_SYSTEST register.
3STRR/W0hStream command (MMC cards only) This bit must be set to 1 only for the stream data transfers (read or write) of the adtc commands. Stream read is a class 1 command (CMD11READ_DAT_UNTIL_STOP). Stream write is a class 3 command (CMD20WRITE_DAT_UNTIL_STOP).
  • 0h = Block oriented data transfer
  • 1h = Stream oriented data transfer
2HRR/W0hBroadcast host response (MMC cards only) This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core. In order to have the host response to be generated in open drain mode, the IO must be configured accordingly in EXT_IOMUX. When SD_CON.CEATA bit is set to 1 and SD_ARG cleared to 0, when writing the value of 0 into SD_CMD register, the host controller performs a 'command completion signal disable' token (i.e., mmc_cmd line held to 0 during 47 cycles followed by a 1).
  • 0h = The host does not generate a 48-bit response instead of a command
  • 1h = The host generates a 48-bit response instead of a command or a command completion signal disable token
1INITR/W0hSend initialization stream (all cards) When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the mmc_cmd line to 1 during 80 clock cycles. The initialization sequence is mandatory - but it is not required to do it through this bit - this bit makes it easier. Clock divider should be set to ensure that 80 clock periods are greater than 1ms. Note: In this mode, there is no command sent to the card and no response is expected. A command complete interrupt will be generated once the initialization sequence is completed.
  • 0h = The host does not send an initialization sequence
  • 1h = The host sends an initialization sequence
0ODR/W0hCard open drain mode This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typically, during card identification mode when the card is either in idle, ready or ident state. It is also necessary to set this bit to 1, for a broadcast host response (see Broadcast host response register SD_CON.HR).
  • 0h = No Open Drain
  • 1h = Open Drain or Broadcast host response

20.4.6 PWCNT Register (Offset = 130h) [Reset = 00000000h]

PWCNT is shown in Table 20-19.

Return to the Summary Table.

SDMMC Power counter register This register is used to program a MMC counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage.

Table 20-19 PWCNT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0NUMDELR/W0hPower counter This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued. 0h = No additional delay added 1h = TCF delay (card clock period) 2h = TCF x 2 delay (card clock period) FFFEh = TCF x 65534 delay (card clock period) FFFFh = TCF x 65535 delay (card clock period)
  • 0h = Minimum value of PWCNT
  • FFFFh = Maximum value of PWCNT

20.4.7 SDMASA Register (Offset = 200h) [Reset = 00000000h]

SDMASA is shown in Table 20-20.

Return to the Summary Table.

DMA System Address This register contains the system memory address for a SDMA transfer. When the Host Controller stops a SDMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing (i.e., after a transaction has stopped). Read operations during transfers may return an invalid value. The Host Driver shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data position can be read from this register. The SDMA transfer waits at the every boundary specified by the Host SDMA Buffer Boundary in the Block Size register. The Host Controller generates DMA Interrupt to request the Host Driver to update this register. The Host Driver sets the next system address of the next data position to this register. When the most upper byte of this register (003h) is written, the Host Controller restarts the SDMA transfer. When restarting SDMA by the Resume command or by setting Continue Request in the Block Gap Control register, the Host Controller shall start at the next contiguous address stored here in the SDMA System Address register.

Table 20-20 SDMASA Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR/W0hSDMA System Address register
  • 0h = Minimum value
  • FFFFFFFFh = Maximum value

20.4.8 BLK Register (Offset = 204h) [Reset = 00000000h]

BLK is shown in Table 20-21.

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Transfer Length Configuration Register BLEN is the block size register. NBLK is the block count register. This register shall be used for any card.

Table 20-21 BLK Register Field Descriptions
BitFieldTypeResetDescription
31-16NBLKR/W0hBlock count for current transfer This register is enabled when Block count Enable (SD_CMD.BCE bit) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note: The host controller decrements the block count after each block transfer and stops when the count reaches zero. This register can be accessed only if no transaction is executing (i.e., after a transaction has stopped). Read operations during transfers may return an invalid value and write operation will be ignored. 0h = Stop count 1h = 1 block 2h = 2 blocks FFFFh = 65535 blocks
  • 0h = Minimum value
  • FFFFh = Maximum value
15-11RESERVEDR0hReserved
10-0BLENR/W0hTransfer block size This register is enabled when Block Count Enable (SD_CMD.BCE) is set to 1 and is valid only for multiple block transfers. It specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. 0h = No data transfer 1h = 1 byte block length 2h = 2 bytes block length 3h = 3 bytes block length 1FFh = 511 bytes block length 200h = 512 bytes block length 3FFh = 1023 bytes block length 400h = 1024 bytes block length
  • 0h = Minimum value
  • 7FFh = Maximum value

20.4.9 ARG Register (Offset = 208h) [Reset = 00000000h]

ARG is shown in Table 20-22.

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Command argument register This register contains command argument specified as bit 39-8 of Command-Format. These registers must be initialized prior to sending the command itself to the card (write action into the register SD_CMD register). Only exception is for a command index specifying stuff bits in arguments, making a write unnecessary.

Table 20-22 ARG Register Field Descriptions
BitFieldTypeResetDescription
31-0CMDARGR/W0hCommand argument
  • 0h = Minimum value
  • FFFFFFFFh = Maximum value

20.4.10 CMD Register (Offset = 20Ch) [Reset = 00000000h]

CMD is shown in Table 20-23.

Return to the Summary Table.

Command and data transfer register This register configures the data and command transfers. A write into the most significant byte send the command. A write into SD_CMD[15:0] during data transfer has no effect. This register can be used for any card. In SYSTEST mode, a write to the SD_CMD register will not start a transfer.

Table 20-23 CMD Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-24IDXR/W0hCommand index Binary encoded value from 0 to 63 specifying the command number to send to card. Examples: - INDEX = 7h, sends CMD7 to the card - INDEX = 29h, sends CMD41 to the card
  • 0h = Minimum value
  • 3Fh = Maximum value
23-22CMDTYPR/W0hCommand type This bitfield specifies three types of special commands: - Suspend - Resume - Abort The bitfield is cleared to 0 for all other commands.
  • 0h = Others commands
  • 1h = Upon CMD52 "Bus Suspend" operation
  • 2h = Upon CMD52 "Function Select" operation
  • 3h = Upon CMD12 or CMD52 "I/O Abort" command
21DPR/W0hData present select This register indicates that data is present and DAT line(s) shall be used. It must be cleared to 0 in the following conditions: - Command using only CMD line - Command with no data transfer but using busy signal on DAT[0] line - Resume command
  • 0h = Command with no data transfer
  • 1h = Command with data transfer
20CICER/W0hCommand Index check enable If this bit is set to 1, the host checks the index field in the response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. If this bit is set to 0, the Index field is not checked.
  • 0h = Index check disable
  • 1h = Index check enable
19CCCER/W0hCommand CRC check enable If this bit is set to 1, the host checks the CRC field in the response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked.
  • 0h = CRC field check disable
  • 1h = CRC field check enable
18RESERVEDR0hReserved
17-16RSPTYPER/W0hResponse type This bits defines the response type of the command.
  • 0h = No response
  • 1h = Response Length 136 bits
  • 2h = Response Length 48 bits
  • 3h = Response Length 48 bits with busy after response
15-6RESERVEDR0hReserved
5MSBSR/W0hMulti/Single block select This bit must be set to 1 for data transfer in case of multi block command. For any others command this bit must be cleared to 0.
  • 0h = Single block
  • 1h = Multiple block
4DDIRR/W0hData transfer Direction Select This bit defines the data transfer direction
  • 0h = Data Write (host to card)
  • 1h = Data Read (card to host)
3-2ACENR/W0hAuto CMD Enable This field determines use of auto command functions. There are two methods to stop Multiple-block read and write operation (1) Auto CMD12 Enable When this field is set to 01b, the Host Controller issues CMD12 automatically when last block transfer is completed. Auto CMD12 error is indicated to the Auto CMD Error Status register. The Host Driver shall not set this bit if the command does not require CMD12. In particular, secure commands defined in the Part 3 File Security specification do not require CMD12. (2) Auto CMD23 Enable When this bit field is set to 10b, the Host Controller issues a CMD23 automatically before issuing a command specified in the Command Register. The Host Controller Version 3.00 and later shall support this function. The following conditions are required to use the Auto CMD23. - Auto CMD23 Supported (Host Controller Version is 3.00 or later) - A memory card that supports CMD23 (SCR[33]=1) - If DMA is used, it shall be ADMA. - Only when CMD18 or CMD25 is issued (Note, the Host Controller does not check command index.) Auto CMD23 can be used with or without ADMA. By writing the Command register, the Host Controller issues a CMD23 first and then issues a command specified by the Command Index in Command register. If response errors of CMD23 are detected, the second command is not issued. A CMD23 error is indicated in the Auto CMD Error Status register. 32-bit block count value for CMD23 is set to SDMA System Address / Argument 2 register.
  • 0h = Auto CMD12 disable
  • 1h = Auto CMD12 enable or CCS detection enabled
  • 2h = Auto CMD23 enable
1BCER/W0hBlock Count Enable This bit is used to enable the Block count register, which is only relevant for multiple block transfers. When this bit is 0, the Block Count register is disabled, which is useful in executing an infinite transfer.
  • 0h = Block count disabled for infinite transfer
  • 1h = Block count enabled for multiple block transfer with known number of blocks
0DER/W0hDMA enable DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1, a DMA operation starts when the host writes to the upper byte of Command register (00Fh).
  • 0h = DMA mode disable
  • 1h = DMA mode enable

20.4.11 RSP10 Register (Offset = 210h) [Reset = 00000000h]

RSP10 is shown in Table 20-24.

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Response register 10 This 32-bit register holds bits positions [31:0] of command response type R1, R1b, R2, R3, R4, R5, R5b or R6.

Table 20-24 RSP10 Register Field Descriptions
BitFieldTypeResetDescription
31-16RSP1R0hCommand Response [31:16]
  • 0h = Minimum value
  • FFFFh = Maximum value
15-0RSP0R0hCommand Response [15:0]
  • 0h = Minimum value
  • FFFFh = Maximum value

20.4.12 RSP32 Register (Offset = 214h) [Reset = 00000000h]

RSP32 is shown in Table 20-25.

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Response register 32 This 32-bit register holds bits positions [63:32] of command response type R2.

Table 20-25 RSP32 Register Field Descriptions
BitFieldTypeResetDescription
31-16RSP3R0hCommand Response [63:48]
  • 0h = Minimum value
  • FFFFh = Maximum value
15-0RSP2R0hCommand Response [47:32]
  • 0h = Minimum value
  • FFFFh = Maximum value

20.4.13 RSP54 Register (Offset = 218h) [Reset = 00000000h]

RSP54 is shown in Table 20-26.

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Response register 54 This 32-bit register holds bits positions [95:64] of command response type R2.

Table 20-26 RSP54 Register Field Descriptions
BitFieldTypeResetDescription
31-16RSP5R0hCommand Response [95:80]
  • 0h = Minimum value
  • FFFFh = Maximum value
15-0RSP4R0hCommand Response [79:64]
  • 0h = Minimum value
  • FFFFh = Maximum value

20.4.14 RSP76 Register (Offset = 21Ch) [Reset = 00000000h]

RSP76 is shown in Table 20-27.

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Response register 76 This 32-bit register holds bits positions [127:96] of command response type R2.

Table 20-27 RSP76 Register Field Descriptions
BitFieldTypeResetDescription
31-16RSP7R0hCommand Response [127:112]
  • 0h = Minimum value
  • FFFFh = Maximum value
15-0RSP6R0hCommand Response [111:96]
  • 0h = Minimum value
  • FFFFh = Maximum value

20.4.15 DATA Register (Offset = 220h) [Reset = 00000000h]

DATA is shown in Table 20-28.

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Data register This register is the 32-bit entry point of the buffer for read or write data transfers. The buffer size is 32bits x 256 (1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput. Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. If the local host accesses this register byte-wise or 16bit-wise, the least significant byte (bits [7:0]) must always be written/read first. The update of the buffer address is done on the most significant byte write.

Table 20-28 DATA Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hBuffer data register In functional mode (SD_CON.MODE = FUNC): - a read access to this register is allowed only when the buffer read enable status is set to 1 (SD_PSTATE.BREN), otherwise a bad access (SD_STAT.BADA) is signaled. - a write access to this register is allowed only when the buffer write enable status is set to 1 (SD_PSTATE.BWEN), otherwise a bad access (SD_STAT.BADA) is signaled and the data is not written.
  • 0h = Minimum value
  • FFFFFFFFh = Maximum value

20.4.16 PSTATE Register (Offset = 224h) [Reset = 00000000h]

PSTATE is shown in Table 20-29.

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SDMMC controller status register The host can get the status of the SDMMC controller from this 32-bit read only register.

Table 20-29 PSTATE Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24CLEVR0hCommand line signal level This status is used to check the CMD line level to recover from errors, and for debugging.
  • 0h = The mmc_cmd line level is 0
  • 1h = The mmc_cmd line level is 1
23-20DLEVR0hDATA line 0 to 3 signal level Bit 3 reflects DATA[3] signal level. Bit 2 reflects DATA[2] signal level. Bit 1 reflects DATA[1] signal level. Bit 0 reflects DATA[0] signal level. This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0].
  • 0h = Minimum value
  • Fh = Maximum value
19WPR0hWrite Protect This bit reflects the write protect input pin (SDWP) level.
  • 0h = The card is write protected. Note: SD_CON.WPP need to reflect the correct active setting of the write protect input signal (SDWP).
  • 1h = The card is not write protected Note: SD_CON.WPP need to reflect the correct active setting of the write protect input signal (SDWP).
18CDPLR0hCard Detect Pin Level This bit reflects the inverse value of the card detect input pin (SDCD).
  • 0h = The value of the card detect input pin (SDCD) is 1
  • 1h = The value of the card detect input pin (SDCD) is 0
17CSSR0hCard State Stable This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable (SD_PSTATE.CPDL). Debouncing is performed on the card detect input pin (SDCD) to detect card stability. This bit is not affected by software reset.
  • 0h = Card detect pin level is debouncing
  • 1h = Card detect pin level is stable
16CINSR0hCard inserted This bit is the debounced value of the card detect input pin (SDCD). An inactive to active transition of the card detect input pin (SDCD) will generate a card insertion interrupt (SD_STAT.CINS). An active to inactive transition of the card detect input pin (SDCD) will generate a card removal interrupt (SD_STAT.REM). This bit is not affected by a software reset.
  • 0h = No card is detected Note: SD_CON.CDP need to reflect the correct active level of the write protect input signal (SDCD).
  • 1h = Card is detected Note: SD_CON.CDP need to reflect the correct active level of the write protect input signal (SDCD).
15-12RESERVEDR0hReserved
11BRER0hBuffer read enable This bit is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1, readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the block data is read from the buffer. A change of this bit from 0 to 1 occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt.
  • 0h = Read BLEN bytes disable
  • 1h = Read BLEN bytes enable. Readable data exists in the buffer.
10BWER0hBuffer write enable This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1, data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written to the buffer. A change of this bit from 0 to 1 occurs when top of block data can be written to the buffer and generates the Buffer Write Ready Interrupt.
  • 0h = There is no room left in the buffer to write BLEN bytes of data.
  • 1h = There is enough space in the buffer to write BLEN bytes of data
9RTAR0hRead transfer active (SD mode only) This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: - After the end bit of the read command - When writing a 1 to continue Request in the Block Gap Control register to restart a read transfer This bit is cleared to 0 for either of the following conditions: - When the last data block as specified by block length is transferred to the system. - When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop At Block Gap Request set to 1. A transfer complete interrupt is generated when this bit changes to 0.
  • 0h = No valid data
  • 1h = Read data transfer on going
8WTAR0hWrite transfer active This status indicates a write transfer active. If this bit is 0, it means no valid write data exists. This bit is set in either of the following cases: - After the end bit of the write command. - When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer. This bit is cleared in either of the following cases: - After getting the CRC status of the last data block as specified by the transfer count (Single or Multiple) - After getting a CRC status of any block where data transmission is about to be stopped by a Stop At Block Gap Request. During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0, as a result of the Stop At Block Gap Request being set. This status is useful for the host to determine when to issue commands during write busy.
  • 0h = No valid data
  • 1h = Write data transfer on going
7-3RESERVEDR0hReserved
2DLAR0hDATA Line Active (SD Mode only) This bit indicates whether one of the DATA lines on SD bus is in use.
  • 0h = mmc_data line inactive
  • 1h = mmc_data line active
1DATIR0hCommand Inhibit (DAT) (SD Mode Only) This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0, it indicates the host can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type). Changing from 1 to 0 generates a Transfer Complete interrupt. Note: The SD Host Driver can save registers in the range of 000-00Dh for a suspend transaction after this bit has changed from 1 to 0.
  • 0h = Issuing of command using the DAT lines is allowed
  • 1h = Issuing of command using DAT lines is not allowed
0CMDIR0hCommand Inhibit (CMD) (SD Mode Only) If this bit is 0, it indicates the CMD line is not in use and the host can issue a SD command using the CMD line. This bit is set immediately after the Command register (00Fh) is written. This bit is cleared when the command response is received. Even if the Command Inhibit (DAT) is set to 1, Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 generates a Command complete interrupt. If the host cannot issue the command because of a command conflict error or because of Command Not Issued By Auto CMD12 Error, this bit shall remain 1 and the Command Complete is not set. Status issuing Auto CMD12 is not read from this bit. Auto CMD12 and Auto CMD23 consist of two responses. In this case, this bit is not cleared by the response of CMD12 or CMD23 but cleared by the response of a read/write command. Status issuing Auto CMD12 is not read from this bit. So if a command is issued during Auto CMD12 operation, Host Controller shall manage to issue two commands: CMD12 and a command set by Command register.
  • 0h = Issuing of command using mmc_cmd line is allowed
  • 1h = Issuing of command using mmc_cmd line is not allowed

20.4.17 HCTL Register (Offset = 228h) [Reset = 00000000h]

HCTL is shown in Table 20-30.

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Host Control Register This register defines the host controls to set power, wakeup and transfer parameters. SD_HCTL[31:24] = Wakeup control SD_HCTL[23:16] = Block gap control SD_HCTL[15:8] = Power control SD_HCTL[7:0] = Host control

Table 20-30 HCTL Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27RESERVEDR0hReserved
26RESERVEDR0hReserved
25RESERVEDR0hReserved
24RESERVEDR0hReserved
23-20RESERVEDR0hReserved
19IBGR/W0hInterrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit should be cleared to 0.
  • 0h = Disable interrupt detection at the block gap in 4-bit mode
  • 1h = Enable interrupt detection at the block gap in 4-bit mode
18RWCR/W0hRead wait control The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap (SD_HCTL.SBGR) generates a read wait period after the current end of block. Note: If read wait is not supported it may cause a conflict on mmc_dat line.
  • 0h = Disable read wait control. Suspend/resume cannot be supported
  • 1h = Enable read wait control
17CRR/W0hContinue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (SD_HCTL[16] SBGR bit). Set this bit to 1 restarts the transfer. The bit is automatically cleared to 0 by the host controller when transfer has restarted, that is, mmc_dat line is active (SD_PSTATE.DLA) or transferring data (SD_PSTATE.WTA). The Stop at block gap request must be disabled (SD_HCTL[16] SBGR bit =0) before setting this bit.
  • 0h = No effect
  • 1h = Transfer restart
16SBGRR/W0hStop at block gap request This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request (SD_HCTL.CR) or during a suspend/resume sequence. In case of read transfer, the card must support read wait control. In case of write transfer, the host driver must set this bit after all block data written. Until the transfer completion (SD_STAT.TC bit set to 1), the host driver must leave this bit set to 1. If this bit is set, the local host may not write to the data register (DATA).
  • 0h = Transfer mode
  • 1h = Stop at block gap
15-12RESERVEDR0hReserved
11-9SDVSR/W0hSD bus voltage select (All cards). The host driver should set these bits to select the voltage level for the card according to the voltage supported by the system (SD_CAPA[26] VS18 bit, SD_CAPA[25] VS30 bit, SD_CAPA[24] VS33 bit) before starting a transfer.
  • 5h = 1.8V (Typical)
  • 6h = 3.0V (Typical)
  • 7h = 3.3V (Typical)
8SDBPR/W0hSD bus power. Before setting this bit, the host driver shall select the SD bus voltage (SD_HCTL[11:9] SDVS bits). If the host controller detects the No card state, this bit is automatically cleared to 0. If the module is power off, a write in the command register (SD_CMD) will not start the transfer. A write to this bit has no effect if the selected SD bus voltage is not supported according to capability register (SD_CAPA[26] VS18 bit, SD_CAPA[25] VS30 bit or SD_CAPA[24] VS33 bit).
  • 0h = Power off
  • 1h = Power on
7CDSSR/W0hCard Detect Signal Selection This bit selects the source for the card detection. When the source for the card detection is switched, the Card insertion and removal interrupts should be disabled to avoid unexpected interrupts. In Card Detect Test Level mode, the card insertion and removal signal can be controlled by SD_HCTL.CDTL.
  • 0h = SDCD signal is selected (for normal use)
  • 1h = The Card Detect Test Level is selected (for test purposes)
6CDTLR/W0hCard Detect Test Level This bit is only functional when the Card Detect Signal Selection selects the Card Detect Test Level mode (SD_HCTL.CDSS = 1).
  • 0h = No card
  • 1h = Card inserted
5RESERVEDR0hReserved
4-3RESERVEDR0hReserved
2HSPER/W0hHigh Speed Enable Before setting this bit, the Host Driver shall check the High Speed Support in the Capabilities register. If this bit is cleared to 0 (default), the Host Controller outputs CMD line and DAT lines at the falling edge of the SD Clock. If this bit is set to 1, the Host Controller outputs CMD line and DAT lines at the rising edge of the SD Clock.
  • 0h = Normal speed mode
  • 1h = High speed mode
1DTWR/W0hData transfer width This bit must be set following a valid SET_BUS_WIDTH command (ACMD6) with the value written in bit 1 of the argument. Prior to this command, the SD card configuration register (SCR) must be verified for the supported bus width by the SD card.
  • 0h = 1-bit Data width (mmc_dat0 used)
  • 1h = 4-bit Data width (mmc_dat[3:0] used)
0RESERVEDR0hReserved

20.4.18 SYSCTL Register (Offset = 22Ch) [Reset = 00000000h]

SYSCTL is shown in Table 20-31.

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SD System Control Register This register defines the system controls clock frequency management and data timeout. SD_SYSCTL[23:16] = Timeout control SD_SYSCTL[15:0] = Clock control

Table 20-31 SYSCTL Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR0hReserved
26SRDR/W0hSoftware reset for mmc_dat line This bit is set to 1 for reset and released to 0 when completed. Note: This subreset should not to be used by software, as it can lead to unexpected side-effects. Reset of the SDMMC module should always be through GPRCM.RSTCTL.RESETASSERT
  • 0h = Reset completed
  • 1h = Reset asserted
25SRCR/W0hSoftware reset for mmc_cmd line This bit is set to 1 for reset and released to 0 when completed. Note: This subreset should not to be used by software, as it can lead to unexpected side-effects. Reset of the SDMMC module should always be through GPRCM.RSTCTL.RESETASSERT
  • 0h = Reset completed
  • 1h = Reset asserted
24SRAR/W0hSoftware reset for all This bit is set to 1 for reset, and released to 0 when completed. Note: This subreset should not to be used by software, as it can lead to unexpected side-effects. Reset of the SDMMC module should always be through GPRCM.RSTCTL.RESETASSERT
  • 0h = Reset completed
  • 1h = Reset asserted
23-20RESERVEDR0hReserved
19-16DTOR/W0hData timeout counter value and busy timeout This value determines the interval to detect mmc_dat lines timeouts. The host driver needs to set this bitfield based on: - the maximum read access time (NAC) (Refer to the SD Specification Part1 Physical Layer) - the data read access time values (TAAC and NSAC) in the card specific data register (CSD) of the card - the timeout clock base frequency (SD_CAPA.TCF) If the card does not respond within the specified number of cycles, a data timeout error occurs (SD_STAT.DTO). The Data timeout counter can also be used to check busy duration, to generate busy timeout for commands with busy response or for busy programming during a write command. Timeout on CRC status is generated if no CRC token is present after a block write. 0h = TCF x 213 1h = TCF x 214 Eh = TCF x 227 Fh = Reserved
  • 0h = Minimum value
  • Eh = Maximum value
15-6CLKDR/W0hClock frequency select This bitfield defines the ratio between a reference clock frequency (system dependent) and the output clock frequency on the mmc_clk pin of the memory card (MMC, SD, or SDIO). 0h = Clock Ref bypass 1h = Clock Ref bypass 2h = Clock Ref / 2 3h = Clock Ref / 3 3FFh = Clock Ref / 1023
  • 0h = Minimum value
  • 3FFh = Maximum value
5-3RESERVEDR0hReserved
2CENR/W0hCard clock enable This bit controls the clock to the card.
  • 0h = The clock is not provided to the card . Clock frequency can be changed.
  • 1h = The clock is provided to the card and can be automatically gated when SD_SYSCONFIG.AUTOIDLE bit is set to 1 (default value). The host driver must wait to set this bit to 1 until the internal clock is stable (SYSSTAT.ICS).
1ICSR0hInternal clock stable (status) This bit indicates that the internal clock is stable
  • 0h = The internal clock is not stable
  • 1h = The internal clock is stable after enabling the clock (SD_SYSCTL.ICEN) or after changing the clock ratio (SD_SYSCTL.CLKD).
0ICER/W0hInternal clock enable This bit controls the internal clock activity. In very low power state, the internal clock is stopped. Note: The activity of the debounce clock (used for wake-up events) and the interface clock (used for reads and writes to the module register map) are not affected by this register.
  • 0h = The internal clock is stopped (very low power state).
  • 1h = The internal clock oscillates and can be automatically gated when SD_SYSCONFIG.AUTOIDLE bit is set to 1 (default value).

20.4.19 STAT Register (Offset = 230h) [Reset = 00000000h]

STAT is shown in Table 20-32.

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The interrupt status regroups all the status of the module internal events that can generate an interrupt. SD_STAT[31:16] = Error Interrupt Status SD_STAT[15:0] = Normal Interrupt Status The error bits are located in the upper 16 bits of the SD_STAT register. All bits are cleared by writing a 1 to them. Additionally, bits 15 and 8 serve as special error bits. These cannot be cleared by writing a 1 to them. Bit 15 (ERRI) is automatically cleared when the error causing to ERRI to be set is handled. (that is, when bits 31:16 are cleared, bit 15 will be automatically cleared). Bit 8 (CIRQ) is cleared by writing a 0 to SD_IE[8] (masking the interrupt) and servicing the interrupt.

Table 20-32 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29BADAR/W0hBad access to data space. This bit is set automatically to indicate a bad access to buffer when not allowed: During a read access to the data register (SD_DATA) while buffer reads are not allowed (SD_PSTATE[11] BRE bit =0). During a write access to the data register (SD_DATA) while buffer writes are not allowed (SD_PSTATE[10] BWE bit=0). 0h (W) = Status bit unchanged 0h (R) = No interrupt 1h (W) = Status is cleared. 1h (R) = Bad access
  • 0h = No interrupt occured
  • 1h = Interrupt occured
28CERRR/W0hCard error. This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E (error) in status field in the response can set a card status error. An error bit in the response is flagged only if corresponding bit in card status response error SD_CSRE in set. There is no card error detection for autoCMD12 command. The host driver shall read SD_RSP76 register to detect error bits in the command response. 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Card error
  • 0h = No interrupt occured
  • 1h = Interrupt occured
27-25RESERVEDR0hReserved
24ACER/W0hAuto CMD12 error. This bit is set automatically when one of the bits in Auto CMD12 Error status register has changed from 0 to 1. 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = AutoCMD12 error
  • 0h = No interrupt occured
  • 1h = Interrupt occured
23RESERVEDR0hReserved
22DEBR/W0hData End Bit error. This bit is set automatically when detecting a 0 at the end bit position of read data on mmc_dat line or at the end position of the CRC status in write mode. 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Data end bit error
  • 0h = No interrupt occured
  • 1h = Interrupt occured
21DCRCR/W0hData CRC Error. This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position "010" token during a block write command. 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Data CRC error
  • 0h = No interrupt occured
  • 1h = Interrupt occured
20DTOR/W0hData timeout error. This bit is set automatically according to the following conditions: Busy timeout for R1b, R5b response type. Busy timeout after write CRC status. Write CRC status timeout. Read data timeout. 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Time out
  • 0h = No interrupt occured
  • 1h = Interrupt occured
19CIER/W0hCommand index error. This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable bit (SD_CMD[20] CICE). 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Command index error
  • 0h = No interrupt occured
  • 1h = Interrupt occured
18CEBR/W0hCommand end bit error. This bit is set automatically when detecting a 0 at the end bit position of a command response. 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Command end bit error
  • 0h = No interrupt occured
  • 1h = Interrupt occured
17CCRCR/W0hCommand CRC error. This bit is set automatically when there is a CRC7 error in the command response depending on the enable bit (SD_CMD[19] CCCE). 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Command CRC error
  • 0h = No interrupt occured
  • 1h = Interrupt occured
16CTOR/W0hCommand timeout error. This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles. 0h (W) = Status bit unchanged 0h (R) = No error 1h (W) = Status is cleared. 1h (R) = Time Out
  • 0h = No interrupt occured
  • 1h = Interrupt occured
15ERRIR0hError interrupt. If any of the bits in the Error Interrupt Status register (SD_STAT [31:16]) are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit are ignored. 0h (R) = No interrupt 1h (R) = Error interrupt event(s) occurred
  • 0h = No interrupt occured
  • 1h = Interrupt occured
14-10RESERVEDR0hReserved
9OBIR/W0hOut-of-band interrupt (This interrupt is only useful for MMC card). Note: Out-of-band interrupt (OBI) is not supported.
  • 0h = No interrupt occured
  • 1h = Interrupt occured
8CIRQR0hCard interrupt. This bit is only used for SD and SDIO cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wake-up). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-ATA mode, interrupt source is detected when the card drives mmc_cmd line to zero during one cycle after data transmission end. All modes above are fully exclusive. The controller interrupt must be clear by setting SD_IE[8] CIRQ_ENABLE to 0, then the host driver must start the interrupt service with card (clearing card interrupt status) to remove card interrupt source. Otherwise the Controller interrupt will be reasserted as soon as SD_IE[8] CIRQ_ENABLE is set to 1. Writes to this bit are ignored. 0h (R) = No card interrupt 1h (R) = Generate card interrupt
  • 0h = No interrupt occured
  • 1h = Interrupt occured
7CREMR/W0hCard Removal. This bit is set automatically when SD_PSTATE[CINS] changes from 1 to 0. A clear of this bit doesn't affect Card inserted present state (SD_PSTATE[CINS]). 0h (W) = Status bit unchanged 0h (R) = Card State stable or debouncing 1h (W) = Status is cleared 1h (R) = Card Removed
  • 0h = No interrupt occured
  • 1h = Interrupt occured
6CINSR/W0hCard Insertion. This bit is set automatically when SD_PSTATE[CINS] changes from 0 to 1. A clear of this bit doesn't affect Card inserted present state (SD_PSTATE[CINS]). 0h (W) = Status bit unchanged 0h (R) = Card State stable or debouncing 1h (W) = Status is cleared. 1h (R) = Card inserted
  • 0h = No interrupt occured
  • 1h = Interrupt occured
5BRRR/W0hBuffer read ready. This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by the SD_BLK [10:0] BLEN bit field is completely written in the buffer. It indicates that the memory card has filled out the buffer and that the local host needs to empty the buffer by reading it. Note: If the DMA receive-mode is enabled, this bit is never set instead a DMA receive request to the main DMA controller of the system is generated. 0h (W) = Status bit unchanged 0h (R) = Not ready to read buffer 1h (W) = Status is cleared. 1h (R) = Ready to read buffer
  • 0h = No interrupt occured
  • 1h = Interrupt occured
4BWRR/W0hBuffer write ready. This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by SD_BLK [10:0] BLEN. It indicates that the memory card has emptied one block from the buffer and that the local host is able to write one block of data into the buffer. Note: If the DMA transmit mode is enabled, this bit is never set instead, a DMA transmit request to the main DMA controller of the system is generated. 0h (W) = Status bit unchanged 0h (R) = Not ready to write buffer 1h (W) = Status is cleared. 1h (R) = Ready to write buffer
  • 0h = No interrupt occured
  • 1h = Interrupt occured
3DMAR/W0hDMA Interrupt This status is set when an interrupt is required after the data transfer is complete.
  • 0h = No interrupt occured
  • 1h = Interrupt occured
2BGER/W0hBlock gap event. When a stop at block gap is requested (SD_HCTL[16] SBGR bit), this bit is automatically set when transaction is stopped at the block gap during a read or write operation. 0h (W) = Status bit unchanged 0h (R) = No block gap event 1h (W) = Status is cleared 1h (R) = Transaction stopped at block gap
  • 0h = No interrupt occured
  • 1h = Interrupt occured
1TCR/W0hTransfer completed. This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (SD_HCTL[16] SBGR bit). 0h (W) = Status bit unchanged 0h (R) = No transfer complete 1h (W) = Status is cleared 1h (R) = Data transfer complete
  • 0h = No interrupt occured
  • 1h = Interrupt occured
0CCR/W0hCommand complete. This bit is set when a 1-to-0 transition occurs in the register command inhibit (SD_PSTATE[0] CMDI bit) 0h (W) = Status bit unchanged 0h (R) = No command complete 1h (W) = Status is cleared 1h (R) = Command complete
  • 0h = No interrupt occured
  • 1h = Interrupt occured

20.4.20 IE Register (Offset = 234h) [Reset = 00000000h]

IE is shown in Table 20-33.

Return to the Summary Table.

This register allows to enable/disable the module to set status bits on an event-by-event basis. SD_IE[31:16] = Error Interrupt Status Enable SD_IE[15:0] = Normal Interrupt Status Enable

Table 20-33 IE Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29BADAENR/W0hBad access to data space interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
28CERRENR/W0hCard error interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
27RESERVEDR0hReserved
26NOUSE1R/W0hNo use Note: Writing values other than 0 might produce undesired results. Always set this bits to 0.
  • 0h = Minimum value
  • 1h = Maximum value
25ADMAEENR/W0hADMA Error Status Enable Note: This functionality is not supported, since MADMA_EN is set to 0 in the design.
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
24ACEENR/W0hAuto CMD12 error interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
23RESERVEDR0hReserved
22DEBENR/W0hData end bit error interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
21DCRCENR/W0hData CRC error interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
20DTOENR/W0hData timeout error interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
19CIEENR/W0hCommand index error interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
18CEBENR/W0hCommand end bit error interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
17CCRCENR/W0hCommand CRC error interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
16CTOENR/W0hCommand timeout error interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
15NULLR0hFixed to 0. The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored.
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
14-11RESERVEDR0hReserved
10NOUSE0R/W0hNo use Note: Writing values other than 0 might produce undesired results. Always set this bits to 0.
  • 0h = Minimum value
  • 1h = Maximum value
9OBIENR/W0hOut-of-band interrupt enable A write to this register when SD_CON[14] OBIE is cleared to 0 is ignored. Note: The OBI functionallity is not supported!
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
8CIRQENR/W0hCard interrupt enable. A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine does not remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is set to 1.
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
7CREMENR/W0hCard Removal interrupt Enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
6CINSENR/W0hCard Insertion interrupt Enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
5BRRENR/W0hBuffer read ready interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
4BWRENR/W0hBuffer write ready interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
3DMAENR/W0hDMA interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
2BGEENR/W0hBlock gap event interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
1TCENR/W0hTransfer completed interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
0CCENR/W0hCommand completed interrupt enable
  • 0h = Interrupt masked
  • 1h = Interrupt enabled

20.4.21 ISE Register (Offset = 238h) [Reset = 00000000h]

ISE is shown in Table 20-34.

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This register allows to enable/disable the module internal interrupt signaling on an event-by-event basis. SD_ISE[31:16] = Error Interrupt Signal Enable SD_ISE[15:0] = Normal Interrupt Signal Enable

Table 20-34 ISE Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29BADASENR/W0hBad access to data space interrupt enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
28CERRSENR/W0hCard error interrupt signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
27RESERVEDR0hReserved
26NOUSE1R/W0hNo use Note: Writing values other than 0 might produce undesired results. Always set this bit to 0.
  • 0h = Always set this bit to 0
  • 1h = Do not set this bit
25ADMAESENR/W0hADMA Error Signal Enable Note: This functionality is not supported, since MADMA_EN is set to 0 in the design.
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
24ACESENR/W0hAuto CMD12 error signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
23RESERVEDR0hReserved
22DEBSENR/W0hData end bit error signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
21DCRCSENR/W0hData CRC error signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
20DTOSENR/W0hData timeout error signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
19CIESENR/W0hCommand index error signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
18CEBSENR/W0hCommand end bit error signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
17CCRCSENR/W0hCommand CRC error signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
16CTOSENR/W0hCommand timeout error signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
15NULLR0hFixed to 0. The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored.
  • 0h = Interrupt masked
  • 1h = Interrupt enabled
14-11RESERVEDR0hReserved
10NOUSE0R/W0hNo use Note: Writing values other than 0 might produce undesired results. Always set this bit to 0.
  • 0h = Always set this bit to 0
  • 1h = Do not set this bit
9OBISENR/W0hOut-of-band interrupt signal status enable. A write to this register when SD_CON[14] OBIE is cleared to 0 is ignored. Note: The OBI functionallity is not supported!
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
8CIRQSENR/W0hCard interrupt signal status enable. A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine does not remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is set to 1.
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
7CREMSENR/W0hCard Removal signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
6CINSSENR/W0hCard Insertion signal status enable.
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
5BRRSENR/W0hBuffer read ready signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
4BWRSENR/W0hBuffer write ready signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
3DMASENR/W0hDMA signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
2BGESENR/W0hBlock gap event signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
1TCSENR/W0hTransfer completed signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled
0CCSENR/W0hCommand completed signal status enable
  • 0h = Status Interrupt signaling disabled
  • 1h = Status Interrupt signaling enabled

20.4.22 AC12 Register (Offset = 23Ch) [Reset = 00000000h]

AC12 is shown in Table 20-35.

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SD_AC12 Error register The host driver may determine which of the errors cases related to Auto CMD12 has occurred by checking this SD_AC12 register when an auto CMD12 error interrupt occurs. This register is valid only when auto CMD12 is enabled (SD_CMD.ACEN) and auto CMD12Error (SD_STAT.ACE) is set to 1. These bits are automatically reset when starting a new adtc command with data.

Table 20-35 AC12 Register Field Descriptions
BitFieldTypeResetDescription
31NOUSE1R/W0hNo use Note: Writing values other than 0 might produce undesired results. Always set this bit to 0.
  • 0h = Always set this bit to 0
  • 1h = Do not set this bit
30AIENR/W0hAsynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode (and zero is set to Interrupt Pin Select in the Shared Bus Control register). If this bit is set to 1, the Host Driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the Host Controller continues to deliver the Card Interrupt to the host when it is asserted by the Card.
  • 0h = Asynchronous Interrupt disabled
  • 1h = Asynchronous Interrupt enabled
29-24RESERVEDR0hReserved
23-22NOUSE0R/W0hNo use Note: Writing values other than 0 might produce undesired results. Always set this bit to 0.
  • 0h = Always set this bit to 0
  • 1h = Do not set this bit
21-20DSSELR/W0hDriver Strength Select Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective. This field can be set depends on Driver Type A, C and D support bits in the Capabilities register.
  • 0h = Driver Type B is selected
  • 1h = Driver Type A is selected
  • 2h = Driver Type C is selected
  • 3h = Driver Type D is selected
19V1P8SENR/W0h1.8V Signaling Enable This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within 5ms. Host Controller clears this bit if switching to 1.8V signaling fails. Clearing this bit from 1 to 0 starts changing signal voltage from 1.8V to 3.3V. 3.3V regulator output shall be stable within 5ms. Host Driver can set this bit to 1 when Host Controller supports 1.8V signaling (One of support bits is set to 1: SDR50, SDR104 or DDR50 in the Capabilities register) and the card or device supports UHS-I (S18A=1. Refer to Bus Signal Voltage Switch Sequence in the Physical Layer Specification Version 3.0x). Note: Dragon supports only 3.3V. Always set this bit to 0.
  • 0h = 3.3V Signaling
  • 1h = 1.8V Signaling
18-16UHSMSR/W0hUHS Mode Select This field is used to select one of UHS-I modes or e.MMC HS200 mode and effective when 1.8V Signaling Enable is set to 1. Note: Dragon does not support 1.8V signaling and UHS modes. Always set this bitfield to 0.
  • 0h = SDR12
  • 1h = SDR25
  • 2h = SDR50
  • 3h = SDR104 / HS200
  • 4h = DDR50
15-8RESERVEDR0hReserved
7CNIR0hCommand not issue by auto CMD12 error If this bit is set to 1, a pending command is not executed due to auto CMD12 error ACEB, ACCE, ACTO, or ACNE.
  • 0h = No error
  • 1h = Error occurred
6-5RESERVEDR0hReserved
4ACIER0hAuto CMD12 index error This bit is a set to 1 when response index differs from corresponding command auto CMD12 index previously emitted. This bit depends on the command index check enable (SD_CMD.CICEN).
  • 0h = No error
  • 1h = Error occurred
3ACEBR0hAuto CMD12 end bit error. This bit is set to 1 when detecting a 0 at the end bit position of auto CMD12 command response.
  • 0h = No error
  • 1h = Error occurred
2ACCER0hAuto CMD12 CRC error. This bit is set to 1 when a CRC7 error is detected in the auto CMD12 command response.
  • 0h = No error
  • 1h = Error occurred
1ACTOR0hAuto CMD12 timeout error. This bit is set to 1 if no response is received within 64 clock cycles from the end bit of the auto CMD12 command.
  • 0h = No error
  • 1h = Error occurred
0ACNER0hAuto CMD12 not executed. This bit is set to 1 if multiple block data transfer command has started and if an error occurs in command before auto CMD12 starts.
  • 0h = Auto CMD12 executed
  • 1h = Auto CMD12 not executed

20.4.23 CAPA Register (Offset = 240h) [Reset = 20E10080h]

CAPA is shown in Table 20-36.

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Capability register This register lists the capabilities of the MMC/SD/SDIO host controller.

Table 20-36 CAPA Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29AISR1hAsynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt.
  • 0h = Not supported
  • 1h = Supported
28BUS64BITR0h64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus. 0h (R) = 32-bit System bus address 1h (R) = 64-bit System bus address
  • 0h = Not supported
  • 1h = Supported
27RESERVEDR0hReserved
26VS18R/W0hVoltage support 1.8 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initialization. This register is only reinitialized by a hard reset (via mmc_RESET signal). 0h (W) = 1.8 V not supported 0h (R) = 1.8 V not supported 1h (W) = 1.8 V supported 1h (R) = 1.8 V supported
  • 0h = Not supported
  • 1h = Supported
25VS30R/W0hVoltage support 3.0V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initialization. This register is only reinitialized by a hard reset (via mmc_RESET signal). 0h (W) = 3.0 V not supported 0h (R) = 3.0 V not supported 1h (W) = 3.0 V supported 1h (R) = 3.0 V supported
  • 0h = Not supported
  • 1h = Supported
24VS33R/W0hVoltage support 3.3V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initialization. This register is only reinitialized by a hard reset (via mmc_RESET signal). 0h (W) = 3.3 V not supported 0h (R) = 3.3 V not supported 1h (W) = 3.3 V supported 1h (R) = 3.3 V supported
  • 0h = Not supported
  • 1h = Supported
23SRSR1hSuspend/resume support (SDIO cards only). This bit indicates whether the host controller supports suspend/resume functionality.
  • 0h = Not supported
  • 1h = Supported
22DSR1hDMA support This bit indicates that the Host controller is able to use DMA to transfer data between system memory and the Host controller directly.
  • 0h = Not supported
  • 1h = Supported
21HSSR1hHigh-speed support This bit indicates that the host controller supports high speed operations and can supply an up-to-52 MHz clock to the card.
  • 0h = Not supported
  • 1h = Supported
20RESERVEDR0hReserved
19AD2SR0hThis bit indicates whether the Host Controller is capable of using ADMA2.
  • 0h = Not supported
  • 1h = Supported
18RESERVEDR0hReserved
17-16MBLR1hMaximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. The host controller supports 512 bytes and 1024 bytes block transfers. 0h = 512 bytes 1h = 1024 bytes 2h = 2048 bytes
  • 0h = Minimum value
  • 3h = Maximum value
15-14RESERVEDR0hReserved
13-8BCFR0hBase clock frequency for clock provided to the card. ARRAY(0x1bfe1b0)
  • 0h = Minimum value
  • 3Fh = Maximum value
7TCUR1hTimeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error.
  • 0h = kHz
  • 1h = MHz
6RESERVEDR0hReserved
5-0TCFR0hTimeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (DTO interrupt). The timeout clock frequency depends on the frequency of the clock provided to the card. The value of the timeout clock frequency is not available in this register.
  • 0h = Minimum value
  • 3Fh = Maximum value

20.4.24 CURCAPA Register (Offset = 248h) [Reset = 00000000h]

CURCAPA is shown in Table 20-37.

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Current capability register This register indicates the maximum current capability for each voltage.

Table 20-37 CURCAPA Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16CUR18R/W0hMaximum current for 1.8V The maximum current capability for this voltage is not available. Feature not implemented.
  • 0h = Minimum value
  • FFh = Maximum value
15-8CUR30R/W0hMaximum current for 3.0V The maximum current capability for this voltage is not available. Feature not implemented.
  • 0h = Minimum value
  • FFh = Maximum value
7-0CUR33R/W0hMaximum current for 3.3V The maximum current capability for this voltage is not available. Feature not implemented.
  • 0h = Minimum value
  • FFh = Maximum value

20.4.25 FE Register (Offset = 250h) [Reset = 00000000h]

FE is shown in Table 20-38.

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The Force Event register is not a physically implemented register. Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt Status Register, if corresponding bit of the Error Interrupt Status Enable Register is set.

Table 20-38 FE Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29BADAW0hForce Event Bad access to data space
  • 0h = No interrupt
  • 1h = Interrupt forced
28CERRW0hForce Event Card error
  • 0h = No interrupt
  • 1h = Interrupt forced
27-25RESERVEDR0hReserved
24ACEW0hForce Event Auto CMD12 error
  • 0h = No interrupt
  • 1h = Interrupt forced
23RESERVEDR0hReserved
22DEBW0hForce Event Data End Bit error
  • 0h = No interrupt
  • 1h = Interrupt forced
21DCRCW0hForce Event Data CRC error
  • 0h = No interrupt
  • 1h = Interrupt forced
20DTOW0hForce Event Data timeout error
  • 0h = No interrupt
  • 1h = Interrupt forced
19CIEW0hForce Event Command index error
  • 0h = No interrupt
  • 1h = Interrupt forced
18CEBW0hForce Event Command end bit error
  • 0h = No interrupt
  • 1h = Interrupt forced
17CCRCW0hForce Event Comemand CRC error
  • 0h = No interrupt
  • 1h = Interrupt forced
16CTOW0hForce Event Command Timeout error
  • 0h = No interrupt
  • 1h = Interrupt forced
15-8RESERVEDR0hReserved
7CNIW0hForce Event Command not issue by Auto CMD12 error
  • 0h = No interrupt
  • 1h = Interrupt forced
6-5RESERVEDR0hReserved
4ACIEW0hForce Event Auto CMD12 index error
  • 0h = No interrupt
  • 1h = Interrupt forced
3ACEBW0hForce Event Auto CMD12 end bit error
  • 0h = No interrupt
  • 1h = Interrupt forced
2ACCEW0hForce Event Auto CMD12 CRC error
  • 0h = No interrupt
  • 1h = Interrupt forced
1ACTOW0hForce Event Auto CMD12 timeout error
  • 0h = No interrupt
  • 1h = Interrupt forced
0ACNEW0hForce Event Auto CMD12 not executed.
  • 0h = No interrupt
  • 1h = Interrupt forced

20.4.26 REV Register (Offset = 2FCh) [Reset = 33020000h]

REV is shown in Table 20-39.

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Revision register This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy.

Table 20-39 REV Register Field Descriptions
BitFieldTypeResetDescription
31-24VREVR33hVendor Version Number Bits 7 to 4 are the major revision, bits 3 to 0 are the minor revision. Examples: 0x10 for 1.0 and 0x21 for 2.1. Reset value is 0x31.
  • 0h = Minimum value
  • FFh = Maximum value
23-16SREVR2hSpecification Version Number This status indicates the Standard SD Host Controller Specification Version. The upper and lower 4 bits indicate the version. 0h: SD Host Specification Version 1.00. 1h: SD Host Specification Version 2.00. 2h: SD Host Specification Version 3.00. 3h: Reserved
  • 0h = Minimum value
  • FFh = Maximum value
15-1RESERVEDR0hReserved
0SISR0hSlot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all, the interrupt signal shall be deasserted and this status shall read 0.
  • 0h = No interrupt is asserted
  • 1h = Interrupt is asserted

20.4.27 TPSEL Register (Offset = 1040h) [Reset = 00000000h]

TPSEL is shown in Table 20-40.

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Test-Port select.

Table 20-40 TPSEL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0VALR/W0hTest port 0 or 1
  • 0h = 0
  • 1h = 1

20.4.28 DMAMODE Register (Offset = 1048h) [Reset = 00000001h]

DMAMODE is shown in Table 20-41.

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DMA mode select: This register define the behavior of DMA request signal that allow tranmission of data.

Table 20-41 DMAMODE Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0VALR/W1h0h = In this case, DMA required to read/write data from SD_DATA register, the value of DMA_INDICATION_SELECT register is d'ont care and the trigger to transmit data from the internal FIFO defined by SD_BLK.BLEN register as a threshold. 1h = DMA required to read/write data from BUFIF register the value of DMA_INDICATION_SELECT define the trigger of the internal FIFO.
  • 0h = Disable to trig the internal FIFO with threshold, using DMA indication instead
  • 1h = Enable to trig the internal FIFO with threshold

20.4.29 DMAIND Register (Offset = 1050h) [Reset = 00000001h]

DMAIND is shown in Table 20-42.

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DMA indication select: This register define the behavior of transmitting data from/to the card using DMA If DMA_MODE_SELECT =1, then the value of of this register is d'ont care, else it define the trigger of the internal FIFO

Table 20-42 DMAIND Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0VALR/W1h0h = IP transmit the data to/from the card after each DMA 'BLOCK' transmitted. In this case SDMMC.SD_BLK.BLEN shoud be equal to HOST_DMA.JOB_CTRL_CH7.MEM_JOB_CTRL_CHAN_7_BLOCK_SIZE 1h = IP transmit the data to the card after each DMA 'JOB' transmitted. In this case SDMMC.SD_BLK.BLEN shoud be equal to HOST_DMA.TRANS_CTRL_CH7.MEM_TRANS_CTRL_CHAN_7_TRANS_NUM_B
  • 0h = The IP transmit the data to/from the card, after each DMA transmitted block.
  • 1h = The IP transmit the data to/from the card, only in the end of the DMA job.

20.4.30 CLKSEL Register (Offset = 1054h) [Reset = 00000000h]

CLKSEL is shown in Table 20-43.

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This register define the functional clock frequency, and whether the clock is synchronized to main clock.

Table 20-43 CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0VALR/W0h0h = 40MHz post-swallowing 1h = 80MHz pro-swallowing
  • 0h = post-swallowing 40MHz clock to main clock
  • 1h = pre-swallowing 80MHz clock

20.4.31 EVTMODE Register (Offset = 10E0h) [Reset = 00000001h]

EVTMODE is shown in Table 20-44.

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Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Table 20-44 EVTMODE Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0INT0CFGR/W1hEvent line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]
  • 0h = The interrupt or event line is disabled.
  • 1h = The interrupt or event line is in software mode. Software must clear the RIS.
  • 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

20.4.32 DESC Register (Offset = 10FCh) [Reset = 02111000h]

DESC is shown in Table 20-45.

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This register identifies the peripheral and its exact version.

Table 20-45 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR2111hModule identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
  • 0h = Smallest value
  • FFFFh = Highest possible value
15-12FEATURSTR0hFeature Set for the module *instance*
  • 0h = Smallest value
  • Fh = Highest possible value
11-8INSTNUMR0hInstance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
  • 0h = Smallest value
  • Fh = Highest possible value
7-4MAJREVR0hMajor rev of the IP
  • 0h = Smallest value
  • Fh = Highest possible value
3-0MINREVR0hMinor rev of the IP
  • 0h = Smallest value
  • Fh = Highest possible value

20.4.33 SDMMCSTAT Register (Offset = 1100h) [Reset = X0000000h]

SDMMCSTAT is shown in Table 20-46.

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SDMMC Status register

Table 20-46 SDMMCSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0STATERXhSDMMC state indication
  • 0h = IP is active but is not transmitting
  • 1h = IP is active and transmitting

20.4.34 BUFIF_y Register (Offset = 1110h + formula) [Reset = 00000000h]

BUFIF_y is shown in Table 20-47.

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SRAM Data Access Registers These registers are the 32-bit entry point of the SRAM buffer for read or write data transfers to and from the SDMMC card. Data[1] register is an alias for the SD_BUFIF register and needs to be used for normal (non safety, non burst) buffer accesses. Data[1..4] registers need to be used for non safety, incremental VBUSP burst accesses. For safety accesses (write with readback and double read), DataS[1..4] registers need to be used. The SRAM buffer size is 32bits x 256 (1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput. Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. If the local host accesses this register byte-wise or 16bit-wise, the least significant byte (bits [7:0]) must always be written/read first. The update of the buffer address is done on the most significant byte write.

Offset = 1110h + (y * 4h); where y = 0h to 3h

Table 20-47 BUFIF_y Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hBuffer data register In functional mode (SD_CON.MODE = FUNC): - a read access to this register is allowed only when the buffer read enable status is set to 1 (SD_PSTATE.BREN), otherwise a bad access (SD_STAT.BADA) is signaled. - a write access to this register is allowed only when the buffer write enable status is set to 1 (SD_PSTATE.BWEN), otherwise a bad access (SD_STAT.BADA) is signaled and the data is not written.
  • 0h = Minimum value
  • FFFFFFFFh = Maximum value

20.4.35 CLKCFG Register (Offset = 4000h) [Reset = 00000000h]

CLKCFG is shown in Table 20-48.

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Clock Enable Register

Table 20-48 CLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENR/W0hClock Disable / Enable for: * bus_clk (main clock) - 80MHz ; * card_clk (pll_clk) - 40MHz ; * lf_clk (slow_clk) - 32KHz ;