SWRU626 December   2025 CC3501E , CC3551E

 

  1.   1
  2. 1 Read This First
    1. 1.1 About This Manual
    2. 1.2 Register, Field, and Bit Calls
    3.     Trademarks
  3. 2 Architecture Overview
    1. 2.1  Target Applications
    2. 2.2  Introduction
    3. 2.3  Internal System Diagram
    4. 2.4  Arm Cortex M33
      1. 2.4.1 Processor Core
      2. 2.4.2 SysTick Timer
      3. 2.4.3 Nested Vectored Interrupt Controller
      4. 2.4.4 System Control Block (SCB)
      5. 2.4.5 TI AI instruction extensions
    5. 2.5  Power Management
      1. 2.5.1 VDD_MAIN
      2. 2.5.2 VDD_IO
      3. 2.5.3 VDDSF
      4. 2.5.4 VDD_PA
    6. 2.6  Debug Subsystem (DEBUGSS)
    7. 2.7  Memory Subsystem (MEMSS)
      1. 2.7.1 External Memory Interface
    8. 2.8  Hardware Security Module
    9. 2.9  General Purpose Timers (GPT)
    10. 2.10 Real Time Clock (RTC)
    11. 2.11 Direct Memory Access
    12. 2.12 GPIOs
    13. 2.13 Communication Peripherals
      1. 2.13.1 UART
      2. 2.13.2 I2C
      3. 2.13.3 SPI
      4. 2.13.4 I2S
      5. 2.13.5 SDMMC
      6. 2.13.6 SDIO
      7. 2.13.7 CAN
      8. 2.13.8 ADC
  4. 3  Arm Cortex-M33 Processor
    1. 3.1 Arm Cortex-M33 Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 M33 instantiation parameters
    4. 3.4 Arm Cortex-M33 System Peripheral Details
      1. 3.4.1 Floating Point Unit (FPU)
      2. 3.4.2 Memory Protection Unit (MPU)
      3. 3.4.3 Digital Signal Processing (DSP)
      4. 3.4.4 Security Attribution Unit (SAU)
      5. 3.4.5 System Timer
      6. 3.4.6 Nested Vectored Interrupt Controller
      7. 3.4.7 System Control Block
      8. 3.4.8 System Control Space
    5. 3.5 CPU Sub-System Peripheral Details
      1. 3.5.1 Trace Port Interface Unit (TPIU)
      2. 3.5.2 DAP Bridge and Debug Authentication
      3. 3.5.3 Implementation Defined Attribution Unit (IDAU)
    6. 3.6 Programming Model
      1. 3.6.1 Modes of operation and execution
        1. 3.6.1.1 Security states
        2. 3.6.1.2 Operating modes
        3. 3.6.1.3 Operating states
        4. 3.6.1.4 Privileged access and unprivileged user access
      2. 3.6.2 Instruction set summary
      3. 3.6.3 Memory model
        1. 3.6.3.1 Private Peripheral Bus
        2. 3.6.3.2 Unaligned accesses
      4. 3.6.4 Processor core registers summary
      5. 3.6.5 Exceptions
        1. 3.6.5.1 Exception handling and prioritization
    7. 3.7 TrustZone-M
      1. 3.7.1 Overview
      2. 3.7.2 M33 Configuration
      3. 3.7.3 Description of elements
        1. 3.7.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 3.7.3.1.1 Expected use
    8. 3.8 CC35xx Host MCU Registers
      1. 3.8.1 HOSTMCU_AON Registers
      2. 3.8.2 HOST_MCU Registers
      3. 3.8.3 HOST_MCU_SEC Registers
    9. 3.9 Arm® Cortex®-M33 Registers
      1. 3.9.1  CPU_ROM_TABLE Registers
      2. 3.9.2  TPIU Registers
      3. 3.9.3  DCB Registers
      4. 3.9.4  DIB Registers
      5. 3.9.5  DWT Registers
      6. 3.9.6  FPB Registers
      7. 3.9.7  FPE Registers
      8. 3.9.8  ICB Registers
      9. 3.9.9  ITM Registers
      10. 3.9.10 MPU Registers
      11. 3.9.11 NVIC Registers
      12. 3.9.12 SAU Registers
      13. 3.9.13 SCB Registers
      14. 3.9.14 SYSTIMER Registers
      15. 3.9.15 SYSTICK Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation to HardFault
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Manager
      1. 5.4.1 Introduction
      2. 5.4.2 Interrupts List
      3. 5.4.3 Wakeup Sources
      4. 5.4.4 Shared Peripherals MUX Selector
        1. 5.4.4.1 ADC HW Event Selector Mux
        2. 5.4.4.2 I2S HW Event Selector Mux
        3. 5.4.4.3 PDM HW Event Selector Mux
      5. 5.4.5 Timers MUX Selector Mux
        1. 5.4.5.1 SysTimer0 HW Event Selector Mux
        2. 5.4.5.2 SysTimer1 HW Event Selector Mux
        3. 5.4.5.3 RTC HW Event Selector Mux
      6. 5.4.6 GPTIMERs MUX Selector Mux
        1. 5.4.6.1 GPTIMER0 HW Event Selector Mux
        2. 5.4.6.2 GPTIMER1 HW Event Selector Mux
    5. 5.5 SOC_IC Registers
    6. 5.6 SOC_AON Registers
    7. 5.7 SOC_AAON Registers
  7. 6 Debug Subsystem (DEBUGSS)
    1. 6.1 Introduction
    2. 6.2 Block Diagram
    3. 6.3 Overview
    4. 6.4 Physical Interface
    5. 6.5 Debug Access Ports
    6. 6.6 Debug Features
      1. 6.6.1 Processor Debug
      2. 6.6.2 Breakpoint Unit (BPU)
      3. 6.6.3 Peripheral Debug
    7. 6.7 Behavior in Low Power Modes
    8. 6.8 Debug Access Control
    9. 6.9 SOC_DEBUGSS Registers
  8. 7 Power, Reset, Clock Management
    1. 7.1 Power Management
      1. 7.1.1 Power Supply System
        1. 7.1.1.1 VDD_MAIN
        2. 7.1.1.2 VIO
        3. 7.1.1.3 VDDSF
        4. 7.1.1.4 VPA
      2. 7.1.2 Power States
      3. 7.1.3 Power Domains
      4. 7.1.4 Brownout (BOR)
      5. 7.1.5 Boot Sequence
    2. 7.2 Reset
      1. 7.2.1 Reset Cause
      2. 7.2.2 Watchdog Timer (WDT)
    3. 7.3 Clocks
      1. 7.3.1 Fast Clock
      2. 7.3.2 Slow Clock
        1. 7.3.2.1 Slow Clock Overview
        2. 7.3.2.2 Slow Clock Tree
        3. 7.3.2.3 Slow Clock Boot Process
    4. 7.4 PRCM_AON Registers
    5. 7.5 PRCM_SCRATCHPAD Registers
  9. 8 Memory Subsystem (MEMSS)
    1. 8.1  Introduction
    2. 8.2  SRAM
    3. 8.3  D-Cache
    4. 8.4  Flash
    5. 8.5  PSRAM
    6. 8.6  XiP Memory Access
      1. 8.6.1 OTFDE
      2. 8.6.2 xSPI
      3. 8.6.3 Topology
      4. 8.6.4 µDMA
      5. 8.6.5 Arbiter
    7. 8.7  ICACHE Registers
    8. 8.8  DCACHE Registers
    9. 8.9  OSPI Registers
    10. 8.10 HOST_XIP Registers
  10. 9 Hardware Security Module (HSM)
    1. 9.1 Introduction
    2. 9.2 Overview
    3. 9.3 Mailbox and Register Access Firewall
    4. 9.4 DMA Firewall
    5. 9.5 HSM Key Storage
    6. 9.6 HSM Registers
    7. 9.7 HSM_NON_SEC Registers
    8. 9.8 HSM_SEC Registers
  11. 10Device Boot and Bootloader
    1. 10.1 CC35xx Boot Concept
    2. 10.2 Features
    3. 10.3 Vendor Images Format and Processing
      1. 10.3.1 External Flash Arrangement
      2. 10.3.2 Vendor Images Format
    4. 10.4 Boot Flows
      1. 10.4.1 Application Execution Boot Flow
      2. 10.4.2 Activation Flow
      3. 10.4.3 Initial Programming Flow
      4. 10.4.4 Reprogramming Flow
      5. 10.4.5 Wireless Connectivity Testing Tool Flow
    5. 10.5 Chain of Trust
  12. 11Direct Memory Access (DMA)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Channels Assignment
      2. 11.3.2 Transfer Types
      3. 11.3.3 Addressing Modes
      4. 11.3.4 Transfer Modes
      5. 11.3.5 DMA Aligner Support
      6. 11.3.6 Initiating DMA Transfers
      7. 11.3.7 Stopping DMA Transfers
      8. 11.3.8 Channel Priorities
      9. 11.3.9 DMA Interrupts
    4. 11.4 HOST_DMA Registers
  13. 12One Time Programming (OTP)
  14. 13General Purpose Timers (GPT)
    1. 13.1 Overview
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1  Prescaler
      2. 13.3.2  Counter
      3. 13.3.3  Target
      4. 13.3.4  Channel Input Logic
      5. 13.3.5  Channel Output Logic
      6. 13.3.6  Channel Actions
        1. 13.3.6.1 Period and Pulse Width Measurement
        2. 13.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 13.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 13.3.7  Channel Capture Configuration
      8. 13.3.8  Channel Filters
        1. 13.3.8.1 Setting up the Channel Filters
      9. 13.3.9  Synchronize Multiple GPTimers
      10. 13.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 13.4 Timer Modes
      1. 13.4.1 Quadrature Decoder
      2. 13.4.2 DMA
      3. 13.4.3 IR Generation
      4. 13.4.4 Fault and Park
      5. 13.4.5 Dead-Band
      6. 13.4.6 Dead-Band, Fault and Park
      7. 13.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 13.5 GPTIMER Registers
  15. 14System Timer (SysTimer)
    1. 14.1 Overview
    2. 14.2 Block Diagram
    3. 14.3 Functional Description
      1. 14.3.1 Common Channel Features
        1. 14.3.1.1 Compare Mode
        2. 14.3.1.2 Capture Mode
        3. 14.3.1.3 Additional Channel Arming Methods
      2. 14.3.2 Interrupts and Events
    4. 14.4 SYSRESOURCES Registers
    5. 14.5 SYSTIM Registers
  16. 15Real-Time Clock (RTC)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Interrupts and Events
      1. 15.3.1 Input Event
      2. 15.3.2 Output Event
      3. 15.3.3 Arming and Disarming Channels
    4. 15.4 CAPTURE and COMPARE Configurations
      1. 15.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 15.4.2 CHANNEL 1 - CAPTURE CHANNEL
    5. 15.5 RTC Registers
  17. 16General Purpose Input/Output (GPIOs)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 I/O Mapping and Configuration
      1. 16.3.1 Basic I/O Mapping
      2. 16.3.2 Pin Mapping
    4. 16.4 Edge Detection
    5. 16.5 GPIO
    6. 16.6 I/O Pins
    7. 16.7 Unused Pins
    8. 16.8 IOMUX Registers
  18. 17Universal Asynchronous Receivers/Transmitters (UART)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 UART Functional Description
      1. 17.3.1 Transmit and Receive Logic
      2. 17.3.2 Baud Rate Generation
      3. 17.3.3 FIFO Operation
        1. 17.3.3.1 FIFO Remapping
      4. 17.3.4 Data Transmission
      5. 17.3.5 Flow Control
      6. 17.3.6 IrDA Encoding and Decoding
      7. 17.3.7 Interrupts
      8. 17.3.8 Loopback Operation
    4. 17.4 UART-LIN Specification
      1. 17.4.1 Break transmission in UART mode
      2. 17.4.2 Break reception in UART mode
      3. 17.4.3 Break/Synch transmission in LIN mode
      4. 17.4.4 Break/Synch reception in LIN mode
      5. 17.4.5 Dormant mode operation
      6. 17.4.6 Event signal generation
      7. 17.4.7 Event signal detection when device is in active/idle modes
      8. 17.4.8 Event signal detection when device is in sleep mode
    5. 17.5 Interface to Host DMA
    6. 17.6 Initialization and Configuration
    7. 17.7 UART Registers
  19. 18Serial Peripheral Interface (SPI)
    1. 18.1 Overview
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Signal Description
    3. 18.3 Functional Description
      1. 18.3.1  Clock Control
      2. 18.3.2  FIFO Operation
        1. 18.3.2.1 Transmit FIFO
        2. 18.3.2.2 Repeated Transmit Operation
        3. 18.3.2.3 Receive FIFO
        4. 18.3.2.4 FIFO Flush
      3. 18.3.3  Interrupts
      4. 18.3.4  Data Format
      5. 18.3.5  Delayed Data Sampling
      6. 18.3.6  Chip Select Control
      7. 18.3.7  Command Data Control
      8. 18.3.8  Protocol Descriptions
        1. 18.3.8.1 Motorola SPI Frame Format
        2. 18.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 18.3.8.3 MICROWIRE Frame Format
      9. 18.3.9  CRC Configuration
      10. 18.3.10 Auto CRC Functionality
      11. 18.3.11 SPI Status
      12. 18.3.12 Debug Halt
    4. 18.4 Host DMA Operation
    5. 18.5 Initialization and Configuration
    6. 18.6 SPI Registers
  20. 19Inter-Integrated Circuit (I2C) Interface
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Clock Control
        1. 19.3.1.1 Internal Clock
        2. 19.3.1.2 External Clock
      2. 19.3.2 General Architecture
        1. 19.3.2.1  Start and Stop Conditions
        2. 19.3.2.2  Data Format with 7-Bit Address
        3. 19.3.2.3  Data Format with 10-Bit Addressing
          1. 19.3.2.3.1 Additional 10-Bit Scenarios
        4. 19.3.2.4  Acknowledge
        5. 19.3.2.5  Repeated Start
        6. 19.3.2.6  Clock Stretching
        7. 19.3.2.7  Arbitration
        8. 19.3.2.8  Multi-Controller mode
        9. 19.3.2.9  Glitch Suppression
        10. 19.3.2.10 FIFO Operation
        11. 19.3.2.11 Burst Mode Operation
        12. 19.3.2.12 DMA Operation
        13. 19.3.2.13 Flush Stale Tx Data in Target Mode
          1. 19.3.2.13.1 Recommended Sequence
        14. 19.3.2.14 SMBUS 3.0 Support
          1. 19.3.2.14.1 Quick Command
          2. 19.3.2.14.2 Acknowledge Control
          3. 19.3.2.14.3 Alert Response protocol
          4. 19.3.2.14.4 Address Resolution Protocol
          5. 19.3.2.14.5 Enhanced Acknowledge Control
    4. 19.4 Initialization and Configuration
    5. 19.5 Interrupts
    6. 19.6 I2C Registers
  21. 20Secure Digital Multimedia Card (SDMMC)
    1. 20.1 Introduction
      1. 20.1.1 SDMMC Features
      2. 20.1.2 Integration
    2. 20.2 Functional Description
      1. 20.2.1  SDMMC Functional Modes
        1. 20.2.1.1 SDMMC Connected to an SD Card
        2. 20.2.1.2 Protocol and Data Format
          1. 20.2.1.2.1 Protocol
          2. 20.2.1.2.2 Data Format
      2. 20.2.2  SD Card Feedback
      3. 20.2.3  Resets
        1. 20.2.3.1 Hardware Reset
        2. 20.2.3.2 Software Reset
      4. 20.2.4  Interrupt Requests
        1. 20.2.4.1 Interrupt-Driven Operation
        2. 20.2.4.2 Polling
      5. 20.2.5  DMA Modes
        1. 20.2.5.1 DMA Peripheral Mode Operations
          1. 20.2.5.1.1 DMA Receive Mode
          2. 20.2.5.1.2 DMA Transmit Mode
      6. 20.2.6  Buffer Management
        1. 20.2.6.1 Data Buffer
          1. 20.2.6.1.1 Memory Size and Block Length
          2. 20.2.6.1.2 Data Buffer Status
      7. 20.2.7  Transfer Process
        1. 20.2.7.1 Different Types of Commands
        2. 20.2.7.2 Different Types of Responses
      8. 20.2.8  Transfer or Command Status and Error Reporting
        1. 20.2.8.1 Busy Timeout for R1b, R5b Response Type
        2. 20.2.8.2 Busy Timeout After Write CRC Status
        3. 20.2.8.3 Write CRC Status Timeout
        4. 20.2.8.4 Read Data Timeout
      9. 20.2.9  Auto Command 12 Timings
        1. 20.2.9.1 Auto Command 12 Timings During Write Transfer
        2. 20.2.9.2 Auto Command 12 Timings During Read Transfer
      10. 20.2.10 Transfer Stop
      11. 20.2.11 Output Signals Generation
        1. 20.2.11.1 Generation on Falling Edge of SDMMC Clock
        2. 20.2.11.2 Generation on Rising Edge of SDMMC Clock
      12. 20.2.12 Test Registers
      13. 20.2.13 SDMMC Hardware Status Features
    3. 20.3 Low-Level Programming Models
      1. 20.3.1 SDMMC Initialization Flow
        1. 20.3.1.1 Enable OCP and CLKADPI Clocks
        2. 20.3.1.2 SD Soft Reset Flow
        3. 20.3.1.3 Set SD Default Capabilities
        4. 20.3.1.4 SDMMC Host and Bus Configuration
      2. 20.3.2 Operational Modes Configuration
        1. 20.3.2.1 Basic Operations for SDMMC
        2. 20.3.2.2 Card Detection, Identification, and Selection
    4. 20.4 SDMMC Registers
  22. 21Secure Digital Input/Output (SDIO)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 SDIO Interface Description
      2. 21.3.2 Protocol and Data Format
      3. 21.3.3 I/O Read/Write Command
        1. 21.3.3.1 IO_WR_DIRECT Command (CMD52)
        2. 21.3.3.2 IO_WR_EXTENDED Command (CMD53)
      4. 21.3.4 Reset
      5. 21.3.5 FIFO Operation
        1. 21.3.5.1 Rx FIFO (For Host Write)
        2. 21.3.5.2 Tx FIFO (For Host Read)
      6. 21.3.6 Interrupt Request
        1. 21.3.6.1 External Host IRQ
        2. 21.3.6.2 M33 IRQ
      7. 21.3.7 Transaction Details
        1. 21.3.7.1 Host write to SDIO IP (Rx FIFO)
          1. 21.3.7.1.1 Host write to SDIO IP (Rx FIFO) – Long SW latency case
          2. 21.3.7.1.2 Host write to SDIO IP (Rx FIFO) – CRC Error Case
        2. 21.3.7.2 Host reads from SDIO (TX buffer)
    4. 21.4 SDIO_CORE Registers
    5. 21.5 SDIO_CARD_FN1 Registers
  23. 22Inter-Integrated Circuit Sound (I2S)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  Signal Descriptions
    4. 22.4  Functional Description
      1. 22.4.1 Pin Configuration
      2. 22.4.2 Serial Format Configuration
        1. 22.4.2.1 Register Configuration
      3. 22.4.3 Left-Justified (LJF)
        1. 22.4.3.1 Register Configuration
      4. 22.4.4 Right-Justified (RJF)
        1. 22.4.4.1 Register Configuration
      5. 22.4.5 DSP
        1. 22.4.5.1 Register Configuration
      6. 22.4.6 Clock Configuration
    5. 22.5  Memory Interface
      1. 22.5.1 Sample Word Length
      2. 22.5.2 Padding Mechanism
      3. 22.5.3 Channel Mapping
      4. 22.5.4 Sample Storage in Memory
      5. 22.5.5 DMA Operation
        1. 22.5.5.1 Start-Up
        2. 22.5.5.2 Operation
        3. 22.5.5.3 Shutdown
    6. 22.6  Samplestamp Generator
      1. 22.6.1 Samplestamp Counters
      2. 22.6.2 Start-Up Triggers
      3. 22.6.3 Samplestamp Capture
      4. 22.6.4 Achieving constant audio latency
    7. 22.7  Error Detection
    8. 22.8  Usage
      1. 22.8.1 Start-Up Sequence
      2. 22.8.2 Shutdown Sequence
    9. 22.9  I2S Configuration Guideline
    10. 22.10 I2S Registers
  24. 23Pulse Density Modulation (PDM)
    1. 23.1  Introduction
    2. 23.2  Block Diagram
    3. 23.3  Input Selection
      1. 23.3.1 PDM Data Mode
      2. 23.3.2 Manchester Input Mode
    4. 23.4  CIC Filter
      1. 23.4.1 Filter Design
      2. 23.4.2 Digital Filter Output
      3. 23.4.3 Offset Binary Mode
      4. 23.4.4 Twos-Complement Mode
    5. 23.5  FIFO Organization in Different Modes
      1. 23.5.1 Single Mono Microphone Configuration
        1. 23.5.1.1 24-bit Sample Size
          1. 23.5.1.1.1 32-bit Data Read
        2. 23.5.1.2 16-bit Sample Size
          1. 23.5.1.2.1 32-bit Data Read
          2. 23.5.1.2.2 16-bit Data Read
        3. 23.5.1.3 8-bit Sample Size
          1. 23.5.1.3.1 32-bit Data Read
          2. 23.5.1.3.2 16-bit Data Read
          3. 23.5.1.3.3 8-bit Data Read
      2. 23.5.2 Stereo or Dual Mono Microphone Configuration
        1. 23.5.2.1 24-bit Sample Size
          1. 23.5.2.1.1 32-bit Data Read
        2. 23.5.2.2 16-bit Sample Size
          1. 23.5.2.2.1 32-bit Data Read
          2. 23.5.2.2.2 16-bit Data Read
        3. 23.5.2.3 8-bit Sample Size
          1. 23.5.2.3.1 32-bit Data Read
          2. 23.5.2.3.2 16-bit Data Read
          3. 23.5.2.3.3 8-bit Data Read
      3. 23.5.3 FIFO Threshold Setting
      4. 23.5.4 Reset FIFO
    6. 23.6  Automatic Gain Control (AGC)
      1. 23.6.1 Operation in 2's Complement Format
      2. 23.6.2 Operation in Offset Binary Format
    7. 23.7  Interrupts
    8. 23.8  Clock Select and Control
    9. 23.9  DMA Operation
    10. 23.10 Samplestamp Generator
      1. 23.10.1 Samplestamp Counters
      2. 23.10.2 Start-Up Triggers
      3. 23.10.3 Samplestamp Capture
      4. 23.10.4 Achieving Constant Audio Latency
    11. 23.11 Debug‑Mode Flag Behavior
    12. 23.12 Software Guidelines
    13. 23.13 PDM Registers
  25. 24Analog to Digital Converter (ADC)
    1. 24.1 Overview
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1  ADC Core
      2. 24.3.2  Voltage Reference Options
      3. 24.3.3  Internal Channels
      4. 24.3.4  Resolution Modes
      5. 24.3.5  ADC Clocking
      6. 24.3.6  Power Down Behavior
      7. 24.3.7  Sampling Trigger Sources and Sampling Modes
        1. 24.3.7.1 AUTO Sampling Mode
        2. 24.3.7.2 MANUAL Sampling Mode
      8. 24.3.8  Sampling Period
      9. 24.3.9  Conversion Modes
      10. 24.3.10 ADC Data Format
      11. 24.3.11 Status Register
      12. 24.3.12 ADC Events
        1. 24.3.12.1 Generic Event Publishers (INT_EVENT0 & INT_EVENT1)
        2. 24.3.12.2 DMA Trigger Event Publisher (INT_EVENT2)
        3. 24.3.12.3 Generic Event Subscriber
      13. 24.3.13 Advanced Features
        1. 24.3.13.1 Window Comparator
        2. 24.3.13.2 DMA & FIFO Operation
          1. 24.3.13.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
          2. 24.3.13.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
          3. 24.3.13.2.3 DMA/CPU Operation Summary Matrix
        3. 24.3.13.3 Ad-hoc Single Conversion
    4. 24.4 ADC Registers
  26. 25Controller Area Network (CAN)
    1. 25.1 Introduction
    2. 25.2 Functions
    3. 25.3 DCAN Subsystem
    4. 25.4 DCAN Functional Description
      1. 25.4.1 Operating Modes
        1. 25.4.1.1 Software Initialization
        2. 25.4.1.2 Normal Operation
        3. 25.4.1.3 Restricted Operation Mode
        4. 25.4.1.4 Bus Monitoring Mode
        5. 25.4.1.5 Disabled Automatic Retransmission
          1. 25.4.1.5.1 Frame Transmission in DAR Mode
        6. 25.4.1.6 Power Down (Sleep Mode)
          1. 25.4.1.6.1 DCAN clock stop and wake operations
          2. 25.4.1.6.2 DCAN debug suspend operation
        7. 25.4.1.7 Test Modes
          1. 25.4.1.7.1 External Loop Back Mode
          2. 25.4.1.7.2 Internal Loop Back Mode
      2. 25.4.2 Timestamp Generation
        1. 25.4.2.1 Block Diagram
      3. 25.4.3 Timeout Counter
      4. 25.4.4 Rx Handling
        1. 25.4.4.1 Acceptance Filtering
          1. 25.4.4.1.1 Range Filter
          2. 25.4.4.1.2 Filter for specific IDs
          3. 25.4.4.1.3 Classic Bit Mask Filter
          4. 25.4.4.1.4 Standard Message ID Filtering
          5. 25.4.4.1.5 Extended Message ID Filtering
        2. 25.4.4.2 Rx FIFOs
          1. 25.4.4.2.1 Rx FIFO Blocking Mode
          2. 25.4.4.2.2 Rx FIFO Overwrite Mode
        3. 25.4.4.3 Dedicated Rx Buffers
          1. 25.4.4.3.1 Rx Buffer Handling
        4. 25.4.4.4 Debug on CAN Support
          1. 25.4.4.4.1 Filtering for Debug Messages
          2. 25.4.4.4.2 Debug Message Handling
      5. 25.4.5 Tx Handling
        1. 25.4.5.1 Transmit Pause
        2. 25.4.5.2 Dedicated Tx Buffers
        3. 25.4.5.3 Tx FIFO
        4. 25.4.5.4 Tx Queue
        5. 25.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 25.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 25.4.5.7 Transmit Cancellation
        8. 25.4.5.8 Tx Event Handling
      6. 25.4.6 FIFO Acknowledge Handling
      7. 25.4.7 DCAN Message RAM
        1. 25.4.7.1 Message RAM Configuration
        2. 25.4.7.2 Rx Buffer and FIFO Element
        3. 25.4.7.3 Tx Buffer Element
        4. 25.4.7.4 Tx Event FIFO Element
        5. 25.4.7.5 Standard Message ID Filter Element
        6. 25.4.7.6 Extended Message ID Filter Element
      8. 25.4.8 Interrupt Requests
    5. 25.5 DCAN Wrapper
    6. 25.6 DCAN Clock Enable
    7. 25.7 DCAN Registers
  27. 26Revision History

19.6 I2C Registers

Table 19-5 lists the memory-mapped registers for the I2C registers. All register offset addresses not listed in Table 19-5 should be considered as reserved locations and the register contents should not be modified.

Table 19-5 I2C Registers
OffsetAcronymRegister NameSection
100hGFCTLGlitch Filter ControlSection 19.6.1
104hCSAI2C Controller Target Address RegisterSection 19.6.2
108hCCTRHost ControlSection 19.6.3
10ChCSRController StatusSection 19.6.4
110hCTPRTimer PeriodSection 19.6.5
114hCCRController ConfigurationSection 19.6.6
118hCBMONBus Signal StatusSection 19.6.7
11ChTOARTarget Own AddressSection 19.6.8
120hTOAR2I2C Target Own Address 2Section 19.6.9
124hTCTRI2C Target Control RegisterSection 19.6.10
128hTSRI2C Target Status RegisterSection 19.6.11
12ChRXDATAReceive DataSection 19.6.12
130hTXDATATransmit DataSection 19.6.13
134hTACKCTLAcknowledgment ControlSection 19.6.14
138hFIFOCTLFIFO ControlSection 19.6.15
13ChFIFOSRFIFO StatusSection 19.6.16
140hFCLKDIVClock DividerSection 19.6.17
400hPDBGCTLDebug ControlSection 19.6.18
404hEVENT0_IMASKInterrupt Mask RegisterSection 19.6.19
408hEVENT0_RISRaw Interrupt StatusSection 19.6.20
40ChEVENT0_MISMasked Interrupt StatusSection 19.6.21
410hEVENT0_IENInterrupt EnableSection 19.6.22
414hEVENT0_IDISInterrupt DisableSection 19.6.23
418hEVENT0_IMENInterrupt Mask EnableSection 19.6.24
41ChEVENT0_IMDISInterrupt DisableSection 19.6.25
420hEVT_MODEEvent Mode SelectionSection 19.6.26
424hDESCModule IdentificationSection 19.6.27
1000hCLKCFGClock ConfigurationSection 19.6.28

Complex bit access types are encoded to fit into small table cells. Table 19-6 shows the codes that are used for access types in this section.

Table 19-6 I2C Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

19.6.1 GFCTL Register (Offset = 100h) [Reset = 00000000h]

GFCTL is shown in Table 19-7.

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This register controls the glitch filter on the SCL and SDA lines

Table 19-7 GFCTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3-0GFSELR/W0hGlitch suppression pulse width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks.
  • 0h = Bypass
  • 1h = 1 clock
  • 2h = 2 clocks
  • 3h = 3 clocks
  • 4h = 4 clocks
  • 5h = 5 clocks
  • 6h = 6 clocks
  • 7h = 7 clocks
  • 8h = 8 clocks
  • 9h = 10 clocks
  • Ah = 12 clocks
  • Bh = 14 clocks
  • Ch = 16 clocks
  • Dh = 20 clocks
  • Eh = 24 clocks
  • Fh = 31 clocks

19.6.2 CSA Register (Offset = 104h) [Reset = 00000000h]

CSA is shown in Table 19-8.

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Controller target address register

Table 19-8 CSA Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
15CMODER/W0hThis field selects the addressing mode(7-field/10-field) to be used in controller mode
  • 0h = 7-field addressing mode
  • 1h = 10-field addressing mode
14-11RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
10-1TADDRR/W0h*I2C* Target Address This field specifies bits A9 through A0 of the target address. In 7-field addressing mode as selected by MODE field, the top 3 bits are don't care
  • 0h = Smallest value
  • 3FFh = Highest possible value
0DIRR/W0hThis field specifies if the next controller operation is a Receive or Transmit
  • 0h = The controller is in transmit mode.
  • 1h = The controller is in receive mode.

19.6.3 CCTR Register (Offset = 108h) [Reset = 00000000h]

CCTR is shown in Table 19-9.

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This control register configures the *I2C* controller operation. The START field generates the START or REPEATED START condition. The STOP field determines if the cycle stops at the end of the data cycle or continues to the next transfer cycle, which could be a repeated START. To generate a single transmit cycle, the *I2C* Controller Target Address CSA register is written with the desired address, the RS field is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the operation is completed (or aborted due an error), an byte transaction completed interrupt becomes active and the data may be read from the RXDATA register. When the I2C module operates in Controller receiver mode, a set ACK field causes the I2C bus controller to transmit an acknowledge automatically after each byte. This field must be cleared when the *I2C* bus controller requires no further data to be transmitted from the target transmitter.

Table 19-9 CCTR Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
27-16MBLENR/W0hTransaction length This field contains the programmed length of bytes of the Transaction.
  • 0h = Smallest value
  • FFFh = Highest possible value
15-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
5RDONTXEMPTYR/W0hRead on TXFIFO empty
  • 0h = No special behaviour
  • 1h = When 1 the controller will transmit all bytes from the TX FIFO before continuing with the programmed Burst Run Read. If the DIR is not set to read, then this field is ignored. The Start must be set in the CCTR for proper *I2C* protocol. The controller will first send the Start Condition, *I2C* Address with R/W field set to write, before sending the bytes in the TX FIFO. When the TX FIFO is empty, the *I2C* transaction will continue as programmed in CCTR and CSA without sending a Stop Condition. This is intended to be used to perform simple *I2C* command based reads transition that will complete after initiating them without having to get an interrupt to turn the bus around.
4CACKOENR/W0hController ACK overrride enable
  • 0h = No special behavior
  • 1h = When 1 and the controller is receiving data and the number of bytes indicated in MBLEN have been received, the state machine will generate an rxdone interrupt and wait at the start of the ACK for FW to indicate if an ACK or NACK should be sent. The ACK or NACK is selected by writing the CCTR register and setting ACK accordingly. The other fields in this register can also be written at this time to continue on with the transaction. If a NACK is sent the state machine will automatically send a Stop.
3ACKR/W0hData Acknowledge Enable. Configure this field to send the ACK or NACK.
  • 0h = The last received data byte of a transaction is not acknowledged automatically by the controller.
  • 1h = The last received data byte of a transaction is acknowledged automatically by the controller.
2STOPR/W0hGenerate STOP
  • 0h = The controller does not generate the STOP condition.
  • 1h = The controller generates the STOP condition
1STARTR/W0hGenerate START
  • 0h = The controller does not generate the START condition.
  • 1h = The controller generates the START or repeated START condition
0BURSTRUNR/W0hController enable and start transaction
  • 0h = In standard mode, the controller will be unable to transmit or receive data.
  • 1h = The controller will be able to transmit or receive data

19.6.4 CSR Register (Offset = 10Ch) [Reset = 00000000h]

CSR is shown in Table 19-10.

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The status register indicates the state of the bus controller.

Table 19-10 CSR Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
27-16CBCNTR0hController Transaction Count This field contains the current count-down value of the transaction.
  • 0h = Smallest value
  • FFFh = Highest possible value
15-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6BUSBSYR0hBus is busy Controller state machine will wait until this field is cleared before starting a transaction. When first enabling the controller in multi controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the CCTR register to start the transaction so that if SCL goes low it will trigger the BUSBSY.
  • 0h = The bus is idle.
  • 1h = This Status field is set on a START or when SCL goes low. It is cleared on a STOP, or when a SCL high bus busy timeout occurs and SCL and SDA are both high. This status is cleared when the ACTIVE field is low. Note that the controller state machine will wait until this field is cleared before starting a transaction. When first enabling the controller in multi controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the CCTR register to start the transaction so that if SCL goes low it will trigger the BUSBSY.
5IDLER1h*I2C* Idle
  • 0h = The controller is not idle.
  • 1h = The controller is idle.
4ARBLSTR0hArbitration lost
  • 0h = The controller won arbitration.
  • 1h = The controller lost arbitration.
3DATACKR0hAcknowledge data
  • 0h = The transmitted data was acknowledged
  • 1h = The transmitted data was not acknowledged.
2ADRACKR0hAcknowledge address
  • 0h = The transmitted address was acknowledged
  • 1h = The transmitted address was not acknowledged.
1ERRR0hError The error can be from the target address not being acknowledged or the transmit data not being acknowledged.
  • 0h = No error was detected on the last operation.
  • 1h = An error occurred on the last operation.
0BUSYR0hController FSM busy The field is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction.
  • 0h = The controller is idle.
  • 1h = The controller is busy.

19.6.5 CTPR Register (Offset = 110h) [Reset = 00000001h]

CTPR is shown in Table 19-11.

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This register is programmed to set the timer period for the SCL clock and assign the SCL clock to standard mode.

Table 19-11 CTPR Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6-0TPRR/W1hTimer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) x (SCL_LP + SCL_HP ) x INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). INT_CLK_PRD is the functional clock period in ns. Note: INT_CLK_PRD is based on divider value selected in [FCLK_DIV:FCLK:DIV]
  • 0h = Smallest value
  • 7Fh = Highest possible value

19.6.6 CCR Register (Offset = 114h) [Reset = 00000000h]

CCR is shown in Table 19-12.

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Controller configuration register

Table 19-12 CCR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReads to this field return zero.Writes to this field are ignored.
8LPBKR/W0hI2C Loopback
  • 0h = Normal operation.
  • 1h = The controller in a test mode loopback configuration.
7-3RESERVEDR0hReads to this field return zero.Writes to this field are ignored.
2CLKSTRETCHR/W0hClock Stretching. This field controls the support for clock stretching of the *I2C* bus.
  • 0h = Disables the clock stretching detection. This can be disabled if no target on the bus does support clock streching, so that the maximum speed on the bus can be reached.
  • 1h = Enables the clock stretching detection. Enabling the clock strechting ensures compliance to the I2C standard but could limit the speed due the clock stretching.
1MCSTR/W0hMulticontroller mode. In Multicontroller mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the *I2C* controller.
  • 0h = Disable Multicontroller mode.
  • 1h = Enable Multicontroller mode.
0ACTIVER/W0hDevice Active After this field has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur.
  • 0h = Disables the *I2C* controller operation.
  • 1h = Enables the *I2C* controller operation.

19.6.7 CBMON Register (Offset = 118h) [Reset = 00000003h]

CBMON is shown in Table 19-13.

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This register is used to determine the SCL and SDA signal status.

Table 19-13 CBMON Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1SDAR1hSDA status
  • 0h = The SDA signal is low.
  • 1h = The SDA signal is high. Note: During and right after reset, the SDA pin is in GPIO input mode without the internal pull enabled. For proper *I2C* operation, the user should have the external pull-up resistor in place.
0SCLR1hSCL status
  • 0h = The SCL signal is low.
  • 1h = The SCL signal is high Note: During and right after reset, the SCL pin is in GPIO input mode without the internal pull enabled. For proper *I2C* operation, the user should have the external pull-up resistor in place.

19.6.8 TOAR Register (Offset = 11Ch) [Reset = 00004000h]

TOAR is shown in Table 19-14.

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This register consists of seven address bits that identify the I2C device on the I2C bus.

Table 19-14 TOAR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
15MODER/W0hThis field selects the addressing mode(7-field/10-field) to be used in target mode.
  • 0h = Enable 7-field addressing
  • 1h = Enable 10-field addressing
14OARENR/W1hTarget own address enable
  • 0h = Disable OAR address
  • 1h = Enable OAR address
13-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9-0OARR/W0hTarget own address: This field specifies bits A9 through A0 of the target address. In 7-field addressing mode as selected by MODE field, the top 3 bits are don't care
  • 0h = Smallest value
  • 3FFh = Highest possible value

19.6.9 TOAR2 Register (Offset = 120h) [Reset = 00000000h]

TOAR2 is shown in Table 19-15.

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This register consists of seven address bits that identify the alternate address for the *I2C* device on the *I2C* bus.

Table 19-15 TOAR2 Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
22-16OAR2_MASKR/W0hTarget own address 2 mask: This field specifies bits A6 through A0 of the target address. The bits with value '1' in this field will make the corresponding incoming address bits to match by default regardless of the value inside this field i.e. corresponding bits of this field are don't care.
  • 0h = Minimum Value
  • 7Fh = Maximum Value
15-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7OAR2ENR/W0hTarget own address 2 enable
  • 0h = The alternate address is disabled.
  • 1h = Enables the use of the alternate address in the OAR2 field.
6-0OAR2R/W0hTarget own address 2 This field specifies the alternate target own address.
  • 0h = Smallest value
  • 7Fh = Highest possible value

19.6.10 TCTR Register (Offset = 124h) [Reset = 00000004h]

TCTR is shown in Table 19-16.

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Target control register

Table 19-16 TCTR Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9ENDEFDEVADRR/W0hEnable default device address
  • 0h = When this field is 0, the default device address is not matched. NOTE: it may still be matched if programmed inside TOAR/TOAR2.
  • 1h = When this field is 1, default device address of 7'h110_0001 is always matched by the target address match logic.
8ENALRESPADRR/W0hEnable alert response address
  • 0h = The alert response address is not matched. NOTE: It may still be matched if programmed inside TOAR/TOAR2
  • 1h = Alert response address of 7'h000_1100 is always matched by the target address match logic.
7RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
6RXFULLONRREQR/W0hRx full interrupt generated based on RREQ filed.
  • 0h = EVENT0_RIS.TRXFULL will be set when only the Target RX FIFO is full. This allows the EVENT0_RIS.TRXFULL interrupt to be used to indicate that the I2C bus is being clock stretched and that the FW must either read the RX FIFO or ACK/NACK the current RX byte.
  • 1h = EVENT0_RIS.SRXFULL will be set when the target state machine is in the RX_WAIT or RX_ACK_WAIT states which occurs when the transaction is clock stretched because the RX FIFO is full or the ACKOEN has been set and the state machine is waiting for FW to ACK/NACK the current byte.
5TXWAITSTALETXFIFOR/W0hTx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with [TCTR:TXEMPTY_ON_TREQ] set to prevent the Target State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.
  • 0h = The TX FIFO empty signal to the Target State Machine indicates that the TX FIFO is empty.
  • 1h = The TX FIFO empty signal to the Target State Machine will indicate that the TX FIFO is empty or that the TX FIFO data is stale. The TX FIFO data is determined to be stale when there is data in the TX FIFO when the target state machine leaves the TXMODE field. This can occur is a stop or timeout occur when there are bytes left in the TX FIFO.
4TXTRIGXMODER/W0hTx trigger when target FSM is in TX mode
  • 0h = No special behavior
  • 1h = EVENT0_RIS.TXFIFOTRG will be set when the Target TX FIFO has reached the trigger level AND the target state machine is in the as defined in the TXMODE field. When cleared EVENT0_RIS.TXFIFOTRG will be set when the Target TX FIFO is at or above the trigger level. This setting can be used to hold off the TX DMA until a transaction starts. This allows the DMA to be configured when the *I2C* is idle but have it wait till the transaction starts to load the Target TX FIFO, so it can load from a memory buffer that might be changing over time.
3TXEMPTYONTREQR/W0hTx Empty Interrupt on TREQ
  • 0h = EVENT0_RIS.TTXEMPTY will be set when only the target TX FIFO is empty. This allows the EVENT0_RIS.TTXEMPTY interrupt to be used to indicate that the bus is being clock stretched and that target TX data is required.
  • 1h = EVENT0_RIS.STXEMPTY will be set when the Target State Machine is in the TX_WAIT state which occurs when the TX FIFO is empty and the transaction is clock stretched waiting for the FIFO to receive data.
2CLKSTRETCHR/W1hTarget clock stretch enable
  • 0h = Target clock stretching is disabled
  • 1h = Target clock stretching is enabled
1GENCALLR/W0hGeneral call response enable.
  • 0h = Do not respond to a general call
  • 1h = Respond to a general call
0ACTIVER/W0hDevice active. Setting this field enables the target functionality.
  • 0h = Disables the target operation.
  • 1h = Enables the target operation.

19.6.11 TSR Register (Offset = 128h) [Reset = 00000000h]

TSR is shown in Table 19-17.

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Target status register

Table 19-17 TSR Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
18-9ADDRMATCHR0hIndicates the address for which target address match happened
  • 0h = Minimum Value
  • 3FFh = Maximum Value
8STALETXFIFOR0hStale TX FIFO
  • 0h = Tx FIFO is not stale
  • 1h = The TX FIFO is stale. This occurs when the TX FIFO was not emptied during the previous transaction.
7TXMODER0hTarget FSM is in TX MODE
  • 0h = The target state machine is not in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read.
  • 1h = The target state machine is in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read.
6BUSBSYR0hBus is busy
  • 0h = Bus is not busy
  • 1h = Bus is busy. This is cleared on a timeout.
5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3OAR2SELR0hOAR2 address matched This field gets re-evaluated after every address comparison.
  • 0h = Either the OAR2 address is not matched or the match is in legacy mode.
  • 1h = OAR2 address matched and acknowledged by the target.
2RXMODER0hTarget FSM is in RX MODE
  • 0h = The target state machine is not in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write.
  • 1h = The target state machine is in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write.
1TREQR0hTransmit Request
  • 0h = No outstanding transmit request.
  • 1h = The controller has been addressed as a target transmitter and is using clock stretching to delay the controller until data has been written to the TXDATA FIFO (Target TX FIFO is empty).
0RREQR0hReceive Request
  • 0h = No outstanding receive data.
  • 1h = The controller has outstanding receive data and is using clock stretching to delay the controller until the data has been read from the RXDATA FIFO (target RX FIFO is full).

19.6.12 RXDATA Register (Offset = 12Ch) [Reset = 00000000h]

RXDATA is shown in Table 19-18.

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RX FIFO read data byte This field contains the current byte being read in the RX FIFO stack. If the FIFO is disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register.

Table 19-18 RXDATA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7-0VALUER0hReceived Data. This field contains the last received data.
  • 0h = Smallest value
  • FFh = Highest possible value

19.6.13 TXDATA Register (Offset = 130h) [Reset = 00000000h]

TXDATA is shown in Table 19-19.

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Transmit data register. This register is the transmit data register (the interface to the FIFOs). For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).

Table 19-19 TXDATA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7-0VALUER/W0hTransmit data This byte contains the data to be transferred during the next transaction.
  • 0h = Smallest value
  • FFh = Highest possible value

19.6.14 TACKCTL Register (Offset = 134h) [Reset = 00000000h]

TACKCTL is shown in Table 19-20.

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This register enables the target to not acknowledge (NACK) for invalid data or command or acknowledge (ACK) for valid data or command. The *I2C* clock is pulled low after the last data field until this register is written.

Table 19-20 TACKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
2ACKOENONSTARTR/W0hWhen set this field will automatically turn on the target ACKOEN field following a start condition.
  • 0h = No special behavior
  • 1h = When set this field will automatically turn on the Target ACKOEN field following a start condition.
1ACKOVALR/W0hTarget ACK override Value Note: For general call this field will be ignored if set to NACK and target continues to receive data.
  • 0h = An ACK is sent indicating valid data or command.
  • 1h = A NACK is sent indicating invalid data or command.
0ACKOENR/W0hTarget ACK override enable
  • 0h = A response in not provided.
  • 1h = An ACK or NACK is sent according to the value written to the ACKOVAL field.

19.6.15 FIFOCTL Register (Offset = 138h) [Reset = 00000000h]

FIFOCTL is shown in Table 19-21.

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Target FIFO control

Table 19-21 FIFOCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReads to this field return zero.Writes to this field are ignored.
15RXFLUSHR/W0hRX FIFO flush Setting this field will flush the RX FIFO. Before resetting this field to stop flush the RXFIFOCNT should be checked to be 0 and indicating that the flush has completed.
  • 0h = Do not flush FIFO
  • 1h = Flush FIFO
14-11RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
10-8RXTRIGR/W0hRX FIFO trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming this field to 0x0 has no effect since no data is present to transfer out of RX FIFO.
  • 4h = Trigger when RX FIFO contains >= 5 byte
  • 5h = Trigger when RX FIFO contains >= 6 byte
  • 6h = Trigger when RX FIFO contains >= 7 byte
  • 7h = Trigger when RX FIFO contains >= 8 byte
7TXFLUSHR/W0hTX FIFO flush Setting this field will flush the TX FIFO. Before resetting this field to stop flush the TXFIFOCNT should be checked to be 8 and indicating that the flush has completed.
  • 0h = Do not flush FIFO
  • 1h = flush FIFO
6-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
2-0TXTRIGR/W0hTX FIFO trigger Indicates at what fill level in the TX FIFO a trigger will be generated.
  • 4h = Trigger when TX FIFO contains bigger or equal to 4 byte
  • 5h = Trigger when TX FIFO contains bigger or equal to 5 byte
  • 6h = Trigger when TX FIFO contains bigger or equal to 6 byte
  • 7h = Trigger when TX FIFO contains bigger or equal to 7 byte

19.6.16 FIFOSR Register (Offset = 13Ch) [Reset = 00000800h]

FIFOSR is shown in Table 19-22.

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FIFO status register Note: This register should only be read when BUSY is 0

Table 19-22 FIFOSR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
15TXFLUSHR0hTX FIFO flush When this field is set a flush operation for the TX FIFO is active. Clear TXFLUSH to stop.
  • 0h = FIFO flush not active
  • 1h = FIFO flush active
14-12RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
11-8TXFIFOCNTR8hNumber of bytes which could be put into the TX FIFO
  • 0h = Smallest value
  • 8h = Highest possible value
7RXFLUSHR0hRX FIFO flush When this field is set a flush operation for the RX FIFO is active. Clear the RXFLUSH field to stop.
  • 0h = FIFO flush not active
  • 1h = FIFO flush active
6-4RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3-0RXFIFOCNTR0hNumber of bytes which could be read from the RX FIFO
  • 0h = Smallest value
  • 8h = Highest possible value

19.6.17 FCLKDIV Register (Offset = 140h) [Reset = 00000000h]

FCLKDIV is shown in Table 19-23.

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Register for the selection of divider value to generate functional clock from SVT clock

Table 19-23 FCLKDIV Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-0FCLKDIVR/W0hDivider value selection
  • 0h = Divide by 1 = 80MHz
  • 1h = Divide by 2 = 40MHz
  • 2h = Divide by 4 = 20MHz
  • 3h = Divide by 5 = 16MHz
  • 4h = Divide by 8 = 10MHz
  • 5h = Divide by 10 = 8MHz
  • 6h = Divide by 16 = 5MHz
  • 7h = Divide by 20 = 4MHz
  • 8h = Divide by 25 = 3.2MHz
  • 9h = Divide by 32 = 2.5MHz
  • Ah = Divide by 40 = 2MHz
  • Bh = Divide by 80 = 1MHz

19.6.18 PDBGCTL Register (Offset = 400h) [Reset = 00000000h]

PDBGCTL is shown in Table 19-24.

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This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input

Table 19-24 PDBGCTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1SOFTR/W1hSoft halt boundary control. This function is only available, if FREE is set to 'STOP'
  • 0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted
  • 1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption
0FREER/W1hFree run control
  • 0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.
  • 1h = The peripheral ignores the state of the Core Halted input

19.6.19 EVENT0_IMASK Register (Offset = 404h) [Reset = 00000000h]

EVENT0_IMASK is shown in Table 19-25.

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Interrupt Mask. If a field is set, then corresponding interrupt is masked. Un-masking the interrupt causes the raw interrupt to be visible in [RIS], as well as [MIS].

Table 19-25 EVENT0_IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
27TARBLOSTR/W0hTarget arbitration lost
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
26RX_OVFL_TR/W0hRX FIFO overflow in target mode
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
25TX_UNFL_TR/W0hTX FIFO underflow in target mode
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
24TGENCALLR/W0hGeneral call interrupt
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
23TSTOPR/W0hStop condition interrupt
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
22TSTARTR/W0hTarget start condition interrupt. Asserted when the received address matches the target address
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
21TXEMPTYTR/W0hTX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the Transmit FIFO in target mode have been shifted out and the transmit goes into idle mode.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
20RXFIFOFULLTR/W0hRX FIFO full event. This interrupt is set if an target RX FIFO is full in target mode.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
19TXFIFOTRGTR/W0hTX FIFO trigger in target mode
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
18RXFIFOTRGMTR/W0hRX FIFO trigger in target mode
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
17TTXDONER/W0hTarget transmit transaction completed interrupt
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
16TRXDONER/W0hTarget receive data interrupt. Signals that a byte has been received
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
15-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9CARBLOSTR/W0hArbitration lost interrupt
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
8CSTOPR/W0hSTOP detection interrupt
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
7CSTARTR/W0hSTART detection interrupt
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
6CNACKR/W0hAddress/Data NACK interrupt
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
5TXEMPTYCR/W0hTXFIFO empty interrupt in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
4RXFIFOFULLCR/W0hRXFIFO full event in controller mode. This interrupt is set if an RX FIFO is full in controller mode.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
3TXFIFOTRGCR/W0hTransmit FIFO trigger in controller mode Trigger when TX FIFO contains <= defined bytes
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
2RXFIFOTRGCR/W0hReceive FIFO trigger in controller code Trigger when RX FIFO contains >= defined bytes
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
1CTXDONER/W0hController transmit transaction completed Interrupt
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask
0CRXDONER/W0hController receive transaction completed Interrupt
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrrupt Mask

19.6.20 EVENT0_RIS Register (Offset = 408h) [Reset = 00000000h]

EVENT0_RIS is shown in Table 19-26.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the [ICLR] register field even if the corresponding [IMASK] field is not enabled.

Table 19-26 EVENT0_RIS Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
27TARBLOSTR0 hTarget arbitration lost
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
26RX_OVFL_TR0hRX FIFO overflow in target mode
  • 0h = Interrupt did not occur
  • 1h = Interrupt Occured
25TX_UNFL_TR0hTX FIFO underflow in target mode
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
24TGENCALLR0hGeneral call interrupt
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
23TSTOPR0h Stop condition interrupt
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
22TSTARTR0hTarget start condition interrupt.When the received address matches the target address, this interrupt asserted.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
21TXEMPTYTR0hTX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
20RXFIFOFULLTR0hRX FIFO full event in target mode. This interrupt is set if an RX FIFO is full in target mode.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
19TXFIFOTRGTR0hTX FIFO trigger in target mode
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
18RXFIFOTRGTR0hRX FIFO trigger in target mode
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
17TTXDONER0hTarget transmit transaction completed interrupt
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
16TRXDONER0hTarget receive data interrupt. Signals that a byte has been received
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
15-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9CARBLOSTR0h Arbitration lost interrupt
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
8CSTOPR0h STOP detection interrupt
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
7CSTARTR0h START detection interrupt
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
6CNACKR0h Address/Data NACK interrupt
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
5TXEMPTYCR0hTX FIFO empty interrupt mask in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
4RXFIFOFULLCR0hRX FIFO full event in controller mode. This interrupt is set if an RX FIFO is full in controller mode.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
3TXFIFOTRGCR0hTX FIFO Trigger in Transmit Mode Trigger when TX FIFO contains <= defined bytes
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
2RXFIFOTRGCR0hRX FIFO trigger in controller mode Trigger when RX FIFO contains >= defined bytes
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
1CTXDONER0hController transmit transaction completed interrupt
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured
0CRXDONER0hController receive transaction completed interrupt
  • 0h = Interrupt did not occur
  • 1h = Interrupt occured

19.6.21 EVENT0_MIS Register (Offset = 40Ch) [Reset = 00000000h]

EVENT0_MIS is shown in Table 19-27.

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Masked interrupt status. This is an AND of the [IMASK] and [RIS] registers.

Table 19-27 EVENT0_MIS Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
27TARBLOSTR0hTarget arbitration lost
  • 0h = Clear interrupt mask
  • 1h = Masked interrupt occured
26TRX_OVFLR0hRX FIFO overflow in target mode
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
25TTX_UNFLR0hTX FIFO underflow in target mode
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
24TGENCALLR0hGeneral call interrupt
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
23TSTOPR0hTarget STOP detection interrupt
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
22TSTARTR0hTarget start condition interrupt. Asserted when the received address matches the target address
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
21TXEMPTYTR0hTX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
20RXFIFOFULLTR0hRXFIFO full event in Target mode. This interrupt is set if an RX FIFO is full in target mode.
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
19TXFIFOTRGTR0hTX FIFO trigger in target mode
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
18RXFIFOTRGTR0hTarget RX FIFO trigger
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
17TTXDONER0hTarget transmit transaction completed interrupt
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
16TRXDONER0hTarget receive data interrupt. Signals that a byte has been received
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
15-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9CARBLOSTR0h Arbitration lost interrupt
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
8CSTOPR0h STOP detection interrupt
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
7CSTARTR0h START detection interrupt
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
6CNACKR0h Address/Data NACK interrupt
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
5TXEMPTYCR0hTX FIFO Empty interrupt mask in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
4RXFIFOFULLCR0hRX FIFO full event. This interrupt is set if the RX FIFO is full in controller mode.
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
3TXFIFOTRGCR0hTX FIFO trigger in controller mode Trigger when TX FIFO contains <= defined bytes
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
2RXFIFOTRGCR0hRX FIFO trigger in controller mode Trigger when RX FIFO contains >= defined bytes
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
1CTXDONER0hController transmit transaction completed interrupt
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured
0CRXDONER0hController receive data interrupt
  • 0h = Masked Interrupt did not occur
  • 1h = Masked interrupt occured

19.6.22 EVENT0_IEN Register (Offset = 410h) [Reset = 00000000h]

EVENT0_IEN is shown in Table 19-28.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a field in IEN will set the event and therefore the related RIS field also gets set. If the interrupt is enabled through the mask, then the corresponding MIS field is also set.

Table 19-28 EVENT0_IEN Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDW0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
27TARBLOSTW0hTarget arbitration lost
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
26RX_OVFL_TW0hRX FIFO overflow in target mode
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
25TX_UNFL_TW0hTX FIFO underflow in target mode
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt
24TGENCALLW0hGeneral call interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
23TSTOPW0h Stop condition interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
22TSTARTW0hTarget start condition interrupt. Asserted when the received address matches the target address
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
21TXEMPTYTW0hTX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
20RXFIFOFULLTW0hRXFIFO full event in Target mode. This interrupt is set if an RX FIFO is full in Target mode.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
19TXFIFOTRGTW0hTX FIFO trigger in target mode
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
18RXFIFOTRGTW0hRX FIFO trigger in target mode
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
17TTXDONEW0hTarget transmit transaction completed Interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
16TRXDONEW0hTarget receive data interrupt. Signals that a byte has been received
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
15-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9CARBLOSTW0h Arbitration lost interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
8CSTOPW0h STOP detection interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
7CSTARTW0h START detection interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
6CNACKW0h Address/Data NACK interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
5TXEMPTYCW0hTX FIFO empty interrupt mask in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
4RXFIFOFULLCW0hRXFIFO full event in controller mode.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
3TXFIFOTRGCW0hTX FIFO trigger in controller mode Trigger when TX FIFO contains <= defined bytes
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
2RXFIFOTRGCW0hRX FIFO trigger in controller mode Trigger when RX FIFO contains >= defined bytes
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
1CTXDONEW0hController transmit transaction completed interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt
0CRXDONEW0hController receive data interrupt Signals that a byte has been received
  • 0h = Writing 0 has no effect
  • 1h = Set Interrrupt

19.6.23 EVENT0_IDIS Register (Offset = 414h) [Reset = 00000000h]

EVENT0_IDIS is shown in Table 19-29.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 19-29 EVENT0_IDIS Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
27TARBLOSTW0hTarget arbitration lost
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
26RX_OVFL_TW0hRX FIFO overflow in target mode
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
25TX_UNFL_TW0hTX FIFO underflow in target mode
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
24TGENCALLW0hGeneral call interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
23TSTOPW0hTarget STOP detection interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
22TSTARTW0hTarget start condition interrupt. Asserted when the received address matches the target address
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
21TXEMPTYTW0hTX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
20RXFIFOFULLTW0hRXFIFO full event in target mode. This interrupt is set if an RX FIFO is full in target mode.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
19TXFIFOTRGTW0hTX FIFO trigger in target mode
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
18RXFIFOTRGTW0hRX FIFO trigger in target mode
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
17TTXDONEW0hTarget transmit transaction completed interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
16TRXDONEW0hTarget receive data interrupt Signals that a byte has been received
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
15-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9CARBLOSTW0h Arbitration lost interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
8CSTOPW0h STOP detection interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
7CSTARTW0h START detection interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
6CNACKW0h Address/Data NACK interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
5TXEMPTYCW0hTX FIFO empty interrupt mask. This interrupt is set if all data in the TX FIFO have been shifted out and the transmit goes into idle mode.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
4RXFIFOFULLCW0hRXFIFO full event in controller mode.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
3TXFIFOTRGCW0hTX FIFO trigger in controller mode Trigger when TX FIFO contains <= defined bytes
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
2RXFIFOTRGCW0hRX FIFO trigger in controller mode Trigger when RX FIFO contains >= defined bytes
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
1CTXDONEW0hController transmit transaction completed interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
0CRXDONEW0hController receive data interrupt. Signals that a byte has been received
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt

19.6.24 EVENT0_IMEN Register (Offset = 418h) [Reset = 00000000h]

EVENT0_IMEN is shown in Table 19-30.

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Interrupt mask set. Writing a 1 to a field in IMEN will set the related IMASK field.

Table 19-30 EVENT0_IMEN Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDW0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
27TARBLOSTW0hTarget srbitration lost
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
26RX_OVFL_TW0hRX FIFO overflow in target mode
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
25TX_UNFL_TW0hTX FIFO underflow in target mode
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
24TGENCALLW0hGeneral call interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
23TSTOPW0h Stop condition interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
22TSTARTW0hTarget start condition interrupt. Asserted when the received address matches the target address
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
21TXEMPTYTW0hTX FIFO Empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
20RXFIFOFULLTW0hRXFIFO full event in target mode. This interrupt is set if an RX FIFO is full in target mode.
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
19TXFIFOTRGSTW0hTX FIFO trigger in target mode
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
18RXFIFOTRGTW0hRX FIFO trigger in target mode
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
17TTXDONEW0hTarget transmit transaction completed interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
16SRXDONEW0hTarget receive data interrupt. Signals that a byte has been received
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
15-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9CARBLOSTW0h Arbitration lost interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
8CSTOPW0h STOP detection interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
7CSTARTW0h START detection interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
6CNACKW0h Address/Data NACK interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
5TXEMPTYCW0hTX FIFO empty interrupt mask in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
4RXFIFOFULLCW0hRXFIFO full event in controller mode.
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
3TXFIFOTRGCW0hTX FIFO trigger in Controller mode Trigger when TX FIFO contains <= defined bytes
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
2RXFIFOTRGCW0hRX FIFO trigger in controller mode Trigger when RX FIFO contains >= defined bytes
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
1CTXDONEW0hController transmit transaction completed interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt
0CRXDONEW0hController receive data interrupt. Signals that a byte has been received
  • 0h = Writing 0 has no effect
  • 1h = Set masked interrrupt

19.6.25 EVENT0_IMDIS Register (Offset = 41Ch) [Reset = 00000000h]

EVENT0_IMDIS is shown in Table 19-31.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 19-31 EVENT0_IMDIS Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
27TARBLOSTW0hTarget arbitration lost
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
26RX_OVFL_TW0hRX FIFO overflow in target mode
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
25TX_UNFL_TW0hTX FIFO underflow in target mode
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
24TGENCALLW0hGeneral call interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
23TSTOPW0hTarget STOP detection interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
22TSTARTW0hTarget start condition interrupt. Asserted when the received address matches the target address.
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
21TXEMPTYTW0hTX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
20RXFIFOFULLTW0hRXFIFO full event in target mode. This interrupt is set if an RX FIFO is full in target mode.
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
19TXFIFOTRGTW0hTX FIFO trigger in target mode
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
18RXFIFOTRGTW0hRX FIFO trigger in target mode
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
17TTXDONEW0hTarget transmit transaction completed interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
16TRXDONEW0hTarget receive data interrupt. Signals that a byte has been received
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
15-10RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9CARBLOSTW0h Arbitration lost interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
8CSTOPW0h STOP detection interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
7CSTARTW0h START detection interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
6CNACKW0h Address/Data NACK interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
5TXEMPTYCW0hTX FIFO empty interrupt mask. This interrupt is set if all data in the TX FIFO have been shifted out and the transmit goes into idle mode.
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
4RXFIFOFULLCW0hRX FIFO full event in controller mode.
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
3TXFIFOTRGCW0hTX FIFO trigger in controller mode Trigger when TX FIFO contains <= defined bytes
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
2RXFIFOTRGCW0hRX FIFO trigger in controller mode Trigger when RX FIFO contains >= defined bytes
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
1CTXDONEW0hController transmit transaction completed interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt
0CRXDONEW0hController receive data interrupt. Signals that a byte has been received
  • 0h = Writing 0 has no effect
  • 1h = Clear masked interrupt

19.6.26 EVT_MODE Register (Offset = 420h) [Reset = 00000000h]

EVT_MODE is shown in Table 19-32.

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Event mode register. It is used to select whether each line is disabled, in software mode (software clears the [RIS]) or in hardware mode (hardware clears the [RIS])

Table 19-32 EVT_MODE Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1-0INT0_CFGR1hEvent line mode select for event corresponding to [INT_EVENT0]
  • 0h = The interrupt or event line is disabled.
  • 1h = The interrupt or event line is in software mode. Software must clear the RIS.
  • 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

19.6.27 DESC Register (Offset = 424h) [Reset = 00000000h]

DESC is shown in Table 19-33.

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This register identifies the peripheral and its exact version.

Table 19-33 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR1511hModule identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
  • 0h = Smallest value
  • FFFFh = Highest possible value
15-12FEATUREVERR0hFeature Set for the module *instance*
  • 0h = Smallest value
  • Fh = Highest possible value
11-8INSTNUMR0hInstance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
  • 0h = Smallest value
  • Fh = Highest possible value
7-4MAJREVR1hMajor rev of the IP
  • 0h = Smallest value
  • Fh = Highest possible value
3-0MINREVR0hMinor rev of the IP
  • 0h = Smallest value
  • Fh = Highest possible value

19.6.28 CLKCFG Register (Offset = 1000h) [Reset = 00000000h]

CLKCFG is shown in Table 19-34.

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This register controls the bus clock to *I2C*

Table 19-34 CLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReads to this field return zero.Writes to this field are ignored.
0ENABLER/W0hThis field enables or disables the bus clock to *I2C*
  • 0h = I2C clock disabled
  • 1h = I2C clock disabled