SWCU195A December   2024  – May 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755P10 , CC2755R10

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M33
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
      5. 1.3.5 TI Machine Learning Instruction Extensions
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDIO
      3. 1.5.3 VDDR
      4. 1.5.4 VDDD Digital Core Supply
      5. 1.5.5 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  Hardware Security Module
    8. 1.8  AES 128-Bit Cryptographic Accelerator
    9. 1.9  System Timer (SYSTIM)
    10. 1.10 General Purpose Timers (LGPT)
    11. 1.11 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.11.1 Watchdog Timer
      2. 1.11.2 Battery and Temperature Monitor
      3. 1.11.3 Voltage Glitch Monitor (VGM)
      4. 1.11.4 Real-Time Clock (RTC)
      5. 1.11.5 Low Power Comparator
    12. 1.12 Direct Memory Access
    13. 1.13 System Control and Clock
    14. 1.14 Communication Peripherals
      1. 1.14.1 UART
      2. 1.14.2 I2C
      3. 1.14.3 SPI
      4. 1.14.4 CAN-FD
      5. 1.14.5 I2S
    15. 1.15 Programmable I/Os
    16. 1.16 Algorithm Processing Unit (APU)
    17. 1.17 Serial Wire Debug (SWD)
  4. 2 Arm® Cortex®-M33 Processor
    1. 2.1 Arm® Cortex®-M33 Processor Introduction
    2. 2.2 M33 Instantiation Parameters
    3. 2.3 Arm® Cortex®-M33 System Peripheral Details
      1. 2.3.1 Floating Point Unit (FPU)
      2. 2.3.2 Memory Protection Unit (MPU)
      3. 2.3.3 Digital Signal Processing (DSP)
      4. 2.3.4 Security Attribution Unit (SAU)
      5. 2.3.5 System Timer (SysTick)
      6. 2.3.6 Nested Vectored Interrupt Controller (NVIC)
      7. 2.3.7 System Control Block (SCB)
      8. 2.3.8 System Control Space (SCS)
    4. 2.4 CPU Sub-System Peripheral Details
      1. 2.4.1 Trace Port Interface Unit (TPIU)
      2. 2.4.2 DAP Bridge and Debug Authentication
      3. 2.4.3 Implementation Defined Attribution Unit (IDAU)
      4. 2.4.4 Custom Datapath Extension (CDE)
    5. 2.5 Programming Model
      1. 2.5.1 Modes of Operation and Execution
        1. 2.5.1.1 Security States
        2. 2.5.1.2 Operating Modes
        3. 2.5.1.3 Operating States
        4. 2.5.1.4 Privileged Access and Unprivileged User Access
      2. 2.5.2 Instruction Set Summary
      3. 2.5.3 Memory Model
        1. 2.5.3.1 Private Peripheral Bus
        2. 2.5.3.2 Unaligned Accesses
      4. 2.5.4 Processor Core Registers Summary
      5. 2.5.5 Exceptions
        1. 2.5.5.1 Exception Handling and Prioritization
    6. 2.6 TrustZone-M
      1. 2.6.1 Overview
      2. 2.6.2 M33 Configuration
      3. 2.6.3 Description of Elements
        1. 2.6.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 2.6.3.1.1 Expected Use
        2. 2.6.3.2 Gaskets
          1. 2.6.3.2.1 Periphery Gasket
          2. 2.6.3.2.2 Controller Gasket
        3. 2.6.3.3 Memories
        4. 2.6.3.4 TCM
      4. 2.6.4 TCM Registers
    7. 2.7 Arm® Cortex®-M33 Registers
      1. 2.7.1  CPU_ROM_TABLE Registers
      2. 2.7.2  TPIU Registers
      3. 2.7.3  DCB Registers
      4. 2.7.4  DIB Registers
      5. 2.7.5  DWT Registers
      6. 2.7.6  FPB Registers
      7. 2.7.7  FPE Registers
      8. 2.7.8  ICB Registers
      9. 2.7.9  ITM Registers
      10. 2.7.10 MPU Registers
      11. 2.7.11 NVIC Registers
      12. 2.7.12 SAU Registers
      13. 2.7.13 SCB Registers
      14. 2.7.14 SYSTIMER Registers
      15. 2.7.15 SYSTICK Registers
      16. 2.7.16 Clock Control
      17. 2.7.17 Protocol Descriptions
      18. 2.7.18 Reset Considerations
        1. 2.7.18.1 Hardware Reset Considerations
      19. 2.7.19 Initialization
      20. 2.7.20 Interrupt and Event Support
        1. 2.7.20.1 Connection to Event Fabric
      21. 2.7.21 Power Management
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Interrupt Priority Grouping
      7. 4.1.7 Exception Entry and Return
        1. 4.1.7.1 Exception Entry
        2. 4.1.7.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Fault Types
      2. 4.2.2 Fault Escalation to HardFault
      3. 4.2.3 Fault Status Registers and Fault Address Registers
      4. 4.2.4 Lockup
    3. 4.3 Security State Switches
    4. 4.4 Event Fabric
      1. 4.4.1 Introduction
      2. 4.4.2 Overview
      3. 4.4.3 Registers
      4. 4.4.4 AON Event Fabric
        1. 4.4.4.1 AON Common Input Events List
        2. 4.4.4.2 AON Event Subscribers
        3. 4.4.4.3 Power Management Controller (PMCTL)
        4. 4.4.4.4 Real Time Clock (RTC)
        5. 4.4.4.5 AON to MCU Event Fabric
      5. 4.4.5 MCU Event Fabric
        1. 4.4.5.1 Common Input Event List
        2. 4.4.5.2 MCU Event Subscribers
          1. 4.4.5.2.1 System CPU
          2. 4.4.5.2.2 Non-Maskable Interrupt (NMI)
    5. 4.5 Digital Test Bus (DTB)
    6. 4.6 EVTSVT Registers
    7. 4.7 EVTULL Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1 Introduction
    2. 6.2 System CPU Modes
    3. 6.3 Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4 Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
      6. 6.4.6 PMCTL Registers
    5. 6.5 Digital Power Partitioning
    6. 6.6 Clocks
      1. 6.6.1 Block Diagram
      2. 6.6.2 LF clock
        1. 6.6.2.1 LFINC Measurement Mechanism
        2. 6.6.2.2 LFINC Filtering
      3. 6.6.3 HFOSC
        1. 6.6.3.1 HFOSC Control and Qualification
        2. 6.6.3.2 HFOSC Tracking Loop
      4. 6.6.4 AFOSC
        1. 6.6.4.1 AFOSC Control and Qualification
        2. 6.6.4.2 AFOSC Tracking Loop
        3. 6.6.4.3 AFOSC Ratio
      5. 6.6.5 CLKSVT
      6. 6.6.6 CLKULL
      7. 6.6.7 CKM Registers
      8. 6.6.8 CKMD Registers
      9. 6.6.9 CLKCTL Registers
    7. 6.7 Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 RTC Reset
      3. 6.7.3 LF Loss Detection
    8. 6.8 AON (REG3V3) Register Bank
  9. 7 Internal Memory
    1. 7.1 SRAM
      1. 7.1.1 Overview
        1. 7.1.1.1 Purpose of the Peripheral
        2. 7.1.1.2 Features
        3. 7.1.1.3 Functional Block Diagram
      2. 7.1.2 Peripheral Functional Description
        1. 7.1.2.1 Parity Error Detection
          1. 7.1.2.1.1 Parity Error Debug Register
        2. 7.1.2.2 Extension Mode
        3. 7.1.2.3 Initialization
        4. 7.1.2.4 TrustZone Watermarking
      3. 7.1.3 SRAM Registers
      4. 7.1.4 SRAMCTRL Registers
    2. 7.2 VIMS
      1. 7.2.1 Overview
        1. 7.2.1.1 Purpose of the Peripheral
        2. 7.2.1.2 Features
        3. 7.2.1.3 Functional Block Diagram
      2. 7.2.2 Peripheral Functional Description
        1. 7.2.2.1 Dedicated 8KB CPU Cache
        2. 7.2.2.2 Dedicated 2KB HSM Cache
        3. 7.2.2.3 Dedicated 128-Bit Line Buffer
        4. 7.2.2.4 ROM
        5. 7.2.2.5 Flash
        6. 7.2.2.6 Auxiliary Regions
        7. 7.2.2.7 Flash Partition and Protection
          1. 7.2.2.7.1 Main Region
          2. 7.2.2.7.2 Read Protection
          3. 7.2.2.7.3 Sticky Write/Erase Protection
        8. 7.2.2.8 TrustZoneTM Watermark
        9. 7.2.2.9 Debug Access
      3. 7.2.3 VIMS Registers
    3. 7.3 FLASH
      1. 7.3.1 FLASH Registers
  10. 8 Hardware Security Module (HSM)
    1. 8.1 Introduction
    2. 8.2 Overview
    3. 8.3 One-Time-Programmable (OTP) Controller
      1. 8.3.1 High-Level Sequence to Handle OTP Requests
    4. 8.4 Mailbox and Register Access Firewall
    5. 8.5 DMA Firewall
    6. 8.6 Coprocessor
    7. 8.7 HSM FW
      1. 8.7.1 Acquiring the Latest HSM FW
      2. 8.7.2 Programming HSM FW
      3. 8.7.3 Optional Customer Signing of HSM FW
    8. 8.8 HSM Registers
    9. 8.9 HSMCRYPTO Registers
  11. 9 Device Boot and Bootloader
    1. 9.1 Device Boot and Programming
      1. 9.1.1 Boot Flow
      2. 9.1.2 Boot Status
      3. 9.1.3 Boot Protection/Locking Mechanisms
      4. 9.1.4 Debug and Active SWD Connections at Boot
        1. 9.1.4.1 Secure Debug and Persistent Debug
      5. 9.1.5 Flashless Test Mode and Tools Client Mode
        1. 9.1.5.1 Flashless Test Mode
        2. 9.1.5.2 Tools Client Mode
      6. 9.1.6 Retest Mode and Return-to-Factory Procedure
      7. 9.1.7 Disabling SWD Debug Port
    2. 9.2 Flash Programming
      1. 9.2.1 CCFG
      2. 9.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 9.2.3 SACI Flash Programming Commands
      4. 9.2.4 Flash Programming Flows
        1. 9.2.4.1 Initial Programming of a New Device
        2. 9.2.4.2 Reprogramming of Previously Programmed Device
        3. 9.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 9.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 9.2.4.5 Reprogramming of Only the Main Flash Application of a Previously Programmed Device
    3. 9.3 Device Management Command Interface
      1. 9.3.1 SACI Communication Protocol
        1. 9.3.1.1 Host Side Protocol
        2. 9.3.1.2 Command Format
        3. 9.3.1.3 Response Format
        4. 9.3.1.4 Response Result Field
        5. 9.3.1.5 Command Sequence Tag
        6. 9.3.1.6 Host Side Timeout
      2. 9.3.2 SACI Commands
        1. 9.3.2.1 Miscellaneous Commands
          1. 9.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 9.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 9.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
          4. 9.3.2.1.4 SACI_CMD_GET_SECBOOT_HSMFW_UPDATE_STATUS
          5. 9.3.2.1.5 SACI_CMD_HSM_GET_SYS_INFO
        2. 9.3.2.2 Debug Commands
          1. 9.3.2.2.1 SACI_CMD_DEBUG_EXIT_SACI_HALT
          2. 9.3.2.2.2 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          3. 9.3.2.2.3 SACI_CMD_DEBUG_REQ_KEY_ID
          4. 9.3.2.2.4 SACI_CMD_DEBUG_REQ_CHALLENGE
          5. 9.3.2.2.5 SACI_CMD_DEBUG_SUBMIT_CHALLENGE_RESP
          6. 9.3.2.2.6 SACI_CMD_DEBUG_CLOSE_SESSION
          7. 9.3.2.2.7 SACI_CMD_BLDR_APP_RESET_DEVICE
          8. 9.3.2.2.8 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 9.3.2.3 Flash Programming Commands
          1. 9.3.2.3.1  SACI_CMD_FLASH_ERASE_CHIP
          2. 9.3.2.3.2  SACI_CMD_FLASH_ERASE_MAIN_APP
          3. 9.3.2.3.3  SACI_CMD_FLASH_PROG_CCFG_SECTOR
          4. 9.3.2.3.4  SACI_CMD_FLASH_PROG_CCFG_USER_REC
          5. 9.3.2.3.5  SACI_CMD_FLASH_PROG_SCFG_SECTOR
          6. 9.3.2.3.6  SACI_CMD_FLASH_PROG_MAIN_SECTOR
          7. 9.3.2.3.7  SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          8. 9.3.2.3.8  SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          9. 9.3.2.3.9  SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
          10. 9.3.2.3.10 SACI_CMD_FLASH_VERIFY_SCFG_SECTOR
    4. 9.4 Bootloader Support
      1. 9.4.1 Bootloader v.s Secure Boot
    5. 9.5 ROM Serial Bootloader
      1. 9.5.1 ROM Serial Bootloader Interfaces
        1. 9.5.1.1 Packet Handling
          1. 9.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 9.5.1.2 Transport Layer
          1. 9.5.1.2.1 UART Transport
            1. 9.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 9.5.1.2.2 SPI Transport
      2. 9.5.2 ROM Serial Bootloader Parameters
      3. 9.5.3 ROM Serial Bootloader Commands
        1. 9.5.3.1 BLDR_CMD_PING
        2. 9.5.3.2 BLDR_CMD_GET_STATUS
        3. 9.5.3.3 BLDR_CMD_GET_PART_ID
        4. 9.5.3.4 BLDR_CMD_RESET
        5. 9.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 9.5.3.6 BLDR_CMD_CRC32
        7. 9.5.3.7 BLDR_CMD_DOWNLOAD
        8. 9.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 9.5.3.9 BLDR_CMD_SEND_DATA
      4. 9.5.4 Bootloader Firmware Update Example
  12. 10Device Configuration
    1. 10.1 Guidelines for Securely Configuring Your Device
      1. 10.1.1 Enabling and Configuring Secure Boot
      2. 10.1.2 Configure Debug Access
      3. 10.1.3 Configure Flash Protections
      4. 10.1.4 Configure Device Permissions
      5. 10.1.5 Configure HSM FW Update Keys
      6. 10.1.6 Configure emSensor
    2. 10.2 Factory Configuration (FCFG)
    3. 10.3 Customer Configuration (CCFG)
    4. 10.4 Security Configuration (SCFG)
  13. 11Secure Boot
    1. 11.1  Secure Boot
    2. 11.2  Execution Flow
    3. 11.3  ROM API
      1. 11.3.1 HAPI (Hardware API)
      2. 11.3.2 Registers
    4. 11.4  Configuration
      1. 11.4.1 Slot Configuration
      2. 11.4.2 Policy
        1. 11.4.2.1 Authentication Method
        2. 11.4.2.2 Authentication Algorithm
        3. 11.4.2.3 Update Mode
          1. 11.4.2.3.1 Overwrite
          2. 11.4.2.3.2 XIP Revert Enabled/Disabled
      3. 11.4.3 Key Update Key Hash
      4. 11.4.4 Key Ring
      5. 11.4.5 Boot Seed
    5. 11.5  Generic Image Format
    6. 11.6  Application Update
      1. 11.6.1 Image Format
    7. 11.7  Secondary Secure Bootloader Update
      1. 11.7.1 Image Format
      2. 11.7.2 Update Pattern
    8. 11.8  Key Update
      1. 11.8.1 Image Format
    9. 11.9  Antirollback
    10. 11.10 Version Log (VLOG)
      1. 11.10.1 Record structure
    11. 11.11 Fallback
    12. 11.12 ROM Panic
  14. 12General Purpose Timers (LGPT)
    1. 12.1 Overview
    2. 12.2 Block Diagram
    3. 12.3 Functional Description
      1. 12.3.1  Prescaler
      2. 12.3.2  Counter
      3. 12.3.3  Target
      4. 12.3.4  Channel Input Logic
      5. 12.3.5  Channel Output Logic
      6. 12.3.6  Channel Actions
        1. 12.3.6.1 Period and Pulse Width Measurement
        2. 12.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 12.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 12.3.7  Channel Capture Configuration
      8. 12.3.8  Channel Filters
        1. 12.3.8.1 Setting up the Channel Filters
      9. 12.3.9  Synchronize Multiple LGPT Timers
      10. 12.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 12.4 Timer Modes
      1. 12.4.1 Quadrature Decoder
      2. 12.4.2 DMA
      3. 12.4.3 IR Generation
      4. 12.4.4 Fault and Park
      5. 12.4.5 Deadband
      6. 12.4.6 Deadband, Fault, and Park
      7. 12.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 12.5 LGPT0 Registers
    6. 12.6 LGPT1 Registers
    7. 12.7 LGPT2 Registers
    8. 12.8 LGPT3 Registers
  15. 13Algorithm Processing Unit (APU)
    1. 13.1 Introduction
    2. 13.2 APU Related Collateral
    3. 13.3 Functional Description
    4. 13.4 APU Operation
    5. 13.5 Interrupts and Events
    6. 13.6 Data Representation
    7. 13.7 Data Memory
    8. 13.8 Software
    9. 13.9 APU Registers
  16. 14Voltage Glitch Monitor (VGM)
    1. 14.1 Overview
    2. 14.2 Features and Operation
  17. 15System Timer (SYSTIM)
    1. 15.1 Overview
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1 Common Channel Features
        1. 15.3.1.1 Compare Mode
        2. 15.3.1.2 Capture Mode
        3. 15.3.1.3 Additional Channel Arming Methods
      2. 15.3.2 Interrupts and Events
    4. 15.4 SYSTIM Registers
  18. 16Real Time Clock (RTC)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Interrupts and Events
      1. 16.3.1 Input Event
      2. 16.3.2 Output Event
      3. 16.3.3 Arming and Disarming Channels
    4. 16.4 CAPTURE and COMPARE Configurations
      1. 16.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 16.4.2 CHANNEL 1—CAPTURE CHANNEL
    5. 16.5 RTC Registers
  19. 17Low Power Comparator (SYS0)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 Input Selection
      2. 17.3.2 Voltage Divider
      3. 17.3.3 Hysteresis
      4. 17.3.4 Wake-Up
    4. 17.4 SYS0 Registers
  20. 18Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 18.1 Introduction
    2. 18.2 Functional Description
      1. 18.2.1 BATMON
      2. 18.2.2 DCDC
    3. 18.3 PMUD Registers
  21. 19Micro Direct Memory Access (µDMA)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1  Channel Assignments
      2. 19.3.2  Priority
      3. 19.3.3  Arbitration Size
      4. 19.3.4  Request Types
        1. 19.3.4.1 Single Request
        2. 19.3.4.2 Burst Request
      5. 19.3.5  Channel Configuration
      6. 19.3.6  Transfer Modes
        1. 19.3.6.1 Stop Mode
        2. 19.3.6.2 Basic Mode
        3. 19.3.6.3 Auto Mode
        4. 19.3.6.4 Ping-Pong Mode
        5. 19.3.6.5 Memory Scatter-Gather Mode
        6. 19.3.6.6 Peripheral Scatter-Gather Mode
      7. 19.3.7  Transfer Size and Increments
      8. 19.3.8  Peripheral Interface
      9. 19.3.9  Software Request
      10. 19.3.10 Interrupts and Errors
      11. 19.3.11 Initialization and Configuration
        1. 19.3.11.1 Module Initialization
        2. 19.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 19.3.11.3 Configure the Channel Attributes
        4. 19.3.11.4 Configure the Channel Control Structure
        5. 19.3.11.5 Start the Transfer
        6. 19.3.11.6 Software Considerations
    4. 19.4 DMA Registers
  22. 20Advanced Encryption Standard (AES)
    1. 20.1 Introduction
      1. 20.1.1 AES Performance
    2. 20.2 Functional Description
      1. 20.2.1 Reset Considerations
      2. 20.2.2 Interrupt and Event Support
        1. 20.2.2.1 Interrupt Events and Requests
        2. 20.2.2.2 Connection to Event Fabric
      3. 20.2.3 µDMA
        1. 20.2.3.1 µDMA Example
    3. 20.3 Encryption and Decryption Configuration
      1. 20.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 20.3.2  CBC (Cipher Block Chaining) Encryption
      3. 20.3.3  CBC Decryption
      4. 20.3.4  CTR (Counter) Encryption/Decryption
      5. 20.3.5  ECB (Electronic Code Book) Encryption
      6. 20.3.6  ECB Decryption
      7. 20.3.7  CFB (Cipher Feedback) Encryption
      8. 20.3.8  CFB Decryption
      9. 20.3.9  OFB (Open Feedback) Encryption
      10. 20.3.10 OFB Decryption
      11. 20.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 20.3.12 PCBC Decryption
      13. 20.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 20.3.14 CCM
    4. 20.4 AES Registers
    5. 20.5 CRYPTO Registers
  23. 21Analog to Digital Converter (ADC)
    1. 21.1 Overview
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1  ADC Core
      2. 21.3.2  Voltage Reference Options
      3. 21.3.3  Resolution Modes
      4. 21.3.4  ADC Clocking
      5. 21.3.5  Power Down Behavior
      6. 21.3.6  Sampling Trigger Sources and Sampling Modes
        1. 21.3.6.1 AUTO Sampling Mode
        2. 21.3.6.2 MANUAL Sampling Mode
      7. 21.3.7  Sampling Period
      8. 21.3.8  Conversion Modes
      9. 21.3.9  ADC Data Format
      10. 21.3.10 Status Register
      11. 21.3.11 ADC Events
        1. 21.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 21.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 21.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 21.3.11.4 Generic Event Subscriber
    4. 21.4 Advanced Features
      1. 21.4.1 Window Comparator
      2. 21.4.2 DMA & FIFO Operation
        1. 21.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 21.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 21.4.2.3 DMA/CPU Operation Summary Matrix
      3. 21.4.3 Ad-hoc Single Conversion
    5. 21.5 ADC Registers
  24. 22I/O Controller (IOC)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  I/O Mapping and Configuration
      1. 22.3.1 Basic I/O Mapping
      2. 22.3.2 Radio GPO
      3. 22.3.3 Pin Mapping
      4. 22.3.4 DTB Muxing
    4. 22.4  Edge Detection
    5. 22.5  GPIO
    6. 22.6  I/O Pins
    7. 22.7  Unused Pins
    8. 22.8  Debug Configuration
    9. 22.9  IOC Registers
    10. 22.10 GPIO Registers
  25. 23Universal Asynchronous Receiver/Transmitter (UART-LIN)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 UART Functional Description
      1. 23.3.1 Transmit and Receive Logic
      2. 23.3.2 Baud Rate Generation
      3. 23.3.3 FIFO Operation
        1. 23.3.3.1 FIFO Remapping
      4. 23.3.4 Data Transmission
      5. 23.3.5 Flow Control
      6. 23.3.6 IrDA Encoding and Decoding
      7. 23.3.7 Interrupts
      8. 23.3.8 Loopback Operation
    4. 23.4 UART-LIN Specification
      1. 23.4.1 Break transmission in UART mode
      2. 23.4.2 Break reception in UART mode
      3. 23.4.3 Break/Synch transmission in LIN mode
      4. 23.4.4 Break/Synch reception in LIN mode
      5. 23.4.5 Dormant mode operation
      6. 23.4.6 Wakeup signal generation
      7. 23.4.7 Wakeup signal detection when device is in active/idle modes
      8. 23.4.8 Wakeup signal detection when device is in standby mode
    5. 23.5 Interface to µDMA
    6. 23.6 Initialization and Configuration
    7. 23.7 UART Registers
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Overview
      1. 24.1.1 Features
      2. 24.1.2 Block Diagram
    2. 24.2 Signal Description
    3. 24.3 Functional Description
      1. 24.3.1  Clock Control
      2. 24.3.2  FIFO Operation
        1. 24.3.2.1 Transmit FIFO
        2. 24.3.2.2 Repeated Transmit Operation
        3. 24.3.2.3 Receive FIFO
        4. 24.3.2.4 FIFO Flush
      3. 24.3.3  Interrupts
      4. 24.3.4  Data Format
      5. 24.3.5  Delayed Data Sampling
      6. 24.3.6  Chip Select Control
      7. 24.3.7  Command Data Control
      8. 24.3.8  Protocol Descriptions
        1. 24.3.8.1 Motorola SPI Frame Format
        2. 24.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 24.3.8.3 MICROWIRE Frame Format
      9. 24.3.9  CRC Configuration
      10. 24.3.10 Auto CRC Functionality
      11. 24.3.11 Auto Header Functionality
      12. 24.3.12 SPI Status
      13. 24.3.13 Debug Halt
    4. 24.4 µDMA Operation
    5. 24.5 Initialization and Configuration
    6. 24.6 SPI Registers
  27. 25Inter-Integrated Circuit (I2C)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Functional Description
      1. 25.3.1 Functional Overview
        1. 25.3.1.1 Start and Stop Conditions
        2. 25.3.1.2 Data Format with 7-Bit Address
        3. 25.3.1.3 Data Validity
        4. 25.3.1.4 Acknowledge
        5. 25.3.1.5 Arbitration
      2. 25.3.2 Available Speed Modes
      3. 25.3.3 Interrupts
        1. 25.3.3.1 I2C Controller Interrupts
        2. 25.3.3.2 I2C Target Interrupts
      4. 25.3.4 Loopback Operation
      5. 25.3.5 Command Sequence Flowcharts
        1. 25.3.5.1 I2C Controller Command Sequences
        2. 25.3.5.2 I2C Target Command Sequences
    4. 25.4 Initialization and Configuration
    5. 25.5 I2C Registers
  28. 26Inter-IC Sound (I2S)
    1. 26.1  Introduction
    2. 26.2  Block Diagram
    3. 26.3  Clock Architecture
    4. 26.4  Signal Descriptions
    5. 26.5  Functional Description
      1. 26.5.1 Pin Configuration
      2. 26.5.2 Serial Format Configuration
      3. 26.5.3 I2S Format Schematic
        1. 26.5.3.1 Register Configuration
      4. 26.5.4 Left-Justified (LJF)
        1. 26.5.4.1 Register Configuration
      5. 26.5.5 Right-Justified (RJF)
        1. 26.5.5.1 Register Configuration
      6. 26.5.6 DSP
        1. 26.5.6.1 Register Configuration
      7. 26.5.7 Clock Configuration
    6. 26.6  Memory Interface
      1. 26.6.1 Sample Word Length
      2. 26.6.2 Padding Mechanism
      3. 26.6.3 Channel Mapping
      4. 26.6.4 Sample Storage in Memory
      5. 26.6.5 DMA Operation
        1. 26.6.5.1 Start-Up
        2. 26.6.5.2 Operation
        3. 26.6.5.3 Shutdown
    7. 26.7  Samplestamp Generator
      1. 26.7.1 Samplestamp Counters
      2. 26.7.2 Start-Up Triggers
      3. 26.7.3 Samplestamp Capture
      4. 26.7.4 Achieving Constant Audio Latency
    8. 26.8  Error Detection
    9. 26.9  Usage
      1. 26.9.1 Start-Up Sequence
      2. 26.9.2 Shutdown Sequence
    10. 26.10 I2S Configuration Guideline
    11. 26.11 I2S Registers
  29. 27CAN-FD
    1. 27.1 Introduction
    2. 27.2 Functions
    3. 27.3 MCAN Subsystem
    4. 27.4 MCAN Functional Description
      1. 27.4.1 Operating Modes
        1. 27.4.1.1 Software Initialization
        2. 27.4.1.2 Normal Operation
        3. 27.4.1.3 CAN FD Operation
        4. 27.4.1.4 Transmitter Delay Compensation
          1. 27.4.1.4.1 Description
          2. 27.4.1.4.2 Transmitter Delay Compensation Measurement
        5. 27.4.1.5 Restricted Operation Mode
        6. 27.4.1.6 Bus Monitoring Mode
        7. 27.4.1.7 Disabled Automatic Retransmission
          1. 27.4.1.7.1 Frame Transmission in DAR Mode
        8. 27.4.1.8 Power Down (Sleep Mode)
          1. 27.4.1.8.1 MCAN Clock Stop and Wake Operations
          2. 27.4.1.8.2 MCAN Debug Suspend Operation
        9. 27.4.1.9 Test Modes
          1. 27.4.1.9.1 External Loop Back Mode
          2. 27.4.1.9.2 Internal Loop Back Mode
      2. 27.4.2 Timestamp Generation
        1. 27.4.2.1 External Timestamp Counter
        2. 27.4.2.2 Block Diagram
      3. 27.4.3 Timeout Counter
      4. 27.4.4 Rx Handling
        1. 27.4.4.1 Acceptance Filtering
          1. 27.4.4.1.1 Range Filter
          2. 27.4.4.1.2 Filter for specific IDs
          3. 27.4.4.1.3 Classic Bit Mask Filter
          4. 27.4.4.1.4 Standard Message ID Filtering
          5. 27.4.4.1.5 Extended Message ID Filtering
        2. 27.4.4.2 Rx FIFOs
          1. 27.4.4.2.1 Rx FIFO Blocking Mode
          2. 27.4.4.2.2 Rx FIFO Overwrite Mode
        3. 27.4.4.3 Dedicated Rx Buffers
          1. 27.4.4.3.1 Rx Buffer Handling
        4. 27.4.4.4 Debug on CAN Support
          1. 27.4.4.4.1 Filtering for Debug Messages
          2. 27.4.4.4.2 Debug Message Handling
      5. 27.4.5 Tx Handling
        1. 27.4.5.1 Transmit Pause
        2. 27.4.5.2 Dedicated Tx Buffers
        3. 27.4.5.3 Tx FIFO
        4. 27.4.5.4 Tx Queue
        5. 27.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 27.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 27.4.5.7 Transmit Cancellation
        8. 27.4.5.8 Tx Event Handling
      6. 27.4.6 FIFO Acknowledge Handling
      7. 27.4.7 MCAN Message RAM
        1. 27.4.7.1 Message RAM Configuration
        2. 27.4.7.2 Rx Buffer and FIFO Element
        3. 27.4.7.3 Tx Buffer Element
        4. 27.4.7.4 Tx Event FIFO Element
        5. 27.4.7.5 Standard Message ID Filter Element
        6. 27.4.7.6 Extended Message ID Filter Element
      8. 27.4.8 Interrupt Requests
    5. 27.5 CC27xx MCAN Wrapper
    6. 27.6 MCAN Clock Enable
    7. 27.7 Additional Notes
    8. 27.8 CANFD Registers
  30. 28Radio
    1. 28.1  Introduction
    2. 28.2  Block Diagram
    3. 28.3  Overview
      1. 28.3.1 Radio Sub-Domains
      2. 28.3.2 Radio RAMs
      3. 28.3.3 Doorbell (DBELL)
        1. 28.3.3.1 Interrupts
        2. 28.3.3.2 GPIO Control
        3. 28.3.3.3 SYSTIM Interface
    4. 28.4  Radio Usage Model
      1. 28.4.1 CRC and Whitening
    5. 28.5  LRFDDBELL Registers
    6. 28.6  LRFDMDM32 Registers
    7. 28.7  LRFDPBE Registers
    8. 28.8  LRFDPBE32 Registers
    9. 28.9  LRFDRFE Registers
    10. 28.10 LRFDRFE32 Registers
    11. 28.11 LRFDRXF Registers
    12. 28.12 LRFDS2R Registers
    13. 28.13 LRFDTRC Registers
    14. 28.14 LRFDTXF Registers
  31. 29Revision History

20.4 AES Registers

Table 20-1 lists the memory-mapped registers for the AES registers. All register offset addresses not listed in Table 20-1 should be considered as reserved locations and the register contents should not be modified.

Table 20-1 AES Registers
OffsetAcronymRegister NameSection
0hDESCDescription Register.Section 20.4.1
10hTRGTriggerSection 20.4.2
14hABORTAbortSection 20.4.3
18hCLRClearSection 20.4.4
1ChSTAStatusSection 20.4.5
20hDMADirect Memory AccessSection 20.4.6
24hDMACHADMA Channel A data transferSection 20.4.7
28hDMACHBDMA Channel B data transferSection 20.4.8
2ChAUTOCFGAutomatic ConfigurationSection 20.4.9
50hKEY0Key Word 0Section 20.4.10
54hKEY1Key Word 1Section 20.4.11
58hKEY2Key Word 2Section 20.4.12
5ChKEY3Key Word 3Section 20.4.13
70hTXT0Text Word 0Section 20.4.14
74hTXT1Text Word 1Section 20.4.15
78hTXT2Text Word 2Section 20.4.16
7ChTXT3Text Word 3Section 20.4.17
80hTXTX0Text Word 0 XORSection 20.4.18
84hTXTX1Text Word 1 XORSection 20.4.19
88hTXTX2Text Word 2 XORSection 20.4.20
8ChTXTX3Text Word 3 XORSection 20.4.21
90hBUF0Buffer Word 0Section 20.4.22
94hBUF1Buffer Word 1Section 20.4.23
98hBUF2Buffer Word 2Section 20.4.24
9ChBUF3Buffer Word 3Section 20.4.25
A0hTXTXBUF0Text Word 0 XOR Buffer Word 0Section 20.4.26
A4hTXTXBUF1Text Word 1 XOR Buffer Word 1Section 20.4.27
A8hTXTXBUF2Text Word 2 XOR Buffer Word 2Section 20.4.28
AChTXTXBUF3Text Word 3 XOR Buffer Word3Section 20.4.29
104hIMASKInterrupt Mask registerSection 20.4.30
108hRISRaw Interrupt Status registerSection 20.4.31
10ChMISMasked Interrupt Status registerSection 20.4.32
110hISETInterrupt Set registerSection 20.4.33
114hICLRInterrupt Clear registerSection 20.4.34
118hIMSETInterrupt Mask Set registerSection 20.4.35
11ChIMCLRInterrupt Mask Clear registerSection 20.4.36

Complex bit access types are encoded to fit into small table cells. Table 20-2 shows the codes that are used for access types in this section.

Table 20-2 AES Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RHR
H		Read
Set or cleared by hardware
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

20.4.1 DESC Register (Offset = 0h) [Reset = 00000000h]

DESC is shown in Table 20-3.

Return to the Summary Table.

Description Register.
This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 20-3 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR6B42hModule Identifier
This register is used to uniquely identify this IP.
15-12STDIPOFFR4hStandard IP MMR block offset
Standard IP MMRs are the set from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist.
0x1-0xF: Standard IP MMRs begin at offset of 64*STDIPOFF from the base IP address.
11-8INSTIDXR0hIP Instance ID number
If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
7-4MAJREVR1hMajor revision of IP (0-15)
3-0MINREVR0hMinor Revision of IP(0-15)

20.4.2 TRG Register (Offset = 10h) [Reset = 00000000h]

TRG is shown in Table 20-4.

Return to the Summary Table.

Trigger
This register is used to manually trigger operations.

Table 20-4 TRG Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3DMACHAW0hManually trigger channel A request
  • 0h = Writing 0 has no effect
  • 1h = Triggers channel A request
2DMACHBW0hManually trigger channel B request
  • 0h = Writing 0 has no effect
  • 1h = Triggers channel B request
1-0AESOPW0hAES Operation
Write an enumerated value to this field when STA.STATE = IDLE to manually trigger an AES operation. If condition is not met, the trigger is ignored. Non-enumerated values are ignored.
Enumerated value indicates source of AES operation
  • 1h = TXT = AES(KEY,TXT)
  • 2h = TXT = AES(KEY,BUF)
  • 3h = TXT = AES(KEY, TXT XOR BUF)

20.4.3 ABORT Register (Offset = 14h) [Reset = 00000000h]

ABORT is shown in Table 20-5.

Return to the Summary Table.

Abort
This register is used to abort current AES operation.

Table 20-5 ABORT Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ABORTAESW0hAbort AES operation
Abort an ongoing AES operation. An abort will clear TXT, BUF, DMA, AUTOCFG registers
  • 0h = Writing 0 has no effect
  • 1h = Aborts an ongoing AES operation

20.4.4 CLR Register (Offset = 18h) [Reset = 00000000h]

CLR is shown in Table 20-6.

Return to the Summary Table.

Clear
This register is used to clear contents of TXT and BUF when STA.STATE = IDLE. If condition is not met, the contents remain unchanged.

Table 20-6 CLR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1TXTW0hClear TXT
  • 0h = Writing 0 has no effect
  • 1h = Clears TXT
0BUFW0hClear BUF
  • 0h = Writing 0 has no effect
  • 1h = Clears BUF

20.4.5 STA Register (Offset = 1Ch) [Reset = 00000000h]

STA is shown in Table 20-7.

Return to the Summary Table.

Status
This register provides information on AES accellerator state and BUF status.

Table 20-7 STA Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4-3KEYINTIDR0hKEY Initiator ID
ID of the most recent AHB Initiator which has written into one of the KEY0 to KEY3 registers
  • 0h = KEY was last written by CM33
  • 3h = KEY was last written by HSM
2KEYSTATER0hKEY State
Indicates whether data in KEY0 to KEY3 is valid or not. AES operations are not allowed until KEY is valid
  • 0h = KEY0 to KEY3 are partially written or empty. Hence they do not have valid KEY value. ;AES operations are not allowed
  • 1h = KEY0 to KEY3 are completely written by same AHB Initiator . Hence they have valid KEY value. ;AES operations are allowed.
1BUFSTAR0h BUF Status
Field gives the status of BUF, indicating EMPTY or FULL, when AUTOCFG.TRGAES = WRBUF3.
If AUTOCFG.TRGAES != WRBUF3, then STA.BUFSTA will hold the value 0.
Note : Useful for CBC-MAC
  • 0h = Data stored in BUF is already consumed by the AES engine and next block of data can be written in BUF.
  • 1h = Data stored in BUF is not yet consumed by the AES engine. Next block of data cannot be written into BUF until STA.STATE = IDLE.
0STATER0hState
Field gives the state of the AES engine.
  • 0h = AES engine is IDLE
  • 1h = AES operation active

20.4.6 DMA Register (Offset = 20h) [Reset = 00000000h]

DMA is shown in Table 20-8.

Return to the Summary Table.

Direct Memory Access
This register controls the conditions that will generate burst requests on each DMA channel.

Table 20-8 DMA Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16DONEACTR/W0hDone Action
This field determines the side effects of DMA done. It is allowed to configure this field with an OR-combination of supported enums, with the exception that GATE_TRGAES_ON_CHA and GATE_TRGAES_ON_CHA_DEL must be mutually exclusive
  • 0h = DMA done has no side effect
  • 1h = Triggers defined in AUTOCFG.TRGAES are gated when RIS.CHADONE = SET
  • 2h = Delayed gating of triggers defined in AUTOCFG.TRGAES; Due to the pipelining of BUF writes, in certain modes, DMA CHA Done appears before the last but one AES operation has completed. Setting this bit, will gate the triggers defined in AUTOCFG.TRGAES only after the last write by CHA is consumed by AES FSM. Used in ECB,CBC,CBC-MAC modes (having multiple blocks encryption/decryption) to avoid spurious AES operation triggered on last read by CHB. For single mode operation, DMA.GATE_TRGAES_ON_CHA must be used.
  • 4h = DMA channel A done event clears TXT0 thru TXT3 if STA.STATE = IDLE. Event is ignored if condition is not met.
  • 8h = DMA channel B done event clears TXT0 thru TXT3 if STA.STATE = IDLE. Event is ignored if condition is not met.
15-14RESERVEDR0hReserved
13-12ADRCHBR/W0hChannel B Read Write Address
The DMA accesses DMACHB to read or write contents of TXT and BUF as a response to a burst request. This field specifes the start address of the first DMA transfer that follows the burst request. The internal address gets incremented automatically for subsequent accesses. The DMA can transfer 8-bit, 16-bit, or 32-bit words, and must always complete a 16-byte transfer before re-arbitration.
  • 0h = Start address is TXT0
  • 1h = Start address is TXTX0
  • 2h = Start address is BUF0
  • 3h = Start address is TXTXBUF0
11RESERVEDR0hReserved
10-8TRGCHBR/W0hChannel B Trigger
Select the condition that triggers DMA channel B request. Non-enumerated values are not supported and ignored.
  • 0h = DMA requests are disabled
  • 1h = Start of AES operation triggers request
  • 2h = Completion of AES operation triggers request
  • 3h = Writes to TXT3, TXTX3, or TXTXBUF3 trigger request
  • 4h = Reads of TXT3, or TXTXBUF3 trigger request
7-6RESERVEDR0hReserved
5-4ADRCHAR/W0hChannel A Read Write Address
The DMA accesses DMACHA to read or write contents of TXT and BUF as a response to a burst request. This field specifes the start address of the first DMA transfer that follows the burst request. The internal address gets incremented automatically for subsequent accesses. The DMA can transfer 8-bit, 16-bit, or 32-bit words, and must always complete a 16-byte transfer before re-arbitration.
  • 0h = Start address is TXT0
  • 1h = Start address is TXTX0
  • 2h = Start address is BUF0
  • 3h = Start address is TXTXBUF0
3RESERVEDR0hReserved
2-0TRGCHAR/W0hChannel A Trigger
Select the condition that triggers DMA channel A request. Non-enumerated values are not supported and ignored.
  • 0h = DMA requests are disabled
  • 1h = Start of AES operation triggers request
  • 2h = Completion of AES operation triggers request
  • 3h = Writes to TXT3 or TXTX3 trigger request
  • 4h = Reads of TXT3 or TXTXBUF3 trigger request

20.4.7 DMACHA Register (Offset = 24h) [Reset = 00000000h]

DMACHA is shown in Table 20-9.

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DMA Channel A data transfer
DMA accesses this register to read or write contents from sequential addresses specifed by DMA.ADRCHA.

Table 20-9 DMACHA Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hValue transferred through DMA Channel A

20.4.8 DMACHB Register (Offset = 28h) [Reset = 00000000h]

DMACHB is shown in Table 20-10.

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DMA Channel B data transfer
DMA accesses this register to read or write contents from sequential addresses specifed by DMA.ADRCHB.

Table 20-10 DMACHB Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hValue transferred through DMA Channel B

20.4.9 AUTOCFG Register (Offset = 2Ch) [Reset = 00000000h]

AUTOCFG is shown in Table 20-11.

Return to the Summary Table.

Automatic Configuration
This register configures automatic hardware updates to TXT and BUF. Configure this register to reduce software overhead during cipher modes.

Table 20-11 AUTOCFG Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28CHBDNCLRR/W0hThis field enable auto-clear of RIS.CHBDONE interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 .
  • 0h = Disable auto-clear of RIS.CHBDONE interrupt
  • 1h = Enable auto-clear of RIS.CHBDONE interrupt
27CHADNCLRR/W0hThis field enables auto-clear of RIS.CHADONE interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 .
  • 0h = Disable auto-clear of RIS.CHADONE interrupt
  • 1h = Enable auto-clear of RIS.CHADONE interrupt
26CLRAESSTR/W0hClear AES Start
This field enables auto-clear of RIS.AESSTART interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 .
  • 0h = Disable auto-clear of RIS.AESSTART interrupt
  • 1h = Enable auto-clear of RIS.AESSTART interrupt
25CLRAESDNR/W0hClear AES Done
This field enables auto-clear of RIS.AESDONE interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 .
  • 0h = Disable auto-clear of RIS.AESDONE interrupt
  • 1h = Enable auto-clear of RIS.AESDONE interrupt
24BUSHALTR/W0hBus Halt
This field decides if bus halts on access to KEY, TXT, BUF, TXTX and TXTXBUF when STA.STATE = BUSY.
  • 0h = Disable bus halt;When STA.STATE = BUSY, writes to KEY, TXT, TXTX are ignored, reads from TXT, TXTXBUF return zero.;When STA.STATE = BUSY and if either STA.BUFSTA = FULL or AUTOCFG.CTRSIZE != DISABLE, writes to BUF are ignored, reads return zero.
  • 1h = Enable bus halt;When STA.STATE = BUSY, access to KEY, TXT, TXTX, TXTXBUF halt the bus until STA.STATE = IDLE.;When STA.STATE = BUSY and if either STA.BUFSTA = FULL or AUTOCFG.CTRSIZE != DISABLE, access to BUF halts the bus until STA.STATE = IDLE.
23-22RESERVEDR0hReserved
21-19CTRSIZER/W0hCounter Size
Configures size of counter as either 8,16,32,64 or 128
Non-enumerated values are not supported and ignored
  • 0h = Disable CTR operation
  • 1h = Configures counter size as 8-bit
  • 2h = Configures counter size as 16-bit
  • 3h = Configures counter size as 32-bit
  • 4h = Configures counter size as 64-bit
  • 5h = Configures counter size as 128-bit
18CTRALIGNR/W0hCounter Alignment
Specifies alignment of counter
  • 0h = Indicates Left Aligned Counter;Not applicable for 128-bit counter size. ;For 128-bit counter, all octets will be considered;When left aligned,,octet 0-7 will be considered , based on counter size and endianness
  • 1h = Indicates right aligned counter;Not applicable when counter size is 128-bit;For 128-bit counter, all octets will be considered;If right aligned, octet 8-15 will be considered based on endianness and counter size
17CTRENDNR/W0hCounter Endianness
Specifies Endianness of counter
  • 0h = Specifies Little Endian Counter;Carry will flow from octet 'n' to octet 'n+1'
  • 1h = Specifies Big Endian Counter;Carry will flow from octet 'n' to octet 'n-1'
16-10RESERVEDR0hReserved
9-8TRGTXTR/W0hTrigger for TXT
This field determines if and when hardware automatically XORs BUF into TXT. Non-enumerated values are not supported and ignored. It is allowed to configure this field with an OR-combination of supported enums.
  • 0h = No hardware update of TXT
  • 1h = Hardware XORs content of BUF into TXT upon read of TXT3
  • 2h = Hardware XORs content of BUF into TXT upon read of TXTXBUF3
7-6RESERVEDR0hReserved
5-4AESSRCR/W0hAES Source
This field specifies the data source to hardware-triggered AES operations. Non-enumerated values are not supported and ignored.
  • 1h = TXT = AES(KEY,TXT)
  • 2h = TXT = AES(KEY,BUF)
  • 3h = TXT = AES(KEY, TXT XOR BUF)
3-0TRGAESRH/W0hTrigger Electronic Codebook
This field specifies one or more actions that indirectly trigger AES operation.
It is allowed to configure this field with an OR-combination of supported enums.
  • 0h = No user action indirectly triggers AES operation
  • 1h = All writes to TXT3 or TXTX3 trigger action, only when STA.STATE = IDLE
  • 2h = All reads of TXT3 or TXTXBUF3 trigger action, only when STA.STATE = IDLE
  • 4h = All writes to BUF3 will schedule to trigger action once STA.STATE is or becomes IDLE, only when AUTOCFG.CTRSIZE = DIS
  • 8h = Write to BUF3 will schedule to trigger single action once STA.STATE is or becomes IDLE. Subsequent writes do not trigger action unless this setting is written again to this field.

20.4.10 KEY0 Register (Offset = 50h) [Reset = 00000000h]

KEY0 is shown in Table 20-12.

Return to the Summary Table.

Key Word 0
Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the hardware. It is hence not required to reload the key for subsequent block encryptions/decryptions unless required by the application.

Table 20-12 KEY0 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue of KEY[31:0]

20.4.11 KEY1 Register (Offset = 54h) [Reset = 00000000h]

KEY1 is shown in Table 20-13.

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Key Word 1
Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the hardware. It is hence not required to reload the key for subsequent block encryptions/decryptions unless required by the application.

Table 20-13 KEY1 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue of KEY[63:32]

20.4.12 KEY2 Register (Offset = 58h) [Reset = 00000000h]

KEY2 is shown in Table 20-14.

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Key Word 2
Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the hardware. It is hence not required to reload the key for subsequent block encryptions/decryptions unless required by the application.

Table 20-14 KEY2 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue of KEY[95:64]

20.4.13 KEY3 Register (Offset = 5Ch) [Reset = 00000000h]

KEY3 is shown in Table 20-15.

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Key Word 3
Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the hardware. It is hence not required to reload the key for subsequent block encryptions/decryptions unless required by the application.

Table 20-15 KEY3 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue of KEY[127:96]

20.4.14 TXT0 Register (Offset = 70h) [Reset = 00000000h]

TXT0 is shown in Table 20-16.

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Text Word 0
TXT is the 128-bit buffer, the AES-128 algorithm performs its operations on. AES input can be written to TXT, and ciphertext can be read from TXT.

Table 20-16 TXT0 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of TXT[31:0]

20.4.15 TXT1 Register (Offset = 74h) [Reset = 00000000h]

TXT1 is shown in Table 20-17.

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Text Word 1
TXT is the 128-bit buffer, the AES-128 algorithm performs its operations on. AES input can be written to TXT, and ciphertext can be read from TXT.

Table 20-17 TXT1 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of TXT[63:32]

20.4.16 TXT2 Register (Offset = 78h) [Reset = 00000000h]

TXT2 is shown in Table 20-18.

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Text Word 2
TXT is the 128-bit buffer, the AES-128 algorithm performs its operations on. AES input can be written to TXT, and ciphertext can be read from TXT.

Table 20-18 TXT2 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of TXT[95:64]

20.4.17 TXT3 Register (Offset = 7Ch) [Reset = 00000000h]

TXT3 is shown in Table 20-19.

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Text Word 3
TXT is the 128-bit buffer, the AES-128 algorithm performs its operations on. AES input can be written to TXT, and ciphertext can be read from TXT.

Table 20-19 TXT3 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of TXT[127:96]
AUTOCFG.TRGAES decides if a write to or a read of this field triggers an AES operation.

20.4.18 TXTX0 Register (Offset = 80h) [Reset = 00000000h]

TXTX0 is shown in Table 20-20.

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Text Word 0 XOR
Write data to this register to XOR data with contents in TXT0.VAL.

Table 20-20 TXTX0 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue in TXT0 will be TXT0.VAL = VAL XOR TXT0.VAL

20.4.19 TXTX1 Register (Offset = 84h) [Reset = 00000000h]

TXTX1 is shown in Table 20-21.

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Text Word 1 XOR
Write data to this register to XOR data with contents in TXT1.VAL.

Table 20-21 TXTX1 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue in TXT1 will be TXT1.VAL = VAL XOR TXT1.VAL

20.4.20 TXTX2 Register (Offset = 88h) [Reset = 00000000h]

TXTX2 is shown in Table 20-22.

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Text Word 2 XOR
Write data to this register to XOR data with contents in TXT2.VAL.

Table 20-22 TXTX2 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue in TXT2 will be TXT2.VAL = VAL XOR TXT2.VAL

20.4.21 TXTX3 Register (Offset = 8Ch) [Reset = 00000000h]

TXTX3 is shown in Table 20-23.

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Text Word 3 XOR
Write data to this register to XOR data with contents in TXT3.VAL.
AUTOCFG.TRGAES decides if a write to or a read of this field triggers an AES operation.

Table 20-23 TXTX3 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue in TXT3 will be TXT3.VAL = VAL XOR TXT3.VAL

20.4.22 BUF0 Register (Offset = 90h) [Reset = 00000000h]

BUF0 is shown in Table 20-24.

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Buffer Word 0
BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.

Table 20-24 BUF0 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of BUF[31:0]

20.4.23 BUF1 Register (Offset = 94h) [Reset = 00000000h]

BUF1 is shown in Table 20-25.

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Buffer Word 1
BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.

Table 20-25 BUF1 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of BUF[63:32]

20.4.24 BUF2 Register (Offset = 98h) [Reset = 00000000h]

BUF2 is shown in Table 20-26.

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Buffer Word 2
BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.

Table 20-26 BUF2 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of BUF[95:64]

20.4.25 BUF3 Register (Offset = 9Ch) [Reset = 00000000h]

BUF3 is shown in Table 20-27.

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Buffer Word 3
BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.
AUTOCFG.TRGAES decides if a write to this field triggers an AES operation.

Table 20-27 BUF3 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of BUF[127:96]

20.4.26 TXTXBUF0 Register (Offset = A0h) [Reset = 00000000h]

TXTXBUF0 is shown in Table 20-28.

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Text Word 0 XOR Buffer Word 0
Read this register to obtain plaintext during CFB decryption.

Table 20-28 TXTXBUF0 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hValue read will be TXT0.VAL XOR BUF0.VAL

20.4.27 TXTXBUF1 Register (Offset = A4h) [Reset = 00000000h]

TXTXBUF1 is shown in Table 20-29.

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Text Word 1 XOR Buffer Word 1
Read this register to obtain plaintext during CFB decryption.

Table 20-29 TXTXBUF1 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hValue read will be TXT1.VAL XOR BUF1.VAL

20.4.28 TXTXBUF2 Register (Offset = A8h) [Reset = 00000000h]

TXTXBUF2 is shown in Table 20-30.

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Text Word 2 XOR Buffer Word 2
Read this register to obtain plaintext during CFB decryption.

Table 20-30 TXTXBUF2 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hValue read will be TXT2.VAL XOR BUF2.VAL

20.4.29 TXTXBUF3 Register (Offset = ACh) [Reset = 00000000h]

TXTXBUF3 is shown in Table 20-31.

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Text Word 3 XOR Buffer Word3
Read this register to obtain plaintext during CFB decryption.

Table 20-31 TXTXBUF3 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hValue read will be TXT3.VAL XOR BUF3.VAL

20.4.30 IMASK Register (Offset = 104h) [Reset = 00000000h]

IMASK is shown in Table 20-32.

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Interrupt Mask register

Table 20-32 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CHBDONER/W0hDMA Channel B Done interrupt mask
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask
2CHADONER/W0hDMA Channel A Done interrupt mask
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask
1AESSTARTR/W0hAES Start interrupt mask
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask
0AESDONER/W0hAES Done interrupt mask
  • 0h = Disable interrupt mask
  • 1h = Enable interrupt mask

20.4.31 RIS Register (Offset = 108h) [Reset = 00000000h]

RIS is shown in Table 20-33.

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Raw Interrupt Status register

Table 20-33 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CHBDONER0hRaw Interrupt Status for DMA Channel B Done
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
2CHADONER0hRaw Interrupt Status for DMA Channel A Done
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
1AESSTARTR0hRaw Interrupt Status for AES Start
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
0AESDONER0hRaw Interrupt Status for AES Done
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred

20.4.32 MIS Register (Offset = 10Ch) [Reset = 00000000h]

MIS is shown in Table 20-34.

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Masked Interrupt Status register

Table 20-34 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CHBDONER0hMasked Interrupt Status for DMA Channel B Done
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
2CHADONER0hMasked Interrupt Status for DMA Channel A Done
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
1AESSTARTR0hMasked Interrupt Status for AES Start
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
0AESDONER0hMasked Interrupt Status for AES Done
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred

20.4.33 ISET Register (Offset = 110h) [Reset = 00000000h]

ISET is shown in Table 20-35.

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Interrupt Set register

Table 20-35 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CHBDONEW0hSet DMA Channel B Done interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt
2CHADONEW0hSet DMA Channel A Done interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt
1AESSTARTW0hSet AES Start interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt
0AESDONEW0hSet AES Done interrupt
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt

20.4.34 ICLR Register (Offset = 114h) [Reset = 00000000h]

ICLR is shown in Table 20-36.

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Interrupt Clear register

Table 20-36 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CHBDONEW0hClear DMA Channel B Done interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt
2CHADONEW0hClear DMA Channel A Done interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt
1AESSTARTW0hClear AES Start interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt
0AESDONEW0hClear AES Done interrupt
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt

20.4.35 IMSET Register (Offset = 118h) [Reset = 00000000h]

IMSET is shown in Table 20-37.

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Interrupt Mask Set register

Table 20-37 IMSET Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CHBDONEW0hSet DMA Channel B Done interrupt mask
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
2CHADONEW0hSet DMA Channel A Done interrupt mask
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
1AESSTARTW0hSet AES Start interrupt mask
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask
0AESDONEW0hSet AES Done interrupt mask
  • 0h = Writing 0 has no effect
  • 1h = Set interrupt mask

20.4.36 IMCLR Register (Offset = 11Ch) [Reset = 00000000h]

IMCLR is shown in Table 20-38.

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Interrupt Mask Clear register

Table 20-38 IMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CHBDONEW0hClear DMA Channel B Done interrupt mask
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
2CHADONEW0hClear DMA Channel A Done interrupt mask
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
1AESSTARTW0hClear AES Start interrupt mask
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask
0AESDONEW0hClear AES Done interrupt mask
  • 0h = Writing 0 has no effect
  • 1h = Clear interrupt mask