SWCU195A December   2024  â€“ May 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755P10 , CC2755R10

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M33
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
      5. 1.3.5 TI Machine Learning Instruction Extensions
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDIO
      3. 1.5.3 VDDR
      4. 1.5.4 VDDD Digital Core Supply
      5. 1.5.5 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  Hardware Security Module
    8. 1.8  AES 128-Bit Cryptographic Accelerator
    9. 1.9  System Timer (SYSTIM)
    10. 1.10 General Purpose Timers (LGPT)
    11. 1.11 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.11.1 Watchdog Timer
      2. 1.11.2 Battery and Temperature Monitor
      3. 1.11.3 Voltage Glitch Monitor (VGM)
      4. 1.11.4 Real-Time Clock (RTC)
      5. 1.11.5 Low Power Comparator
    12. 1.12 Direct Memory Access
    13. 1.13 System Control and Clock
    14. 1.14 Communication Peripherals
      1. 1.14.1 UART
      2. 1.14.2 I2C
      3. 1.14.3 SPI
      4. 1.14.4 CAN-FD
      5. 1.14.5 I2S
    15. 1.15 Programmable I/Os
    16. 1.16 Algorithm Processing Unit (APU)
    17. 1.17 Serial Wire Debug (SWD)
  4. 2 Arm® Cortex®-M33 Processor
    1. 2.1 Arm® Cortex®-M33 Processor Introduction
    2. 2.2 M33 Instantiation Parameters
    3. 2.3 Arm® Cortex®-M33 System Peripheral Details
      1. 2.3.1 Floating Point Unit (FPU)
      2. 2.3.2 Memory Protection Unit (MPU)
      3. 2.3.3 Digital Signal Processing (DSP)
      4. 2.3.4 Security Attribution Unit (SAU)
      5. 2.3.5 System Timer (SysTick)
      6. 2.3.6 Nested Vectored Interrupt Controller (NVIC)
      7. 2.3.7 System Control Block (SCB)
      8. 2.3.8 System Control Space (SCS)
    4. 2.4 CPU Sub-System Peripheral Details
      1. 2.4.1 Trace Port Interface Unit (TPIU)
      2. 2.4.2 DAP Bridge and Debug Authentication
      3. 2.4.3 Implementation Defined Attribution Unit (IDAU)
      4. 2.4.4 Custom Datapath Extension (CDE)
    5. 2.5 Programming Model
      1. 2.5.1 Modes of Operation and Execution
        1. 2.5.1.1 Security States
        2. 2.5.1.2 Operating Modes
        3. 2.5.1.3 Operating States
        4. 2.5.1.4 Privileged Access and Unprivileged User Access
      2. 2.5.2 Instruction Set Summary
      3. 2.5.3 Memory Model
        1. 2.5.3.1 Private Peripheral Bus
        2. 2.5.3.2 Unaligned Accesses
      4. 2.5.4 Processor Core Registers Summary
      5. 2.5.5 Exceptions
        1. 2.5.5.1 Exception Handling and Prioritization
    6. 2.6 TrustZone-M
      1. 2.6.1 Overview
      2. 2.6.2 M33 Configuration
      3. 2.6.3 Description of Elements
        1. 2.6.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 2.6.3.1.1 Expected Use
        2. 2.6.3.2 Gaskets
          1. 2.6.3.2.1 Periphery Gasket
          2. 2.6.3.2.2 Controller Gasket
        3. 2.6.3.3 Memories
        4. 2.6.3.4 TCM
      4. 2.6.4 TCM Registers
    7. 2.7 Arm® Cortex®-M33 Registers
      1. 2.7.1  CPU_ROM_TABLE Registers
      2. 2.7.2  TPIU Registers
      3. 2.7.3  DCB Registers
      4. 2.7.4  DIB Registers
      5. 2.7.5  DWT Registers
      6. 2.7.6  FPB Registers
      7. 2.7.7  FPE Registers
      8. 2.7.8  ICB Registers
      9. 2.7.9  ITM Registers
      10. 2.7.10 MPU Registers
      11. 2.7.11 NVIC Registers
      12. 2.7.12 SAU Registers
      13. 2.7.13 SCB Registers
      14. 2.7.14 SYSTIMER Registers
      15. 2.7.15 SYSTICK Registers
      16. 2.7.16 Clock Control
      17. 2.7.17 Protocol Descriptions
      18. 2.7.18 Reset Considerations
        1. 2.7.18.1 Hardware Reset Considerations
      19. 2.7.19 Initialization
      20. 2.7.20 Interrupt and Event Support
        1. 2.7.20.1 Connection to Event Fabric
      21. 2.7.21 Power Management
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Interrupt Priority Grouping
      7. 4.1.7 Exception Entry and Return
        1. 4.1.7.1 Exception Entry
        2. 4.1.7.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Fault Types
      2. 4.2.2 Fault Escalation to HardFault
      3. 4.2.3 Fault Status Registers and Fault Address Registers
      4. 4.2.4 Lockup
    3. 4.3 Security State Switches
    4. 4.4 Event Fabric
      1. 4.4.1 Introduction
      2. 4.4.2 Overview
      3. 4.4.3 Registers
      4. 4.4.4 AON Event Fabric
        1. 4.4.4.1 AON Common Input Events List
        2. 4.4.4.2 AON Event Subscribers
        3. 4.4.4.3 Power Management Controller (PMCTL)
        4. 4.4.4.4 Real Time Clock (RTC)
        5. 4.4.4.5 AON to MCU Event Fabric
      5. 4.4.5 MCU Event Fabric
        1. 4.4.5.1 Common Input Event List
        2. 4.4.5.2 MCU Event Subscribers
          1. 4.4.5.2.1 System CPU
          2. 4.4.5.2.2 Non-Maskable Interrupt (NMI)
    5. 4.5 Digital Test Bus (DTB)
    6. 4.6 EVTSVT Registers
    7. 4.7 EVTULL Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1 Introduction
    2. 6.2 System CPU Modes
    3. 6.3 Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4 Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
      6. 6.4.6 PMCTL Registers
    5. 6.5 Digital Power Partitioning
    6. 6.6 Clocks
      1. 6.6.1 Block Diagram
      2. 6.6.2 LF clock
        1. 6.6.2.1 LFINC Measurement Mechanism
        2. 6.6.2.2 LFINC Filtering
      3. 6.6.3 HFOSC
        1. 6.6.3.1 HFOSC Control and Qualification
        2. 6.6.3.2 HFOSC Tracking Loop
      4. 6.6.4 AFOSC
        1. 6.6.4.1 AFOSC Control and Qualification
        2. 6.6.4.2 AFOSC Tracking Loop
        3. 6.6.4.3 AFOSC Ratio
      5. 6.6.5 CLKSVT
      6. 6.6.6 CLKULL
      7. 6.6.7 CKM Registers
      8. 6.6.8 CKMD Registers
      9. 6.6.9 CLKCTL Registers
    7. 6.7 Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 RTC Reset
      3. 6.7.3 LF Loss Detection
    8. 6.8 AON (REG3V3) Register Bank
  9. 7 Internal Memory
    1. 7.1 SRAM
      1. 7.1.1 Overview
        1. 7.1.1.1 Purpose of the Peripheral
        2. 7.1.1.2 Features
        3. 7.1.1.3 Functional Block Diagram
      2. 7.1.2 Peripheral Functional Description
        1. 7.1.2.1 Parity Error Detection
          1. 7.1.2.1.1 Parity Error Debug Register
        2. 7.1.2.2 Extension Mode
        3. 7.1.2.3 Initialization
        4. 7.1.2.4 TrustZone Watermarking
      3. 7.1.3 SRAM Registers
      4. 7.1.4 SRAMCTRL Registers
    2. 7.2 VIMS
      1. 7.2.1 Overview
        1. 7.2.1.1 Purpose of the Peripheral
        2. 7.2.1.2 Features
        3. 7.2.1.3 Functional Block Diagram
      2. 7.2.2 Peripheral Functional Description
        1. 7.2.2.1 Dedicated 8KB CPU Cache
        2. 7.2.2.2 Dedicated 2KB HSM Cache
        3. 7.2.2.3 Dedicated 128-Bit Line Buffer
        4. 7.2.2.4 ROM
        5. 7.2.2.5 Flash
        6. 7.2.2.6 Auxiliary Regions
        7. 7.2.2.7 Flash Partition and Protection
          1. 7.2.2.7.1 Main Region
          2. 7.2.2.7.2 Read Protection
          3. 7.2.2.7.3 Sticky Write/Erase Protection
        8. 7.2.2.8 TrustZoneTM Watermark
        9. 7.2.2.9 Debug Access
      3. 7.2.3 VIMS Registers
    3. 7.3 FLASH
      1. 7.3.1 FLASH Registers
  10. 8 Hardware Security Module (HSM)
    1. 8.1 Introduction
    2. 8.2 Overview
    3. 8.3 One-Time-Programmable (OTP) Controller
      1. 8.3.1 High-Level Sequence to Handle OTP Requests
    4. 8.4 Mailbox and Register Access Firewall
    5. 8.5 DMA Firewall
    6. 8.6 Coprocessor
    7. 8.7 HSM FW
      1. 8.7.1 Acquiring the Latest HSM FW
      2. 8.7.2 Programming HSM FW
      3. 8.7.3 Optional Customer Signing of HSM FW
    8. 8.8 HSM Registers
    9. 8.9 HSMCRYPTO Registers
  11. 9 Device Boot and Bootloader
    1. 9.1 Device Boot and Programming
      1. 9.1.1 Boot Flow
      2. 9.1.2 Boot Status
      3. 9.1.3 Boot Protection/Locking Mechanisms
      4. 9.1.4 Debug and Active SWD Connections at Boot
        1. 9.1.4.1 Secure Debug and Persistent Debug
      5. 9.1.5 Flashless Test Mode and Tools Client Mode
        1. 9.1.5.1 Flashless Test Mode
        2. 9.1.5.2 Tools Client Mode
      6. 9.1.6 Retest Mode and Return-to-Factory Procedure
      7. 9.1.7 Disabling SWD Debug Port
    2. 9.2 Flash Programming
      1. 9.2.1 CCFG
      2. 9.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 9.2.3 SACI Flash Programming Commands
      4. 9.2.4 Flash Programming Flows
        1. 9.2.4.1 Initial Programming of a New Device
        2. 9.2.4.2 Reprogramming of Previously Programmed Device
        3. 9.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 9.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 9.2.4.5 Reprogramming of Only the Main Flash Application of a Previously Programmed Device
    3. 9.3 Device Management Command Interface
      1. 9.3.1 SACI Communication Protocol
        1. 9.3.1.1 Host Side Protocol
        2. 9.3.1.2 Command Format
        3. 9.3.1.3 Response Format
        4. 9.3.1.4 Response Result Field
        5. 9.3.1.5 Command Sequence Tag
        6. 9.3.1.6 Host Side Timeout
      2. 9.3.2 SACI Commands
        1. 9.3.2.1 Miscellaneous Commands
          1. 9.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 9.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 9.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
          4. 9.3.2.1.4 SACI_CMD_GET_SECBOOT_HSMFW_UPDATE_STATUS
          5. 9.3.2.1.5 SACI_CMD_HSM_GET_SYS_INFO
        2. 9.3.2.2 Debug Commands
          1. 9.3.2.2.1 SACI_CMD_DEBUG_EXIT_SACI_HALT
          2. 9.3.2.2.2 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          3. 9.3.2.2.3 SACI_CMD_DEBUG_REQ_KEY_ID
          4. 9.3.2.2.4 SACI_CMD_DEBUG_REQ_CHALLENGE
          5. 9.3.2.2.5 SACI_CMD_DEBUG_SUBMIT_CHALLENGE_RESP
          6. 9.3.2.2.6 SACI_CMD_DEBUG_CLOSE_SESSION
          7. 9.3.2.2.7 SACI_CMD_BLDR_APP_RESET_DEVICE
          8. 9.3.2.2.8 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 9.3.2.3 Flash Programming Commands
          1. 9.3.2.3.1  SACI_CMD_FLASH_ERASE_CHIP
          2. 9.3.2.3.2  SACI_CMD_FLASH_ERASE_MAIN_APP
          3. 9.3.2.3.3  SACI_CMD_FLASH_PROG_CCFG_SECTOR
          4. 9.3.2.3.4  SACI_CMD_FLASH_PROG_CCFG_USER_REC
          5. 9.3.2.3.5  SACI_CMD_FLASH_PROG_SCFG_SECTOR
          6. 9.3.2.3.6  SACI_CMD_FLASH_PROG_MAIN_SECTOR
          7. 9.3.2.3.7  SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          8. 9.3.2.3.8  SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          9. 9.3.2.3.9  SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
          10. 9.3.2.3.10 SACI_CMD_FLASH_VERIFY_SCFG_SECTOR
    4. 9.4 Bootloader Support
      1. 9.4.1 Bootloader v.s Secure Boot
    5. 9.5 ROM Serial Bootloader
      1. 9.5.1 ROM Serial Bootloader Interfaces
        1. 9.5.1.1 Packet Handling
          1. 9.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 9.5.1.2 Transport Layer
          1. 9.5.1.2.1 UART Transport
            1. 9.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 9.5.1.2.2 SPI Transport
      2. 9.5.2 ROM Serial Bootloader Parameters
      3. 9.5.3 ROM Serial Bootloader Commands
        1. 9.5.3.1 BLDR_CMD_PING
        2. 9.5.3.2 BLDR_CMD_GET_STATUS
        3. 9.5.3.3 BLDR_CMD_GET_PART_ID
        4. 9.5.3.4 BLDR_CMD_RESET
        5. 9.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 9.5.3.6 BLDR_CMD_CRC32
        7. 9.5.3.7 BLDR_CMD_DOWNLOAD
        8. 9.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 9.5.3.9 BLDR_CMD_SEND_DATA
      4. 9.5.4 Bootloader Firmware Update Example
  12. 10Device Configuration
    1. 10.1 Guidelines for Securely Configuring Your Device
      1. 10.1.1 Enabling and Configuring Secure Boot
      2. 10.1.2 Configure Debug Access
      3. 10.1.3 Configure Flash Protections
      4. 10.1.4 Configure Device Permissions
      5. 10.1.5 Configure HSM FW Update Keys
      6. 10.1.6 Configure emSensor
    2. 10.2 Factory Configuration (FCFG)
    3. 10.3 Customer Configuration (CCFG)
    4. 10.4 Security Configuration (SCFG)
  13. 11Secure Boot
    1. 11.1  Secure Boot
    2. 11.2  Execution Flow
    3. 11.3  ROM API
      1. 11.3.1 HAPI (Hardware API)
      2. 11.3.2 Registers
    4. 11.4  Configuration
      1. 11.4.1 Slot Configuration
      2. 11.4.2 Policy
        1. 11.4.2.1 Authentication Method
        2. 11.4.2.2 Authentication Algorithm
        3. 11.4.2.3 Update Mode
          1. 11.4.2.3.1 Overwrite
          2. 11.4.2.3.2 XIP Revert Enabled/Disabled
      3. 11.4.3 Key Update Key Hash
      4. 11.4.4 Key Ring
      5. 11.4.5 Boot Seed
    5. 11.5  Generic Image Format
    6. 11.6  Application Update
      1. 11.6.1 Image Format
    7. 11.7  Secondary Secure Bootloader Update
      1. 11.7.1 Image Format
      2. 11.7.2 Update Pattern
    8. 11.8  Key Update
      1. 11.8.1 Image Format
    9. 11.9  Antirollback
    10. 11.10 Version Log (VLOG)
      1. 11.10.1 Record structure
    11. 11.11 Fallback
    12. 11.12 ROM Panic
  14. 12General Purpose Timers (LGPT)
    1. 12.1 Overview
    2. 12.2 Block Diagram
    3. 12.3 Functional Description
      1. 12.3.1  Prescaler
      2. 12.3.2  Counter
      3. 12.3.3  Target
      4. 12.3.4  Channel Input Logic
      5. 12.3.5  Channel Output Logic
      6. 12.3.6  Channel Actions
        1. 12.3.6.1 Period and Pulse Width Measurement
        2. 12.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 12.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 12.3.7  Channel Capture Configuration
      8. 12.3.8  Channel Filters
        1. 12.3.8.1 Setting up the Channel Filters
      9. 12.3.9  Synchronize Multiple LGPT Timers
      10. 12.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 12.4 Timer Modes
      1. 12.4.1 Quadrature Decoder
      2. 12.4.2 DMA
      3. 12.4.3 IR Generation
      4. 12.4.4 Fault and Park
      5. 12.4.5 Deadband
      6. 12.4.6 Deadband, Fault, and Park
      7. 12.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 12.5 LGPT0 Registers
    6. 12.6 LGPT1 Registers
    7. 12.7 LGPT2 Registers
    8. 12.8 LGPT3 Registers
  15. 13Algorithm Processing Unit (APU)
    1. 13.1 Introduction
    2. 13.2 APU Related Collateral
    3. 13.3 Functional Description
    4. 13.4 APU Operation
    5. 13.5 Interrupts and Events
    6. 13.6 Data Representation
    7. 13.7 Data Memory
    8. 13.8 Software
    9. 13.9 APU Registers
  16. 14Voltage Glitch Monitor (VGM)
    1. 14.1 Overview
    2. 14.2 Features and Operation
  17. 15System Timer (SYSTIM)
    1. 15.1 Overview
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1 Common Channel Features
        1. 15.3.1.1 Compare Mode
        2. 15.3.1.2 Capture Mode
        3. 15.3.1.3 Additional Channel Arming Methods
      2. 15.3.2 Interrupts and Events
    4. 15.4 SYSTIM Registers
  18. 16Real Time Clock (RTC)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Interrupts and Events
      1. 16.3.1 Input Event
      2. 16.3.2 Output Event
      3. 16.3.3 Arming and Disarming Channels
    4. 16.4 CAPTURE and COMPARE Configurations
      1. 16.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 16.4.2 CHANNEL 1—CAPTURE CHANNEL
    5. 16.5 RTC Registers
  19. 17Low Power Comparator (SYS0)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 Input Selection
      2. 17.3.2 Voltage Divider
      3. 17.3.3 Hysteresis
      4. 17.3.4 Wake-Up
    4. 17.4 SYS0 Registers
  20. 18Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 18.1 Introduction
    2. 18.2 Functional Description
      1. 18.2.1 BATMON
      2. 18.2.2 DCDC
    3. 18.3 PMUD Registers
  21. 19Micro Direct Memory Access (µDMA)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1  Channel Assignments
      2. 19.3.2  Priority
      3. 19.3.3  Arbitration Size
      4. 19.3.4  Request Types
        1. 19.3.4.1 Single Request
        2. 19.3.4.2 Burst Request
      5. 19.3.5  Channel Configuration
      6. 19.3.6  Transfer Modes
        1. 19.3.6.1 Stop Mode
        2. 19.3.6.2 Basic Mode
        3. 19.3.6.3 Auto Mode
        4. 19.3.6.4 Ping-Pong Mode
        5. 19.3.6.5 Memory Scatter-Gather Mode
        6. 19.3.6.6 Peripheral Scatter-Gather Mode
      7. 19.3.7  Transfer Size and Increments
      8. 19.3.8  Peripheral Interface
      9. 19.3.9  Software Request
      10. 19.3.10 Interrupts and Errors
      11. 19.3.11 Initialization and Configuration
        1. 19.3.11.1 Module Initialization
        2. 19.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 19.3.11.3 Configure the Channel Attributes
        4. 19.3.11.4 Configure the Channel Control Structure
        5. 19.3.11.5 Start the Transfer
        6. 19.3.11.6 Software Considerations
    4. 19.4 DMA Registers
  22. 20Advanced Encryption Standard (AES)
    1. 20.1 Introduction
      1. 20.1.1 AES Performance
    2. 20.2 Functional Description
      1. 20.2.1 Reset Considerations
      2. 20.2.2 Interrupt and Event Support
        1. 20.2.2.1 Interrupt Events and Requests
        2. 20.2.2.2 Connection to Event Fabric
      3. 20.2.3 µDMA
        1. 20.2.3.1 µDMA Example
    3. 20.3 Encryption and Decryption Configuration
      1. 20.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 20.3.2  CBC (Cipher Block Chaining) Encryption
      3. 20.3.3  CBC Decryption
      4. 20.3.4  CTR (Counter) Encryption/Decryption
      5. 20.3.5  ECB (Electronic Code Book) Encryption
      6. 20.3.6  ECB Decryption
      7. 20.3.7  CFB (Cipher Feedback) Encryption
      8. 20.3.8  CFB Decryption
      9. 20.3.9  OFB (Open Feedback) Encryption
      10. 20.3.10 OFB Decryption
      11. 20.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 20.3.12 PCBC Decryption
      13. 20.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 20.3.14 CCM
    4. 20.4 AES Registers
    5. 20.5 CRYPTO Registers
  23. 21Analog to Digital Converter (ADC)
    1. 21.1 Overview
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1  ADC Core
      2. 21.3.2  Voltage Reference Options
      3. 21.3.3  Resolution Modes
      4. 21.3.4  ADC Clocking
      5. 21.3.5  Power Down Behavior
      6. 21.3.6  Sampling Trigger Sources and Sampling Modes
        1. 21.3.6.1 AUTO Sampling Mode
        2. 21.3.6.2 MANUAL Sampling Mode
      7. 21.3.7  Sampling Period
      8. 21.3.8  Conversion Modes
      9. 21.3.9  ADC Data Format
      10. 21.3.10 Status Register
      11. 21.3.11 ADC Events
        1. 21.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 21.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 21.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 21.3.11.4 Generic Event Subscriber
    4. 21.4 Advanced Features
      1. 21.4.1 Window Comparator
      2. 21.4.2 DMA & FIFO Operation
        1. 21.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 21.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 21.4.2.3 DMA/CPU Operation Summary Matrix
      3. 21.4.3 Ad-hoc Single Conversion
    5. 21.5 ADC Registers
  24. 22I/O Controller (IOC)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  I/O Mapping and Configuration
      1. 22.3.1 Basic I/O Mapping
      2. 22.3.2 Radio GPO
      3. 22.3.3 Pin Mapping
      4. 22.3.4 DTB Muxing
    4. 22.4  Edge Detection
    5. 22.5  GPIO
    6. 22.6  I/O Pins
    7. 22.7  Unused Pins
    8. 22.8  Debug Configuration
    9. 22.9  IOC Registers
    10. 22.10 GPIO Registers
  25. 23Universal Asynchronous Receiver/Transmitter (UART-LIN)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 UART Functional Description
      1. 23.3.1 Transmit and Receive Logic
      2. 23.3.2 Baud Rate Generation
      3. 23.3.3 FIFO Operation
        1. 23.3.3.1 FIFO Remapping
      4. 23.3.4 Data Transmission
      5. 23.3.5 Flow Control
      6. 23.3.6 IrDA Encoding and Decoding
      7. 23.3.7 Interrupts
      8. 23.3.8 Loopback Operation
    4. 23.4 UART-LIN Specification
      1. 23.4.1 Break transmission in UART mode
      2. 23.4.2 Break reception in UART mode
      3. 23.4.3 Break/Synch transmission in LIN mode
      4. 23.4.4 Break/Synch reception in LIN mode
      5. 23.4.5 Dormant mode operation
      6. 23.4.6 Wakeup signal generation
      7. 23.4.7 Wakeup signal detection when device is in active/idle modes
      8. 23.4.8 Wakeup signal detection when device is in standby mode
    5. 23.5 Interface to µDMA
    6. 23.6 Initialization and Configuration
    7. 23.7 UART Registers
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Overview
      1. 24.1.1 Features
      2. 24.1.2 Block Diagram
    2. 24.2 Signal Description
    3. 24.3 Functional Description
      1. 24.3.1  Clock Control
      2. 24.3.2  FIFO Operation
        1. 24.3.2.1 Transmit FIFO
        2. 24.3.2.2 Repeated Transmit Operation
        3. 24.3.2.3 Receive FIFO
        4. 24.3.2.4 FIFO Flush
      3. 24.3.3  Interrupts
      4. 24.3.4  Data Format
      5. 24.3.5  Delayed Data Sampling
      6. 24.3.6  Chip Select Control
      7. 24.3.7  Command Data Control
      8. 24.3.8  Protocol Descriptions
        1. 24.3.8.1 Motorola SPI Frame Format
        2. 24.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 24.3.8.3 MICROWIRE Frame Format
      9. 24.3.9  CRC Configuration
      10. 24.3.10 Auto CRC Functionality
      11. 24.3.11 Auto Header Functionality
      12. 24.3.12 SPI Status
      13. 24.3.13 Debug Halt
    4. 24.4 µDMA Operation
    5. 24.5 Initialization and Configuration
    6. 24.6 SPI Registers
  27. 25Inter-Integrated Circuit (I2C)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Functional Description
      1. 25.3.1 Functional Overview
        1. 25.3.1.1 Start and Stop Conditions
        2. 25.3.1.2 Data Format with 7-Bit Address
        3. 25.3.1.3 Data Validity
        4. 25.3.1.4 Acknowledge
        5. 25.3.1.5 Arbitration
      2. 25.3.2 Available Speed Modes
      3. 25.3.3 Interrupts
        1. 25.3.3.1 I2C Controller Interrupts
        2. 25.3.3.2 I2C Target Interrupts
      4. 25.3.4 Loopback Operation
      5. 25.3.5 Command Sequence Flowcharts
        1. 25.3.5.1 I2C Controller Command Sequences
        2. 25.3.5.2 I2C Target Command Sequences
    4. 25.4 Initialization and Configuration
    5. 25.5 I2C Registers
  28. 26Inter-IC Sound (I2S)
    1. 26.1  Introduction
    2. 26.2  Block Diagram
    3. 26.3  Clock Architecture
    4. 26.4  Signal Descriptions
    5. 26.5  Functional Description
      1. 26.5.1 Pin Configuration
      2. 26.5.2 Serial Format Configuration
      3. 26.5.3 I2S Format Schematic
        1. 26.5.3.1 Register Configuration
      4. 26.5.4 Left-Justified (LJF)
        1. 26.5.4.1 Register Configuration
      5. 26.5.5 Right-Justified (RJF)
        1. 26.5.5.1 Register Configuration
      6. 26.5.6 DSP
        1. 26.5.6.1 Register Configuration
      7. 26.5.7 Clock Configuration
    6. 26.6  Memory Interface
      1. 26.6.1 Sample Word Length
      2. 26.6.2 Padding Mechanism
      3. 26.6.3 Channel Mapping
      4. 26.6.4 Sample Storage in Memory
      5. 26.6.5 DMA Operation
        1. 26.6.5.1 Start-Up
        2. 26.6.5.2 Operation
        3. 26.6.5.3 Shutdown
    7. 26.7  Samplestamp Generator
      1. 26.7.1 Samplestamp Counters
      2. 26.7.2 Start-Up Triggers
      3. 26.7.3 Samplestamp Capture
      4. 26.7.4 Achieving Constant Audio Latency
    8. 26.8  Error Detection
    9. 26.9  Usage
      1. 26.9.1 Start-Up Sequence
      2. 26.9.2 Shutdown Sequence
    10. 26.10 I2S Configuration Guideline
    11. 26.11 I2S Registers
  29. 27CAN-FD
    1. 27.1 Introduction
    2. 27.2 Functions
    3. 27.3 MCAN Subsystem
    4. 27.4 MCAN Functional Description
      1. 27.4.1 Operating Modes
        1. 27.4.1.1 Software Initialization
        2. 27.4.1.2 Normal Operation
        3. 27.4.1.3 CAN FD Operation
        4. 27.4.1.4 Transmitter Delay Compensation
          1. 27.4.1.4.1 Description
          2. 27.4.1.4.2 Transmitter Delay Compensation Measurement
        5. 27.4.1.5 Restricted Operation Mode
        6. 27.4.1.6 Bus Monitoring Mode
        7. 27.4.1.7 Disabled Automatic Retransmission
          1. 27.4.1.7.1 Frame Transmission in DAR Mode
        8. 27.4.1.8 Power Down (Sleep Mode)
          1. 27.4.1.8.1 MCAN Clock Stop and Wake Operations
          2. 27.4.1.8.2 MCAN Debug Suspend Operation
        9. 27.4.1.9 Test Modes
          1. 27.4.1.9.1 External Loop Back Mode
          2. 27.4.1.9.2 Internal Loop Back Mode
      2. 27.4.2 Timestamp Generation
        1. 27.4.2.1 External Timestamp Counter
        2. 27.4.2.2 Block Diagram
      3. 27.4.3 Timeout Counter
      4. 27.4.4 Rx Handling
        1. 27.4.4.1 Acceptance Filtering
          1. 27.4.4.1.1 Range Filter
          2. 27.4.4.1.2 Filter for specific IDs
          3. 27.4.4.1.3 Classic Bit Mask Filter
          4. 27.4.4.1.4 Standard Message ID Filtering
          5. 27.4.4.1.5 Extended Message ID Filtering
        2. 27.4.4.2 Rx FIFOs
          1. 27.4.4.2.1 Rx FIFO Blocking Mode
          2. 27.4.4.2.2 Rx FIFO Overwrite Mode
        3. 27.4.4.3 Dedicated Rx Buffers
          1. 27.4.4.3.1 Rx Buffer Handling
        4. 27.4.4.4 Debug on CAN Support
          1. 27.4.4.4.1 Filtering for Debug Messages
          2. 27.4.4.4.2 Debug Message Handling
      5. 27.4.5 Tx Handling
        1. 27.4.5.1 Transmit Pause
        2. 27.4.5.2 Dedicated Tx Buffers
        3. 27.4.5.3 Tx FIFO
        4. 27.4.5.4 Tx Queue
        5. 27.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 27.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 27.4.5.7 Transmit Cancellation
        8. 27.4.5.8 Tx Event Handling
      6. 27.4.6 FIFO Acknowledge Handling
      7. 27.4.7 MCAN Message RAM
        1. 27.4.7.1 Message RAM Configuration
        2. 27.4.7.2 Rx Buffer and FIFO Element
        3. 27.4.7.3 Tx Buffer Element
        4. 27.4.7.4 Tx Event FIFO Element
        5. 27.4.7.5 Standard Message ID Filter Element
        6. 27.4.7.6 Extended Message ID Filter Element
      8. 27.4.8 Interrupt Requests
    5. 27.5 CC27xx MCAN Wrapper
    6. 27.6 MCAN Clock Enable
    7. 27.7 Additional Notes
    8. 27.8 CANFD Registers
  30. 28Radio
    1. 28.1  Introduction
    2. 28.2  Block Diagram
    3. 28.3  Overview
      1. 28.3.1 Radio Sub-Domains
      2. 28.3.2 Radio RAMs
      3. 28.3.3 Doorbell (DBELL)
        1. 28.3.3.1 Interrupts
        2. 28.3.3.2 GPIO Control
        3. 28.3.3.3 SYSTIM Interface
    4. 28.4  Radio Usage Model
      1. 28.4.1 CRC and Whitening
    5. 28.5  LRFDDBELL Registers
    6. 28.6  LRFDMDM32 Registers
    7. 28.7  LRFDPBE Registers
    8. 28.8  LRFDPBE32 Registers
    9. 28.9  LRFDRFE Registers
    10. 28.10 LRFDRFE32 Registers
    11. 28.11 LRFDRXF Registers
    12. 28.12 LRFDS2R Registers
    13. 28.13 LRFDTRC Registers
    14. 28.14 LRFDTXF Registers
  31. 29Revision History

2.7.13 SCB Registers

Table 2-479 lists the memory-mapped registers for the SCB registers. All register offset addresses not listed in Table 2-479 should be considered as reserved locations and the register contents should not be modified.

Table 2-479 SCB Registers
OffsetAcronymRegister NameSection
0hREVIDRProvides implementation-specific minor revision informationSection 2.7.13.1
4hCPUIDProvides identification information for the PE, including an implementer code for the device and a device ID numberSection 2.7.13.2
8hICSRControls and provides status information for NMI, PendSV, SysTick and interruptsSection 2.7.13.3
ChVTORIndicates the offset of the vector table base address from memory address 0x00000000Section 2.7.13.4
10hAIRCRThis register is used to determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point).Section 2.7.13.5
14hSCRThis register is used for power-management functions, i.e., signaling to the system when the processor can enter a low power state, controlling how the processor enters and exits low power states.Section 2.7.13.6
18hCCRSets or returns configuration and control dataSection 2.7.13.7
1ChSHPR1Sets or returns priority for system handlers 4 - 7Section 2.7.13.8
20hSHPR2Sets or returns priority for system handlers 8 - 11Section 2.7.13.9
24hSHPR3Sets or returns priority for system handlers 12 - 15Section 2.7.13.10
28hSHCSRProvides access to the active and pending status of system exceptionsSection 2.7.13.11
2ChCFSRContains the three Configurable Fault Status RegistersSection 2.7.13.12
30hHFSRShows the cause of any HardFaultsSection 2.7.13.13
34hDFSRShows which debug event occurredSection 2.7.13.14
38hMMFARShows the address of the memory location that caused an MPU faultSection 2.7.13.15
3ChBFARShows the address associated with a precise data access BusFaultSection 2.7.13.16
40hAFSRThis register is used to determine additional system fault information to software. Single-cycle high level on an auxiliary faults is latched as one. The bit can only be cleared by writing a one to the corresponding bit. Auxiliary fault inputs to the **CPU** are tied to 0.Section 2.7.13.17
44hID_PFR0Gives top-level information about the instruction set supported by the PESection 2.7.13.18
48hID_PFR1Gives information about the programmers' model and Extensions supportSection 2.7.13.19
4ChID_DFR0Provides top level information about the debug systemSection 2.7.13.20
50hID_AFR0Provides information about the IMPLEMENTATION DEFINED features of the PESection 2.7.13.21
54hID_MMFR0Provides information about the implemented memory model and memory management supportSection 2.7.13.22
58hID_MMFR1Provides information about the implemented memory model and memory management supportSection 2.7.13.23
5ChID_MMFR2Provides information about the implemented memory model and memory management supportSection 2.7.13.24
60hID_MMFR3Provides information about the implemented memory model and memory management supportSection 2.7.13.25
64hID_ISAR0Provides information about the instruction set implemented by the PESection 2.7.13.26
68hID_ISAR1Provides information about the instruction set implemented by the PESection 2.7.13.27
6ChID_ISAR2Provides information about the instruction set implemented by the PESection 2.7.13.28
70hID_ISAR3Provides information about the instruction set implemented by the PESection 2.7.13.29
74hID_ISAR4Provides information about the instruction set implemented by the PESection 2.7.13.30
78hID_ISAR5Provides information about the instruction set implemented by the PESection 2.7.13.31
7ChCLIDRIdentifies the type of caches implemented and the level of coherency and unificationSection 2.7.13.32
80hCTRThe CTR provides information about the architecture of the currently selected cacheSection 2.7.13.33
84hCCSIDRProvides information about the architecture of the caches. CCSIDR is RES0 if CLIDR is zero.Section 2.7.13.34
88hCSSELRSelects the current Cache Size ID Register, CCSIDR, by specifying the required cache level and the cacheSection 2.7.13.35
8ChCPACRSpecifies the access privileges for coprocessors and the FP ExtensionSection 2.7.13.36
90hNSACRDefines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7Section 2.7.13.37

Complex bit access types are encoded to fit into small table cells. Table 2-480 shows the codes that are used for access types in this section.

Table 2-480 SCB Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

2.7.13.1 REVIDR Register (Offset = 0h) [Reset = 00000000h]

REVIDR is shown in Table 2-481.

Return to the Summary Table.

Provides implementation-specific minor revision information

Table 2-481 REVIDR Register Field Descriptions
BitFieldTypeResetDescription
31-0IMPLEMENTAION_DEFINEDR411FD210hThe contents of this field are IMPLEMENTATION DEFINED

2.7.13.2 CPUID Register (Offset = 4h) [Reset = 00000000h]

CPUID is shown in Table 2-482.

Return to the Summary Table.

Provides identification information for the PE, including an implementer code for the device and a device ID number

Table 2-482 CPUID Register Field Descriptions
BitFieldTypeResetDescription
31-24ImplementerR41hThis field must hold an implementer code that has been assigned by ARM
23-20VariantR1hIMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product
19-16ArchitectureRFhDefines the Architecture implemented by the PE
15-4PartNoRD21hIMPLEMENTATION DEFINED primary part number for the device
3-0RevisionR0hIMPLEMENTATION DEFINED revision number for the device

2.7.13.3 ICSR Register (Offset = 8h) [Reset = 00000000h]

ICSR is shown in Table 2-483.

Return to the Summary Table.

Controls and provides status information for NMI, PendSV, SysTick and interrupts

Table 2-483 ICSR Register Field Descriptions
BitFieldTypeResetDescription
31PENDNMISETR0hIndicates whether the NMI exception is pending
30PENDNMICLRW0hAllows the NMI exception pend state to be cleared
29RES0R0hReserved, RES0
28PENDSVSETR0hIndicates whether the PendSV `FTSSS exception is pending
27PENDSVCLRW0hAllows the PendSV exception pend state to be cleared `FTSSS
26PENDSTSETR0hIndicates whether the SysTick `FTSSS exception is pending
25PENDSTCLRW0hAllows the SysTick exception pend state to be cleared `FTSSS
24STTNSR/W0hControls whether in a single SysTick implementation, the SysTick is Secure or Non-secure
23ISRPREEMPTR0hIndicates whether a pending exception will be serviced on exit from debug halt state
22ISRPENDINGR0hIndicates whether an external interrupt, generated by the NVIC, is pending
21RES0_1R0hReserved, RES0
20-12VECTPENDINGR0hThe exception number of the highest priority pending and enabled interrupt
11RETTOBASER0hIn Handler mode, indicates whether there is more than one active exception
10-9RES0_2R0hReserved, RES0
8-0VECTACTIVER0hThe exception number of the current executing exception

2.7.13.4 VTOR Register (Offset = Ch) [Reset = 00000000h]

VTOR is shown in Table 2-484.

Return to the Summary Table.

Indicates the offset of the vector table base address from memory address 0x00000000

Table 2-484 VTOR Register Field Descriptions
BitFieldTypeResetDescription
31-7TBLOFFR00823FA4hBits 31 down to 7 of the vector table base offset.
6-0RES0R10hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.7.13.5 AIRCR Register (Offset = 10h) [Reset = 00000000h]

AIRCR is shown in Table 2-485.

Return to the Summary Table.

This register is used to determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point).

Table 2-485 AIRCR Register Field Descriptions
BitFieldTypeResetDescription
31-16VECTKEYR/WFA05hRegister key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. Otherwise the write value is ignored. Read always returns 0xFA05.
15ENDIANESSR0hData endianness bit
0 Little-endian.
1 Big-endian.
14PRISR0hPrioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is
enabled.
13BFHFNMINSR/W0hBusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI
exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception
0x0 BusFault, HardFault, and NMI are Secure.
0x1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault.
12-11RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
10-8PRIGROUPR/W0hInterrupt priority grouping field. This field determines the split of group priority from
subpriority
7-4RES4R0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3SYSRESETREQSR/W0hSystem reset request Secure only. The value of this bit defines whether the SYSRESETREQ bit is functional
for Non-secure use
2SYSRESETREQW0hSystem reset request. This bit allows software or a debugger to request a system reset:
0 Do not request a system reset.
1 Request a system reset.
This bit is not banked between Security states.
1VECTCLRACTIVEW0hReserved for Debug use. This bit reads as 0. When writing to the register you must write
0 to this bit, otherwise behavior is UNPREDICTABLE.
1RESERVEDR0hReserved
0RES0R0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.7.13.6 SCR Register (Offset = 14h) [Reset = 00000000h]

SCR is shown in Table 2-486.

Return to the Summary Table.

This register is used for power-management functions, i.e., signaling to the system when the processor can enter a low power state, controlling how the processor enters and exits low power states.

Table 2-486 SCR Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4SEVONPENDR/W0hSend Event on Pending bit:
0 Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
1 Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the
processor is not waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction or an external event.
This bit is banked between Security states.
3SLEEPDEEPSR/W0hControls whether the SLEEPDEEP bit is only accessible from the Secure state:
0 The SLEEPDEEP bit accessible from both Security states.
1 The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state.
This bit in only accessible from the Secure state, and behaves as RAZ/WI when accessed from the Nonsecure
state.
This bit is not banked between Security states.
2SLEEPDEEPR/W0hControls whether the processor uses sleep or deep sleep as its low power mode.
0 Sleep.
1 Deep sleep.
This bit is not banked between Security states.
1SLEEPONEXITR/W0hIndicates sleep-on-exit when returning from Handler mode to Thread mode:
0 Do not sleep when returning to Thread mode.
1 Enter sleep, or deep sleep, on return from an ISR.
Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
This bit is banked between Security states.
0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.7.13.7 CCR Register (Offset = 18h) [Reset = 00000000h]

CCR is shown in Table 2-487.

Return to the Summary Table.

Sets or returns configuration and control data

Table 2-487 CCR Register Field Descriptions
BitFieldTypeResetDescription
31-19RES0R0hReserved, RES0
18BPR0hEnables program flow prediction `FTSSS
17ICR0hThis is a global enable bit for instruction caches in the selected Security state
16DCR0hEnables data caching of all data accesses to Normal memory `FTSSS
15-11RES0_1R0hReserved, RES0
10STKOFHFNMIGNR/W0hControls the effect of a stack limit violation while executing at a requested priority less than 0
9RES1R1hReserved, RES1
8BFHFNMIGNR/W0hDetermines the effect of precise BusFaults on handlers running at a requested priority less than 0
7-5RES0_2R0hReserved, RES0
4DIV_0_TRPR/W0hControls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero
3UNALIGN_TRPR/W0hControls the trapping of unaligned word or halfword accesses
2RES0_3R0hReserved, RES0
1USERSETMPENDR/W0hDetermines whether unprivileged accesses are permitted to pend interrupts via the STIR
0RES1_1R1hReserved, RES1

2.7.13.8 SHPR1 Register (Offset = 1Ch) [Reset = 00000000h]

SHPR1 is shown in Table 2-488.

Return to the Summary Table.

Sets or returns priority for system handlers 4 - 7

Table 2-488 SHPR1 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_7R/W0hPriority of system handler 7, SecureFault
23-16PRI_6R/W0hPriority of system handler 6, UsageFault
15-8PRI_5R/W0hPriority of system handler 5, BusFault
7-0PRI_4R/W0hPriority of system handler 4, MemManage

2.7.13.9 SHPR2 Register (Offset = 20h) [Reset = 00000000h]

SHPR2 is shown in Table 2-489.

Return to the Summary Table.

Sets or returns priority for system handlers 8 - 11

Table 2-489 SHPR2 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_11R/W0hPriority of system handler 11, SVCall
23-0RES0RXhReserved, RES0

2.7.13.10 SHPR3 Register (Offset = 24h) [Reset = 00000000h]

SHPR3 is shown in Table 2-490.

Return to the Summary Table.

Sets or returns priority for system handlers 12 - 15

Table 2-490 SHPR3 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_15R/W0hPriority of system handler 15, SysTick
23-16PRI_14R/W0hPriority of system handler 14, PendSV
15-0RES0_0R0hReserved, RES0

2.7.13.11 SHCSR Register (Offset = 28h) [Reset = 00000000h]

SHCSR is shown in Table 2-491.

Return to the Summary Table.

Provides access to the active and pending status of system exceptions

Table 2-491 SHCSR Register Field Descriptions
BitFieldTypeResetDescription
31-22RES0R0hReserved, RES0
21HARDFAULTPENDEDR/W0h`IAAMO the pending state of the HardFault exception `CTTSSS
20SECUREFAULTPENDEDR/W0h`IAAMO the pending state of the SecureFault exception
19SECUREFAULTENAR/W0h`DW the SecureFault exception is enabled
18USGFAULTENAR/W0h`DW the UsageFault exception is enabled `FTSSS
17BUSFAULTENAR/W0h`DW the BusFault exception is enabled
16MEMFAULTENAR/W0h`DW the MemManage exception is enabled `FTSSS
15SVCALLPENDEDR/W0h`IAAMO the pending state of the SVCall exception `FTSSS
14BUSFAULTPENDEDR/W0h`IAAMO the pending state of the BusFault exception
13MEMFAULTPENDEDR/W0h`IAAMO the pending state of the MemManage exception `FTSSS
12USGFAULTPENDEDR/W0hThe UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS
11SYSTICKACTR/W0h`IAAMO the active state of the SysTick exception `FTSSS
10PENDSVACTR/W0h`IAAMO the active state of the PendSV exception `FTSSS
9RES0_1R0hReserved, RES0
8MONITORACTR/W0h`IAAMO the active state of the DebugMonitor exception
7SVCALLACTR/W0h`IAAMO the active state of the SVCall exception `FTSSS
6RES0_2R0hReserved, RES0
5NMIACTR/W0h`IAAMO the active state of the NMI exception
4SECUREFAULTACTR/W0h`IAAMO the active state of the SecureFault exception
3USGFAULTACTR/W0h`IAAMO the active state of the UsageFault exception `FTSSS
2HARDFAULTACTR/W0hIndicates and allows limited modification of the active state of the HardFault exception `FTSSS
1BUSFAULTACTR/W0h`IAAMO the active state of the BusFault exception
0MEMFAULTACTR/W0h`IAAMO the active state of the MemManage exception `FTSSS

2.7.13.12 CFSR Register (Offset = 2Ch) [Reset = 00000000h]

CFSR is shown in Table 2-492.

Return to the Summary Table.

Contains the three Configurable Fault Status Registers

Table 2-492 CFSR Register Field Descriptions
BitFieldTypeResetDescription
31-26RES0_3R0hReserved, RES0
25DIVBYZEROR/W0hSticky flag indicating whether an integer division by zero error has occurred
24UNALIGNEDR/W0hSticky flag indicating whether an unaligned access error has occurred
23-21RES0_1_2R0hReserved, RES0
20STKOFR/W0hSticky flag indicating whether a stack overflow error has occurred
19NOCPR/W0hSticky flag indicating whether a coprocessor disabled or not present error has occurred
18INVPCR/W0hSticky flag indicating whether an integrity check error has occurred
17INVSTATER/W0hSticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred
16UNDEFINSTRR/W0hSticky flag indicating whether an undefined instruction error has occurred
15BFARVALIDR/W0hIndicates validity of the contents of the BFAR register
14RES0_2R0hReserved, RES0
13LSPERRR/W0hRecords whether a BusFault occurred during FP lazy state preservation
12STKERRR/W0hRecords whether a derived BusFault occurred during exception entry stacking
11UNSTKERRR/W0hRecords whether a derived BusFault occurred during exception return unstacking
10IMPRECISERRR/W0hRecords whether an imprecise data access error has occurred
9PRECISERRR/W0hRecords whether a precise data access error has occurred
8IBUSERRR/W0hRecords whether a BusFault on an instruction prefetch has occurred
7MMARVALIDR/W0hIndicates validity of the MMFAR register
6RES0R0hReserved, RES0
5MLSPERRR/W0hRecords whether a MemManage fault occurred during FP lazy state preservation
4MSTKERRR/W0hRecords whether a derived MemManage fault occurred during exception entry stacking
3MUNSTKERRR/W0hRecords whether a derived MemManage fault occurred during exception return unstacking
2RES0_1R0hReserved, RES0
1DACCVIOLR/W0hRecords whether a data access violation has occurred
0IACCVIOLR/W0hRecords whether an instruction related memory access violation has occurred

2.7.13.13 HFSR Register (Offset = 30h) [Reset = 00000000h]

HFSR is shown in Table 2-493.

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Shows the cause of any HardFaults

Table 2-493 HFSR Register Field Descriptions
BitFieldTypeResetDescription
31DEBUGEVTR/W0hIndicates when a Debug event has occurred
30FORCEDR/W0hIndicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled
29-2RES0RXhReserved, RES0
1VECTTBLR/W0hIndicates when a fault has occurred because of a vector table read error on exception processing
0RES0_1R0hReserved, RES0

2.7.13.14 DFSR Register (Offset = 34h) [Reset = 00000000h]

DFSR is shown in Table 2-494.

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Shows which debug event occurred

Table 2-494 DFSR Register Field Descriptions
BitFieldTypeResetDescription
31-5RES0RXhReserved, RES0
4EXTERNALR/W0hSticky flag indicating whether an External debug request debug event has occurred
3VCATCHR/W0hSticky flag indicating whether a Vector catch debug event has occurred
2DWTTRAPR/W0hSticky flag indicating whether a Watchpoint debug event has occurred
1BKPTR/W0hSticky flag indicating whether a Breakpoint debug event has occurred
0HALTEDR/W0hSticky flag indicating that a Halt request debug event or Step debug event has occurred

2.7.13.15 MMFAR Register (Offset = 38h) [Reset = 00000000h]

MMFAR is shown in Table 2-495.

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Shows the address of the memory location that caused an MPU fault

Table 2-495 MMFAR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/W0hThis register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN

2.7.13.16 BFAR Register (Offset = 3Ch) [Reset = 00000000h]

BFAR is shown in Table 2-496.

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Shows the address associated with a precise data access BusFault

Table 2-496 BFAR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/W0hThis register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN

2.7.13.17 AFSR Register (Offset = 40h) [Reset = 00000000h]

AFSR is shown in Table 2-497.

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This register is used to determine additional system fault information to software. Single-cycle high level on an auxiliary faults is latched as one. The bit can only be cleared by writing a one to the corresponding bit. Auxiliary fault inputs to the CPU are tied to 0.

Table 2-497 AFSR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0IMPDEFR/W0hImplementation defined. The bits map directly onto the signal assignment to the auxiliary fault inputs. Tied to 0

2.7.13.18 ID_PFR0 Register (Offset = 44h) [Reset = 00000000h]

ID_PFR0 is shown in Table 2-498.

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Gives top-level information about the instruction set supported by the PE

Table 2-498 ID_PFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RES0RXhReserved, RES0
7-4State1R3hT32 instruction set support
3-0State0R0hA32 instruction set support

2.7.13.19 ID_PFR1 Register (Offset = 48h) [Reset = 00000000h]

ID_PFR1 is shown in Table 2-499.

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Gives information about the programmers' model and Extensions support

Table 2-499 ID_PFR1 Register Field Descriptions
BitFieldTypeResetDescription
31-12RES0RXhReserved, RES0
11-8MProgModR2hIdentifies support for the M-Profile programmers' model support
7-4SecurityR1hIdentifies whether the Security Extension is implemented
3-0RES0_1R0hReserved, RES0

2.7.13.20 ID_DFR0 Register (Offset = 4Ch) [Reset = 00000000h]

ID_DFR0 is shown in Table 2-500.

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Provides top level information about the debug system

Table 2-500 ID_DFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-24RES0R0hReserved, RES0
23-20MProfDbgR2hIndicates the supported M-profile debug architecture
19-0RES0_1RXhReserved, RES0

2.7.13.21 ID_AFR0 Register (Offset = 50h) [Reset = 00000000h]

ID_AFR0 is shown in Table 2-501.

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Provides information about the IMPLEMENTATION DEFINED features of the PE

Table 2-501 ID_AFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RES0R0hReserved, RES0
15-12IMPDEF3R0hIMPLEMENTATION DEFINED meaning
11-8IMPDEF2R0hIMPLEMENTATION DEFINED meaning
7-4IMPDEF1R0hIMPLEMENTATION DEFINED meaning
3-0IMPDEF0R0hIMPLEMENTATION DEFINED meaning

2.7.13.22 ID_MMFR0 Register (Offset = 54h) [Reset = 00000000h]

ID_MMFR0 is shown in Table 2-502.

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Provides information about the implemented memory model and memory management support

Table 2-502 ID_MMFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-24RES0R0hReserved, RES0
23-20AuxRegR1hIndicates support for Auxiliary Control Registers
19-16TCMR0hIndicates support for tightly coupled memories (TCMs)
15-12ShareLvlR1hIndicates the number of shareability levels implemented
11-8OuterShrRFhIndicates the outermost shareability domain implemented
7-4PMSAR4hIndicates support for the protected memory system architecture (PMSA)
3-0RES0_1R0hReserved, RES0

2.7.13.23 ID_MMFR1 Register (Offset = 58h) [Reset = 00000000h]

ID_MMFR1 is shown in Table 2-503.

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Provides information about the implemented memory model and memory management support

Table 2-503 ID_MMFR1 Register Field Descriptions
BitFieldTypeResetDescription
31-0RES0R0hReserved, RES0

2.7.13.24 ID_MMFR2 Register (Offset = 5Ch) [Reset = 00000000h]

ID_MMFR2 is shown in Table 2-504.

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Provides information about the implemented memory model and memory management support

Table 2-504 ID_MMFR2 Register Field Descriptions
BitFieldTypeResetDescription
31-28RES0R0hReserved, RES0
27-24WFIStallR1hIndicates the support for Wait For Interrupt (WFI) stalling
23-0RES0_1RXhReserved, RES0

2.7.13.25 ID_MMFR3 Register (Offset = 60h) [Reset = 00000000h]

ID_MMFR3 is shown in Table 2-505.

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Provides information about the implemented memory model and memory management support

Table 2-505 ID_MMFR3 Register Field Descriptions
BitFieldTypeResetDescription
31-12RES0RXhReserved, RES0
11-8BPMaintR0hIndicates the supported branch predictor maintenance
7-4CMaintSWR0hIndicates the supported cache maintenance operations by set/way
3-0CMaintVAR0hIndicates the supported cache maintenance operations by address

2.7.13.26 ID_ISAR0 Register (Offset = 64h) [Reset = 00000000h]

ID_ISAR0 is shown in Table 2-506.

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Provides information about the instruction set implemented by the PE

Table 2-506 ID_ISAR0 Register Field Descriptions
BitFieldTypeResetDescription
31-28RES0R0hReserved, RES0
27-24DivideR1hIndicates the supported Divide instructions
23-20DebugR1hIndicates the implemented Debug instructions
19-16CoprocR4hIndicates the supported Coprocessor instructions
15-12CmpBranchR1hIndicates the supported combined Compare and Branch instructions
11-8BitFieldR1hIndicates the supported bit field instructions
7-4BitCountR1hIndicates the supported bit count instructions
3-0RES0_1R0hReserved, RES0

2.7.13.27 ID_ISAR1 Register (Offset = 68h) [Reset = 00000000h]

ID_ISAR1 is shown in Table 2-507.

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Provides information about the instruction set implemented by the PE

Table 2-507 ID_ISAR1 Register Field Descriptions
BitFieldTypeResetDescription
31-28RES0R0hReserved, RES0
27-24InterworkR2hIndicates the implemented Interworking instructions
23-20ImmediateR2hIndicates the implemented for data-processing instructions with long immediates
19-16IfThenR1hIndicates the implemented If-Then instructions
15-12ExtendR2hIndicates the implemented Extend instructions
11-0RES0_1R0hReserved, RES0

2.7.13.28 ID_ISAR2 Register (Offset = 6Ch) [Reset = 00000000h]

ID_ISAR2 is shown in Table 2-508.

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Provides information about the instruction set implemented by the PE

Table 2-508 ID_ISAR2 Register Field Descriptions
BitFieldTypeResetDescription
31-28ReversalR2hIndicates the implemented Reversal instructions
27-24RES0R0hReserved, RES0
23-20MultUR2hIndicates the implemented advanced unsigned Multiply instructions
19-16MultSR3hIndicates the implemented advanced signed Multiply instructions
15-12MultR2hIndicates the implemented additional Multiply instructions
11-8MultiAccessIntR2hIndicates the support for interruptible multi-access instructions
7-4MemHintR3hIndicates the implemented Memory Hint instructions
3-0LoadStoreR2hIndicates the implemented additional load/store instructions

2.7.13.29 ID_ISAR3 Register (Offset = 70h) [Reset = 00000000h]

ID_ISAR3 is shown in Table 2-509.

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Provides information about the instruction set implemented by the PE

Table 2-509 ID_ISAR3 Register Field Descriptions
BitFieldTypeResetDescription
31-28RES0R0hReserved, RES0
27-24TrueNOPR1hIndicates the implemented true NOP instructions
23-20T32CopyR1hIndicates the support for T32 non flag-setting MOV instructions
19-16TabBranchR1hIndicates the implemented Table Branch instructions
15-12SynchPrimR1hUsed in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions
11-8SVCR1hIndicates the implemented SVC instructions
7-4SIMDR3hIndicates the implemented SIMD instructions
3-0SaturateR1hIndicates the implemented saturating instructions

2.7.13.30 ID_ISAR4 Register (Offset = 74h) [Reset = 00000000h]

ID_ISAR4 is shown in Table 2-510.

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Provides information about the instruction set implemented by the PE

Table 2-510 ID_ISAR4 Register Field Descriptions
BitFieldTypeResetDescription
31-28RES0R0hReserved, RES0
27-24PSR_MR1hIndicates the implemented M profile instructions to modify the PSRs
23-20SyncPrim_fracR3hUsed in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions
19-16BarrierR1hIndicates the implemented Barrier instructions
15-12RES0_1R0hReserved, RES0
11-8WritebackR1hIndicates the support for writeback addressing modes
7-4WithShiftsR3hIndicates the support for writeback addressing modes
3-0UnprivR2hIndicates the implemented unprivileged instructions

2.7.13.31 ID_ISAR5 Register (Offset = 78h) [Reset = 00000000h]

ID_ISAR5 is shown in Table 2-511.

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Provides information about the instruction set implemented by the PE

Table 2-511 ID_ISAR5 Register Field Descriptions
BitFieldTypeResetDescription
31-0RES0R0hReserved, RES0

2.7.13.32 CLIDR Register (Offset = 7Ch) [Reset = 00000000h]

CLIDR is shown in Table 2-512.

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Identifies the type of caches implemented and the level of coherency and unification

Table 2-512 CLIDR Register Field Descriptions
BitFieldTypeResetDescription
31-30ICBR0hThis field indicates the boundary between inner and outer domain
  • 0h = Not disclosed in this mechanism
  • 1h = L1 cache is the highest inner level
  • 2h = L2 cache is the highest inner level
  • 3h = L3 cache is the highest inner level
29-27LoUUR0hThis field indicates the Level of Unification Uniprocessor for the cache
hierarchy
26-24LoCR0hThis field indicates the Level of Coherence for the cache hierarchy
23-21LoUISR0hEnables Non-secure access to coprocessor CP0
20-18Ctype7R0hCache type field 7. Indicates the type of cache implemented at level 7.
  • 0h = No cache
  • 1h = Instruction cache only
  • 2h = Data cache only
  • 3h = Separate instruction and data caches
  • 4h = Unified cache
17-15Ctype6R0hCache type field 6. Indicates the type of cache implemented at level 6.
  • 0h = No cache
  • 1h = Instruction cache only
  • 2h = Data cache only
  • 3h = Separate instruction and data caches
  • 4h = Unified cache
14-12Ctype5R0hCache type field 5. Indicates the type of cache implemented at level 5.
  • 0h = No cache
  • 1h = Instruction cache only
  • 2h = Data cache only
  • 3h = Separate instruction and data caches
  • 4h = Unified cache
11-9Ctype4R0hCache type field 4. Indicates the type of cache implemented at level 4.
  • 0h = No cache
  • 1h = Instruction cache only
  • 2h = Data cache only
  • 3h = Separate instruction and data caches
  • 4h = Unified cache
8-6Ctype3R0hCache type field 3. Indicates the type of cache implemented at level 3.
  • 0h = No cache
  • 1h = Instruction cache only
  • 2h = Data cache only
  • 3h = Separate instruction and data caches
  • 4h = Unified cache
5-3Ctype2R0hCache type field 2. Indicates the type of cache implemented at level 2.
  • 0h = No cache
  • 1h = Instruction cache only
  • 2h = Data cache only
  • 3h = Separate instruction and data caches
  • 4h = Unified cache
2-0Ctype1R0hCache type field 1. Indicates the type of cache implemented at level 1.
  • 0h = No cache
  • 1h = Instruction cache only
  • 2h = Data cache only
  • 3h = Separate instruction and data caches
  • 4h = Unified cache

2.7.13.33 CTR Register (Offset = 80h) [Reset = 00000000h]

CTR is shown in Table 2-513.

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The CTR provides information about the architecture of the currently selected cache

Table 2-513 CTR Register Field Descriptions
BitFieldTypeResetDescription
31RES1R1hReserved, RES1
30-28RES0R0hReserved, RES0
27-24CWGR0hLog2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified
23-20ERGR0hLog2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions
19-16DminLineR0hLog2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE
15-14RES1_1R3hReserved, RES1
13-4RES0_1R0hReserved, RES0
3-0IminLineR0hLog2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE

2.7.13.34 CCSIDR Register (Offset = 84h) [Reset = 00000000h]

CCSIDR is shown in Table 2-514.

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Provides information about the architecture of the caches. CCSIDR is RES0 if CLIDR is zero.

Table 2-514 CCSIDR Register Field Descriptions
BitFieldTypeResetDescription
31WTR1hIndicates whether the currently selected cache level supports Write-Through
  • 0h = Not supported
  • 1h = Supported
30WBR0hIndicates whether the currently selected cache level supports Write-Back
  • 0h = Not supported
  • 1h = Supported
29RAR0hIndicates whether the currently selected cache level supports read-allocation
  • 0h = Not supported
  • 1h = Supported
28WAR0hIndicates whether the currently selected cache level supports write-allocation
  • 0h = Not supported
  • 1h = Supported
27-13NumSetsR6hIndicates (Number of sets in the currently selected cache) - 1. Therefore, a value of 0
indicates that 1 is set in the cache. The number of sets does not have to be a power of 2
12-3AssociativityR0hIndicates (Associativity of cache) - 1. A value of 0 indicates an associativity of 1. The
associativity does not have to be a power of 2
2-0LineSizeR0hIndicates (Log2(Number of words per line in the currently selected cache)) - 2.

2.7.13.35 CSSELR Register (Offset = 88h) [Reset = 00000000h]

CSSELR is shown in Table 2-515.

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Selects the current Cache Size ID Register, CCSIDR, by specifying the required cache level and the cache
type (either instruction or data cache)

Table 2-515 CSSELR Register Field Descriptions
BitFieldTypeResetDescription
31-4Res0R08000C00hReserved,Res0
3-1LevelR0hSelects which cache level is to be identified. Permitted values are from 0b000, indicating Level
1 cache, to 0b110 indicating Level 7 cache
  • 0h = Level 1 cache
  • 1h = Level 2 cache
  • 2h = Level 3 cache
  • 3h = Level 4 cache
  • 4h = Level 5 cache
  • 5h = Level 6 cache
  • 6h = Level 7 cache
0InDR0hSelects whether the instruction or the data cache is to be identified
  • 0h = Data or unified cache
  • 1h = Instruction cache

2.7.13.36 CPACR Register (Offset = 8Ch) [Reset = 00000000h]

CPACR is shown in Table 2-516.

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Specifies the access privileges for coprocessors and the FP Extension

Table 2-516 CPACR Register Field Descriptions
BitFieldTypeResetDescription
31-24RES0R0hReserved, RES0
23-22CP11R/W0hThe value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN
21-20CP10R/W0hDefines the access rights for the floating-point functionality
19-16RES0_1R0hReserved, RES0
15-14CP7R/W0h Controls access privileges for coprocessor 7
13-12CP6R/W0h Controls access privileges for coprocessor 6
11-10CP5R/W0h Controls access privileges for coprocessor 5
9-8CP4R/W0h Controls access privileges for coprocessor 4
7-6CP3R/W0h Controls access privileges for coprocessor 3
5-4CP2R/W0h Controls access privileges for coprocessor 2
3-2CP1R/W0h Controls access privileges for coprocessor 1
1-0CP0R/W0h Controls access privileges for coprocessor 0

2.7.13.37 NSACR Register (Offset = 90h) [Reset = 00000000h]

NSACR is shown in Table 2-517.

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Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7

Table 2-517 NSACR Register Field Descriptions
BitFieldTypeResetDescription
31-12RES0RXhReserved, RES0
11CP11R/W0hEnables Non-secure access to the Floating-point Extension
10CP10R/W0hEnables Non-secure access to the Floating-point Extension
9-8RES0_1R0hReserved, RES0
7CP7R/W0hEnables Non-secure access to coprocessor CP7
6CP6R/W0hEnables Non-secure access to coprocessor CP6
5CP5R/W0hEnables Non-secure access to coprocessor CP5
4CP4R/W0hEnables Non-secure access to coprocessor CP4
3CP3R/W0hEnables Non-secure access to coprocessor CP3
2CP2R/W0hEnables Non-secure access to coprocessor CP2
1CP1R/W0hEnables Non-secure access to coprocessor CP1
0CP0R/W0hEnables Non-secure access to coprocessor CP0