SPRUJ64 September   2022

 

  1.   Abstract
  2.   Trademarks
  3. 1Key Features
  4. 2AM64x SKEVM Overview
    1. 2.1 Board Version Identification
  5. 3Functional Block Diagram
  6. 4System Description
    1. 4.1  Clocking
      1. 4.1.1 Ethernet PHY Clock
      2. 4.1.2 AM64x SoC Clock
    2. 4.2  Reset
    3. 4.3  Power Requirements
      1. 4.3.1 Power Input
      2. 4.3.2 USB Type-C Interface for Power Input
      3. 4.3.3 Power Fault Indication
      4. 4.3.4 Power Supply
      5. 4.3.5 Power Sequencing
      6. 4.3.6 SOC Power
    4. 4.4  Configuration
      1. 4.4.1 Boot Modes
    5. 4.5  JTAG
    6. 4.6  Test Automation
    7. 4.7  UART Interface
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 MMC Interface
        1. 4.8.2.1 Micro SD Interface
        2. 4.8.2.2 WiLink Interface
        3. 4.8.2.3 OSPI Interface
        4. 4.8.2.4 Board ID EEPROM Interface
    9. 4.9  Ethernet Interface
      1. 4.9.1 DP83867 PHY Default Configuration
      2. 4.9.2 DP83867 – Power, Clock, Reset, Interrupt, and LEDs
      3. 4.9.3 Industrial Application LEDs for Indication
    10. 4.10 USB 3.0 Interface
    11. 4.11 PRU Connector
    12. 4.12 User Expansion Connector
    13. 4.13 MCU Connector
    14. 4.14 Interrupt
    15. 4.15 I2C Interface
    16. 4.16 IO Expander (GPIOs)
  7. 5Known Issues and Modifications
    1. 5.1 Issue 1 - Silkscreen Missprint on Initial Board Batch
  8. 6Revision History

4.9.1 DP83867 PHY Default Configuration

The DP83867 PHY uses four level configurations based on resistor strapping, which generate four distinct voltages ranges. The resistors are connected to the RX data and control pins, which are normally driven by the PHY and are inputs to the AM64x. The voltage range for each mode is shown below.

Mode 1 - 0 V to 0.3234 V

Mode 2 – 0.462 V to 0.6303 V

Mode 3 – 0.7425 V to 0.9372 V

Mode 4 – 2.2902 V to 2.904 V

The DP83867 device includes an internal pull-down resistor. The value of the external pull resistors is selected to provide voltage at the pins of the AM64x as close to ground or 3.3 V as possible. The strapping is shown in Figure 4-13. The strap values are given in Table 4-17

Table 4-17 Strap Value Configuration
ModeTarget VoltageIdeal Rhi
(k Ω)		Ideal Rlo
(k Ω)
Vmin(V)Vtyp(V)Vmax(V)
1000.098 * VDDIOOPENOPEN
20.140 * VDDIO0.165 * VDDIO0.191 * VDDIO102.49
30.225 * VDDIO0.255 * VDDIO0.284 * VDDIO5.762.49
40.694 * VDDIO0.763 * VDDIO0.886 * VDDIO2.49OPEN

Address strapping is provided for CPSW PHY-1 to set address -00000 (0h) and CPSW PHY-2 to set address 00001(01h). By default, strapping pins have internal pull-down resistors. Footprint for both pull up and pull down is provided on all the strapping pins except LED_0. LED_0 is for Mirror Enable, which is set to mode 1 by default, Mode 4 is not applicable and Mode2, Mode3 option is not desired. Default strap setting of CPSW RGM I 1Ethernet PHY and CPSW RGMII1 Ethernet PHY are given in Table 4-18 and Table 4-19.

GUID-8154AB19-D586-4D80-BD57-B401C6706CCA-low.pngFigure 4-13 CPSW Ethernet PHY-1 Strap settings
GUID-168AF6D1-DEC8-443B-A156-D2E77299C7CA-low.pngFigure 4-14 CPSW Ethernet PHY-2 Strap settings
Table 4-18 Default Strap Setting of CPSW RGMII-1 Ethernet PHY
Strap SettingPin NameStrap FunctionMode for PRG1_PRU1, PRG1_PRU0Value of Strap Function for PRG1Description
PHY AddressRX_D2PHY_AD310PHY Address: 0000
PHY_AD210

RX_D0

PHY_AD110
PHY_AD010
Auto NegotiationRX_DV/RX_CTRLAuto- neg30Auto neg Disable=0
Modes of OperationLED2RGMII Clock Skew TX[1]50RGMII TX Clock Skew is set to 0 ns
RGMII Clock Skew TX[0]50
LED_1RGMII Clock Skew TX[2]51
ANEG_SEL10advertise ability of 10/100/1000
LED_0Mirror Enable10Mirror Enable Disabled
GPIO_1RGMII Clock Skew RX[2]10RGMII RX Clock Skew is set to 2 ns
RGMII Clock Skew TX[1]10
GPIO_0RGMII Clock Skew RX[0]10
Table 4-19 Default Strap Setting of CPSW RGMII-2 Ethernet PHY
Strap SettingPin NameStrap FunctionMode for PRG1_PRU1, PRG1_PRU0Value of Strap Function for PRG0 and PRG1Description
PHY AddressRX_D2PHY_AD310PHY Address: 0001
PHY_AD210

RX_D0

PHY_AD120
PHY_AD021
Auto NegotiationRX_DV/RX_CTRLAuto- neg30Auto neg Disable=0
Modes of OperationLED2RGMII Clock Skew TX[1]50RGMII TX Clock Skew is set to 0 ns
RGMII Clock Skew TX[0]50
LED_1RGMII Clock Skew TX[2]51
ANEG_SEL10advertise ability of 10/100/1000
LED_0Mirror Enable10Mirror Enable Disabled
GPIO_1RGMII Clock Skew RX[2]10RGMII RX Clock Skew is set to 2 ns
RGMII Clock Skew TX[1]10
GPIO_0RGMII Clock Skew RX[0]10