SPRUJ64 September   2022

 

  1.   Abstract
  2.   Trademarks
  3. 1Key Features
  4. 2AM64x SKEVM Overview
    1. 2.1 Board Version Identification
  5. 3Functional Block Diagram
  6. 4System Description
    1. 4.1  Clocking
      1. 4.1.1 Ethernet PHY Clock
      2. 4.1.2 AM64x SoC Clock
    2. 4.2  Reset
    3. 4.3  Power Requirements
      1. 4.3.1 Power Input
      2. 4.3.2 USB Type-C Interface for Power Input
      3. 4.3.3 Power Fault Indication
      4. 4.3.4 Power Supply
      5. 4.3.5 Power Sequencing
      6. 4.3.6 SOC Power
    4. 4.4  Configuration
      1. 4.4.1 Boot Modes
    5. 4.5  JTAG
    6. 4.6  Test Automation
    7. 4.7  UART Interface
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 MMC Interface
        1. 4.8.2.1 Micro SD Interface
        2. 4.8.2.2 WiLink Interface
        3. 4.8.2.3 OSPI Interface
        4. 4.8.2.4 Board ID EEPROM Interface
    9. 4.9  Ethernet Interface
      1. 4.9.1 DP83867 PHY Default Configuration
      2. 4.9.2 DP83867 – Power, Clock, Reset, Interrupt, and LEDs
      3. 4.9.3 Industrial Application LEDs for Indication
    10. 4.10 USB 3.0 Interface
    11. 4.11 PRU Connector
    12. 4.12 User Expansion Connector
    13. 4.13 MCU Connector
    14. 4.14 Interrupt
    15. 4.15 I2C Interface
    16. 4.16 IO Expander (GPIOs)
  7. 5Known Issues and Modifications
    1. 5.1 Issue 1 - Silkscreen Missprint on Initial Board Batch
  8. 6Revision History

4.8.1 LPDDR4 Interface

The SK EVM has 2GB, 16-bit wide LPDDR4 memory with operating data rate of 1666 MTps. Micron's MT53E1G16D1FW-046 WT: A is used. The LPDDR memory is mounted on-board (single chip) and requires 1.1 V and thus reduces power demand. The LPDDR4 device requires I/O power and core 2 power of 1.1 V, DRAM activating power supply (core 1) of 1.8 V.

LPDDR4 reset is active high signal, which is controlled by SOC, and the signal is pulled low to set the default active state and a footprint for pull-down is also provided. A 240-Ω resistor is connected from ZQ pin to 1.1-V supply for the LPDDR4 device and the SoC DDR0_CAL pin is grounded.

The ODT (On Die Termination) is applied to DQ, DQS, and DM_n signals. The device is capable of providing three different ODT modes: Nominal, Dynamic, and Park with termination values: RTT (Park), RTT (NOM), and RTT (WR). Figure 4-8 shows the DDR interface between LPDDR4 and AM64x.

GUID-8AB8793C-C575-4966-8E11-5C129A1A1C70-low.pngFigure 4-8 LPDDR4 Interface