SPRUJ64 September   2022

 

  1.   Abstract
  2.   Trademarks
  3. 1Key Features
  4. 2AM64x SKEVM Overview
    1. 2.1 Board Version Identification
  5. 3Functional Block Diagram
  6. 4System Description
    1. 4.1  Clocking
      1. 4.1.1 Ethernet PHY Clock
      2. 4.1.2 AM64x SoC Clock
    2. 4.2  Reset
    3. 4.3  Power Requirements
      1. 4.3.1 Power Input
      2. 4.3.2 USB Type-C Interface for Power Input
      3. 4.3.3 Power Fault Indication
      4. 4.3.4 Power Supply
      5. 4.3.5 Power Sequencing
      6. 4.3.6 SOC Power
    4. 4.4  Configuration
      1. 4.4.1 Boot Modes
    5. 4.5  JTAG
    6. 4.6  Test Automation
    7. 4.7  UART Interface
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 MMC Interface
        1. 4.8.2.1 Micro SD Interface
        2. 4.8.2.2 WiLink Interface
        3. 4.8.2.3 OSPI Interface
        4. 4.8.2.4 Board ID EEPROM Interface
    9. 4.9  Ethernet Interface
      1. 4.9.1 DP83867 PHY Default Configuration
      2. 4.9.2 DP83867 – Power, Clock, Reset, Interrupt, and LEDs
      3. 4.9.3 Industrial Application LEDs for Indication
    10. 4.10 USB 3.0 Interface
    11. 4.11 PRU Connector
    12. 4.12 User Expansion Connector
    13. 4.13 MCU Connector
    14. 4.14 Interrupt
    15. 4.15 I2C Interface
    16. 4.16 IO Expander (GPIOs)
  7. 5Known Issues and Modifications
    1. 5.1 Issue 1 - Silkscreen Missprint on Initial Board Batch
  8. 6Revision History

4.6 Test Automation

The SKEVM has a 40-pin test automation header (J16) to allow an external controller to manipulate some basic operations such as Power Down, POR, Warm Reset, Boot Mode control, and so forth. The test automation header includes four GPIOs and two I2C interfaces (I2C1, Boot mode I2C0).

The test automation circuit has voltage translation circuits so that the controller is isolated from the IO voltages used by the AM64x. Boot mode for the AM64x must be controlled by either the user using DIP Switches or the test automation header through the I2C IO Expander.

Boot Mode Buffers are used to isolate the Boot Mode controls driven through DIP Switches or the I2C IO Expanders. Power to Test Automation Circuit is provided from a Power Mux (TPS2121RUXT), which has the input supplies VCC3V3_TA supply generated from a dedicated regulator and VCC3V3_XDS generated from an LDO (it is the supply for XDS110 Debugger section). The basic controls of test automation header J16 are as follows. Table 4-14 gives details about test automation header signals.

Optionally, the Test Automation header functionality can be implemented by the XDS110 controller. Hence resistor options (R420, R421, R422, R423, R424, R425, R426, R427, R436, R437, R438, and R439) are provided for Power Down, POR, Warm Reset, Boot Mode controls, and GPIO signals. By default, these resistors are made as DNI so that an external controller controls the basic operations through the Automation header. When the firmware for the XDS110 is developed, mount the above mentioned resistors and DNI the resistors R380, R381, R382, R383, R384, R385, R386, R432, R433, R434, and R435 to control the basic operations through the XDS110 microcontroller.

Proper Isolation to be provided on Boot Mode signals to allow normal operation. Two I2Cs are available on the test automation header. SoC _I2C [1] is connected to test automation header to communicate with external controller, and the other I2C is connected to Boot mode buffer to control boot mode of AM64x.

Table 4-14 lists the reset signals routed from test automation header. The boot mode for the AM64x can be controlled by either the user or the test automation header.

Table 4-14 List of Signals Routed to Test Automation Header J16
Signal Signal Type Function
POWER_DOWN GPIO Used to Power down the Board
PORZn GPIO Used to Reset the SoC PORz
WARM_RESETn GPIO Used to Reset the SoC Warmreset
GPIO1 GPIO

Used to Generate the interrupt on

GPIO1_59_INTn Pin
GPIO2 GPIO GPIO for communication with AM64X
GPIO3 GPIO Used to Enable the BOOTMODE Buffer
GPIO4 GPIO Used to Reset the Boot mode IO Expander
Bootmode I2C0 I2C Communicates with boot mode I2C buffer
I2C1 I2C Communicates with AM64x

If the test automation circuit is going to control the boot mode, all the switches must be manually be set to the off position. The pins used for boot mode also have other functions which are isolated by disabling the boot mode buffer during normal operation. Figure 4-6 shows the test automation signal connection with AM64x.

GUID-577F53B1-527F-485D-8A92-AB0E353E94C0-low.png Figure 4-6 Test Automation Header

Test Automation Header signals are optionally connected to the XDS110 microcontroller through zero ohm resistors. By default, those resistors are made as DNI.

Table 4-15 Automation Header Signals Connected to XDS110
TM4C1294 PIN Name Signal Name
PM0 TEST_POWERDOWN
PM1 TEST_PORZn
PM2 TEST_WARMRESETn
PM3 TEST_GPIO1
PM4 TEST_GPIO2
PM5 TEST_GPIO3
PM6 TEST_GPIO4
PM7 TEST_POWERDOWN
PG0 TEST_PORZn
PG1 TEST_WARMRESETn

Table 4-16 lists test automation header’s pin-out and IO direction.

Table 4-16 Test Automation Header (J16) Pin-Outs
Pin No.Signal NameIO Direction (wrt SoC)
1VCC3V3_TAPower (out)
2VCC3V3_TAPower (out)
3VCC3V3_TAPower (out)
4NCNA
5NCNA
6NCNA
7DGNDGround
8NCNA
9NCNA
10NCNA
11NCNA
12NCNA
13NCNA
14NCNA
15NCNA
16DGNDGround
17NCNA
18NCNA
19NCNA
20NCNA
21NCNA
22NCNA
23NCNA
24NCNA
25DGNDGround
26TEST_POWERDOWNInput
27TEST_PORZnInput
28TEST_WARMRESETnInput
29NCNA
30TEST_GPIO1Bidirectional
31TEST_GPIO2Bidirectional
32TEST_GPIO3Input
33TEST_GPIO4Input
34DGNDGround
35NCNA
36SOC_I2C1_TA_SCLBidirectional
37BOOTMODE_I2C_SCLBidirectional
38SOC_I2C1_TA_SDABidirectional
39BOOTMODE_I2C_SDABidirectional
40DGNDGround
41DGNDGround
42DGNDGround