SPRUJ64 September   2022

 

  1.   Abstract
  2.   Trademarks
  3. 1Key Features
  4. 2AM64x SKEVM Overview
    1. 2.1 Board Version Identification
  5. 3Functional Block Diagram
  6. 4System Description
    1. 4.1  Clocking
      1. 4.1.1 Ethernet PHY Clock
      2. 4.1.2 AM64x SoC Clock
    2. 4.2  Reset
    3. 4.3  Power Requirements
      1. 4.3.1 Power Input
      2. 4.3.2 USB Type-C Interface for Power Input
      3. 4.3.3 Power Fault Indication
      4. 4.3.4 Power Supply
      5. 4.3.5 Power Sequencing
      6. 4.3.6 SOC Power
    4. 4.4  Configuration
      1. 4.4.1 Boot Modes
    5. 4.5  JTAG
    6. 4.6  Test Automation
    7. 4.7  UART Interface
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 MMC Interface
        1. 4.8.2.1 Micro SD Interface
        2. 4.8.2.2 WiLink Interface
        3. 4.8.2.3 OSPI Interface
        4. 4.8.2.4 Board ID EEPROM Interface
    9. 4.9  Ethernet Interface
      1. 4.9.1 DP83867 PHY Default Configuration
      2. 4.9.2 DP83867 – Power, Clock, Reset, Interrupt, and LEDs
      3. 4.9.3 Industrial Application LEDs for Indication
    10. 4.10 USB 3.0 Interface
    11. 4.11 PRU Connector
    12. 4.12 User Expansion Connector
    13. 4.13 MCU Connector
    14. 4.14 Interrupt
    15. 4.15 I2C Interface
    16. 4.16 IO Expander (GPIOs)
  7. 5Known Issues and Modifications
    1. 5.1 Issue 1 - Silkscreen Missprint on Initial Board Batch
  8. 6Revision History

4.8.2.3 OSPI Interface

The SK EVM board has a 512-Mbit OSPI memory device of part number S28HS512TGABHM010 from Cypress connected to the OSPI0 interface of the AM64x SOC. The OSPI interface supports memory speed up to 166 MHz. The OSPI flash is powered by 1.8-V IO supply. The 1.8-V supply is provided to both the VCC and VCCQ pins of the flash memory.

The reset for the flash is connected to a circuit that ANDs the RESETSTATz, PORz_OUT, and OSPI0_CSN2 (GPIO_OSPI_RSTn) from SoC. This applies reset for warm and cold reset. A pull-up is provided on GPIO_OSPI_RSTn coming from the SOC pin to set the default active state.

Two signals are routed to OSPI0_DQS:

  1. OSPI0_DQS from the memory device
  2. OSPI0_LBCLK from SoC

To route DQS from memory device: DNI R33 and R39.

To route OSPI0_LBCLK from SoC: Mount R33 and R39.

OSPI and QSPI implementation: 0-ohm resistors are provided for DATA [7:0], DQS, INT# and CLK signals. Footprints to mount external pull up resistors are provided on DATA [7:0] to prevent bus floating.

Figure 4-11 shows the OSPI interface block diagram for AM64x SK EVM.

GUID-64911696-6A2F-43FD-BA7C-E14E1B2ECBB0-low.png Figure 4-11 OSPI Interface