SPRUJ64 September   2022

 

  1.   Abstract
  2.   Trademarks
  3. 1Key Features
  4. 2AM64x SKEVM Overview
    1. 2.1 Board Version Identification
  5. 3Functional Block Diagram
  6. 4System Description
    1. 4.1  Clocking
      1. 4.1.1 Ethernet PHY Clock
      2. 4.1.2 AM64x SoC Clock
    2. 4.2  Reset
    3. 4.3  Power Requirements
      1. 4.3.1 Power Input
      2. 4.3.2 USB Type-C Interface for Power Input
      3. 4.3.3 Power Fault Indication
      4. 4.3.4 Power Supply
      5. 4.3.5 Power Sequencing
      6. 4.3.6 SOC Power
    4. 4.4  Configuration
      1. 4.4.1 Boot Modes
    5. 4.5  JTAG
    6. 4.6  Test Automation
    7. 4.7  UART Interface
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 MMC Interface
        1. 4.8.2.1 Micro SD Interface
        2. 4.8.2.2 WiLink Interface
        3. 4.8.2.3 OSPI Interface
        4. 4.8.2.4 Board ID EEPROM Interface
    9. 4.9  Ethernet Interface
      1. 4.9.1 DP83867 PHY Default Configuration
      2. 4.9.2 DP83867 – Power, Clock, Reset, Interrupt, and LEDs
      3. 4.9.3 Industrial Application LEDs for Indication
    10. 4.10 USB 3.0 Interface
    11. 4.11 PRU Connector
    12. 4.12 User Expansion Connector
    13. 4.13 MCU Connector
    14. 4.14 Interrupt
    15. 4.15 I2C Interface
    16. 4.16 IO Expander (GPIOs)
  7. 5Known Issues and Modifications
    1. 5.1 Issue 1 - Silkscreen Missprint on Initial Board Batch
  8. 6Revision History

JTAG

The SKEVM board includes XDS110 class on board emulation and a 20-pin cTI header to support TI internal testing of software builds. The SKEVM board includes the circuitry needed for XDS110 emulation. The connection for the emulator uses an USB2.0 micro-B connector J12 and the circuit acts as a powered USB slave device. The VBUS power from the connector is used to power the emulation circuit such that connection to the emulator is not lost when the power to the EVM is removed. Voltage translation buffers are needed to isolate the XDS110 circuit from the rest of the EVM. Additionally, XDS110 also offers UART to USB signal translation on the same USB port. UART1 of SoC MAIN Domain without flow control is connected to XDS110 UART port via an isolator.

Optionally, JTAG interface on SKEVM is also provided through 20-pin standard JTAG cTI Header J14. This allows the user to connect an external JTAG Emulator cable. Voltage translation buffers are used to isolate the JTAG signals from cTI header from the rest of the EVM. The output from the voltage translators from XDS110 section and cTI Header section is muxed and connected to SoC AM64x JTAG interface. If a connection to the cTI 20-pin JTAG connector is sensed using a present detect circuit, the mux will be set to route the 20-pin signals to the AM64x in place of the on-board emulation circuit.

The pin-outs of cTI 20-pin JTAG connector J14 are given in Table 4-13. An ESD protection part number TPD4E004 is provided on USB signals to steer ESD current pulses to VCC or GND. TPD4E004 protects against ESD pulses up to ±15-kV Human-Body Model (HBM) as specified in IEC 61000-4-2 and provides ±8-kV contact discharge and ±12- kV air-gap discharge.

Table 4-13 cTI 20 Pin Connector (J14) Pin-outs
Pin No.SignalPin No.Signal
1JTAG_TMS11JTAG_cTI_TCK
2JTAG_TRST#12DGND
3JTAG_TDI13JTAG_EMU0
4JTAG_TDIS14JTAG_EMU1
5VCC_3V3_SYS15JTAG_EMU_RSTN
6NC16DGND
7JTAG_TDO17NC
8SEL_XDS110_INV18NC
9JTAG_cTI_RTCK19NC
10DGND20DGND
GUID-C836CD51-4619-4A2A-8EC1-DB1F1ADDB9CE-low.pngFigure 4-5 JTAG Interface