SPRUJ64 September   2022

 

  1.   Abstract
  2.   Trademarks
  3. 1Key Features
  4. 2AM64x SKEVM Overview
    1. 2.1 Board Version Identification
  5. 3Functional Block Diagram
  6. 4System Description
    1. 4.1  Clocking
      1. 4.1.1 Ethernet PHY Clock
      2. 4.1.2 AM64x SoC Clock
    2. 4.2  Reset
    3. 4.3  Power Requirements
      1. 4.3.1 Power Input
      2. 4.3.2 USB Type-C Interface for Power Input
      3. 4.3.3 Power Fault Indication
      4. 4.3.4 Power Supply
      5. 4.3.5 Power Sequencing
      6. 4.3.6 SOC Power
    4. 4.4  Configuration
      1. 4.4.1 Boot Modes
    5. 4.5  JTAG
    6. 4.6  Test Automation
    7. 4.7  UART Interface
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 MMC Interface
        1. 4.8.2.1 Micro SD Interface
        2. 4.8.2.2 WiLink Interface
        3. 4.8.2.3 OSPI Interface
        4. 4.8.2.4 Board ID EEPROM Interface
    9. 4.9  Ethernet Interface
      1. 4.9.1 DP83867 PHY Default Configuration
      2. 4.9.2 DP83867 – Power, Clock, Reset, Interrupt, and LEDs
      3. 4.9.3 Industrial Application LEDs for Indication
    10. 4.10 USB 3.0 Interface
    11. 4.11 PRU Connector
    12. 4.12 User Expansion Connector
    13. 4.13 MCU Connector
    14. 4.14 Interrupt
    15. 4.15 I2C Interface
    16. 4.16 IO Expander (GPIOs)
  7. 5Known Issues and Modifications
    1. 5.1 Issue 1 - Silkscreen Missprint on Initial Board Batch
  8. 6Revision History

4.9 Ethernet Interface

SKEVM offers two Ethernet ports of 1Gigabit speed for external communication. Two channels of RGMII Gigabit Ethernet CPSW ports from the AM64x SoC should be connected to two separate Gigabit Ethernet PHY transceivers DP83867, which is finally terminated on two RJ45 connectors with integrated magnetics.

The 48-pin version of the PHY DP83867 should be configured to advertise 1-Gb operation with the internal delay set to accommodate the internal delay inside the AM64x. The RGMII1 signals shared with PRG1 should be used for the RX path to allow the PRG0 to be connected to the PRU header on the board. CPSW_RGMII1 and CPSW_RGMII2 ports of PRG1 share a common MDIO bus to communicate with the external PHY transceiver.

The two port RJ45 connector (LPJG16314A4NL) used on the board for Ethernet 10/100/1G connectivity. RJ45 connectors have integrated magnetics and LEDs for indicating 1000BASE-T link and receive or transmit activity.