SLUUCP8A June 2024 – April 2025 BQ41Z50
The BQ41Z50 device has a hardware-based short circuit in charge protection with adjustable current and delay time. Additionally, this protection feature can be enabled to create a PF by setting the [AOCCL] bit in the Enabled PF B register.
| Status | Condition | Action |
|---|---|---|
| Normal | Current() < (AOCC Voltage Threshold/RSENSE) | SafetyAlert()[AOCCL]
= 0, if
AOCCL
counter = 0 PFAlert()[AOCCL] = 0 Decrement AOCCL counter by one after each AOCC:Counter Dec Delay period, if AOCCL counter > 0 |
| Trip | Current() ≥ (AOCC Voltage Threshold/RSENSE) for AOCC Delay duration | SafetyStatus()[AOCC]
= 1 BatteryStatus()[TCA] = 1 OperationStatus()[XCHG] = 1 increment AOCCL counter |
| Recovery | SafetyStatus()[AOCC] = 1 for AOCC:Recovery time | SafetyStatus()[AOCC]
= 0 BatteryStatus()[TCA] = 0 OperationStatus()[XCHG] = 0 if SafetyStatus()[AOCCL] = 0. |
| Latch Alert | AOCCL counter > 0 | SafetyAlert()[AOCCL]
= 1 PFAlert()[AOCCL] = 1, if PFEnable()[AOCCL] is set. |
| Latch Trip | AOCCL counter ≥ AOCC:Latch Limit | SafetyAlert()[AOCCL]
= 0 SafetyStatus()[AOCCL] = 1 OperationStatus()[XCHG] = 1 PFAlert()[AOCCL] = 0 PFStatus()[AOCCL] = 1, if PFEnable()[AOCCL] is set. |
| Latch Reset ([NR] = 0) | SafetyStatus()[AOCCL]
= 1 AND DA Configuration[NR] = 0 AND Low-high-low transition on PRES pin | SafetyStatus()[AOCCL]
= 0 OperationStatus()[XCHG] = 0 if SafetyStatus()[AOCC] = 0 |
| Latch Reset ([NR] = 1) | SafetyStatus()[AOCCL]
= 1 AND DA Configuration[NR] = 1 for AOCC:Reset time | SafetyStatus()[AOCCL]
= 0 OperationStatus()[XCHG] = 0 if SafetyStatus()[AOCC] = 0 |