| QIM (Bit 7): QMax Imbalance |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
| OTF (Bit 6): Overtemperature FET |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
| COVL (Bit 5): Cell Overvoltage Latch |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
| SOT (Bit 4): Safety Overtemperature |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
| SOCD (Bit 3): Safety Overcurrent in Discharge |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
| SOCC (Bit 2): Safety Overcurrent in Charge |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
| SOV (Bit 1): Safety Cell Overvoltage |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
| SUV (Bit 0): Safety Cell Undervoltage |
| 1 = | Enabled |
| 0 = | Disabled (default) |