SLUUCP8A June 2024 – April 2025 BQ41Z50
| Class | Subclass | Name | Type | Min | Max | Default | Unit |
|---|---|---|---|---|---|---|---|
| Settings | GPIO | Sealed Access Config | H1 | 0x0 | 0x1F | 0x1F | Hex |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | RSVD | RSVD | RL4_PIN_8_EN | RL3_PIN_7 | RL2_PIN_4 | RL1_PIN_3 | RL0_PIN_32 |
| RSVD (Bit 7-5): Reserved. Do not use. | ||
| RL4_PIN_8_EN (Bit 4): RL4_PIN_8 SEALED mode access | ||
| 1 = | Enabled (default) | |
| 0 = | Disabled | |
| RL3_PIN_7 (Bit 3): RL3_PIN_7 SEALED mode access | ||
| 1 = | Enabled (default) | |
| 0 = | Disabled | |
| RL2_PIN_4 (Bit 2): RL2_PIN_4 SEALED mode access | ||
| 1 = | Enabled (default) | |
| 0 = | Disabled | |
| RL1_PIN_3 (Bit 1): RL1_PIN_3 SEALED mode access | ||
| 1 = | Enabled (default) | |
| 0 = | Disabled | |
| RL0_PIN_32 (Bit 0): RL0_PIN_32 SEALED mode access | ||
| 1 = | Enabled (default) | |
| 0 = | Disabled | |