SLUUCP8A June 2024 – April 2025 BQ41Z50
The BQ41Z50 device has two hardware-based overload in discharge protections (OCD1, 2) with adjustable current and delay time. Additionally, this protection feature can be enabled to create a PF by setting the [AOCDL] bit in the Enabled PF B register. The following table takes OCD1 as an example. OCD2 has the same registers for configuration.
| Status | Condition | Action |
|---|---|---|
| Normal | Current() > (AOCD Voltage Threshold/RSENSE) | SafetyAlert()[AOCDL]
= 0, if OLDL counter = 0 PFAlert()[SAOCDL] = 0 Decrement AOCDL counter by one after each AOCD:Counter Dec Delay period, if AOCDL counter > 0 |
| Trip | Current() ≤ (AOCD Voltage Threshold/RSENSE) for AOCD Delay duration | SafetyStatus()[AOCD]
= 1 OperationStatus()[XDSG] = 1 Increment AOCDL counter |
| Recovery | SafetyStatus()[AOCD] = 1 for AOCD:Recovery time | SafetyStatus()[AOCD]
= 0 OperationStatus()[XDSG] = 0 if SafetyStatus()[AOCDL] = 0. |
| Latch Alert | AOCDL counter > 0 | SafetyAlert()[AOCDL]
= 1 PFAlert()[SAOCDL] = 1, if PFEnable()[SAOCDL] is set. |
| Latch Trip | AOCDL counter ≥ AOCD:Latch Limit | SafetyAlert()[AOCDL]
= 0 SafetyStatus()[AOCDL] = 1 OperationStatus()[XDSG] = 1 PFAlert()[AOCDL] = 0 PFStatus()[AOCDL] = 1, if PFEnable()[AOCDL] is set. |
| Latch Reset ([NR] = 0) | SafetyStatus()[AOCDL]
= 1 AND DA Configuration[NR] = 0 AND Low-high-low transition on PRES pin | SafetyStatus()[AOCDL]
= 0 OperationStatus()[XDSG] = 0 if SafetyStatus()[AOCD] = 0. |
| Latch Reset ([NR] = 1) | SafetyStatus()[AOCDL]
= 1 AND DA Configuration[NR] = 1 for AOCD:Reset time | SafetyStatus()[AOCDL]
= 0 OperationStatus()[XDSG] = 0 if SafetyStatus()[AOCD] = 0. |