The ADC32RF8x (ADC32RF80 and ADC32RF83) is a 14-bit, 3-GSPS, dual-channel telecom receiver and feedback device family that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF8x family delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.
Each channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.
The ADC32RF8x supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 날짜 |
|---|---|---|---|---|
| * | Data sheet | ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices datasheet (Rev. B) | PDF | HTML | 2021/12/21 |
| Application note | Spurs Analysis in the RF Sampling ADC | 2018/02/09 | ||
| Application note | Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) | 2017/09/05 | ||
| Design guide | Wideband Receiver With 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design | 2016/09/23 | ||
| Application note | RF Sampling ADC with 800MHz of IBW LTE | 2016/09/08 | ||
| White paper | Analog advancements make waves in 5G communications | 2016/08/12 |
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
ADC32RF80 평가 모듈(EVM)은 JESD204B 인터페이스를 사용하는 듀얼 3GSPS 14비트 ADC(아날로그-디지털 컨버터)의 성능을 시연합니다. 이 EVM에는 ADC32RF80 장치가 포함되어 있으며, 필요한 전압을 공급하기 위해 LMK04828과 TI 전압 레귤레이터가 JESD204B 클로킹을 제공합니다. ADC의 각 채널에 대한 입력은 기본 설정상 변압기 입력 회로에 연결되어 있으며, 이는 50Ω 단일 종단 신호 소스에 연결할 수 있습니다.
클록 레퍼런스 입력은 변압기 입력을 통해 제공되며, 50Ω 단일 종단 클록 (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.
In the concept phase, a frequency-planning tool enables fine tuning of (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| VQFN (RRH) | 72 | Ultra Librarian |
| VQFNP (RMP) | 72 | Ultra Librarian |
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.
The design resource accessed as www.ti.com/lit/zip/slwc107 or www.ti.com/lit/xx/slwc107w/slwc107w.zip has been migrated to a new user experience at www.ti.com/tool/download/SLWC107. Please update any bookmarks accordingly.