The ADC32RF45 device is a 14-bit, 3.0-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF45 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.
Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.
The ADC32RF45 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
TSW40RF80 평가 모듈(EVM)은 2 전송 2수신(2T2R) RF 샘플링 트랜시버 레퍼런스 설계입니다. 이 모듈에는 DAC38RF80 듀얼 채널 RF 샘플링 디지털-아날로그 컨버터(DAC)와 ADC32RF45 듀얼 채널 RF 샘플링 아날로그-디지털 컨버터(ADC)가 포함되어 있습니다.
DAC38RF80 샘플링 속도는 최대 9GSPS로 작동하며 고주파 클록 생성을 위한 온보드 PLL/VCO를 포함하고 있습니다. 출력은 50Ω 회로에 대한 간편한 인터페이스를 위한 단일 종단입니다. ADC32RF45 샘플링 속도는 최대 (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.
In the concept phase, a frequency-planning tool enables fine tuning of (...)
이 레퍼런스 디자인은 최대 3GSPS의 듀얼 채널, 14비트 분해능 ADC 샘플링인 ADC32RF45를 특징으로 합니다. 최대 (...)
이 레퍼런스 설계는 ADC32RF80 이중 채널, 14비트, 3GSPS RF 샘플링 텔레콤 리시버를 보여줍니다. 이 장치에는 채널당 DDC(디지털 다운 컨버터) 2개가 포함되어 있습니다. DDC는 8에서 32까지 데시메이션 값을 (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| VQFNP (RMP) | 72 | Ultra Librarian |
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.
The design resource accessed as www.ti.com/lit/zip/slwc107 or www.ti.com/lit/xx/slwc107w/slwc107w.zip has been migrated to a new user experience at www.ti.com/tool/download/SLWC107. Please update any bookmarks accordingly.